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Strix Halo (gfx1151) exposes a small device memory pool (~62 GiB set by the BIOS UMA frame buffer), so a resident DeepSeek V4 Flash Q2 (80.76 GiB) failed with OOM while preparing model tensor spans. On integrated APUs the model arena now allocates via hipHostMalloc (fallback hipMallocManaged), mirroring llama.cpp GGML_HIP_UMA: weights live in host RAM and stay GPU visible over the UMA fabric, bypassing the device pool ceiling. Discrete GPUs are unchanged; DS4_ROCM_FORCE_DEVICE_MEM restores previous behavior. Verified on Bosgame M5 (Ryzen AI Max+ 395, Radeon 8060S, 128 GB, ROCm 10): 80.76 GiB resident in ~30 s, prefill ~273-284 tok/s (ctx 4-8k), steady generation ~13 tok/s.
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Follow-up with measured evidence for the scope question, from a machine that ran both configurations. On a Bosgame M5 (Ryzen AI Max+ 395, 128 GB) I measured the same resident model (
So the patch is exactly a no-reconfiguration fallback: where the documented kernel parameters are applied it is unnecessary and marginally slower (weights in GTT rather than pinned host memory); where the host runs stock firmware defaults it is the difference between OOM and a working resident model. Worth keeping that distinction in the description if reviewers want the smaller surface — the alternative would be documentation only ("set these kernel parameters"), which is what upstream already recommends. One extra data point on the same box: the ~62 GiB pool also silently reduced a streaming configuration's expert cache (89 GB requested → 51 GiB admitted), which went back to 81.9 GiB after the kernel parameters were applied. Same root cause, different symptom. |
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Update from the reporting machine: the box now runs the boot parameters documented for Strix Halo ( So on hosts with the documented GTT/TTM settings this patch is no longer needed — it would only remain relevant for stock-kernel systems with the small BIOS-UMA device pool. Happy to close or keep as an optional fallback, maintainer call. |
Fixes OOM loading resident DeepSeek V4 Flash Q2 (80.76 GiB) on Strix Halo systems, and unlocks the other 128 GB UMA resident models on ROCm.
Problem
The ROCm model arena allocates weights with
hipMalloc, which on integrated APUs is bound by the small device memory pool exposed to the GPU (~62 GiB, set by the BIOS UMA frame buffer). A resident Flash Q2 (80.76 GiB) therefore failed during tensor-span preparation:Fix
On integrated APUs, allocate model arena chunks via
hipHostMalloc(falling back tohipMallocManaged), mirroring how llama.cpp'sGGML_HIP_UMAkeeps weights in host RAM while they stay GPU-visible over the UMA fabric. Discrete GPUs keep the existinghipMallocpath untouched;DS4_ROCM_FORCE_DEVICE_MEM=1restores the previous behavior.Scope
The documented alternative for the small-pool problem is raising the GPU-visible pool via kernel boot parameters (
amdgpu.gttsize=126976 ttm.pages_limit=32505856 ttm.page_pool_size=32505856, see docs/STRIX_HALO.md), which gives ~124 GiB GTT. Hosts that already apply those parameters do not need this change.This patch is for the stock case: some integrated systems expose only ~62 GiB to the GPU with default firmware/kernel settings and cannot (or do not want to) change boot parameters or reboot. There, routing the resident weight arena to host memory makes 80-91 GiB resident models load without any host configuration change. Verified on a Bosgame M5 (Ryzen AI Max+ 395, Radeon 8060S, 128 GB) running stock boot parameters.
Verified
Bosgame M5 (Ryzen AI Max+ 395, Radeon 8060S, 128 GB, ROCm 10.0, this branch).
DeepSeek V4 Flash models, resident:
All load in ~30 s; KV is 0.41-0.46 GiB. GLM 5.3 Flash Q2 also runs resident (90 GiB) with
DS4_GLM_MEMORY_GUARD=0(the guard budgets from the ~61 GiB device pool); vision mode (V4 Flash Vision-Exp + encoder) works on ROCm.Note: this approach is complementary to #361 (opt-in
DS4_CUDA_MANAGEDfor high-context OOM on large-carveout UMA APUs): #361 addresses long-context scratch by defaulting weight/scratch placement policy on demand, while the change here makes resident weights work on integrated APUs out of the box by routing the weight arena to host memory.