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Xilinx Versal Gen2 ASU port: trng/wait update
- #11034
#11034
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dgarske
merged 1 commit into
wolfSSL:master
wolfSSL/wolfssl:master
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night1rider:asu-trng-fixes
night1rider/wolfssl:asu-trng-fixes
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Aug 5, 2026
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Xilinx Versal Gen2 ASU port: trng/wait update
#11034
dgarske
merged 1 commit into
wolfSSL:master
wolfSSL/wolfssl:master
from
night1rider:asu-trng-fixes
night1rider/wolfssl:asu-trng-fixes
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Commits
Commits on Aug 3, 2026
Xilinx Versal Gen2 ASU port: make TRNG direct RNG opt-in (seed the software DRBG by default) and wait on completion with Xil_WaitForEvent
night1rider
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f91612b
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