Skip to content

fpga/arty: add TinyRocketArtyBScanConfig, JTAG DTM over the FPGA TAP - #2378

Open
disdi wants to merge 1 commit into
ucb-bar:mainfrom
disdi:arty35t-usb-jtag-dtm
Open

disdi wants to merge 1 commit into
ucb-bar:mainfrom
disdi:arty35t-usb-jtag-dtm

Conversation

@disdi

@disdi disdi commented Sep 3, 2026

Copy link
Copy Markdown

The Arty A7-35T harness brings the SoC's JTAG DTM out on PMOD, so debugging needs a second JTAG adapter even though the board's USB cable already drives the Artix-7 TAP. Add WithArtyBScanJTAGHarnessBinder, which routes the JTAGPort through fpga-shells' JTAGTUNNEL (BSCANE2 on USER4, TCK gated by SEL via BUFGCE), and TinyRocketArtyBScanConfig that selects it in place of the PMOD binder while keeping the stock WithJtagDTM.

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

CI Help:
Add the following labels to modify the CI for a set of features.
Generally, a label added only affect subsequent changes to the PR (i.e. new commits, force pushing, closing/reopening).
See ci:* for full list of labels:

  • ci:fpga-deploy - Run FPGA-based E2E testing
  • ci:local-fpga-buildbitstream-deploy - Build local FPGA bitstreams for platforms that are released
  • ci:disable - Disable CI

…(BSCAN tunnel)

The Arty A7-35T harness brings the SoC's JTAG DTM out on PMOD, so debugging
needs a second JTAG adapter even though the board's USB cable already drives
the Artix-7 TAP. Add WithArtyBScanJTAGHarnessBinder, which routes the JTAGPort
through fpga-shells' JTAGTUNNEL (BSCANE2 on USER4, TCK gated by SEL via
BUFGCE), and TinyRocketArtyBScanConfig that selects it in place of the PMOD
binder while keeping the stock WithJtagDTM.
@disdi disdi changed the title fpga/arty: add TinyRocketArtyBScanConfig, JTAG DTM over the FPGA TAP … fpga/arty: add TinyRocketArtyBScanConfig, JTAG DTM over the FPGA TAP Sep 3, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant