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RISC-V: Do not use vsetivli for THeadVector. #9

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RISC-V: Do not use vsetivli for THeadVector. #9

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2 changes: 1 addition & 1 deletion gcc/config/riscv/riscv-v.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -394,7 +394,7 @@ emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
gcc_assert (!can_create_pseudo_p ());
machine_mode mode = GET_MODE (ops[0]);

if (imm_avl_p (mode))
if (imm_avl_p (mode) && !TARGET_XTHEADVECTOR)
{
/* Even though VL is a real hardreg already allocated since
it is post-RA now, we still gain benefits that we emit
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6 changes: 6 additions & 0 deletions gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c
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@@ -0,0 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mcpu=xt-c920 -mrvv-vector-bits=zvl -fzero-call-used-regs=all" */

void
foo ()
{}