[#942] STM32_GPIOPort: Separate IDR and ODR state

[PhysicistJohn]

Related issue

Fixes renode/renode#942

Description

Separates the STM32 GPIO output latch from the electrical/input pin state.

ODR, BSRR, and BRR now update a dedicated 16-bit latch. Only output-mode pins
drive that value onto their GPIO connection, and switching a pin to output mode
applies its existing latched value. Reset clears both the pin state and the
output latch.

A second commit makes BSRR set bits take priority when the same pin is both set
and reset in one write, matching the STM32 register specification.

Regression tests cover input/ODR independence, input/alternate-function/analog
non-driving behavior, switching to output mode, BSRR, BRR, reset, and BSRR
set-over-reset priority.

Usage example

The reproduction in renode/renode#942 now reads IDR as zero after latching ODR
bit 2, while ODR reads back bit 2. Writing both BSRR halves for bit 2 leaves the
ODR bit set.

Additional information

Validated on macOS Arm64 with .NET 8:

• focused STM32 GPIO tests: 7 passed
• full managed solution: 1,114 passed, 17 existing skips, 0 failures
• dotnet format --verify-no-changes: passed
• STM32F072B Robot suite: 6 passed
• STM32F4 Discovery Robot suite: 12 passed
• stock/patched monitor reproductions: passed