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1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Force cheshire's sim scripts re-generation
- Fix u-boot to support RVV-linux
- Fixed src emul check for vector integer extension operation
- Zero-extend the unsigned vslideup.vi/vslidedown.vi immediate

### Added

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7 changes: 5 additions & 2 deletions hardware/src/ara_dispatcher.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1224,7 +1224,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b001110: begin
ara_req.op = ara_pkg::VSLIDEUP;
ara_req.stride = {{ELEN{insn.varith_type.rs1[19]}}, insn.varith_type.rs1};
// vslideup.vi/vslidedown.vi take an UNSIGNED 5-bit immediate
// (V-spec 16.3.1/16.3.2); it must be zero-extended, not sign-extended.
ara_req.stride = {{ELEN{1'b0}}, insn.varith_type.rs1};
ara_req.eew_vs2 = csr_vtype_q.vsew;
// Encode vslideup/vslide1up on the use_scalar_op field
ara_req.use_scalar_op = 1'b0;
Expand All @@ -1236,7 +1238,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b001111: begin
ara_req.op = ara_pkg::VSLIDEDOWN;
ara_req.stride = {{ELEN{insn.varith_type.rs1[19]}}, insn.varith_type.rs1};
// Unsigned 5-bit immediate (V-spec 16.3.2): zero-extend it.
ara_req.stride = {{ELEN{1'b0}}, insn.varith_type.rs1};
ara_req.eew_vs2 = csr_vtype_q.vsew;
// Encode vslidedown/vslide1down on the use_scalar_op field
ara_req.use_scalar_op = 1'b0;
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