Hi 👋, I'm Om Maheshwari

Hardware Engineer | VLSI Researcher | RISC-V Enthusiast

I'm a Hardware Engineer and VLSI Researcher at IIT Mandi, specializing in processor architecture, FPGA-based systems, and hardware security. My work focuses on building observable, efficient, and secure computing systems from the ground up — because hardware is truth.

• 🔭 Currently working on Efficient FPGA-Based Phase Unwrapping
• 🧠 Researching Neuromorphic RISC-V architectures and event-driven computing
• 🔒 Building hardware-based timing attack detection systems
• 📡 Developing RF signal processing and classification pipelines
• 💡 Passionate about open-source hardware and RISC-V ecosystem
• 🎯 Core belief: Hardware-first thinking, security-aware design

Real-time timing attack detection system
Built custom RISC-V instrumentation for microarchitectural timing analysis. Detects side-channel vulnerabilities through execution time profiling.
C Hardware Security Side-Channel Defense

Advanced branch predictor with temporal properties
Designed and verified branch prediction unit with optimized finite state machine for improved pipeline performance.
Verilog Computer Architecture ⭐ 1

High-throughput parallel pipeline for digital holographic microscopy
Non-iterative DCT-based architecture implementing Laplacian → DCT → Frequency Processing → IDCT stages for fixed, high-throughput phase unwrapping.
VHDL FPGA Signal Processing

Event-driven computing experiments on RISC-V
Exploring neuromorphic computing primitives and spike-based communication protocols on RISC-V architectures.
RISC-V Neuromorphic Hardware Acceleration

Built-in self-test system for processor cores
Logic Built-In Self-Test (LBIST) implementation with power-aware testing strategies for MIPS32 single-cycle architecture.
VHDL DFT Processor Testing

High-speed low-noise analog design
Full-custom CMOS operational amplifier design with layout, DRC/LVS verification, and post-layout simulation.
Analog Design CMOS Cadence/Tanner

Wireless signal intelligence with deep learning
End-to-end RF signal processing pipeline with real-time feature extraction and ML-based classification for spectrum sensing.
Signal Processing Deep Learning RF Systems

PCB design and fabrication
Custom-designed Arduino UNO replica with schematic design, PCB layout, and assembly.
PCB Design Embedded Systems Hardware Prototyping

Hardware Security:
  - Side-channel analysis and defense mechanisms
  - Timing attack detection in processors
  - Secure microarchitectures

Computer Architecture:
  - RISC-V core design and optimization
  - Out-of-order execution and speculation
  - Branch prediction and cache hierarchies

FPGA & SoC Design:
  - High-level synthesis and acceleration
  - Parallel pipeline architectures
  - Real-time signal processing systems

Neuromorphic Computing:
  - Event-driven processing units
  - Spiking neural networks in silicon
  - Low-power compute paradigms

Digital Design & Verification:
  - Formal verification methods
  - Built-in self-test (BIST)
  - Coverage-driven verification

Hardware is truth. Software is proof.

• 🔹 Hardware-first thinking — Optimize at the RTL level, not as an afterthought
• 🔹 Performance-aware design — Every cycle and every gate matters
• 🔹 Security-aware compute — Defense must be built into silicon
• 🔹 Observable systems — What you can't measure, you can't trust
• 🔹 Verifiable correctness — Simulation is necessary, formal verification is sufficient

I'm always interested in discussing hardware design, processor architecture, FPGA prototyping, and hardware security research. Let's build the future of computing together!