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Achievement: Pull Shark

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Achievement: Pull Shark

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@vicharak-in

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nirajumaretiya/README.md

Hello! 馃憢

Physical Design 路 Memories 路 Computer Architecture 路 AI Hardware

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Recent graduate exploring ASICs, RTL, and high-performance architectures - building ASICs from transistors.

Skills: Verilog 路 SystemVerilog 路 C/C++ 路 Python 路 MATLAB 路 Git
EDA: Cadence (Virtuoso, Genus, Innovus, Modus, Conformal) 路 Synopsys (DC, iCC2) 路 Tessent 路 ModelSim 路 OpenRAM

Projects: TinyGPU (SystemVerilog) 路 MBIST & BIRA (Tessent) 路 DDR3 Controller 路 Bitcoin Miner 路 1脳3 Router - all on FPGA/ASIC flows

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Streak

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  1. tinygpu tinygpu Public

    SystemVerilog 2 1

  2. DDR3_controller DDR3_controller Public

    Verilog

  3. 1x3_router_design_and_verification 1x3_router_design_and_verification Public

    Verilog

  4. FIFO-Memory FIFO-Memory Public

    Verilog

  5. vicharak-in/kalpkranti_course vicharak-in/kalpkranti_course Public

    Coursework for kalpkranti

    Python 3 5

  6. Simple_cache_controller Simple_cache_controller Public

    Implementation in Verilog of multilevel cache controller

    Verilog