[nix] add some missing devshell dependencies

[machshev]

With this update I'm able to run the following dvsim sim flow:

> nix develop .
> bazel clean --expunge
> dvsim -pi 1 hw/top_earlgrey/dv/chip_sim_cfg.hjson --tool=xcelium -i chip_sw_uart_tx_rx
...
00:00:30  [    build    ]: [S:         0, Q:      0, R:       0, P:      1, F:      0, K:      0, T:     1] 100%

          [   legend    ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]
00:00:30  [    build    ]: [S:         0, Q:      0, R:       0, P:      1, F:      0, K:      0, T:     1] 100%

          [   legend    ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]
[I 260724 11:30:01 report:477] [results]: [chip]
## CHIP Simulation Results
### Friday July 24 2026 10:13:26 UTC
### GitHub Revision: [`215aac8263`](https://github.com/lowrisc/opentitan/tree/215aac82638ef76bbe81cf05e6f482762aa05fe8)
### Branch: devshell-fix
### [Testplan](https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html)
### Simulator: XCELIUM

### Test Results

|  Stage  |           Name           | Tests              |  Max Job Runtime  |  Simulated Time  |  Passing  |  Total  |  Pass Rate  |
|:-------:|:------------------------:|:-------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
|   V1    |    chip_sw_uart_tx_rx    | chip_sw_uart_tx_rx |     846.000s      |    4887.017us    |     5     |    5    |  100.00 %   |
|   V1    | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx |     846.000s      |    4887.017us    |     5     |    5    |  100.00 %   |
|   V1    |                          | **TOTAL**          |                   |                  |     5     |    5    |  100.00 %   |
|   V3    | chip_sw_uart_watermarks  | chip_sw_uart_tx_rx |     846.000s      |    4887.017us    |     5     |    5    |  100.00 %   |
|   V3    |                          | **TOTAL**          |                   |                  |     5     |    5    |  100.00 %   |
|         |                          | **TOTAL**          |                   |                  |     5     |    5    |  100.00 %   |

## Coverage Results
### [Coverage Dashboard](/home/jamesm/base/opentitan-devshell/scratch/devshell-fix/chip_earlgrey_asic-sim-xcelium/cov_report/index.html)


          [   legend    ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]
00:00:30  [    build    ]: [S:         0, Q:      0, R:       0, P:      1, F:      0, K:      0, T:     1] 100%
00:16:33  [     run     ]: [S:         0, Q:      0, R:       0, P:      5, F:      0, K:      0, T:     5] 100%

[rswarbrick]

I'm a bit confused about the log in the PR description. You ran with --build-only and it reported 5 test runs?!

[machshev]

I'm a bit confused about the log in the PR description. You ran with --build-only and it reported 5 test runs?!

Sorry fixed the "log". Copied the command you gave me to test this. Fixed the build stage issues. Then dropped the build only flag and ran it all the way through.

When writing the description in the PR I copied your original command and forgot to remove the build only flag. Locally I ran it without... hence the tail of the log with 5 sims passing in addition to the one build job.

[engdoreis]

LGTM, thanks for the addition.

[andreaskurth]

LGTM, thanks @machshev