[rtl,sw] RRAM Earlgrey integration: map sw to RRAM - #30424
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This PR needs further changes to map software to RRAM. probably this is required #30390 |
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This commit adds rram_ctrl + rram_macro and connects them to the bus system. The RRAM can already be used for read/write operations through the controller and host port. Software binaries are still mapped to the flash macro, and otp_ctrl is not yet connected to rram_ctrl. No functional change so far as RRAM is not yet used in any testcase (except for chip level csr_rw test). Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit is to be squashed into the previous one before merge. It contains all autogen changes that were generated with `make -C hw` Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Align all security countermeasures in sec_cm_testplan, hjson and RTL Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Updates opentitan alert handler unittest. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This allows to preload RRAM images and write selected pages through the backdoor. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This script gen-rram-img is used to convert a vmem128 file into a loadable vmem128 file that contains address infection and scrambling Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
The RRAM image is 128b wide and requires new rules to call the right script. When building software for the RRAM the "kind" can be switched from "flash" to "rram". This will generate a 128b wide vmem file and call the RRAM specific scripts for scrambling, address infection, etc. (gen-rram-img.py) Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit connects rram_ctrl to the keymgr. This means that the seeds for the keys are now read from RRAM instead of flash. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit contains the autogen files for connecting rram_ctrl to keymgr. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit allows to load RRAM images in verilator runs. The image can be scrambled and then loaded via memload to the RRAM data_array. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit renames the rom_ext_flash section to rom_ext_nvm which can be used for RRAM and flash. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commits removes the connection from flash_ctrl to otp_ctrl to fetch the scrambling keys and adds them to rram_ctrl. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit contains the autogen changes to connect rram_ctrl to otp_ctrl to fetch the scrambling keys Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This test needs to be ported to RRAM because the scrambling keys are now read from RRAM instead of flash. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Add dif_rram_ctrl to initialize and configure the RRAM controller aswell as simple functions to perform read/write operations to the RRAM Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit switches from executing from flash to RRAM. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Adjust the backdoor write operation for the RRAM. This adds the address infection for the backdoor write operation. This commit also adds a task that can wait for the rram_ctrl read-buffers to be idle. This is necessary because the RRAM issues every read twice and a backdoor write between the two reads would result in an integrity error. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Adds a testutils layer over the silicon_creator RRAM driver, mirroring flash_ctrl_testutils, so DV/on-device tests can exercise rram_ctrl without depending on silicon_creator internals directly. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
…tils nv_counter_testutils now stores counters directly in RRAM (via rram_ctrl_testutils) instead of flash_ctrl, since RRAM has no program/erase distinction. nvm_testutils gains an nvm_ctrl-backed implementation alongside its existing flash_ctrl one. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Reads the default NVM region's scrambling/ECC/high-endurance config through the tech-agnostic nvm_testutils API instead of calling dif_flash_ctrl directly, so this power virus test isn't hardcoded to flash anymore. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Adds kModuleRramCtrl and the four kErrorRramCtrl* codes, mirroring the existing kModuleFlashCtrl/kErrorFlashCtrl* codes, for use by the upcoming RRAM driver and nvm_ctrl RRAM backend. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Adds the register-level RRAM controller driver: data/info partition read/write, default-region and per-info-page permissions/config, region protection, and info-page lockdown. write() transparently read-modify-writes unaligned leading/trailing partial write granules, so callers can write arbitrary addr/word_count without worrying about RRAM's 4-word write granularity. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
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…ages under RRAM On RRAM, BootData0/BootData1 are always emulated info pages, so nvm_ctrl_info_perms_set() on them is a no-op that performs zero real register writes; the existing SEC_MMIO_WRITE_INCREMENT(2 * kNvmCtrlSecMmioInfoPermsSet) at each of boot_data's 3 write call sites assumed flash's real per-call writes and must be skipped for RRAM to keep sec_mmio_check_counters() accurate. This will be changed in the future once emulated info pages are fully supported in hardware. kBootDataEntriesPerPage now derives from NVM_BYTES_PER_PAGE instead of a hardcoded 16, since RRAM's page size differs from flash's and the old constant was wrong for RRAM. This constant is only used by boot_data.c and boot_data_functest.c, so it is defined directly in each of those (which already depend on nvm_ctrl.h) rather than in the shared boot_data.h. That header backs boot_data_header, a lightweight, broadly-depended-on target that must stay buildable on tops with neither flash_ctrl nor rram_ctrl (e.g. Darjeeling): pulling nvm_ctrl.h into it drags in nvm_ctrl's device deps, which unconditionally require flash_ctrl, breaking every such consumer. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Mechanically retargets the ROM's EPMP region and the ROM_EXT/bare-metal linker scripts' address-translation checks from the eflash memory region to rram (TOP_EARLGREY_RRAM_CTRL_HOST_*), matching the "1 bank, 2 slots" RRAM addressing already adopted elsewhere. Comments updated from flash-specific wording to generic NVM wording where they no longer apply only to flash. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
…, add 128-bit vmem rules Changes opentitan_test()'s default kind from "flash" to "rram", matching this branch's default NVM technology. Fixes scramble_rram_vmem's output suffix (was "src.vmem", should be "scr.vmem" like scramble_flash_vmem) and adds an optional out attr so callers can control the output name. rom/e2e/BUILD gains 128-bit-word vmem/scr_vmem rules alongside the existing 64-bit ones, needed for RRAM's backdoor-load VMEM format, and chip_rom_tests.hjson is updated for the corresponding empty_test_slot_*_prod_key_0/test_key_0 target renames (no longer fake_ecdsa_-prefixed, since that prefix is now added only where the corrupted-image genrules need it). Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
…tstrap load The spi_device backdoor-load path pointed at flash's ".64.vmem"/ ".64.scr.vmem" and backdoor-loaded FlashBank0Data/FlashBank1Data; RRAM builds never produce a ".64.vmem" file (only ".128.vmem"), and both slots map onto the single RramData memory. Also rewrites read_sw_frames() to a generic, word-size-parametric VMEM tokenizer: the previous fixed 4-token/64-bit-per-line $fscanf parse silently misparsed RRAM's 2-token/128-bit-per-line format (srec_cat varies both the token count and hex-digit width per line with word size), corrupting manifest data read back post-bootstrap. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
…ndaries Each SPI PAGE_PROGRAM command carries at most one 256-byte SPI upload payload, well below NVM_PROG_PAGE_SIZE (512 B on RRAM). Buffers consecutive, contiguous PAGE_PROGRAM payloads up to NVM_PROG_PAGE_SIZE before issuing a single nvm_ctrl_page_program() write, flushing early on a non-contiguous next chunk, a page-boundary crossing, or any non-PAGE_PROGRAM opcode (in particular RESET, so a staged chunk is never silently dropped at the end of a session). On RRAM this halves the number of physical write operations for a full-speed bootstrap image load, since NVM_PROG_PAGE_SIZE matches RRAM's store-buffer size and a write that straddles two of them costs an extra operation. No hardware or protocol change; flash's PROG_PAGE_SIZE equals one SPI payload, so it fills and flushes every command, unchanged from before. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
This commit configures the epmp in the imm_section to the NVM region instead of a hardcoded flash region. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
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Disable flash_ctrl or rram_ctrl depending on what is present in the current top. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
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July 28, 2026 11:20
The shared memory-protection region used for emulated info pages needs a dedicated index that doesn't collide with rom_ext/owner_block's use of regions 0-7 (see following sw commit). Bump NumRegions from 8 to 10 and regenerate the reg_pkg/reg_top RTL accordingly. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
kRramCtrlEmulRegion (the shared region backing the 14 emulated info pages: OwnerSlot0/1, DiceCerts, BootData0/1, ...) previously reused region 7, one of owner_block's configurable slots, as a stopgap. Now that rram_ctrl has 10 regions, give it a real, non-conflicting index (8) instead. nvm_ctrl_init() now actually configures this region, which it previously left unconfigured. nvm_testutils.c has its own parallel implementation of the same emulated-page mechanism (kRramRelocatedRegion, same page range) with the identical latent collision at region 0; fixed the same way for consistency, even though no current caller exercises that path. Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
…ation seed reads Replace remaining direct TOP_EARLGREY_FLASH_CTRL_* address/size references with the tech-agnostic nvm_ctrl.h equivalents (NVM_DATA_BASE_ADDR, NVM_DATA_SIZE_BYTES) in ROM_EXT manifest lookup and boot policy pointer code, and switch otbn_boot_attestation_keygen_seed() to nvm_ctrl_info_read_zeros_on_read_error(). Signed-off-by: Michael Gautschi <mgautschi@lowrisc.org>
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As per RFC , Earlgrey will be extended with support for RRAM based non-volatile memory.
This 5th integration PR maps software from flash to RRAM and enables RRAM execution
This PR is based on #30423
The diff of this PR can be found here:
https://github.com/lowRISC/opentitan/pull/30424/changes/a0e2854383cad7e33c31b70cf8f8d5af05f033be..d8d6d40043f9390e359388f70b6ef51c7dce5cc7