[AArch64] Add support for intent to read prefetch intrinsic

clang/include/clang/Basic/BuiltinsAArch64.def

@@ -96,6 +96,8 @@ TARGET_BUILTIN(__builtin_arm_jcvt, "Zid", "nc", "v8.3a")
 // Prefetch
 BUILTIN(__builtin_arm_prefetch, "vvC*UiUiUiUi", "nc")
 
+BUILTIN(__builtin_arm_prefetch_ir, "vvC*", "nc")
+
 // Range Prefetch
 BUILTIN(__builtin_arm_range_prefetch_x, "vvC*UiUiiUiiz", "n")
 BUILTIN(__builtin_arm_range_prefetch, "vvC*UiUiWUi", "n")

clang/lib/Headers/arm_acle.h

@@ -115,6 +115,7 @@ __swp(uint32_t __x, volatile uint32_t *__p) {
 #else
 #define __plix(cache_level, retention_policy, addr) \
   __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0)
+#define __pldir(addr) __builtin_arm_prefetch_ir(addr)
 #endif
 
 /* 7.7 NOP */

clang/test/CodeGen/arm_acle.c

@@ -186,6 +186,19 @@ void test_pldx_range() {
 
 #endif
 
+#if defined(__ARM_64BIT_STATE)
+
+// AArch64-LABEL: @test_pldir(
+// AArch64-NEXT:  entry:
+// AArch64-NEXT:    call void @llvm.aarch64.prefetch.ir(ptr null)
+// AArch64-NEXT:    ret void
+//
+void test_pldir() {
+  __pldir(0);
+}
+
+#endif
+
 // AArch32-LABEL: @test_pldx(
 // AArch32-NEXT:  entry:
 // AArch32-NEXT:    call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)

clang/test/CodeGen/builtins-arm64.c

@@ -111,6 +111,11 @@ void range_prefetch_x(void) {
   // CHECK: call {{.*}} @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
 }
 
+void read_intent_prefetch() {
+  // CHECK: call {{.*}} @llvm.aarch64.prefetch.ir(ptr null)
+  __builtin_arm_prefetch_ir(0);
+}
+
 __attribute__((target("v8.5a")))
 int32_t jcvt(double v) {
   //CHECK-LABEL: @jcvt(

llvm/include/llvm/IR/IntrinsicsAArch64.td

@@ -76,6 +76,11 @@ def int_aarch64_prefetch : Intrinsic<[],
      ]>,
     ClangBuiltin<"__builtin_arm_prefetch">;
 
+def int_aarch64_prefetch_ir : Intrinsic<[], [llvm_ptr_ty],
+    [IntrHasSideEffects, IntrInaccessibleMemOrArgMemOnly,
+     IntrWillReturn, ReadOnly<ArgIndex<0>>]>,
+    ClangBuiltin<"__builtin_arm_prefetch_ir">;
+
 def int_aarch64_range_prefetch : Intrinsic<[],
     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
     [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn, ReadOnly<ArgIndex<0>>,

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -6279,6 +6279,11 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
                        DAG.getTargetConstant(PrfOp, DL, MVT::i32), Addr,
                        Metadata);
   }
+  case Intrinsic::aarch64_prefetch_ir:
+    return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other,
+                       Op.getOperand(0),                        // Chain
+                       DAG.getTargetConstant(24, DL, MVT::i32), // Rt
+                       Op.getOperand(2));                       // Addr
   case Intrinsic::aarch64_sme_str:
   case Intrinsic::aarch64_sme_ldr: {
     return LowerSMELdrStr(Op, DAG, IntNo == Intrinsic::aarch64_sme_ldr);

llvm/lib/Target/AArch64/AArch64SystemOperands.td

@@ -435,6 +435,7 @@ let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {
 def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>;
 def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>;
 }
+def : PRFM<"ir",  0b11, "",    0b00, "",     0b0>;
 
 //===----------------------------------------------------------------------===//
 // SVE Prefetch instruction options.

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -1769,6 +1769,12 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     MI.eraseFromParent();
     return true;
   }
+  case Intrinsic::aarch64_prefetch_ir: {
+    auto &AddrVal = MI.getOperand(1);
+    MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(24).add(AddrVal);
+    MI.eraseFromParent();
+    return true;
+  }
   case Intrinsic::aarch64_neon_uaddv:
   case Intrinsic::aarch64_neon_saddv:
   case Intrinsic::aarch64_neon_umaxv:

llvm/test/CodeGen/AArch64/arm64-prefetch-ri.ll

@@ -0,0 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+v9a -mattr=+pcdphint --global-isel=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mattr=+v9a -mattr=+pcdphint --global-isel=1 --global-isel-abort=1 < %s | FileCheck %s
+
+define void @read_intent_prefetch(ptr %a, i64 %metadata) {
+; CHECK-LABEL: read_intent_prefetch:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    prfm ir, [x0]
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.prefetch.ir(ptr %a)
+  ret void
+}

llvm/test/MC/AArch64/armv9.6a-pcdphint.s

@@ -3,7 +3,7 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \
-// RUN:        | llvm-objdump -d --mattr=+pcdphint - | FileCheck %s --check-prefix=CHECK-INST
+// RUN:        | llvm-objdump -d --mattr=+pcdphint --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \
 // RUN:        | llvm-objdump -d --mattr=-pcdphint - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 // Disassemble encoding and check the re-encoding (-show-encoding) matches.
@@ -23,3 +23,11 @@ stshh strm
 // CHECK-ENCODING: encoding: [0x3f,0x96,0x01,0xd5]
 // CHECK-ERROR: error: instruction requires: pcdphint
 // CHECK-UNKNOWN:  d501963f      msr S0_1_C9_C6_1, xzr
+
+prfm ir, [x0]
+// CHECK-INST: prfm ir, [x0]
+// CHECK-ENCODING: [0x18,0x00,0x80,0xf9]
+
+prfm ir, [x2, #800]
+// CHECK-INST: prfm ir, [x2, #800]
+// CHECK-ENCODING: [0x58,0x90,0x81,0xf9]