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[AArch64] Add intrinsics support for multi-vector FMUL #163397

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Merged
Lukacma merged 5 commits into from
Dec 9, 2025
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[AArch64] Add intrinsics support for multi-vector FMUL #163397

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0d2b628
Add intrinsics
Lukacma Oct 13, 2025
73aa7ee
remove commented code
Lukacma Oct 14, 2025
e128c90
[AArch64] Add intrinsics support for multi-vector FMUL
Lukacma Oct 14, 2025
82060d8
Merge branch 'main' into sme-mul-acle
Lukacma Dec 5, 2025
eb5cc0e
Merge main
Lukacma Dec 5, 2025
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8 changes: 8 additions & 0 deletions clang/include/clang/Basic/arm_sve.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2400,3 +2400,11 @@ let SVETargetGuard = "sve2,fp8fma", SMETargetGuard = "ssve-fp8fma" in {
def SVFMLALLTB_LANE : SInst<"svmlalltb_lane[_f32_mf8]", "dd~~i>", "f", MergeNone, "aarch64_sve_fp8_fmlalltb_lane", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_7>]>;
def SVFMLALLTT_LANE : SInst<"svmlalltt_lane[_f32_mf8]", "dd~~i>", "f", MergeNone, "aarch64_sve_fp8_fmlalltt_lane", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_7>]>;
}

let SVETargetGuard = InvalidMode, SMETargetGuard = "sme2p2" in {
def FMUL_SINGLE_X2 : SInst<"svmul[_single_{d}_x2]", "22d", "hfd", MergeNone, "aarch64_sve_fmul_single_x2", [IsStreaming], []>;
def FMUL_SINGLE_X4 : SInst<"svmul[_single_{d}_x4]", "44d", "hfd", MergeNone, "aarch64_sve_fmul_single_x4", [IsStreaming], []>;

def FMUL_X2 : SInst<"svmul[_{d}_x2]", "222", "hfd", MergeNone, "aarch64_sve_fmul_x2", [IsStreaming], []>;
def FMUL_X4 : SInst<"svmul[_{d}_x4]", "444", "hfd", MergeNone, "aarch64_sve_fmul_x4", [IsStreaming], []>;
}

@kmclaughlin-arm kmclaughlin-arm Nov 11, 2025

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I think including the definitions here is correct, but I'm not sure if it means that they will be added to arm_sve.h? If so, I think this is different to what the acle doc states:

The intrinsics in this section are defined by the header file
[`<arm_sme.h>`](#arm_sme.h) when `__ARM_FEATURE_SME2p2` is defined.

@Lukacma Lukacma Nov 14, 2025

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Good point ! I will suggest the fix in the ACLE

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