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18c28b5
Install Oroshi doc in the right place.
jpc-lip6 Nov 21, 2023
b3d69de
One less level in the left menu (was too wide).
jpc-lip6 Nov 21, 2023
be1ddfe
New rule "install_docs" to build the documentation.
jpc-lip6 Nov 21, 2023
de901c0
Fix the loading of initHook.py, use Python loading mechanism directly.
jpc-lip6 Nov 21, 2023
7e04bf1
Don't connect with M2 on M3 RoutingPads.
jpc-lip6 Nov 22, 2023
c0ce778
Do not protect with TrackMarkers M2 RoutingPads.
jpc-lip6 Nov 22, 2023
108aae9
Duplicated ".spi" targets in pnrcheck designflow.
jpc-lip6 Nov 22, 2023
bb14cc9
Get version from git tag
robtaylor Dec 5, 2023
ae3b5bf
Fix warning when compiling EtesianEngine
Coloquinte Nov 3, 2023
98fd1ba
Mention hTracksReservedMin in the documentation
Coloquinte Nov 27, 2023
4be2ab6
Show track reserve options for what they are in viewer
Coloquinte Nov 27, 2023
209a411
Hide max number of reserved tracks in doc
Coloquinte Nov 27, 2023
1c9ee86
Add new purple color to debug Sky130 VexRam
Coloquinte Nov 29, 2023
66180ce
Fix bloat factor reporting in Etesian (has wrong % symbol)
Coloquinte Nov 29, 2023
fdd505a
Fix unclear printing in Etesian
Coloquinte Nov 30, 2023
c121970
Use Coloquinte cell expansion instead of Etesian, so that target dens…
Coloquinte Nov 30, 2023
d002ae9
Show placement effort in the logs
Coloquinte Nov 30, 2023
a669af7
Update etesian parameters in techno files
Coloquinte Nov 30, 2023
0b5a992
Fix format specifier in flute printf
Coloquinte Dec 6, 2023
4eece73
Use a maximum expanded width when using Coloquinte expansion
Coloquinte Dec 6, 2023
5fe90e4
Fixed Verilog netlist export with presence of unconnected plugs (#96)
lanserge Dec 7, 2023
f57b9a9
Fix for cell net names with indexes be in proper Verilog format (#97)
lanserge Dec 7, 2023
9cd6938
GDS: Actually skip discarded text
gatecat Dec 6, 2023
3cec6b0
remove python36-devel and liblemon build from docker file
robtaylor Dec 8, 2023
9564fe0
set pkgconfig path for cibuildwheel python
robtaylor Dec 8, 2023
c0d643f
Try adding linker script to ignore libpython symbols
robtaylor Dec 12, 2023
423ef22
Try adding linker script to ignore libpython symbols
robtaylor Dec 12, 2023
c92ac1c
Just allow undefined symbols
robtaylor Dec 12, 2023
5ea2420
set 'b_lundef=false' for the project
robtaylor Dec 12, 2023
97b9e7f
wip
robtaylor Dec 12, 2023
4d98aa9
Revert "wip"
robtaylor Jan 9, 2024
817f718
Revert "Revert "wip""
robtaylor Jan 9, 2024
af2a0f2
Set write-all permission for ghpages workflow
robtaylor Jan 9, 2024
ab686be
anabatic: Fix connectivity for staircases
gatecat Jan 9, 2024
26dbaee
Meson: remove old build system artifacts
robtaylor Sep 29, 2023
b93bfe2
docs: switch to pull_request_target
gatecat Jan 12, 2024
eb9b8f4
cumulus: Allow macros with MY orientation (#108)
gatecat Jan 17, 2024
924c3a7
Add support for MOSIS & AMS350 (c35b4) in designflow.technos.
jpc-lip6 Oct 24, 2023
37349f3
The karakaze tool (AnalogDesign) was forgotten in the installation.
jpc-lip6 Oct 24, 2023
b30ad7a
Intalling the techno files for gf180mcu_c4m from CRL.
jpc-lip6 Oct 20, 2023
9790dc5
The designflow sv2v, svase & surelog were forgotten in the merges.
jpc-lip6 Oct 20, 2023
f8c5614
One more forgotten to install gf180mcu file.
jpc-lip6 Oct 20, 2023
d3a259f
Must setup the Coriolis source directory in regression tests.
jpc-lip6 Oct 24, 2023
ae1ca32
Create separate rules for meson configure & setup.
jpc-lip6 Nov 25, 2023
0cd9828
New Rectilinear::getAsBiggestrectangles() method.
jpc-lip6 Nov 29, 2023
ddba509
In technos.setupCMOS(), find liberty from ALLIANCE_TOP instead of CEL…
jpc-lip6 Nov 29, 2023
ac5cb66
Slightly clrearer display of C++ exception catched through Python.
jpc-lip6 Dec 4, 2023
b406fad
Systematically throw an error in case of faulty contact topology.
jpc-lip6 Dec 4, 2023
f9b4e91
Reorganization of the size detection of RoutingPad.
jpc-lip6 Dec 5, 2023
6549194
Implementation of Pin Rectilinear Support
jpc-lip6 Dec 5, 2023
594bc79
Create the first technical log entry.
jpc-lip6 Dec 5, 2023
50bb168
The karakaze tool (AnalogDesign) was forgotten in the installation.
jpc-lip6 Jan 10, 2024
9e00acb
Make the left menu *not* overlap the page contents.
jpc-lip6 Dec 6, 2023
40c466d
Add all the .rst page dependencies to meson.buil.
jpc-lip6 Dec 6, 2023
08b348f
In GF180MCU techno, configuration now support HV or VH topologies.
jpc-lip6 Dec 18, 2023
3b19622
In LefParser::_pinStdPostProcess(), improved way to choose H/V.
jpc-lip6 Dec 18, 2023
5a94aff
In technos.setupGF180MCU_GF(), provide a flag to select HV or VH.
jpc-lip6 Dec 18, 2023
583dfc3
Support for offgrid M1 & VH topologies (WIP 1).
jpc-lip6 Dec 18, 2023
8790ff5
New type of LayerRoutingGauge : LocalOnly, for local interconnect.
jpc-lip6 Dec 21, 2023
b16f412
Do not process the blockages layers in FlattenPower (not needed).
jpc-lip6 Dec 21, 2023
67c7ffa
A DebugSession was left open in Katana::PropagateCagedConstraints().
jpc-lip6 Dec 26, 2023
f677457
Create a new type of TrakElement : TrackBlockage.
jpc-lip6 Dec 26, 2023
e70a035
More adjustements for the perpandicular track span & positions.
jpc-lip6 Dec 26, 2023
607f598
Keep track of the position of the BreakpointWidget.
jpc-lip6 Dec 26, 2023
cbefb91
Display the "ripup ratio" in Katana::Statistics (NegociateWidow).
jpc-lip6 Dec 28, 2023
4bef82f
Support saving & restoring positions and settings of graphic windows.
jpc-lip6 Dec 30, 2023
4409400
In Rectilinear, support for horizontal slicing.
jpc-lip6 Jan 1, 2024
fcfd3e1
Support Rectilinear in the two setupPowerRails() (Etesian & Katana).
jpc-lip6 Jan 1, 2024
f58a3e9
Fix TrackBlockage::_getString() when the is not yet a track (transient).
jpc-lip6 Jan 1, 2024
36fc3be
protectRoutingPads() call moved from ::digitalInit() to ::runGlobalro…
jpc-lip6 Jan 1, 2024
3a48273
Support for offgrid M1 & VH topologies (WIP 2).
jpc-lip6 Jan 5, 2024
1b0dc7f
Support for offgrid M1 & VH topologies (WIP 3).
jpc-lip6 Jan 10, 2024
5892699
Ignore Emacs backup files.
jpc-lip6 Jan 10, 2024
3dfdb36
Fix in oroshi.Stack, PMOS must be in nWell (not pWell).
jpc-lip6 Jan 10, 2024
560d218
Seems that when doc only is acivated, we no longer could compile.
jpc-lip6 Jan 10, 2024
271e067
Fixes in protectRoutingPads().
jpc-lip6 Jan 10, 2024
525d910
In selectRpComponent(), do not deflate VIAs in symbolic mode.
jpc-lip6 Jan 10, 2024
ab2894c
New Rectilinear::getAsBiggestrectangles() method.
jpc-lip6 Nov 29, 2023
8f45e33
Support for offgrid M1 & VH topologies (WIP 1).
jpc-lip6 Dec 18, 2023
a473c9c
Removing code duplication due to a bad merge in Rectilinear.
jpc-lip6 Jan 11, 2024
084f36e
Force DoglegDown when slackening and AutoSegment from a Terminal.
jpc-lip6 Jan 16, 2024
8d8b8cf
In NetBuilderHV, check for up density before moving up a global.
jpc-lip6 Jan 16, 2024
6840c47
Added isUsable() and getFirstroutingLayer() proxies to Anabatic::Conf…
jpc-lip6 Jan 16, 2024
88439ac
Export RoutingLayerGauge::isHorizontal() & isVertical() to Python.
jpc-lip6 Jan 16, 2024
789a1ad
Add a failsafe in case the graphic style index no longer exists.
jpc-lip6 Jan 16, 2024
fd6b231
Fix wrong import path.
jpc-lip6 Jan 16, 2024
b2336fe
Manage layer change for south terminals of a macro.
jpc-lip6 Jan 16, 2024
1d3b4d2
More accurate search for obstacle of the H-Tree sub-branches.
jpc-lip6 Jan 16, 2024
b0f3ad9
htree: Fix leaf contact selection (#112)
gatecat Jan 22, 2024
505e3d7
htree: Fix a tiny typo (#111)
gatecat Jan 22, 2024
c12b18e
In GdsDriver, support PATH with NULL layer. Fix TEXT/STRANS.
jpc-lip6 Jan 18, 2024
065aca0
Implemented GDSII/AREF record to support GF180MCU SRAM.
jpc-lip6 Jan 20, 2024
2b93f9e
Add debug informations in DataBase::getCell().
jpc-lip6 Jan 20, 2024
85f4715
Forgot to de-activate trace in GdsParser::makeInstances().
jpc-lip6 Jan 20, 2024
72f2454
Add offgrid checking and warnings to RoutingLayerGauge::create().
jpc-lip6 Jan 21, 2024
31b403f
Fix offgrid segment translation problem in LefImport.
jpc-lip6 Jan 21, 2024
542dc3f
Ensure that all the VIA & Horizontal rails are ongrid in powerplane.py.
jpc-lip6 Jan 22, 2024
84df899
In GdsParser, force boundary to be on grid, do it by shrinking.
jpc-lip6 Jan 22, 2024
53a03da
isobar: Wrap Rectilinear.getPoints()
gatecat Jan 24, 2024
9eaf97e
macro: Create a new hierarchy layer for wrapper
gatecat Jan 24, 2024
9b17a59
Never **ever** remove ${HOME}/.local again!
jpc-lip6 Jan 27, 2024
967aad5
macro: Fix naming of wrapper
gatecat Jan 29, 2024
b895bb6
Fixed gds parse to use type in the textbody as datatype for the gds l…
lanserge Jan 29, 2024
37c973f
macro: Ad-hoc patch fix power pin conflict for GF180 SRAMs
gatecat Jan 30, 2024
3402c30
Revert Pull Request target - this was causing all PRs to act like the…
robtaylor Feb 1, 2024
67eb842
Update apt before building website
robtaylor Feb 1, 2024
42bb6b0
Bump versions of gh actions for node 20
robtaylor Feb 1, 2024
6657792
Make only-docs logic more obvious
robtaylor Feb 1, 2024
f5f6f46
Fixed AREF origin and dx, dy calculations.
lanserge Feb 5, 2024
11a1630
Fixed AREF orientation for transformation in case of xReflection
lanserge Feb 5, 2024
495b690
Fixed AREF vertical and horizontal steps
lanserge Feb 7, 2024
dd96857
Fix cell path in designflow.technos for lsxlib.
jpc-lip6 Feb 12, 2024
91c2756
Fix the south I/O stick out extension in case of layer change.
jpc-lip6 Feb 12, 2024
35c75b4
Remove misplaced pin extention patch.
jpc-lip6 Feb 12, 2024
a2dda8d
Added layer map manupulation functions to LefImport (#129)
lanserge Feb 17, 2024
40eaf3f
Fix: info layer selected for text label if found with the same gds2layer
lanserge Feb 26, 2024
4bc9959
Fixed pad spacing calculation (subtract two corner sizes instead of t…
lanserge Feb 21, 2024
5c7b5b6
Fixed misaligned cells.
lanserge Feb 26, 2024
c83a3ca
Fixed horizontal cells alignment in several places
lanserge Mar 1, 2024
50e8fc9
Small fixes for GF130BCD.
jpc-lip6 Mar 8, 2024
1fec9ad
Speed optimization in BuildPowerRails.
jpc-lip6 Mar 10, 2024
5e23e42
Speed up KatanaEngine/AnabaticEngine destructor.
jpc-lip6 Mar 10, 2024
3499947
Provides alternate implementations for the Dijkstra PriorityQueue.
jpc-lip6 Mar 10, 2024
aae445a
Small refactoring and additionnal checks in Etesian.
jpc-lip6 Mar 12, 2024
bf80753
Do not perform bloat analysis in Katana if it's disabled in Etesian.
jpc-lip6 Mar 12, 2024
5ffae3f
Some typos in the pnrcheck integrated rule set.
jpc-lip6 Mar 12, 2024
a6270e9
Extend Layer::Mask to support up to 128 layers.
jpc-lip6 Mar 17, 2024
e33b797
In GdsParser, do not create Net for shapes in Material::info
jpc-lip6 Mar 17, 2024
bb2ec64
Fix bug in PyLefImport_addLayer(), really check the arguments's type.
jpc-lip6 Mar 17, 2024
9d800f6
Fix LefParser, ensure that rectangle not on "two-grid" are not shrinked.
jpc-lip6 Mar 18, 2024
7d2d232
In Configuration:::checkRoutingPadSize(), lower the VSmall threhsold …
jpc-lip6 Mar 18, 2024
f5aa15c
In NetBuilderHV::doRp_Access(), add a non-pref strap if VSmall in V-a…
jpc-lip6 Mar 18, 2024
25b49fe
Revert commits eb1a05354 & 7100e3e86. Finally not useful.
jpc-lip6 Mar 18, 2024
79eb262
The pnrcheck rule generate 'chip_r', not 'chip'.
jpc-lip6 Mar 18, 2024
b696af0
In RoutingPlane::getTrackByPosition(), nullptr was wrongly returned.
jpc-lip6 Mar 18, 2024
c807245
In LefImport, in VH mode, be more selective for vertical creation.
jpc-lip6 Mar 19, 2024
e86a261
Add anabatic.gcellAspectRatio parameter for non-square GCells.
jpc-lip6 Mar 22, 2024
84545b9
Disable drawing of GCell's Id, reduce display cluttering.
jpc-lip6 Mar 22, 2024
4e8edbf
GCell now can compute cumulative density "all above" a given depth.
jpc-lip6 Mar 22, 2024
1bb097c
Add SegmentFsm::relaxHV() to break short range global Metal2 (V).
jpc-lip6 Mar 22, 2024
758b33c
Filtering of "on grid" terminal was too lax in LefImport.
jpc-lip6 Mar 22, 2024
1196a65
AutoSegment::canPivotUp() now takes AllAbove flag into account.
jpc-lip6 Mar 23, 2024
542f3bf
In LayerAssign::RpsInRow::slacken(), manage the VH gauge.
jpc-lip6 Mar 23, 2024
05e1cdc
Fixing clocktree stacked VIAs for deep VH gauges.
jpc-lip6 Mar 23, 2024
7b2db84
Increase threshold for VIA width separation in V power stripes.
jpc-lip6 Mar 24, 2024
d5f239f
In Etesian, new parameter to specify the buffer cell (differ from the…
jpc-lip6 Mar 24, 2024
7be57db
Add some more default X11 color by names...
jpc-lip6 Mar 24, 2024
af84518
Re-enable tie cells (latch-up) insertion in Etesian.
jpc-lip6 Mar 29, 2024
cb08af0
Diode must not replace ties in Etesian::Placement.
jpc-lip6 Mar 29, 2024
fb5d8cd
Enable jumpers in chip.CoreWire for 'StdCellLib'.
jpc-lip6 Mar 29, 2024
d54ce14
In Antennas, do not create the GContact early.
jpc-lip6 Apr 1, 2024
7046919
Various fixes in diode insertion.
jpc-lip6 Apr 1, 2024
aebc27d
More accurate GCell location in DiodeCluster::merge().
jpc-lip6 Apr 2, 2024
822748b
Support '#rrggbb' color naming in the Python wrapper.
jpc-lip6 Apr 8, 2024
c498bd6
Fix BigVia creation that may mistakenly have *no* cut.
jpc-lip6 Apr 8, 2024
659a529
Fix condition to create Vertical terms in LefImport::_pinCbk().
jpc-lip6 Apr 8, 2024
5821023
Add a dedicated ripup limit for non-prefs in Katana (temp. disabled).
jpc-lip6 Apr 8, 2024
7224f3b
Small typo in RoutingPlane::_getString().
jpc-lip6 Apr 8, 2024
d5aad44
In Track::_getRecord(), add the makers attribute.
jpc-lip6 Apr 8, 2024
bacdc09
Small changes in logging info.
jpc-lip6 Apr 8, 2024
9b95c70
In AutoHorizontal::_makeDogleg(), throw an error when called on non-p…
jpc-lip6 Apr 11, 2024
cadc823
In AutoSegment::_computeOptimal(), add a case for terminal connecteds.
jpc-lip6 Apr 11, 2024
2ce17f1
In NetBuilderHV::doRp_Access(), add a non-pref on small V.
jpc-lip6 Apr 11, 2024
03cc0ed
In NetConstraints/propagateConstraintsFromRp(), add a case for non-pr…
jpc-lip6 Apr 11, 2024
7231d3a
In LayerAssign, no need to perform aligned RP check in VH mode.
jpc-lip6 Apr 11, 2024
86b2514
In LefImport, various pin parse fixes.
jpc-lip6 Apr 11, 2024
89ebea0
More accurate RoutingPad component in Anabatic::Configuration.
jpc-lip6 Apr 11, 2024
337d004
In TrackMarker CTOR, fix weight computation for non-symbolic gauges.
jpc-lip6 Apr 11, 2024
deec5bc
In NegociateWidow::createTrackSegment(), better managment of non-pref.
jpc-lip6 Apr 11, 2024
dfabf03
Enable non-pref ripup count in KatanaEngine::getRipupLimit().
jpc-lip6 Apr 11, 2024
94e3db5
In Manipulator::minimize() & _insertInTrack(), manage non-pref.
jpc-lip6 Apr 11, 2024
c6edc07
Protect punctual in VH mode with a TrackSpan.
jpc-lip6 Apr 11, 2024
c91791c
Use allowed depth instead of raw depth in GCell densities computation.
jpc-lip6 Apr 15, 2024
0df9170
In moveUpNetTrunk(), don't check for contact for depth > 2.
jpc-lip6 Apr 15, 2024
4486b97
Added LightSteelBlue & OliveDrab3 to the prefined color set.
jpc-lip6 Apr 15, 2024
98362d3
Fix error in BigVia minimal width & height checking.
jpc-lip6 Apr 29, 2024
bc33544
In Sky130 harness, use wider cap power stripes to accomodate top VIAs.
jpc-lip6 Apr 29, 2024
5f2b719
In EtesianEngine::doHFNS(), check if the buffer is usable (avoid cras…
jpc-lip6 Apr 29, 2024
72a8d8f
Fix possible use of unitialized begin index in Track & SegmentFsm.
jpc-lip6 Apr 29, 2024
3bc006b
Fix bad duplication of EdgeCapacities inside Edge & allow customization.
jpc-lip6 Apr 29, 2024
52ea289
Change edge capacity computation in AnabaticEngine::computeEdgeCapaci…
jpc-lip6 Apr 29, 2024
37d092b
* Change: In Anabatic::Configuration::checkRoutingPadSize(), more acc…
jpc-lip6 Apr 29, 2024
f999c88
Use the new decreaseCapacity() for back annotating the global graph.
jpc-lip6 Apr 29, 2024
38b9ce0
Tune the VIA cost in case of non-square GCells.
jpc-lip6 Apr 29, 2024
42eb455
Disable non-pref in VH topologies, do not give improvement.
jpc-lip6 Apr 29, 2024
0d93687
Adjust breakpoint level in AntennaProtect.
jpc-lip6 May 3, 2024
394a5cd
Replace the "dogleg level" by a "break level" (Anabatic & Katana).
jpc-lip6 May 3, 2024
b156cdf
Cleaner and more coherent computation of GCell::hasFreeTrack().
jpc-lip6 May 4, 2024
e3e86a8
Simplify the code of GCell::updateDensity().
jpc-lip6 May 15, 2024
e0fc10e
Upgraded managment of AutoContact topology change (and various patches).
jpc-lip6 May 15, 2024
f74b51e
Allow and manage layer change for non-pref to pref TrackSegment.
jpc-lip6 May 15, 2024
4fd560f
Add support for the non-documented "-w" (no errors) flag of cougar.
jpc-lip6 May 15, 2024
b22765e
Read the error code from the script in designflow.PnR instead of succ…
jpc-lip6 May 15, 2024
c726e24
Fix bad management of the working library in AllianceFramework.
jpc-lip6 May 17, 2024
29cd7c9
Allow designflow.Graal & Dreal to be run without a cell argument.
jpc-lip6 May 18, 2024
07d7c33
Add support for GRAAL & DREAL config in Task.Where.
jpc-lip6 May 18, 2024
2b36c0c
Add S2R & DRC through KLayout in pnrcheck rules set.
jpc-lip6 May 18, 2024
6e477f4
Add default support for Sky130 NSXLIB2 support in designflow.
jpc-lip6 May 18, 2024
9bdc91a
In protectRoutingPadVH(), use top VIA side to compute the track footp…
jpc-lip6 May 27, 2024
4535e5f
In TrackSegment::revalidate(), fix non-pref span computation.
jpc-lip6 May 27, 2024
e072f8a
Skip TrackFixedSpan when checking for gaps in Tracks (false errors).
jpc-lip6 May 31, 2024
fbe252e
Force early init of AutoSegment. Non-pref fixes.
jpc-lip6 Jun 8, 2024
375563a
Add techno support for LSxLib + Sky130.
jpc-lip6 Jun 19, 2024
7ba7855
Fix in _do_2G_xM1_1PinM3() use HTee when in global E-W case.
jpc-lip6 Jun 26, 2024
e21d3d2
Missing dedents in debug mode in AnabaticEngine::unify().
jpc-lip6 Jun 26, 2024
fe1c304
Display GCell egdes capacities, by layers and aggregated.
jpc-lip6 Jun 26, 2024
b8b1e8a
AutoContact::canMoveUp() now manage/allow non-pref segments.
jpc-lip6 Jun 26, 2024
348962e
Perform specific management for segment below 1 pitch (S/T segment ca…
jpc-lip6 Jun 26, 2024
c08133b
In VH,1G1M1 build V+non-pref on terminals, gives more leeway.
jpc-lip6 Jun 26, 2024
fac44d5
In Track::expandFreeInterval(), ignore non-pref (too restrictive).
jpc-lip6 Jun 26, 2024
1e2c9eb
More fine grained choice in RpsInRow::slacken() in VH case.
jpc-lip6 Jun 26, 2024
1aba8fe
In DataNegociate::update(), in VH, allow a 10 pitch slack non-pref tr…
jpc-lip6 Jun 26, 2024
6b6a3b5
In Manipulator::moveUp(), allow non-pref to move up (ignore contact).
jpc-lip6 Jun 26, 2024
12706b9
In SegmentFsm, reset insert state after slackening. Change in _slacke…
jpc-lip6 Jun 26, 2024
a929fa6
Print yosys cell usage statistics.
jpc-lip6 Jun 26, 2024
5adf20b
Fix erroneous latch-up cell insertion when there is not enough free s…
jpc-lip6 Jun 28, 2024
3a934ac
Fixing an infinite loop of slackening of segments.
jpc-lip6 Jun 29, 2024
2401500
Fix Net::merge(), was iterating over Component collection while modif…
jpc-lip6 Jul 2, 2024
373e6a4
Check for overlaps inside slices from Coloquinte placement, and stop …
jpc-lip6 Jul 2, 2024
2b9c003
Rewrite the punctual terminal & caged terminal management using a Tra…
jpc-lip6 Jul 13, 2024
183e12c
Added support for GCell config 1G+2M1+1PinM3 in NetBuilderHV.
jpc-lip6 Jul 18, 2024
0f5c6ce
Discard $print subckt in Blif parser (new feature from Yosys 0.42).
jpc-lip6 Jul 18, 2024
0727838
Fix in NetBuilderHV::*_xM1_1PinX(), loop over M1 only, not the Pin.
jpc-lip6 Jul 19, 2024
34df142
Adjust management of segments that are both reduceds & fixed.
jpc-lip6 Jul 20, 2024
f1a1da9
In NetBuilderHV::_do_xG_1PinM2(), do fix segments on the pin. Too rigid.
jpc-lip6 Jul 20, 2024
942b7fa
Support for accurate position detection of shorts in Tramontana (text).
jpc-lip6 Jul 30, 2024
b2951ca
Various fixes and enhancement of the GUI.
jpc-lip6 Aug 8, 2024
7aff71c
Implemtation of the short circuit display widget in Tramontana.
jpc-lip6 Aug 8, 2024
faf67b0
Dodo support added in technos for Phenitec 0.6um.
jpc-lip6 Aug 10, 2024
362ec1d
Added Open Circuit display widget support in Tramontana.
jpc-lip6 Aug 10, 2024
4fd34c5
Add optional call to the extract+LVX after the PnR in the block builder.
jpc-lip6 Aug 10, 2024
dd15ca2
Fix position issue when displaying Reference markers.
jpc-lip6 Aug 10, 2024
c11ebbb
Tramontana update to support cut from real technologies (not macro ge…
jpc-lip6 Aug 11, 2024
0cf9657
Supply VIA connexity in GF180MCU for the extractor.
jpc-lip6 Aug 11, 2024
e070ce7
untilities to amplify signal in a netlist using bufferization or cell…
rchotin Aug 16, 2024
f5046be
add documentation
rchotin Aug 16, 2024
d6f85c8
Add comments
rchotin Aug 20, 2024
8dd3d25
Functions to transform a netlist to an adjacence matrix for graphs' m…
rchotin Aug 21, 2024
66ea970
Update README.rst
rchotin Aug 16, 2024
f9b91be
use liberty file to get the bigger cell
rchotin Sep 4, 2024
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change amplification technic, now based on a threshold on the load of…
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get buffer from liberty file
rchotin Sep 10, 2024
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get liberty file from Yosys rule
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merge to rebuild detached HEAD
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Merge remote-tracking branch 'origin/main' into WIP_rchotin
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improve cells' categorization to be more efficient and add generaliza…
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correct typos
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1 change: 1 addition & 0 deletions .pdm-python
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/dsk/l1/misc/roselyne/coriolis/src/coriolis/.venv/bin/python
135 changes: 135 additions & 0 deletions cumulus/src/plugins/netlist/README.rst
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.. -*- Mode: rst -*-

.. |Python wheel builds| image:: https://github.com/lip6/coriolis/actions/workflows/wheels.yml/badge.svg
:target: https://github.com/lip6/coriolis/actions/workflows/wheels.yml

.. image:: example.svg
:alt: Netlist example
:align: center

======================================
Utilities for netlist manipulation
======================================

Introduction
==============
This tutorial introduces all the notions needed to manipulate netlist throw |Coriolis| with Python. It can be useful for optimization technics which need to automatically modify the netlist.

You can refer to the Hurricane+python tutorial for more advance concepts with the |Hurricane| database

Generalities
==============
As shown with figure, a design in Coriolis is refered as a *cell*. It is composed with *instances* (dot lines), *nets* (in blue) and *plugs* (black squares). Each instance refers to a *model* (`MasterCell`) which, in this example, are `OR2` and `AND2`. A model is itself a cell with instances, nets and plugs. Each component of a design has a name which can be obtained by using the method `getName()`. Plugs, nets and instances are collections which can be obtained by the methods `getPlugs()`, `getNets()`, `getInstances()` respectively.

Using Coriolis
=================
Setting up the environment
----------------------------
Coriolis can be used throw Python3. First of all, the adequate environment has to be setup with the following command:
``crlenv.py -- shell``
Where ``shell`` is the shell used by the user (bash, zsh...):

Importing the modules
-----------------------
To use Coriolis with Python, including the Coriolis's modules is mandatory:
``from coriolis import CRL``

To make a design, we need to used a dedicated techno. The configuration of a design flow for a dedicated techno is done in the Python module ``coriolis.designflow.technos`` in which we need to import the techno. As example for SkyWater 130nm the import is:
::
from coriolis.designflow.technos import setupSky130_c4m

And after we use the ``setupSky130_c4m`` python function to run the configuration:
::
setupSky130_c4m( '../../..', '../../../pdkmaster/C4M.Sky130' )

Beginning the session
-----------------------
All the flow in Coriolis is running in a Coriolis session which has to be open:
::
af = AllianceFramework.get()
UpdateSession.open()

Netlist manipulation
======================
First of all the netlist (in blif format) have to be loaded with the following method:
::
cell = CRL.Blif.load("example")

Navigation
-----------
To navigate through the different components of the netlist (`cell`), the different following instructions can be used:
- for nets: ``for net in cell.getNets():``
- for instances: ``for inst in cell.getInstances():``
- for plugs: ``for plug in cell.getPlugs():``

Enter the hierarchy
---------------------
Each instance can also be considered as a cell and follow the same navigation capacities. For that, it is necessary to refer to the model of is instance and access it by using the method ``getMasterCell()`` on the instance. For example, considering Figure |example.svg|, accessing to the nets and instances inside ``inst1`` can be done by the following code:
::
cell1 = inst1.getMasterCell()
for net in cell1.getNets():

Components' properties
------------------------
Each component in the Hurricane database, is a class and has specific properties. The Hurricane's documentation gives all the details.

Net
^^^^^
Nets have ``Direction`` and ``Type`` which are both Hurricane's classes. A direction can be ``IN``, ``OUT``, ``TRISTATE`` etc. A type can be ``LOGICAL``, ``CLOCK`` etc. Lot of method give access to the properties (``getName()``, ``getDirection()``, etc.), test them (``isLogical()``, ``isClock()``, etc.) or set them (``setType()``, ``setExternal()``, etc.)

Instance
^^^^^^^^^^
The main methods of this class concerning netlist manipulation are ``getMasterCell()`` and ``getPlugs()``

Plug
^^^^^^
The method ``getInstance()`` allows to get the instance of the plug and ``getMasterNet()`` to get the net connected to this plug.

Examples
----------

WARNING Hurricane collections are not mutable, so change values outside iterator !!
=> the next sections have to be modify in consequence

Changing a cell
^^^^^^^^^^^^^^^^^
For example a cell from which one output drives more than ``MAX`` cells can be amplified, that mean change a ``_x2`` cell by a ``_x4`` one (i.e: ``a2_x2`` is changed by ``a2_x4`` which is amplified by 2):
::
for net in cell.getNets():
if size(net.getPlugs()) > MAX:
for plug in net.getPlugs():
if plug.getMasterNet().getDirection() == Net.Direction.OUT:
inst = plug.getInstance()
# replace _x1 or_x2 by _x4 in cell's name
cell_name = inst.getMasterCell().getName()[:-1]
cell_name += '4'
# get the corresponding cell (_x4)
new_cell = af.getCell(cell_name, Catalog.State.Views)
# change the cell
inst.setMasterCell(new_cell)

Adding a cell
^^^^^^^^^^^^^^^
For example, a buffer can be inserted to amplify a net which drives more than ``MAX`` cells:
::
for net in cell.getNets():
if size(net.getPlugs()) > MAX:
# get the buffer
buf = af.getCell('buf_x2', Catalog.State.Views)
# create its corresponding instance
buf_i = Instance.create(cell, 'buf_%s' %(net.getName()), buf)
# insert this instance to the net, i.e. cut the net into net and net_b (to be created)
buf_i.getPlug(buf.getNet('i')).setNet(net)
net_b = Net.create(cell, "%s_b" %(net.getName()))
buf_i.getPlug(buf.getNet('q')).setNet(net_b)

A complete example
====================
The ``amplify.py`` code is a concrete example of all the things described in the previous sections. It proposes 2 fonctions that can be applied to a given circuit:

- `amplify_net` that changes the cells that drive a given net
- `bufferize` that bufferizes a given net




122 changes: 122 additions & 0 deletions cumulus/src/plugins/netlist/adjacence.py
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import sys, getopt

import coriolis.technos.symbolic.cmos
from coriolis.Hurricane import *
from coriolis.CRL import *

af = AllianceFramework.get()
UpdateSession.open()

# transform a given netlist to its corresponding adjacence matrix where:
# - cell is the cell corresponding to the netlist
# - tf is a boolean indicating the adjacence matrix's direction, if True (default)
# + lines are the target (to)
# + and columns the source (from)
# the opposite if False
# return:
# - the list of the nets with their index in the adjacence matrix
# - the adjacence matrix
def cell2adj(cell, tf = True):
dnets = {}
mat =[]
n = 0
# Matrix initialization
for n1 in cell.getNets():
if n1.getType() == Net.Type.LOGICAL:
mat.append([])
dnets[n1.getName()] = [n,"Input"]
n += 1
for n2 in cell.getNets():
if n2.getType() == Net.Type.LOGICAL:
mat[-1].append(0)
# adjacence's matrix filling
for ins in cell.getInstances():
target = []
source = []
for plug in ins.getPlugs():
net = plug.getMasterNet()
if net.getType() == Net.Type.LOGICAL:
if net.getDirection() == Net.Direction.IN:
source.append(dnets[plug.getNet().getName()][0])
elif net.getDirection() == Net.Direction.OUT:
target.append(dnets[plug.getNet().getName()][0])
dnets[plug.getNet().getName()][1] = ins.getMasterCell().getName()
for i in range(len(source)):
for j in range(len(target)):
if tf:
mat[target[j]][source[i]] = 1
else:
mat[source[i]][target[j]] = 1
#print(dnets)
#for i in range(len(dnets)):
# print(mat[i])
return (dnets,mat)

# get the adjassors' list of each net in the adjacence matrix mat:
# - if the adjacence matrix is to_from (tf = True) it is a predecessors list
# - if the adjacence matrix is from_to (tf = False) it is a successors list
# return a tuple with:
# - the index of the net in the adjacence matrix
# - the list of the corresponding adjassors
def adjassors(mat):
res = []
l = -1
for line in mat:
l += 1
res.append((l,[]))
for i in range(len(line)):
if line[i] == 1:
res[-1][1].append(i)
if res[-1][1] == []:
res.pop()
#for i in range(len(res)):
# print(res[i])
return res

# write the result in a json file where:
# - fname is the name of the output file
# - nets is the list of the nets and their index
# - mat is the adjacence matrix
# - adj is the list of adjassors
def write_json(fname, nets, mat, adj):
fres = open(fname+'.json', 'wt')
fres.write("{\n")
fres.write(' "Nets" : ' + str(nets))
#fres.write(',\n "Type" : ' + str(ltypes))
fres.write(',\n "Mat" : ' + str(mat))
fres.write(',\n "Adj" : ' + str(adj))
fres.write('\n}')
fres.close()

def usage():
print("python blif2graph.py [option]")
print("Gaphs' utilities on a netlist")
print("-b (blif): the name of the blif netlist")
print("-p (pred): list of predecessors of each net")
print("-s (suc): list of sucessors of each net")
print("-h (help): this message")

def main(argv):
try:
opts, args = getopt.getopt(sys.argv[1:], "hb:ps", ["help", "blif=", "pred", "suc"])
except getopt.GetoptError as err:
print(err)
usage()
sys.exit(2)

for o, a in opts:
if o == '-b':
cell = Blif.load(a)
fname = a
if o == '-p':
tf = True
if o == "-s":
tf = False
if o == "-h":
usage()
(nets,mat) = cell2adj(cell,tf)
adj = adjassors(mat)
write_json(fname,nets,mat,adj)

if __name__ == "__main__":
main(sys.argv)
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