Add saturating add/sub intrinsics to RISC-V vector backend#9185
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rajeshgangam wants to merge 1 commit into
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Add saturating add/sub intrinsics to RISC-V vector backend#9185rajeshgangam wants to merge 1 commit into
rajeshgangam wants to merge 1 commit into
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Map Halide's saturating_add and saturating_sub operations to RVV instructions vsadd/vsaddu and vssub/vssubu respectively. These are commonly used in image processing for clamped arithmetic and were missing from the RISC-V intrinsic tables. Fixes halide#9184
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Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #9185 +/- ##
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Summary
saturating_addto RVVvsadd.vv/vsaddu.vvinstructionssaturating_subto RVVvssub.vv/vssubu.vvinstructionssimd_op_check_riscvtest casesThese are the most commonly used missing operations for image processing workloads (clamped arithmetic). They fit the existing
RISCVIntrinsictable pattern with zero infrastructure changes — just 4 new table entries per signedness.Fixes #9184
Test plan
simd_op_check_riscvchecks forvsadd.vv,vsaddu.vv,vssub.vv,vssubu.vvinstruction patterns in generated assemblyCo-authored-by: Claude Opus 4.6 noreply@anthropic.com