Vertigo scheduler FPGA implementation

This repository provides the FPGA implementation of the scheduler that supports the functionalities that Vertigo requires. Vertigo's deflection process might require extracting a packet from the tail of the queue. Accordingly, we modified PIEO's Code to support this without requiring more cycles than PIEO's supported functionalities. We installed Quartus Prime 20.1 Lite and Modelsim softwares on Windows 10 to compile, synthesize, and simulate our code. To use this code you should:

• Clone this repository
• Compile, Synthesize, and simulate the project

Cloning the repository

We assume that you have the software, i.e., Git Bash, required for running the command to clone the repository. If you don't, you can simply use Github's GUI to clone the repository. To clone this repository in a directory, run git bash and use the following command: git clone https://github.com/foundational-networks/vertigo_scheduler_fpga_implementation.git.

Creating the project and importing the Verilog files

The Intel community provides a guide on how to include the Verilog files in a project and how to synthesize and simulate a project. You should set "vertigo.sv" as Top-Level Entity while compiling the modules. To test the modules, you should create a testbench file to initialize and change the inputs of the scheduler over time. This tutorial provides good introductions on how to create testbench files for a project.