VPR placer port

.gitignore

@@ -25,6 +25,7 @@ build/
 /Testing/*
 CTestTestfile.cmake
 install_manifest.txt
+*.gdb_history
 /bbasm
 /ImportExecutables.cmake
 *-coverage/

CMakeLists.txt

@@ -171,7 +171,7 @@ if (BUILD_PYTHON)
     endif ()
 endif()
 
-include_directories(common/ json/ ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS})
+include_directories(common/ json/ ${Boost_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS} .)
 aux_source_directory(common/ COMMON_SRC_FILES)
 aux_source_directory(json/ JSON_PARSER_FILES)
 set(COMMON_FILES ${COMMON_SRC_FILES} ${JSON_PARSER_FILES})

README.md

@@ -1,6 +1,8 @@
 nextpnr -- a portable FPGA place and route tool
 ===============================================
 
+### *This `vpr_place` branch contains code adapted from the [Verilog-To-Routing](https://verilogtorouting.org/) project.*
+
 nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route
 tool.
 

common/command.cc

@@ -106,6 +106,8 @@ po::options_description CommandHandler::getGeneralOptions()
     general.add_options()("no-tmdriv", "disable timing-driven placement");
     general.add_options()("save", po::value<std::string>(), "project file to write");
     general.add_options()("load", po::value<std::string>(), "project file to read");
+
+    general.add_options()("vpr_place", "use VPR placer");
     return general;
 }
 
@@ -207,7 +209,10 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
         ctx->check();
         print_utilisation(ctx.get());
         if (!vm.count("pack-only")) {
-            if (!ctx->place() && !ctx->force)
+            if (vm.count("vpr_place")) {
+		if (!ctx->place_vpr() && !ctx->force)
+		    log_error("Placing design failed.\n");
+	    } else if (!ctx->place() && !ctx->force)
                 log_error("Placing design failed.\n");
             ctx->check();
             if (!ctx->route() && !ctx->force)

common/placer1.cc

@@ -171,6 +171,8 @@ class SAPlacer
         double avg_metric = curr_metric;
         temp = 10000;
 
+        tot_move = tot_accept = 0;
+
         // Main simulated annealing loop
         for (int iter = 1;; iter++) {
             n_move = n_accept = 0;
@@ -267,9 +269,15 @@ class SAPlacer
                 curr_metric += wl;
             }
 
+            tot_move += n_move;
+            tot_accept += n_accept;
+
             // Let the UI show visualization updates.
             ctx->yield();
         }
+
+        log_info("  swaps attempted: %d acceptance rate: %.3f\n", tot_move, double(tot_accept)/double(tot_move));
+
         // Final post-pacement validitiy check
         ctx->yield();
         for (auto bel : ctx->getBels()) {
@@ -476,6 +484,7 @@ class SAPlacer
     float temp = 1000;
     bool improved = false;
     int n_move, n_accept;
+    int tot_move, tot_accept;
     int diameter = 35, max_x = 1, max_y = 1;
     std::unordered_map<IdString, int> bel_types;
     std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;

common/placer1.h

@@ -16,8 +16,8 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
-#ifndef PLACE_H
-#define PLACE_H
+#ifndef PLACER1_H
+#define PLACER1_H
 
 #include "nextpnr.h"
 #include "settings.h"
@@ -34,4 +34,4 @@ extern bool placer1(Context *ctx, Placer1Cfg cfg);
 
 NEXTPNR_NAMESPACE_END
 
-#endif // PLACE_H
+#endif // PLACER1_H