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1. RISC-V RISC-V Public

   Design and implementation of an advanced 64-bit RISC-V processor in SystemVerilog, progressing from a pipelined in-order core toward an out-of-order architecture with dynamic scheduling, branch pre…

   SystemVerilog 1

2. CXL-Memory-Fabric CXL-Memory-Fabric Public

   SystemVerilog-based CXL-inspired disaggregated memory fabric for multi-host shared memory access, featuring routing, arbitration, flow control, CRC, retry, verification, FPGA prototyping, and PPA a…