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Fix GRBM_STATUS bit positions for RDNA (GFX10+) GPUs#181

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mgajda:fix-initbits-rdna
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Fix GRBM_STATUS bit positions for RDNA (GFX10+) GPUs#181
mgajda wants to merge 1 commit into
clbr:masterfrom
mgajda:fix-initbits-rdna

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@mgajda

@mgajda mgajda commented Apr 14, 2026

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Summary

Independent of #178 — can be merged separately.

On RDNA (GFX10+), the GRBM_STATUS register layout changed from GCN:

Field GCN bit(s) RDNA bit Status
Event Engine bit 10 reserved zeroed
VGT bits 16-17 replaced by GE (bit 21) remapped
Seq. Instr. Cache bit 21 now GE_BUSY zeroed
TA, SX, SPI, SC, PA, DB, CB, GUI unchanged unchanged OK

The VGT field now reads GE_BUSY (Geometry Engine, bit 21) which is the functional successor to VGT on RDNA.

Test plan

  • On RDNA card: VGT/GE shows plausible utilization (not stuck at 0% or 100%)
  • On GCN card: no change in behavior
  • EE and SH show 0% on RDNA (correct — these blocks don't exist)

On RDNA, the GRBM_STATUS register layout changed:
- Bit 10 (Event Engine): reserved/undefined
- Bits 16-17 (VGT): replaced by Geometry Engine at bit 21
- Bit 21 (Sequencer Instruction Cache): now Geometry Engine

Repurpose the VGT field to read GE_BUSY (bit 21) and label it
"Geometry Engine" in the UI and dump output. Hide Event Engine
and Sequencer Instruction Cache on RDNA since those blocks no
longer exist. Other bits (TA, SX, SPI, SC, PA, DB, CB, GUI)
are unchanged across all generations.
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