The compiler for AI silicon. PyTorch model in. Hardware-ready specification out.
Quickstart · Docs · Roadmap
┌──────────────┐ ┌─────────────────┐ ┌───────────────────┐
│ │ │ │ │ Synthesizable │
│ PyTorch │───▶│ ASICify │───▶│ Verilog │
│ checkpoint │ │ compiler │ │ + Cocotb test │
│ │ │ │ │ + Area / cost │
└──────────────┘ └─────────────────┘ │ + FPGA bitstream │
└───────────────────┘
ASICify takes a trained neural network and emits everything you need to put it on silicon: aggressively compressed weights, synthesizable Verilog with those weights hardwired as ROM constants, area / throughput / cost / energy estimates across eleven hardware targets, an FPGA reference implementation, and a verified Cocotb testbench.
Custom AI silicon costs $5–30M per tape-out and takes 6–18 months. The fabrication isn't the bottleneck; the model-to-hardware translation is. Every chip company and edge-AI deployer currently does that translation by hand, with expensive specialist engineers, the same way they did it ten years ago.
Cadence and Synopsys built EDA for general-purpose chips. ASICify is built for one thing: turning a trained inference network into a fixed-function accelerator.
Open the playground in your browser. Drag the sparsity slider, switch between INT4 and ternary, swap targets between TSMC 28nm and Lattice ECP5. Watch silicon area, cost per chip, and throughput recompute in real time. Every number is from a published cost model: no fake gauges, no mock data.
pnpm --filter @asicify/web dev
# → http://localhost:3001/playgroundThere is no PyPI package yet. The CLI runs from a clone:
git clone https://github.com/claynicholson/asicify
cd asicify/apps/worker
uv sync --extra hosted # `hosted` pulls in transformers for HF models
uv run asicify compile gpt2 \
--quantization int4 \
--sparsity structured_2_4 \
--target tsmc28,ecp5Sample output:
-> Loading model: gpt2
Parsed 124,439,808 params
-> Applying sparsity: structured_2_4
-> Quantizing to int4
-> Rendering RTL to ./build
-> Estimate tsmc28 area=8.2 mm² cost@100K=$4.10
-> Estimate ecp5 ...
Done. Output: ./build
The output directory contains top.v, per-layer modules, hardwired
weights, a Cocotb testbench, a bit-exact Python reference, a Makefile,
and synthesis scripts for Yosys, nextpnr, and Vivado. cd in and run
make sim or make synth-yosys.
The API and worker are implemented but not yet deployed publicly. To run them on your own machine, see Quickstart → REST API. You get the project lifecycle, WebSocket progress streaming, and presigned artifact downloads.
| Capability | Status |
|---|---|
| Live client-side estimator | ✓ Real math, real numbers |
| Markdown documentation site | ✓ Auto-rendered from /docs |
| Landing, playground, docs, about | ✓ Functional |
| FastAPI backend (auth + CRUD + queue + WS) | ✓ Endpoints wired |
| Postgres schema + Alembic migrations | ✓ Initial migration shipped |
| Worker pipeline (parse → quantize → … → validate) | ✓ Real kernels, end to end |
Model parsing (torch.fx-style walk) |
✓ Linear, LayerNorm, Embedding, HF attention auto-detection |
| Quantization | ✓ FP16 / INT8 / INT4 / ternary / binary, bit-exact |
| Sparsity + decomposition | ✓ 2:4, 4:8, block, unstructured · SVD, Monarch, butterfly |
| Hardware estimator (server-side) | ✓ Cell library data for 11 targets |
| RTL generator (16 Jinja2 templates) | ✓ Top + linear + attention + layernorm + KV cache + testbench + synthesis scripts |
| Multi-precision multiplier strategies | ✓ binary / ternary / int4 CSD / int8 Booth / fp16 LUT |
| WebGPU in-browser inference comparison | ✓ DistilGPT-2, WASM fallback |
| PDF report generation | ✓ Via /api/report |
| Public deployment (API + worker) | ○ Files committed, not pushed |
| Stripe billing | ○ Not started |
See docs/roadmap.md for the authoritative list of what's shipped, partial, and pending.
asicify/
├── apps/
│ ├── web/ Next.js 15 frontend
│ │ Landing · live playground · markdown docs · about
│ │
│ ├── api/ FastAPI backend
│ │ Clerk JWT auth · project CRUD · Redis job queue · WebSocket progress
│ │
│ └── worker/ Python worker
│ ├── pipeline/ parse · quantize · sparsity · decompose · validate
│ ├── rtl/ Jinja2 → Verilog package
│ └── estimator/ area · throughput · cost · per-target cell library
│
├── packages/
│ └── shared/ TypeScript types (mirrored as Pydantic + Python dataclasses)
│
├── infra/ docker-compose: Postgres · Redis · MinIO (R2 stand-in)
│
└── docs/ User docs (rendered at /docs/*)
└── internals/ Contributor docs (rendered at /docs/internals/*)
No databases, no Python, no GPU. The live estimator runs in your browser.
git clone https://github.com/claynicholson/asicify
cd asicify
pnpm install
pnpm --filter @asicify/web dev
# → http://localhost:3001Adds the API, worker, Postgres, Redis, and an S3-compatible object store.
# 1. Install everything
pnpm install
cd apps/api && uv sync && cd ../..
cd apps/worker && uv sync && cd ../..
# 2. Start infrastructure
docker compose -f infra/docker-compose.yml up -d
# 3. Run database migrations
cd apps/api && uv run alembic upgrade head && cd ../..
# 4. Boot all three apps
pnpm devYou'll get:
| Service | URL |
|---|---|
| Web | http://localhost:3001 |
| API | http://localhost:8000 |
| API docs | http://localhost:8000/docs |
| MinIO console | http://localhost:9001 |
Eleven targets across three categories:
| Category | Target |
|---|---|
| ASIC | SkyWater 130 · GF22FDX · TSMC 28nm · TSMC 16nm · TSMC 7nm |
| FPGA | Lattice ECP5 · Lattice CrossLink-NX · Xilinx Artix-7 · Xilinx Kria K26 |
| Shuttle | TinyTapeout (sky130) · Efabless chipIgnite (sky130) |
Each target ships with cell-library data: ROM bit area, SRAM bit area, INT8 multiplier area, max clock frequency, energy per MAC, wafer cost, defect density. All numbers cite published academic surveys or foundry data sheets and carry ±20–40% confidence bands.
See docs/methodology.md for the full cost-model
derivation.
Five quantization modes, four sparsity patterns, three decompositions, fully composable.
Quantization FP16 · INT8 · INT4 · Ternary · Binary
Sparsity none · 2:4 · 4:8 · block 16×16 · unstructured
Decomposition none · Low-rank · Monarch · Butterfly
Stacked together (ternary at 1.6 bits/weight, plus sparsity, plus decomposition) the effective bits per weight drop below 1.
Each compression method maps to a specific multiplier strategy in the generated RTL:
| Quantization | Multiplier strategy | Approx LUTs/MAC |
|---|---|---|
| Binary | XNOR + popcount | ~1 |
| Ternary | Sign-flip mux + zero-out | ~3 |
| INT4 | CSD shift-add network | ≤ 1 add |
| INT8 | Booth multiplier | ~10 |
| FP16 | Per-multiplier ROM-LUT | small ROM |
Weights become localparam constants in weights.vh. The synthesis tool
folds them directly into the multiplier inputs; for binary and ternary
this collapses entirely into XOR/AND networks, with no real multipliers
on die.
┌────────────────────────────────────────────────┐
│ User (browser) │
└───────────────────────┬────────────────────────┘
│ HTTPS / WSS
┌───────────────────────▼────────────────────────┐
│ Next.js frontend (Vercel) │
│ App Router · server components · estimator │
└───────────────────────┬────────────────────────┘
│ REST / WebSocket
┌───────────────────────▼────────────────────────┐
│ FastAPI backend (Fly.io / Railway) │
│ Clerk JWT auth · job orchestration │
└───────┬────────────────┬────────────────┬──────┘
│ │ │
▼ ▼ ▼
┌─────────────┐ ┌─────────────┐ ┌─────────────┐
│ PostgreSQL │ │ Redis │ │ Modal Labs │
│ (Neon) │ │ (Upstash) │ │ GPU workers │
└─────────────┘ └─────────────┘ └──────┬──────┘
│
▼
┌─────────────┐
│Cloudflare R2│
└─────────────┘
The compiler core (apps/worker/worker/{pipeline,rtl,estimator}/) runs
without the API, the database, Redis, or any auth. The CLI calls it
directly. The hosted product layers convenience on top.
See docs/architecture.md for component
responsibilities and docs/internals/data-flow.md
for end-to-end traces.
| Layer | Choice |
|---|---|
| Frontend | Next.js 15 · React 19 · TypeScript strict · Tailwind v4 · Recharts |
| Backend | FastAPI · Pydantic v2 · SQLAlchemy 2.0 async · Alembic |
| Worker | PyTorch · Transformers · Jinja2 · structlog |
| Database | PostgreSQL (Neon) |
| Queue | Redis lists + pub/sub (Upstash) |
| Storage | Cloudflare R2 (S3-compatible; MinIO locally) |
| Auth | Clerk |
| Compute | Modal Labs |
| Build | Turborepo · pnpm · uv |
| Verification | Cocotb · Verilator |
| Synthesis | Yosys · nextpnr · Vivado |
Multi-target backend. One tool, every target. The same source model emits SkyWater 130 RTL, TSMC 28nm RTL, ECP5 bitstreams, TinyTapeout shuttles. Compare them in one dashboard.
Open-source core. MIT-licensed. The compression pipeline and RTL generator are on GitHub. No NDAs, no per-tape-out licensing. The hosted product is convenience and compute.
Hardware-software co-design. Sub-1-bit effective representation via ternary + sparsity + decomposition. Monarch and butterfly matrix factorization built into the pipeline, with the structured zeros carried all the way into synthesis.
Design space exploration. Pull a slider in the playground, watch the chip change. Cached estimates update in under a millisecond.
For users:
- docs/quickstart.md: compile your first model
- docs/architecture.md: system overview
- docs/methodology.md: cost model derivation
- docs/rtl-generation.md: Verilog templates and multiplier strategies
- docs/roadmap.md: phase plan
For contributors:
- docs/codebase.md: codebase tour. Start here.
- docs/internals/web.md: frontend
- docs/internals/api.md: backend
- docs/internals/worker.md: pipeline + RTL gen + estimator
- docs/internals/data-flow.md: end-to-end traces
- docs/internals/extending.md: recipes to add a target, a precision, a primitive
- docs/internals/conventions.md: code style
- docs/internals/glossary.md: ML, silicon, EDA terminology
Pre-1.0. The compiler spine — model in → compressed model → quality validation → RTL → cost estimate — works end to end and is verified in CI on every push. See docs/roadmap.md for the phase plan and CHANGELOG.md for what landed.
PRs welcome. The high-leverage areas:
- Adding hardware targets (cell library data with citations)
- New compression methods (FP4, FP8 E4M3, MXFP formats)
- New layer kinds (Mamba blocks, MoE routers, diffusion primitives)
- Refining cost-model parameters with foundry data sheets
See CONTRIBUTING.md and docs/internals/extending.md for recipes.
MIT. The hosted version at asicify.com layers convenience and compute over this open-source core. Premium hardware targets (TSMC leading-edge nodes, Samsung) require commercial agreements with the foundries; the open core supports SkyWater 130, GF22FDX, ECP5, Artix-7 directly.
- Tri Dao and the HazyResearch team for Monarch matrices
- Matt Venn for TinyTapeout
- SkyWater and Efabless for the open PDK movement
- The Yosys + nextpnr team for the open synthesis flow
- Cocotb for making hardware verification feel like Python
ASIC|fy · Built for the AI silicon era · MIT licensed