GitHub - aut-ca-lab/lab7

Name		Name	Last commit message	Last commit date
Pre_report		Pre_report
_xmsgs		_xmsgs
iseconfig		iseconfig
isim		isim
screenshots		screenshots
xst/work		xst/work
CAM.cmd_log		CAM.cmd_log
CAM.lso		CAM.lso
CAM.ngc		CAM.ngc
CAM.ngr		CAM.ngr
CAM.prj		CAM.prj
CAM.stx		CAM.stx
CAM.syr		CAM.syr
CAM.vhd		CAM.vhd
CAM.xst		CAM.xst
CAM_envsettings.html		CAM_envsettings.html
CAM_summary.html		CAM_summary.html
CAM_xst.xrpt		CAM_xst.xrpt
LAB_7.gise		LAB_7.gise
LAB_7.xise		LAB_7.xise
RAM.cmd_log		RAM.cmd_log
RAM.lso		RAM.lso
RAM.ngc		RAM.ngc
RAM.ngr		RAM.ngr
RAM.prj		RAM.prj
RAM.stx		RAM.stx
RAM.syr		RAM.syr
RAM.vhd		RAM.vhd
RAM.xst		RAM.xst
RAM_envsettings.html		RAM_envsettings.html
RAM_summary.html		RAM_summary.html
RAM_xst.xrpt		RAM_xst.xrpt
ROM.cmd_log		ROM.cmd_log
ROM.lso		ROM.lso
ROM.ngc		ROM.ngc
ROM.ngr		ROM.ngr
ROM.prj		ROM.prj
ROM.stx		ROM.stx
ROM.syr		ROM.syr
ROM.vhd		ROM.vhd
ROM.xst		ROM.xst
ROM_envsettings.html		ROM_envsettings.html
ROM_summary.html		ROM_summary.html
ROM_xst.xrpt		ROM_xst.xrpt
dual_port_ram.cmd_log		dual_port_ram.cmd_log
dual_port_ram.lso		dual_port_ram.lso
dual_port_ram.ngc		dual_port_ram.ngc
dual_port_ram.ngr		dual_port_ram.ngr
dual_port_ram.prj		dual_port_ram.prj
dual_port_ram.stx		dual_port_ram.stx
dual_port_ram.syr		dual_port_ram.syr
dual_port_ram.vhd		dual_port_ram.vhd
dual_port_ram.xst		dual_port_ram.xst
dual_port_ram_envsettings.html		dual_port_ram_envsettings.html
dual_port_ram_summary.html		dual_port_ram_summary.html
dual_port_ram_xst.xrpt		dual_port_ram_xst.xrpt
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
pepExtractor.prj		pepExtractor.prj
uut_ROM.vhd		uut_ROM.vhd
uut_ROM_isim_beh.exe		uut_ROM_isim_beh.exe
uut_ROM_stx_beh.prj		uut_ROM_stx_beh.prj
uut_cam.vhd		uut_cam.vhd
uut_cam_beh.prj		uut_cam_beh.prj
uut_cam_isim_beh.exe		uut_cam_isim_beh.exe
uut_cam_isim_beh.wdb		uut_cam_isim_beh.wdb
uut_cam_isim_beh1.wdb		uut_cam_isim_beh1.wdb
uut_cam_stx_beh.prj		uut_cam_stx_beh.prj
uut_dual_port_ram.vhd		uut_dual_port_ram.vhd
uut_dual_port_ram_beh.prj		uut_dual_port_ram_beh.prj
uut_dual_port_ram_isim_beh.exe		uut_dual_port_ram_isim_beh.exe
uut_dual_port_ram_isim_beh.wdb		uut_dual_port_ram_isim_beh.wdb
uut_dual_port_ram_stx_beh.prj		uut_dual_port_ram_stx_beh.prj
uut_ram.vhd		uut_ram.vhd
uut_ram_beh.prj		uut_ram_beh.prj
uut_ram_isim_beh.exe		uut_ram_isim_beh.exe
uut_ram_isim_beh.wdb		uut_ram_isim_beh.wdb
uut_ram_stx_beh.prj		uut_ram_stx_beh.prj
uut_single_port_ram.vhd		uut_single_port_ram.vhd
uut_single_port_ram_beh.prj		uut_single_port_ram_beh.prj
uut_single_port_ram_isim_beh.exe		uut_single_port_ram_isim_beh.exe
uut_single_port_ram_isim_beh.wdb		uut_single_port_ram_isim_beh.wdb
uut_single_port_ram_isim_beh1.wdb		uut_single_port_ram_isim_beh1.wdb
uut_single_port_ram_isim_beh2.wdb		uut_single_port_ram_isim_beh2.wdb
uut_single_port_ram_stx_beh.prj		uut_single_port_ram_stx_beh.prj
webtalk_pn.xml		webtalk_pn.xml
xilinxsim.ini		xilinxsim.ini

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