psoc-edge: Add ADC support - #197
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Nice ! some minor things to check before merge
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Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
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Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Apply reviewed ADC fixes and cleanup. - Use mapped sar_block in ADC setup and read flow. - Reload SAR config only on channel config changes. - Compute read_uv from raw 12-bit data using BSP VDDA. - Fix read_uv overflow with 64-bit intermediate arithmetic. - Remove unused ADC block capability macro generation. - Include genhdr/pins_af.h explicitly and drop broad genhdr include path. - Fix ruff formatting in make-pins.py. Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
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Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
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Signed-off-by: AkshayChandra-IFX <akshaychandra.nagzarkar@infineon.com>
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Summary
Adds machine.ADC and machine.ADCBlock support for the PSoC Edge port. The implementation uses the PSoC Edge SAR ADC peripheral via the cy_autanalog / cy_autanalog_sar HAL drivers. BSP peripheral config, pin alternate-function CSV, and modmachine are updated accordingly. Documentation and tests are included.
Testing
Tested on KIT_PSE84_AI. A voltage divider is used as the hardware input to drive the ADC pin, enabling the test script to exercise full ADC functionality: pin read, ADCBlock channel init/deinit, read_u16(), read_uv(), and voltage conversion. All [adc.py] cases pass.
Trade-offs and Alternatives
None significant
Generative AI
I used generative AI tools when creating this PR, but a human has checked the
code and is responsible for the code and the description above.