Engineering student passionate about continuous learning ,problem solving ,and modeling .I use GitHub to document my projects and share knowledge.
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Engennering student
- ALGERIA
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verilog-gatedelay-simulation
verilog-gatedelay-simulation PublicGate-level Verilog simulation with propagation delays and waveform analysis.
SystemVerilog
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16-bit-Adder-Architecture-Comparison
16-bit-Adder-Architecture-Comparison PublicProfessional Verilog implementation and analysis of 16-bit Ripple Carry and Carry Lookahead Adders.
Verilog
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