From 2f0f498f751d5fee7e15ca5a243be640a8744f3d Mon Sep 17 00:00:00 2001
From: Robin Dapp <rdapp.gcc@gmail.com>
Date: Tue, 8 Jul 2025 14:21:06 +0200
Subject: [PATCH] RISC-V: Do not use vsetivli for THeadVector.

Hi,

in emit_vlmax_insn_lra we use a vsetivli for an immediate AVL.
XTHeadVector does not support this, so guard appropriately.

Regtested on rv64gcv_zvl512b.

Regards
 Robin

	PR target/120461

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Do not emit
	vsetivli for XTHeadVector.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/pr120461.c: New test.
---
 gcc/config/riscv/riscv-v.cc                                | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index cb7a0bb3d3d31..20d01319cf7c1 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -394,7 +394,7 @@ emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
   gcc_assert (!can_create_pseudo_p ());
   machine_mode mode = GET_MODE (ops[0]);
 
-  if (imm_avl_p (mode))
+  if (imm_avl_p (mode) && !TARGET_XTHEADVECTOR)
     {
       /* Even though VL is a real hardreg already allocated since
 	 it is post-RA now, we still gain benefits that we emit
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c
new file mode 100644
index 0000000000000..69391570970f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xt-c920 -mrvv-vector-bits=zvl -fzero-call-used-regs=all" */
+
+void
+foo ()
+{}