diff --git a/SUMMARY.md b/SUMMARY.md index 758b78954613d..0f73d07f2ec25 100644 --- a/SUMMARY.md +++ b/SUMMARY.md @@ -348,6 +348,13 @@ - [Hardware Interfaces](./hw/ip/aon_timer/doc/interfaces.md) - [Registers](./hw/ip/ascon/doc/registers.md) - [Checklist](./hw/ip/ascon/doc/checklist.md) + - [CHERIoT Memory Subsystem](./hw/ip/cheriot/README.md) + - [Theory of Operation](./hw/ip/cheriot/doc/theory_of_operation.md) + - [Design Verification](./hw/ip/cheriot/dv/README.md) + - [Testplan](./hw/ip/cheriot/data/cheriot_testplan.hjson) + - [Hardware Interfaces](./hw/ip/cheriot/doc/interfaces.md) + - [Registers](./hw/ip/cheriot/doc/registers.md) + - [Checklist](./hw/ip/cheriot/doc/checklist.md) - [CSRNG](./hw/ip/csrng/README.md) - [Theory of Operation](./hw/ip/csrng/doc/theory_of_operation.md) - [Design Verification](./hw/ip/csrng/dv/README.md) diff --git a/hw/Makefile b/hw/Makefile index 9e354d10e2fea..503d65fdad61e 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -23,6 +23,7 @@ IPS ?= aes \ adc_ctrl \ aon_timer \ bkdr_loader \ + cheriot \ csrng \ dma \ edn \ diff --git a/hw/ip/BUILD b/hw/ip/BUILD index fe658908eaa45..bdcc624d5ded4 100644 --- a/hw/ip/BUILD +++ b/hw/ip/BUILD @@ -18,6 +18,7 @@ filegroup( "//hw/ip/aes:rtl_files", "//hw/ip/aon_timer:rtl_files", "//hw/ip/bkdr_loader:rtl_files", + "//hw/ip/cheriot:rtl_files", "//hw/ip/csrng:rtl_files", "//hw/ip/dma:rtl_files", "//hw/ip/edn:rtl_files", diff --git a/hw/ip/README.md b/hw/ip/README.md index 2502c91844a3b..b29652453a284 100644 --- a/hw/ip/README.md +++ b/hw/ip/README.md @@ -9,6 +9,7 @@ | [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock | | [`ascon`] | Ascon authenticated encryption and decryption engine | | [`bkdr_loader`] | Provides FPGA-only indirect programming to RAMs | +| [`cheriot`] | CHERIoT-aware memory subsystem | | [`csrng`] | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software | | [`dma`] | DMA Controller for the integrated OpenTitan. | | [`edn`] | Distributes random numbers produced by CSRNG to hardware blocks | @@ -44,6 +45,7 @@ [`aon_timer`]: ./aon_timer/README.md [`ascon`]: ./ascon/README.md [`bkdr_loader`]: ./bkdr_loader/README.md +[`cheriot`]: ./cheriot/README.md [`csrng`]: ./csrng/README.md [`dma`]: ./dma/README.md [`edn`]: ./edn/README.md diff --git a/hw/ip/cheriot/BUILD b/hw/ip/cheriot/BUILD new file mode 100644 index 0000000000000..f6177d819d3df --- /dev/null +++ b/hw/ip/cheriot/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ) + [ + "//hw/ip/cheriot/data:all_files", + ], +) + +filegroup( + name = "doc_files", + srcs = glob( + [ + "**/*.md", + "**/*.svg", + ], + allow_empty = True, + ) + ["//hw/ip/cheriot/data:doc_files"], +) diff --git a/hw/ip/cheriot/README.md b/hw/ip/cheriot/README.md new file mode 100644 index 0000000000000..c91c2ce3c6d8c --- /dev/null +++ b/hw/ip/cheriot/README.md @@ -0,0 +1,57 @@ +# CHERIoT Memory Subsystem Technical Specification + +| Regression | Version | [Stages](https://opentitan.org/book/doc/project_governance/development_stages.html) | Results | +|-|-|-|-| + [`cheriot`](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/dashboard.html) | 1.0.0 | D1, V0 | ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/cheriot/test.svg) ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/cheriot/passing.svg) ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/cheriot/functional.svg) ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/cheriot/code.svg) | + + + +# Overview + +This document specifies the CHERIoT memory subsystem. +The subsystem sits between the CHERIoT-capable Ibex core and the main crossbar and follows the +[Comportability Specification](../../../doc/contributing/hw/comportability/README.md). + +A CHERIoT capability is 65 bits in size: 32 bits pointer, 32 bits meta data do the pointer, and a single validity tag bit. +OpenTitan keeps a 32-bit interconnect, so a capabilities are transferred in two consecutive 32-bit +accesses, and the tag is carried on a sideband signal, which shares the handshakes, next to the TL-UL structs +. +The subsystem is responsible for handling and storing the validity tag bit. It splits a data access +of Ibex into the data access towards the interconnect and a tag access towards a dedicated and guarded meta SRAM. + +The capability validity tags for main SRAM and NVM, and the revocation bitmap for the heap stored in the main +SRAM are stored using a `sram_ctrl`. + +## Features + +- Splits Ibex data accesses into a data access towards the interconnect and a capability tag access + towards the meta SRAM, and joins their responses. +- Read-modify-write access to implement bit-granular access to capability bits. +- Clears any capability tag of any location written by a non-capability store. +- Exposes the revocation bitmap in to core's address map and serves the core's TRVK filter.exit +- Per-port access checking: each of the three requesters may only reach the meta SRAM region it owns, + with word-granular accesses only. +- Fatal alert on a meta SRAM response integrity fault or a hardened FIFO pointer error. + +## Description + +The CHERIoT HWIP has three requesters towards the meta SRAM and arbitrates between them: + +- The *tag filter* folled by the *RMW filter* which perform the bit-granular tag update. +- The core's TRVK filter, which reads the revocation bitmap on every capability load. +- The system, which reads and writes the revocation bitmap through the `revbm` memory window. + +Each requester passes an *access checker* module that confirms the address falls in the region that +requester owns and that the operation is a full-word read or write. +Invalid acccesses receive a TL-UL error response. +Because the capability tag regions are not reachable from the `revbm` window, software can neither +read nor write capability tags. + +Requests that the subsystem generates or rewrites get command and data integrity, so end-to-end bus +integrity holds from the Ibex lockstep through the CHERIoT HWIP domain to the storage cells. +An integrity fault raises the `fatal_fault` alert. + + +See the [Theory of Operation](doc/theory_of_operation.md) for the datapath, the meta SRAM address +map, and the access-check rules. + diff --git a/hw/ip/cheriot/cheriot.core b/hw/ip/cheriot/cheriot.core new file mode 100644 index 0000000000000..bf0c5ec80baad --- /dev/null +++ b/hw/ip/cheriot/cheriot.core @@ -0,0 +1,83 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:cheriot:0.1" +description: "CHERIoT memory subsystem" + +filesets: + files_rtl: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - pulp-platform:common_cells:common_cells + files: + - rtl/cheriot_reg_pkg.sv + - rtl/cheriot_regs_reg_top.sv + - rtl/cheriot_rmw_filter.sv + - rtl/cheriot_tag_filter.sv + - rtl/cheriot_access_check.sv + - rtl/cheriot.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/cheriot.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/cheriot.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/cheriot.vbl + file_type: veribleLintWaiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: cheriot + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true diff --git a/hw/ip/cheriot/data/BUILD b/hw/ip/cheriot/data/BUILD new file mode 100644 index 0000000000000..7283123de537c --- /dev/null +++ b/hw/ip/cheriot/data/BUILD @@ -0,0 +1,18 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) + +filegroup( + name = "doc_files", + srcs = glob( + ["*_testplan.hjson"], + allow_empty = True, + ), +) diff --git a/hw/ip/cheriot/data/cheriot.hjson b/hw/ip/cheriot/data/cheriot.hjson new file mode 100644 index 0000000000000..d82ea047a0bec --- /dev/null +++ b/hw/ip/cheriot/data/cheriot.hjson @@ -0,0 +1,254 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "cheriot", + human_name: "CHERIoT Memory Subsystem", + one_line_desc: "CHERIoT-aware memory subsystem", + one_paragraph_desc: ''' + The CHERIoT memory subsystem sits between a CHERIoT-capable Ibex core and the system + interconnect. It enforces capability tag semantics on data-memory accesses, transparently + remapping capability accesses and revocation bitmap reads into a dedicated meta SRAM. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "47", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + version: "1.0.0", + life_stage: "L1", + design_stage: "D1", + verification_stage: "V0", + + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true} + ], + + bus_interfaces: [ + {protocol: "tlul", direction: "device", name: "regs"}, + {protocol: "tlul", direction: "device", name: "revbm"}, + {protocol: "tlul", direction: "host", name: "cored"} + ], + + /////////////////////////// + // Interrupts and Alerts // + /////////////////////////// + + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when an integrity fault is detected or when the tag + filter's transaction FIFO reports a pointer error. + ''' + } + ], + + //////////////// + // Parameters // + //////////////// + + param_list: [ + + ///////////////////// + // Address map // + ///////////////////// + + { name: "MainSramBaseAddr", + desc: "Base address of the main SRAM region (inclusive)", + type: "logic [top_pkg::TL_AW-1:0]", + default: "32'h1000_0000", + local: "false", + expose: "true" + }, + { name: "MainSramTopAddr", + desc: "Top address of the main SRAM region (exclusive).", + type: "logic [top_pkg::TL_AW-1:0]", + default: "32'h1002_0000", + local: "false", + expose: "true" + }, + { name: "NvmBaseAddr", + desc: "Base address of the NVM region (inclusive).", + type: "logic [top_pkg::TL_AW-1:0]", + default: "32'h2000_0000", + local: "false", + expose: "true" + }, + { name: "NvmTopAddr", + desc: "Top address of the NVM region (exclusive).", + type: "logic [top_pkg::TL_AW-1:0]", + default: "32'h2020_0000", + local: "false", + expose: "true" + }, + { name: "MetaSramBaseAddr", + desc: ''' + Base address of the CHERIoT meta SRAM region. + ''', + type: "logic [top_pkg::TL_AW-1:0]", + default: "32'h0000_0000", + local: "false", + expose: "true" + }, + ], + + ////////////// + // Features // + ////////////// + + features: [ + { name: "CHERIOT.TAG_SPLIT", + desc: ''' + A data access from the core is split into the data access towards the interconnect and a + capability tag access towards the meta SRAM. Their responses are joined so that data and + tag are returned together. + ''' + }, + { name: "CHERIOT.TAG_READ", + desc: ''' + On a hinted capability load, the tag bit of the addressed capability is looked up in the + meta SRAM and returned. + ''' + }, + { name: "CHERIOT.TAG_WRITE_RMW", + desc: ''' + Because tags are stored at bit granularity, a write performs a read-modify-write on the + addressed meta SRAM word. + ''' + }, + { name: "CHERIOT.TAG_CLEAR_ON_DATA_WRITE", + desc: ''' + Any non-capability write clears the tag bit of the addressed location, so that data stores + cannot modify a valid capability. + ''' + }, + { name: "CHERIOT.REVOCATION_BITMAP", + desc: ''' + The revocation bitmap is exposed as a memory window on the `revbm` device interface and is + read by the core's TRVK filter through the `corerevbm` port. + ''' + }, + { name: "CHERIOT.ACCESS_CHECK", + desc: ''' + Every meta SRAM access is checked against the region and the operations permitted for its + originating port. + ''' + }, + { name: "CHERIOT.MODE_GATING", + desc: ''' + In ePMP mode the entire meta SRAM is inaccessible through all three ports of the + subsystem. No tag lookups are issued. + ''' + }, + ], + + ///////////////////////////// + // Intermodule Connections // + ///////////////////////////// + + inter_signal_list: [ + // CHERIoT mode enable + { struct: "mubi4", + type: "uni", + name: "cheriot_ena", + act: "rcv", + package: "prim_mubi_pkg", + default: "prim_mubi_pkg::MuBi4False", + desc: "CHERIoT mode enable." + }, + // Data TL-UL interface from the core + { struct: "tl", + type: "req_rsp", + name: "cored_tl_d", + act: "rsp", + package: "tlul_pkg", + desc: "Data port from the core." + }, + // Capability tag sideband - write direction (from core to subsystem) + { struct: "logic", + type: "uni", + name: "cored_tag_h2d", + act: "rcv", + width: "1", + package: "", + default: "1'b0", + desc: "CHERIoT capability tag carried with the A-channel of cored_h." + }, + // Capability tag sideband - read response direction (from subsystem to core) + { struct: "logic", + type: "uni", + name: "cored_tag_d2h", + act: "req", + width: "1", + package: "", + default: "1'b0", + desc: "Capability tag returned on the D-channel of cored_h." + }, + // TRVK revocation bitmap TL-UL host port + { struct: "tl", + type: "req_rsp", + name: "corerevbm_tl", + act: "rsp", + package: "tlul_pkg", + desc: "TRVK (tag revocation) revocation bitmap port from the core." + }, + // Meta SRAM host TL-UL port (to external sram_ctrl RAM interface) + { struct: "tl", + type: "req_rsp", + name: "meta_sram_tl", + act: "req", + package: "tlul_pkg", + desc: "Host TL-UL port to the external meta SRAM controller's RAM interface." + }, + ], + + ///////////////////// + // Countermeasures // + ///////////////////// + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: ''' + End-to-end bus integrity between the Ibex lockstep and the storage cells. + ''' + }, + { name: "LOGIC.SHADOW", + desc: ''' + The CHERIoT subsystem is instantiated in lockstep. + ''' + }, + { name: "MEM.SW_NOACCESS", + desc: ''' + The capability tag store is not memory mapped. + ''' + }, + { name: "INTERSIG.MUBI", + desc: ''' + The CHERIoT mode enable is multi-bit encoded. + ''' + }, + { name: "CTR.REDUN", + desc: ''' + The tag filter's outstanding-transaction FIFO uses redundantly encoded read and write pointers. + ''' + }, + ], + + /////////// + // Memory // + /////////// + + memory: { + revbm: {} + } + + /////////////// + // Registers // + /////////////// + + regwidth: "32", + registers: { + // No additional registers + regs: [] + } +} diff --git a/hw/ip/cheriot/data/cheriot_sec_cm_testplan.hjson b/hw/ip/cheriot/data/cheriot_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..6699609d50e96 --- /dev/null +++ b/hw/ip/cheriot/data/cheriot_sec_cm_testplan.hjson @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../cheriot/data/cheriot.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../cheriot/data/cheriot_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: [] + } + { + name: sec_cm_logic_shadow + desc: "Verify the countermeasure(s) LOGIC.SHADOW." + stage: V2S + tests: [] + } + { + name: sec_cm_mem_sw_noaccess + desc: "Verify the countermeasure(s) MEM.SW_NOACCESS." + stage: V2S + tests: [] + } + { + name: sec_cm_intersig_mubi + desc: "Verify the countermeasure(s) INTERSIG.MUBI." + stage: V2S + tests: [] + } + { + name: sec_cm_ctr_redun + desc: "Verify the countermeasure(s) CTR.REDUN." + stage: V2S + tests: [] + } + ] +} diff --git a/hw/ip/cheriot/data/cheriot_testplan.hjson b/hw/ip/cheriot/data/cheriot_testplan.hjson new file mode 100644 index 0000000000000..6bfc4290c75ca --- /dev/null +++ b/hw/ip/cheriot/data/cheriot_testplan.hjson @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "cheriot" + + // Mirrors the test lists imported by cheriot_sim_cfg.hjson. mem_testplan is not imported: the + // only memory window, `revbm`, has no registers, so reggen emits no RAL model and there is no RAL + // memory to walk. + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"] + + testpoints: [ + { + name: smoke + desc: ''' + Bring the subsystem out of reset in ePMP mode and check that it stays quiescent: no + transaction is generated on either host port, `fatal_fault` stays low, and the CSR + interface responds to a register access. + ''' + stage: V1 + tests: ["cheriot_smoke"] + } + ] + + covergroups: [ + { + name: cheriot_feature_cg + desc: ''' + Placeholder. No covergroup is implemented; SIM_COVERAGE_MODEL_ADDED is Not Started and + scoped for the V1-to-V2 work. + ''' + } + ] +} diff --git a/hw/ip/cheriot/defs.bzl b/hw/ip/cheriot/defs.bzl new file mode 100644 index 0000000000000..ba321a596fc89 --- /dev/null +++ b/hw/ip/cheriot/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +CHERIOT = opentitan_ip( + name = "cheriot", + hjson = "//hw/ip/cheriot/data:cheriot.hjson", +) diff --git a/hw/ip/cheriot/doc/checklist.md b/hw/ip/cheriot/doc/checklist.md new file mode 100644 index 0000000000000..fd3fc171db28f --- /dev/null +++ b/hw/ip/cheriot/doc/checklist.md @@ -0,0 +1,268 @@ +# CHERIOT Checklist + +This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [CHERIOT peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [CHERIOT Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | [CHERIOT Registers](registers.md). +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Not Started | Instantiated in `top_earlgrey` and elaborates cleanly. +RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | Linting using Verilator in-place +Security | [SEC_CM_SCOPED][] | Not Started | Lockstep of the cheriot subsystem, end-to-end integrity between cheriot, Ibex, and the memory endpoints specified. + +[SPEC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#lint_setup +[SEC_CM_SCOPED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_scoped + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [BLOCK_DIAGRAM][] | Done | [Block diagram](theory_of_operation.md#block-diagram) +Documentation | [DOC_INTERFACE][] | Done | [Hardware Interfaces](interfaces.md) +Documentation | [DOC_INTEGRATION_GUIDE][] | Not Started | +Documentation | [MISSING_FUNC][] | Not Started | +Documentation | [FEATURE_FROZEN][] | Not Started | +RTL | [FEATURE_COMPLETE][] | Not Started | +RTL | [PORT_FROZEN][] | Not Started | +RTL | [ARCHITECTURE_FROZEN][] | Not Started | +RTL | [REVIEW_TODO][] | Not Started | +RTL | [STYLE_X][] | Not Started | +RTL | [CDC_SYNCMACRO][] | N/A | +Code Quality | [LINT_PASS][] | Not Started | +Code Quality | [CDC_SETUP][] | Not Started | +Code Quality | [RDC_SETUP][] | Not Started | +Code Quality | [AREA_CHECK][] | Not Started | +Code Quality | [TIMING_CHECK][] | Not Started | +Security | [SEC_CM_DOCUMENTED][] | Not Started | + +[NEW_FEATURES]: ../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | [cheriot.hjson](../data/cheriot.hjson) +Security | [SEC_CM_IMPLEMENTED][] | Not Started | Everything except `LOGIC.SHADOW` is implemented and escalated by the `fatal_fault` alert. +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_CM_SHADOW_REGS][] | N/A | The only CSR is `ALERT_TEST`. +Security | [SEC_CM_RTL_REVIEWED][] | Not Started | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started | + +[SEC_CM_ASSETS_LISTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[NEW_FEATURES_D3]: ../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | Template present [CHERIOT DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Not Started | Template present [Testplan](../data/cheriot_testplan.hjson) +Testbench | [TB_TOP_CREATED][] | Done | [tb.sv](../dv/tb.sv) +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | +Testbench | [SIM_TB_ENV_CREATED][] | Not Started | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Not Started | +Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Code Quality | [TB_LINT_SETUP][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | +Review | [V2_CHECKLIST_SCOPED][] | Not Started | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | +Documentation | [DV_DOC_COMPLETED][] | Not Started | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started | +Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | +Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | +Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | +Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | +Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Not Started | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started | +Tests | [FPV_SEC_CM_VERIFIED][] | Not Started | +Tests | [SIM_SEC_CM_VERIFIED][] | Not Started | +Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started | +Review | [SEC_CM_DV_REVIEWED][] | Not Started | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/ip/cheriot/doc/cheriot_blockdiag.svg b/hw/ip/cheriot/doc/cheriot_blockdiag.svg new file mode 100644 index 0000000000000..212e91752d9f3 --- /dev/null +++ b/hw/ip/cheriot/doc/cheriot_blockdiag.svg @@ -0,0 +1,2088 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ibex Core + + + + Ibex Core + + + + + + + + + + + + + + + + Revocation Engine + + + + + Revocation Engine + + + + + + + + + + + + + + + + + + + + + Main TLUL Crossbar + + + + Main TLUL Crossbar + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRVK Filter + + + + TRVK Filter + + + + + + + + + + + + + + + + + + + + + + Lockstep + + + + + Lockstep + + + + + + + + + + + + + + + I + + + + I + + + + + + + + + + + + + + + D + + + + D + + + + + + + + + + + + + + + rv_core_ibex + + + + rv_core_ibex + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBI - TLUL + + + + + OBI - TLUL + + + + + + + + + + + + + + + + CHERIoT + + + + + CHERIoT + + + + + + + + + + + + + + + + + + + + + + + + + + I + + + + I + + + + + + + + + + + + + + + + D + + + + + D + + + + + + + + + + + + + + + RevBM + + + + RevBM + + + + + + + + + + + + + + + Cfg + + + + Cfg + + + + + + + + + + + + + + + + + + + + Tag Filter + + + + Tag Filter + + + + + + + + + + + + + + + Access Chk + + + + Access Chk + + + + + + + + + + + + + + + Access Chk + + + + Access Chk + + + + + + + + + + + + + + + Access Chk + + + + Access Chk + + + + + + + + + + + + + + + + + + + + + + + + + + + + Lockstep + + + + + Lockstep + + + + + + + + + + + + + + + Sys + + + + Sys + + + + + + + + + + + + + + + CHERIoT Enable + + + + CHERIoT Enable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Main SRAM + + + + Main SRAM + + + + + + + + + + + + + + + NVM + + + + NVM + + + + + + + + + + + + + + + Meta SRAM + + + + Meta SRAM + + + + + + + + + + + + + + + Tags + + + + Tags + + + + + + + + + + + + + + + RMW Filter + + + + RMW Filter + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 128 kiB + + + + 128 kiB + + + + + + + + + + + + + + + 1024 kiB + + + + 1024 kiB + + + + + + + + + + + + + + + 64 kiB + + + + + 36 kiB + + + + + + + + + + diff --git a/hw/ip/cheriot/doc/interfaces.md b/hw/ip/cheriot/doc/interfaces.md new file mode 100644 index 0000000000000..d00f67c279cb9 --- /dev/null +++ b/hw/ip/cheriot/doc/interfaces.md @@ -0,0 +1,59 @@ +# Hardware Interfaces + +## Parameters + +The following table lists the instantiation parameters of the CHERIoT memory subsystem. +[Theory of Operation](theory_of_operation.md#meta-sram-address-map). + +Parameter | Default | Top Earlgrey | Description +-------------------|----------------|----------------|--------------- +`addr_t` | `logic [top_pkg::TL_AW-1:0]` | `logic [31:0]` | TL-UL address type. +`MainSramBaseAddr` | `0x1000_0000` | `0x1000_0000` | Base address of the main SRAM region, inclusive. +`MainSramTopAddr` | `0x1002_0000` | `0x1002_0000` | Top address of the main SRAM region, exclusive. +`NvmBaseAddr` | `0x2000_0000` | `0x2000_0000` | Base address of the NVM region, inclusive. +`NvmTopAddr` | `0x2020_0000` | `0x2020_0000` | Top address of the NVM region, exclusive. +`MetaSramBaseAddr` | `0x0000_0000` | `0x1100_0000` | Base address of the unified meta SRAM. + +## Signals + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`cheriot`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: *none* +- Bus Device Interfaces (TL-UL): **`regs_tl_d`**, **`revbm_tl_d`** +- Bus Host Interfaces (TL-UL): **`cored_tl_h`** +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:--------------|:---------------------|:--------|:------|--------:|:----------------------------------------------------------------------| +| cheriot_ena | prim_mubi_pkg::mubi4 | uni | rcv | 1 | CHERIoT mode enable. | +| cored_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | Data port from the core. | +| cored_tag_h2d | logic | uni | rcv | 1 | CHERIoT capability tag carried with the A-channel of cored_h. | +| cored_tag_d2h | logic | uni | req | 1 | Capability tag returned on the D-channel of cored_h. | +| corerevbm_tl | tlul_pkg::tl | req_rsp | rsp | 1 | TRVK (tag revocation) revocation bitmap port from the core. | +| meta_sram_tl | tlul_pkg::tl | req_rsp | req | 1 | Host TL-UL port to the external meta SRAM controller's RAM interface. | +| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | +| regs_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | +| revbm_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:--------------------------------------------------------------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when an integrity fault is detected or when the tag filter's transaction FIFO reports a pointer error. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:------------------------|:------------------------------------------------------------------------------------------------| +| CHERIOT.BUS.INTEGRITY | End-to-end bus integrity between the Ibex lockstep and the storage cells. | +| CHERIOT.LOGIC.SHADOW | The CHERIoT subsystem is instantiated in lockstep. | +| CHERIOT.MEM.SW_NOACCESS | The capability tag store is not memory mapped. | +| CHERIOT.INTERSIG.MUBI | The CHERIoT mode enable is multi-bit encoded. | +| CHERIOT.CTR.REDUN | The tag filter's outstanding-transaction FIFO uses redundantly encoded read and write pointers. | + + + diff --git a/hw/ip/cheriot/doc/registers.md b/hw/ip/cheriot/doc/registers.md new file mode 100644 index 0000000000000..341c02f9670f1 --- /dev/null +++ b/hw/ip/cheriot/doc/registers.md @@ -0,0 +1,31 @@ +# Registers + +The revocation bitmap is not a register but a memory window on the `revbm` interface; see the +[Theory of Operation](theory_of_operation.md#meta-sram-address-map). + + +## Summary + +| Name | Offset | Length | Description | +|:------------------------------------|:---------|---------:|:--------------------| +| cheriot.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + + + diff --git a/hw/ip/cheriot/doc/theory_of_operation.md b/hw/ip/cheriot/doc/theory_of_operation.md new file mode 100644 index 0000000000000..48590d1f70919 --- /dev/null +++ b/hw/ip/cheriot/doc/theory_of_operation.md @@ -0,0 +1,143 @@ +# Theory of Operation + +## Block Diagram + +![CHERIoT memory subsystem block diagram](cheriot_blockdiag.svg) + +| Port | Direction | Peer | Purpose | +|------|-----------|------|---------| +| `cored_tl_d` | device | `rv_core_ibex` | Core data accesses with the capability tag support.. | +| `cored_tl_h` | host | `xbar_main` | The data half of the access, forwarded to SRAM, NVM and peripherals. | +| `corerevbm_tl` | device | `rv_core_ibex` | Revocation bitmap reads from the core's TRVK filter. | +| `revbm_tl_d` | device | `xbar_main` | Memory window through which software reads and writes the revocation bitmap. | +| `regs_tl_d` | device | `xbar_main` | CSR interface. | +| `meta_sram_tl` | host | `sram_ctrl_meta` | The single port into the unified meta SRAM. | + +`cheriot_ena_i` selects the execution mode. It is a `mubi4_t` driven by the write-once mode switch in +`rv_core_ibex`. + +## Metadata Encoding + +Two kinds of metadata are stored, both at bit granularity, both packed into 32-bit words: + +| Metadata | Covered by one bit | Covered by one 32-bit word | +|----------|--------------------|----------------------------| +| Capability tag | one 8-byte capability | 256 bytes of data | +| Revocation bit | 8 heap bytes | 256 heap bytes | + + +## Meta SRAM Address Map + +The map is derived from the address-map parameters, so it changes with the covered region sizes. +For Earl Grey - 128 KiB main SRAM at `0x1000_0000`, 2 MiB NVM at `0x2000_0000`, meta SRAM at +`0x1100_0000` - it is: + +| Offset | Size | Region | Reachable from | +|---------|--------|------------------------------------|----------------| +| `0x0000` | 2 KiB | Main SRAM revocation bitmap | `revbm_tl_d`, `corerevbm_tl` | +| `0x0800` | 32 KiB | NVM capability tags | RMW filter | +| `0x8800` | 2 KiB | Main SRAM capability tags | RMW filter | +| `0x9000` | - | top | - | + +The revocation bitmap is situated at the base of the meta SRAM. +The `revbm` window and the meta SRAM's own RAM interface consequently share a base address; the +window is the software-visible view of the first region, the RAM interface is only reachable from +`meta_sram_tl`. + +In the `revbm` window, bit `b` of word `w` covers the eight heap bytes starting at +`MainSramBaseAddr + (w * 32 + b) * 8`, setting it marks that granule as revoked. Accesses must be +full 32-bit words, and the window returns a TL-UL error while the system is in ePMP mode. + + +## Datapath + +### Tag Filter + +The tag filter forks each core data access into up to three streams, the host port, the meta port, +and a small metadata FIFO that carries information from the request to the response channel. After +receiving the responses, the streams are joined together and the data response is returned to the +core. + +A meta lookup is needed when CHERIoT mode is enabled, we access memory capable of holding +capabilities and either: + +- the access is a 64-bit-aligned read that the core hints as a capability load. +- the access is a write, of any kind. + +Writes always look up because a non-capability store must clear the tag of the location it +overwrites. + +The returned tag is sticky across the two words of a capability: on a response whose FIFO entry was +marked aligned, the tag read from the meta SRAM is presented and captured; on the following unaligned +response the captured value is presented again and then cleared. This is what lets a 65-bit +capability arrive over two 32-bit responses with one combined validity tag bit. + +The FIFO depth sets the number of outstanding transactions the subsystem supports; it is 2 in the +Earl Grey instantiation. Error responses from either the host or the meta path are merged into +`d_error` towards the core. + +### RMW Filter + +Because tags are bit-granular, a tag write cannot be a plain TL-UL write. The RMW filter turns each +access into meta SRAM traffic with a four-state FSM: + +| State | Behaviour | +|-------|-----------| +| `Passthrough` | A read is forwarded and the tag bit is picked out of the response word. A write is turned into a `Get` of the meta word and the FSM advances to `Fill`. | +| `Fill` | The meta word arrives. If the stored tag bit already equals the tag to be written, the read response is converted into an `AccessAck` towards the core and the FSM returns to `Passthrough`. Otherwise the word is captured, the bit is modified, and the FSM advances. | +| `WriteBackReq` | The modified word is written back with `PutFullData` and freshly computed command and data integrity. | +| `WriteBackAck` | The write response is forwarded to the core and the FSM returns to `Passthrough`. | + +Skipping the write-back is the common case and keeps pressure off the shared meta SRAM: it costs one +meta SRAM read per 32-bit store, and a read plus a write only when the tag actually changes. + +The filter checks the response integrity and response data integrity of every meta SRAM response +and separately reports `d_error`. + + +### Access Checkers + +Each of the three requesters passes an access checker parameterized with the region it owns. An +access is forwarded only if all of the following hold: + +- `cheriot_ena_i` is `MuBi4True`. +- The address is inside the allowable region for the requester. +- The opcode is `Get` or `PutFullData`. + +Everything else is steered to a `tlul_err_resp` instance and answered with a TL-UL error. In +particular, any `cheriot_ena_i` value other than a strict `MuBi4True` - including a strict +`MuBi4False` - makes the entire meta SRAM inaccessible from all three ports. + +### Arbitration + +A `tlul_socket_m1` arbitrates the three checked streams onto `meta_sram_tl`. Arbitration sits behind +the checkers, on transactions that are already integrity-protected end to end. + +## Error Handling + +The subsystem distinguishes a denied access from a fault: + +| Cause | Result | +|-------|--------| +| Any meta SRAM access while in ePMP mode | TL-UL error response, merged into `d_error` towards the core | +| Access outside the region owned by the requesting port | TL-UL error response | +| `PutPartialData` to the meta SRAM | TL-UL error response | +| Meta SRAM controller error | Forwarded as `d_error` towards the core | +| Integrity fault on a meta SRAM response (`rsp_intg` or `data_intg`) | `fatal_fault` alert | +| Integrity fault on the CSR interface | `fatal_fault` alert | +| Pointer error in the tag filter's hardened FIFO | `fatal_fault` alert | + +The first four are reachable by software and surface as a bus fault in the core, so they must not +raise an alert. The last three indicate a fault-injection attempt and latch the fatal alert until +reset. There is no interrupt. + +## Timing + +All internal sockets and the socket towards the meta SRAM are instantiated with zero-depth FIFOs, so +a request propagates combinationally from `cored_tl_d` through the tag filter, RMW filter, access +checker and arbiter to `meta_sram_tl`, and the response propagates back the same way. This keeps the +latency overhead of CHERIoT mode at zero cycles for reads, but places the meta SRAM path on the +critical path. + +The design provisions optional pipeline cuts in front of the access checkers to break that path, at +the cost of two extra cycles per meta SRAM access. They are not implemented yet. diff --git a/hw/ip/cheriot/dv/README.md b/hw/ip/cheriot/dv/README.md new file mode 100644 index 0000000000000..3d11d93ac8726 --- /dev/null +++ b/hw/ip/cheriot/dv/README.md @@ -0,0 +1,30 @@ +# CHERIOT DV document + +## Goals +* Verify the CHERIoT memory subsystem with a SV/UVM testbench based on the + [CIP testbench architecture](../../../dv/sv/cip_lib/README.md). +* Run the tests in the [testplan](#testplan) towards closing code and functional coverage. + +## Current status +* [Design & verification stage](../../../README.md) + * [HW development stages](../../../../doc/project_governance/development_stages.md) + +## Design features +See the [CHERIoT Memory Subsystem HWIP technical specification](../README.md). + +## Testbench +`hw/ip/cheriot/dv/tb.sv` instantiates `hw/ip/cheriot/rtl/cheriot.sv` with: +* [Clock and reset interface](../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../dv/sv/tl_agent/README.md) on the `regs` CSR port +* Alerts ([`alert_esc_if`](../../../dv/sv/alert_esc_agent/README.md)) for `fatal_fault` + +## Building and running tests +Built and run with `dvsim.py`; see the [DV simulation flow](../../../dv/tools/dvsim/README.md). + +```console +$ dvsim hw/ip/cheriot/dv/cheriot_sim_cfg.hjson -i cheriot_smoke # smoke only +$ dvsim hw/ip/cheriot/dv/cheriot_sim_cfg.hjson # CSR, alert and TL-UL suites +``` + +## Testplan +[Testplan](../data/cheriot_testplan.hjson) diff --git a/hw/ip/cheriot/dv/cheriot_sim.core b/hw/ip/cheriot/dv/cheriot_sim.core new file mode 100644 index 0000000000000..12445f00001f5 --- /dev/null +++ b/hw/ip/cheriot/dv/cheriot_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:cheriot_sim:0.1" +description: "CHERIOT DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:cheriot + + files_dv: + depend: + - lowrisc:dv:cheriot_test + - lowrisc:dv:cheriot_sva + files: + - tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + # TODO: add a lint check cfg in `hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson` + lint: + <<: *sim_target diff --git a/hw/ip/cheriot/dv/cheriot_sim_cfg.hjson b/hw/ip/cheriot/dv/cheriot_sim_cfg.hjson new file mode 100644 index 0000000000000..80e62936d0c88 --- /dev/null +++ b/hw/ip/cheriot/dv/cheriot_sim_cfg.hjson @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: cheriot + + // Top level dut name (sv module). + dut: cheriot + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:cheriot_sim:0.1 + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/cheriot/data/cheriot_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{proj_root}/hw/ip/cheriot/data/cheriot.hjson" + + // Import additional common sim cfg files. + // + // mem_tests is not imported: `revbm` has no registers, so reggen emits no RAL model for it and + // there is no RAL memory to walk. stress_tests is not imported: no sequence to stress yet. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["cheriot_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 1 + + // Default UVM test and seq class name. + uvm_test: cheriot_base_test + uvm_test_seq: cheriot_base_vseq + + // List of test specifications. + tests: [ + { + name: cheriot_smoke + uvm_test_seq: cheriot_smoke_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["cheriot_smoke"] + } + ] +} diff --git a/hw/ip/cheriot/dv/env/cheriot_env.core b/hw/ip/cheriot/dv/env/cheriot_env.core new file mode 100644 index 0000000000000..d9bdf0190ac8f --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_env.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:cheriot_env:0.1" +description: "CHERIOT DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + files: + - cheriot_env_pkg.sv + - cheriot_env_cfg.sv: {is_include_file: true} + - cheriot_env_cov.sv: {is_include_file: true} + - cheriot_virtual_sequencer.sv: {is_include_file: true} + - cheriot_scoreboard.sv: {is_include_file: true} + - cheriot_env.sv: {is_include_file: true} + - seq_lib/cheriot_vseq_list.sv: {is_include_file: true} + - seq_lib/cheriot_base_vseq.sv: {is_include_file: true} + - seq_lib/cheriot_common_vseq.sv: {is_include_file: true} + - seq_lib/cheriot_smoke_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: cheriot + ip_hjson: ../../data/cheriot.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - "!chip_level ? (ral)" diff --git a/hw/ip/cheriot/dv/env/cheriot_env.sv b/hw/ip/cheriot/dv/env/cheriot_env.sv new file mode 100644 index 0000000000000..c5884c2a783f1 --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_env.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_env extends cip_base_env #( + .CFG_T (cheriot_env_cfg), + .COV_T (cheriot_env_cov), + .VIRTUAL_SEQUENCER_T(cheriot_virtual_sequencer), + .SCOREBOARD_T (cheriot_scoreboard) + ); + `uvm_component_utils(cheriot_env) + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/ip/cheriot/dv/env/cheriot_env_cfg.sv b/hw/ip/cheriot/dv/env/cheriot_env_cfg.sv new file mode 100644 index 0000000000000..6918dab1f9356 --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_env_cfg.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_env_cfg extends cip_base_env_cfg #(.RAL_T(cheriot_regs_reg_block)); + + // ext component cfgs + + `uvm_object_utils_begin(cheriot_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + virtual function void initialize(); + list_of_alerts = cheriot_env_pkg::LIST_OF_ALERTS; + super.initialize(); + endfunction + +endclass diff --git a/hw/ip/cheriot/dv/env/cheriot_env_cov.sv b/hw/ip/cheriot/dv/env/cheriot_env_cov.sv new file mode 100644 index 0000000000000..e378df70ac4a0 --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_env_cov.sv @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergroups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class cheriot_env_cov extends cip_base_env_cov #(.CFG_T(cheriot_env_cfg)); + `uvm_component_utils(cheriot_env_cov) + + // the base class provides the following handles for use: + // cheriot_env_cfg: cfg + + // covergroups + // [add covergroups here] + + function new(string name, uvm_component parent); + super.new(name, parent); + // [instantiate covergroups here] + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/ip/cheriot/dv/env/cheriot_env_pkg.sv b/hw/ip/cheriot/dv/env/cheriot_env_pkg.sv new file mode 100644 index 0000000000000..ee2c26819c329 --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_env_pkg.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package cheriot_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_base_agent_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import cheriot_regs_ral_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter uint NUM_ALERTS = 1; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal_fault"}; + + // types + + // functions + + // package sources + `include "cheriot_env_cfg.sv" + `include "cheriot_env_cov.sv" + `include "cheriot_virtual_sequencer.sv" + `include "cheriot_scoreboard.sv" + `include "cheriot_env.sv" + `include "cheriot_vseq_list.sv" + +endpackage diff --git a/hw/ip/cheriot/dv/env/cheriot_scoreboard.sv b/hw/ip/cheriot/dv/env/cheriot_scoreboard.sv new file mode 100644 index 0000000000000..8f87ffa67b9d4 --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_scoreboard.sv @@ -0,0 +1,94 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_scoreboard extends cip_base_scoreboard #( + .CFG_T(cheriot_env_cfg), + .RAL_T(cheriot_regs_reg_block), + .COV_T(cheriot_env_cov) + ); + `uvm_component_utils(cheriot_scoreboard) + + // local variables + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + // TODO: remove once support alert checking + do_alert_check = 0; + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + join_none + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end + else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // if incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update prediction at address phase and compare at data phase + case (csr.get_name()) + // add individual case item for each csr + "alert_test": begin + // do_alert_check is disabled above, so no set_exp_alert() call here yet. + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + // reset local fifos queues and variables + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/ip/cheriot/dv/env/cheriot_virtual_sequencer.sv b/hw/ip/cheriot/dv/env/cheriot_virtual_sequencer.sv new file mode 100644 index 0000000000000..fccc54c67f359 --- /dev/null +++ b/hw/ip/cheriot/dv/env/cheriot_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(cheriot_env_cfg), + .COV_T(cheriot_env_cov) + ); + `uvm_component_utils(cheriot_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/ip/cheriot/dv/env/seq_lib/cheriot_base_vseq.sv b/hw/ip/cheriot/dv/env/seq_lib/cheriot_base_vseq.sv new file mode 100644 index 0000000000000..527841553e6d2 --- /dev/null +++ b/hw/ip/cheriot/dv/env/seq_lib/cheriot_base_vseq.sv @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_base_vseq extends cip_base_vseq #( + .RAL_T (cheriot_regs_reg_block), + .CFG_T (cheriot_env_cfg), + .COV_T (cheriot_env_cov), + .VIRTUAL_SEQUENCER_T (cheriot_virtual_sequencer) + ); + `uvm_object_utils(cheriot_base_vseq) + + // various knobs to enable certain routines + bit do_cheriot_init = 1'b1; + + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(); + if (do_cheriot_init) cheriot_init(); + endtask + + virtual task dut_shutdown(); + // check for pending cheriot operations and wait for them to complete + // TODO + endtask + + // setup basic cheriot features + virtual task cheriot_init(); + endtask + +endclass : cheriot_base_vseq diff --git a/hw/ip/cheriot/dv/env/seq_lib/cheriot_common_vseq.sv b/hw/ip/cheriot/dv/env/seq_lib/cheriot_common_vseq.sv new file mode 100644 index 0000000000000..560003fd609ad --- /dev/null +++ b/hw/ip/cheriot/dv/env/seq_lib/cheriot_common_vseq.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_common_vseq extends cheriot_base_vseq; + `uvm_object_utils(cheriot_common_vseq) + + constraint num_trans_c { + num_trans inside {[1:2]}; + } + `uvm_object_new + + virtual task body(); + run_common_vseq_wrapper(num_trans); + endtask : body + +endclass diff --git a/hw/ip/cheriot/dv/env/seq_lib/cheriot_smoke_vseq.sv b/hw/ip/cheriot/dv/env/seq_lib/cheriot_smoke_vseq.sv new file mode 100644 index 0000000000000..af371dd079f07 --- /dev/null +++ b/hw/ip/cheriot/dv/env/seq_lib/cheriot_smoke_vseq.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// smoke test vseq +class cheriot_smoke_vseq extends cheriot_base_vseq; + `uvm_object_utils(cheriot_smoke_vseq) + + `uvm_object_new + + task body(); + endtask : body + +endclass : cheriot_smoke_vseq diff --git a/hw/ip/cheriot/dv/env/seq_lib/cheriot_vseq_list.sv b/hw/ip/cheriot/dv/env/seq_lib/cheriot_vseq_list.sv new file mode 100644 index 0000000000000..81812c6a1668b --- /dev/null +++ b/hw/ip/cheriot/dv/env/seq_lib/cheriot_vseq_list.sv @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "cheriot_base_vseq.sv" +`include "cheriot_smoke_vseq.sv" +`include "cheriot_common_vseq.sv" diff --git a/hw/ip/cheriot/dv/sva/cheriot_bind.sv b/hw/ip/cheriot/dv/sva/cheriot_bind.sv new file mode 100644 index 0000000000000..e1cc19a3fe979 --- /dev/null +++ b/hw/ip/cheriot/dv/sva/cheriot_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module cheriot_bind; + + bind cheriot tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device_regs ( + .clk_i, + .rst_ni, + .h2d (regs_tl_d_i), + .d2h (regs_tl_d_o) + ); + + bind cheriot cheriot_regs_csr_assert_fpv cheriot_regs_csr_assert ( + .clk_i, + .rst_ni, + .h2d (regs_tl_d_i), + .d2h (regs_tl_d_o) + ); + +endmodule diff --git a/hw/ip/cheriot/dv/sva/cheriot_sva.core b/hw/ip/cheriot/dv/sva/cheriot_sva.core new file mode 100644 index 0000000000000..f64670d0767ef --- /dev/null +++ b/hw/ip/cheriot/dv/sva/cheriot_sva.core @@ -0,0 +1,37 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:cheriot_sva:0.1" +description: "CHERIOT assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - cheriot_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:ip:cheriot + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/cheriot.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: cheriot diff --git a/hw/ip/cheriot/dv/tb.sv b/hw/ip/cheriot/dv/tb.sv new file mode 100644 index 0000000000000..6290893c16a0f --- /dev/null +++ b/hw/ip/cheriot/dv/tb.sv @@ -0,0 +1,72 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import cheriot_env_pkg::*; + import cheriot_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + + // interfaces + clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); + tl_if tl_if(.clk(clk), .rst_n(rst_n)); + + `DV_ALERT_IF_CONNECT() + + // dut + cheriot dut ( + .clk_i (clk ), + .rst_ni (rst_n ), + + // Bus interface (device) for CSRs + .regs_tl_d_i (tl_if.h2d), + .regs_tl_d_o (tl_if.d2h), + + // Alerts + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + + // Execution mode + .cheriot_ena_i (prim_mubi_pkg::MuBi4False), + + // Core data port with its capability tag sideband + .cored_tl_d_i (tlul_pkg::TL_H2D_DEFAULT), + .cored_tag_h2d_i (1'b0), + .cored_tl_d_o (), + .cored_tag_d2h_o (), + + // Core revocation bitmap port + .corerevbm_tl_i (tlul_pkg::TL_H2D_DEFAULT), + .corerevbm_tl_o (), + + // System revocation bitmap window + .revbm_tl_d_i (tlul_pkg::TL_H2D_DEFAULT), + .revbm_tl_d_o (), + + // Host port towards the interconnect + .cored_tl_h_o (), + .cored_tl_h_i (tlul_pkg::TL_D2H_DEFAULT), + + // Host port towards the meta SRAM + .meta_sram_tl_o (), + .meta_sram_tl_i (tlul_pkg::TL_D2H_DEFAULT) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/ip/cheriot/dv/tests/cheriot_base_test.sv b/hw/ip/cheriot/dv/tests/cheriot_base_test.sv new file mode 100644 index 0000000000000..65d782841ef13 --- /dev/null +++ b/hw/ip/cheriot/dv/tests/cheriot_base_test.sv @@ -0,0 +1,13 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class cheriot_base_test extends cip_base_test #( + .CFG_T(cheriot_env_cfg), + .ENV_T(cheriot_env) + ); + + `uvm_component_utils(cheriot_base_test) + `uvm_component_new + +endclass : cheriot_base_test diff --git a/hw/ip/cheriot/dv/tests/cheriot_test.core b/hw/ip/cheriot/dv/tests/cheriot_test.core new file mode 100644 index 0000000000000..6dbbf4b5d7a1b --- /dev/null +++ b/hw/ip/cheriot/dv/tests/cheriot_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:cheriot_test:0.1" +description: "CHERIOT DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:cheriot_env + files: + - cheriot_test_pkg.sv + - cheriot_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/ip/cheriot/dv/tests/cheriot_test_pkg.sv b/hw/ip/cheriot/dv/tests/cheriot_test_pkg.sv new file mode 100644 index 0000000000000..c4e984ca4af8d --- /dev/null +++ b/hw/ip/cheriot/dv/tests/cheriot_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package cheriot_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import cheriot_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "cheriot_base_test.sv" + +endpackage diff --git a/hw/ip/cheriot/lint/cheriot.vbl b/hw/ip/cheriot/lint/cheriot.vbl new file mode 100644 index 0000000000000..f92bd0f5fb477 --- /dev/null +++ b/hw/ip/cheriot/lint/cheriot.vbl @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for the CHERIoT memory subsystem diff --git a/hw/ip/cheriot/lint/cheriot.vlt b/hw/ip/cheriot/lint/cheriot.vlt new file mode 100644 index 0000000000000..1cd63068cb1ab --- /dev/null +++ b/hw/ip/cheriot/lint/cheriot.vlt @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for the CHERIoT memory subsystem + +`verilator_config + +// The subsystem chains zero-depth (pass-through) TL-UL sockets, so the request and response +// channels of a single link are combinationally coupled. Verilator reports this as circular logic +// even though there is no combinational loop through a single signal. +lint_off -rule UNOPTFLAT -file "*/rtl/cheriot.sv" -match "*rmw_tl_d2h*" +lint_off -rule UNOPTFLAT -file "*/rtl/tlul_socket_1n.sv" -match "*u_cheriot_access_check_tags*" +lint_off -rule UNOPTFLAT -file "*/rtl/prim_arbiter_ppc.sv" -match "*u_tlul_socket_m1*" + +// The lower bound of the access check is constant whenever the region base address is zero, which +// is the module default. The check is written generically because the base address is a parameter. +lint_off -rule UNSIGNED -file "*/rtl/cheriot_access_check.sv" -match "*Comparison is constant*" + +// Pre-existing prim issue, exposed by the arbiter inside tlul_socket_m1. The equivalent waiver in +// hw/ip/prim/lint/prim_arbiter.vlt only covers prim_arbiter_ppc.sv itself. +lint_off -rule ALWCOMBORDER -file "*/rtl/prim_leading_one_ppc.sv" -match "*ppc_out*" + +// With the default AlertSkewCycles of 1, `skew_cnt_q` is a single bit and is compared against +// the integer parameter SkewCycles. +lint_off -rule WIDTH -file "*/rtl/prim_diff_decode.sv" -match "*skew_cnt_q*" diff --git a/hw/ip/cheriot/lint/cheriot.waiver b/hw/ip/cheriot/lint/cheriot.waiver new file mode 100644 index 0000000000000..f92bd0f5fb477 --- /dev/null +++ b/hw/ip/cheriot/lint/cheriot.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for the CHERIoT memory subsystem diff --git a/hw/ip/cheriot/rtl/cheriot.sv b/hw/ip/cheriot/rtl/cheriot.sv new file mode 100644 index 0000000000000..43faa99b708f4 --- /dev/null +++ b/hw/ip/cheriot/rtl/cheriot.sv @@ -0,0 +1,317 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "prim_assert.sv" +`include "prim_fifo_assert.svh" + +// SEC_CM: LOGIC.SHADOW +// TODO: Implement lockstep operation for this module + +module cheriot + import cheriot_reg_pkg::*; +#( + // TL-UL address type + parameter type addr_t = logic [top_pkg::TL_AW-1:0], + // Top-level address map parameters + parameter addr_t MainSramBaseAddr = 'h1000_0000, + parameter addr_t MainSramTopAddr = 'h1002_0000, + parameter addr_t NvmBaseAddr = 'h2000_0000, + parameter addr_t NvmTopAddr = 'h2020_0000, + parameter addr_t MetaSramBaseAddr = 'h0, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter int unsigned AlertSkewCycles = 1 +) ( + + input logic clk_i, + input logic rst_ni, + + // CHERIoT mode enabled + input prim_mubi_pkg::mubi4_t cheriot_ena_i, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // Device interface for CSRs + input tlul_pkg::tl_h2d_t regs_tl_d_i, + output tlul_pkg::tl_d2h_t regs_tl_d_o, + + // Core data input port + input tlul_pkg::tl_h2d_t cored_tl_d_i, + input logic cored_tag_h2d_i, + output tlul_pkg::tl_d2h_t cored_tl_d_o, + output logic cored_tag_d2h_o, + + // TRVK revocation bitmap input port + input tlul_pkg::tl_h2d_t corerevbm_tl_i, + output tlul_pkg::tl_d2h_t corerevbm_tl_o, + + // System revocation bitmap port + input tlul_pkg::tl_h2d_t revbm_tl_d_i, + output tlul_pkg::tl_d2h_t revbm_tl_d_o, + + // Core data output port towards interconnect + output tlul_pkg::tl_h2d_t cored_tl_h_o, + input tlul_pkg::tl_d2h_t cored_tl_h_i, + + // Meta SRAM host port (to external sram_ctrl) + output tlul_pkg::tl_h2d_t meta_sram_tl_o, + input tlul_pkg::tl_d2h_t meta_sram_tl_i +); + + ///////////////// + // Address map // + ///////////////// + + // Revocation happens on 64-bit or 8-byte granularity. + localparam int unsigned RevocationGranuleByte = 32'd8; + // Number of heap bytes a single TL word in the meta store can track + localparam int unsigned RevocationBytePerWord = top_pkg::TL_DW * RevocationGranuleByte; + + // A capability is 64 bit or 8 byte wide + localparam int unsigned CapabilitySizeByte = 32'd8; + // Number of capability bytes a single TL word in the meta store can track + localparam int unsigned CapabilityBytePerWord = top_pkg::TL_DW * CapabilitySizeByte; + + // Size of the TRVK revocation bitmap + localparam addr_t RevBmSizeWord = (MainSramTopAddr - MainSramBaseAddr) / RevocationBytePerWord; + localparam addr_t RevBmSizeByte = RevBmSizeWord * (top_pkg::TL_DW / 32'd8); + // Size of the SRAM tag store + localparam addr_t SramTagSizeWord = (MainSramTopAddr - MainSramBaseAddr) / CapabilityBytePerWord; + localparam addr_t SramTagSizeByte = SramTagSizeWord * (top_pkg::TL_DW / 32'd8); + // Size of the NVM tag store + localparam addr_t NvmTagSizeWord = (NvmTopAddr - NvmBaseAddr) / CapabilityBytePerWord; + localparam addr_t NvmTagSizeByte = NvmTagSizeWord * (top_pkg::TL_DW / 32'd8); + + // Address map + localparam addr_t MetaRevBmBase = MetaSramBaseAddr; + localparam addr_t MetaNvmTagBase = MetaRevBmBase + RevBmSizeByte; + localparam addr_t MetaMainSramTagBase = MetaNvmTagBase + NvmTagSizeByte; + localparam addr_t MetaTop = MetaMainSramTagBase + SramTagSizeByte; + + typedef struct packed { + logic csr_intg; + logic tag_filter_fifo; + logic meta_sram_intg; + logic meta_sram_data_intg; + logic rwm_error; + } cheriot_fatal_error_t; + + ///////////// + // Signals // + ///////////// + + tlul_pkg::tl_h2d_t rmw_tl_h2d; + logic rmw_tag_h2d; + logic [4:0] rmw_bit_sel; + tlul_pkg::tl_d2h_t rmw_tl_d2h; + logic rmw_tag_d2h; + + tlul_pkg::tl_h2d_t tags_tl_h2d; + tlul_pkg::tl_d2h_t tags_tl_d2h; + + tlul_pkg::tl_h2d_t meta_mux_in_tl_h2d[32'd3]; + tlul_pkg::tl_d2h_t meta_mux_in_tl_d2h[32'd3]; + + cheriot_regs_reg2hw_t reg2hw; + + logic alert_test; + + // Fatal errors + cheriot_fatal_error_t cheriot_fatal_error; + + + ////////////// + // CSR Node // + ////////////// + + cheriot_regs_reg_top u_reg_regs ( + .clk_i, + .rst_ni, + .tl_i (regs_tl_d_i), + .tl_o (regs_tl_d_o), + .reg2hw, + // SEC_CM: BUS.INTEGRITY + .intg_err_o(cheriot_fatal_error.csr_intg) + ); + + + //////////// + // Filter // + //////////// + + cheriot_access_check #( + .addr_t(addr_t), + .CheriotBaseAddr(MetaRevBmBase), + .CheriotTopAddr(MetaNvmTagBase), + .CheriotSubWordAllowed(1'b0) + ) u_cheriot_access_check_trvk ( + .clk_i, + .rst_ni, + .cheriot_ena_i, + .tl_h_i(corerevbm_tl_i), + .tl_h_o(corerevbm_tl_o), + .tl_d_o(meta_mux_in_tl_h2d[32'd0]), + .tl_d_i(meta_mux_in_tl_d2h[32'd0]) + ); + + cheriot_tag_filter #( + .NumOutstanding(32'd2), + .addr_t(addr_t), + .MainSramBaseAddr(MainSramBaseAddr), + .MainSramTopAddr(MainSramTopAddr), + .NvmBaseAddr(NvmBaseAddr), + .NvmTopAddr(NvmTopAddr), + .MetaMainSramTagBase(MetaMainSramTagBase), + .MetaNvmTagBase(MetaNvmTagBase) + ) u_cheriot_tag_filter ( + .clk_i, + .rst_ni, + .cheriot_ena_i, + .tl_d_i (cored_tl_d_i), + .tag_d_i (cored_tag_h2d_i), + .tl_d_o (cored_tl_d_o), + .tag_d_o (cored_tag_d2h_o), + .tl_m_o (rmw_tl_h2d), + .tag_m_o (rmw_tag_h2d), + .bit_sel_m_o (rmw_bit_sel), + .tl_m_i (rmw_tl_d2h), + .tag_m_i (rmw_tag_d2h), + .tl_h_o (cored_tl_h_o), + .tl_h_i (cored_tl_h_i), + .fifo_err_o (cheriot_fatal_error.tag_filter_fifo) + ); + + // SEC_CM: BUS.INTEGRITY + cheriot_rmw_filter #( + .addr_t(addr_t) + ) u_cheriot_rmw_filter ( + .clk_i, + .rst_ni, + .tl_h_i (rmw_tl_h2d), + .tag_h_i (rmw_tag_h2d), + .bit_sel_h_i (rmw_bit_sel), + .tl_h_o (rmw_tl_d2h), + .tag_h_o (rmw_tag_d2h), + .tl_d_o (tags_tl_h2d), + .tl_d_i (tags_tl_d2h), + .data_intg_error_o(cheriot_fatal_error.meta_sram_data_intg), + .rsp_intg_error_o (cheriot_fatal_error.meta_sram_intg), + .device_error_o (cheriot_fatal_error.rwm_error) + ); + + cheriot_access_check #( + .addr_t(addr_t), + .CheriotBaseAddr(MetaNvmTagBase), + .CheriotTopAddr(MetaTop), + .CheriotSubWordAllowed(1'b0) + ) u_cheriot_access_check_tags ( + .clk_i, + .rst_ni, + .cheriot_ena_i, + .tl_h_i(tags_tl_h2d), + .tl_h_o(tags_tl_d2h), + .tl_d_o(meta_mux_in_tl_h2d[32'd1]), + .tl_d_i(meta_mux_in_tl_d2h[32'd1]) + ); + + cheriot_access_check #( + .addr_t(addr_t), + .CheriotBaseAddr(MetaRevBmBase), + .CheriotTopAddr(MetaNvmTagBase), + .CheriotSubWordAllowed(1'b0) + ) u_cheriot_access_check_sys ( + .clk_i, + .rst_ni, + .cheriot_ena_i, + .tl_h_i(revbm_tl_d_i), + .tl_h_o(revbm_tl_d_o), + .tl_d_o(meta_mux_in_tl_h2d[32'd2]), + .tl_d_i(meta_mux_in_tl_d2h[32'd2]) + ); + + + /////////////////////// + // Meta multiplexing // + /////////////////////// + + tlul_socket_m1 #( + .M(32'd3), + .HReqDepth('0), + .HRspDepth('0), + .DReqDepth('0), + .DRspDepth('0) + ) u_tlul_socket_m1 ( + .clk_i, + .rst_ni, + .tl_h_i(meta_mux_in_tl_h2d), + .tl_h_o(meta_mux_in_tl_d2h), + .tl_d_o(meta_sram_tl_o), + .tl_d_i(meta_sram_tl_i) + ); + + + ////////////////// + // Alert Sender // + ////////////////// + + assign alert_test = reg2hw.alert_test.q & reg2hw.alert_test.qe; + + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[0]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1) + ) u_prim_alert_sender_fatal_fault ( + .clk_i, + .rst_ni, + .alert_test_i (alert_test), + .alert_req_i (|cheriot_fatal_error), + .alert_ack_o (), + .alert_state_o (), + .alert_rx_i (alert_rx_i[0]), + .alert_tx_o (alert_tx_o[0]) + ); + + + //////////////// + // Assertions // + //////////////// + + // Device ports: handshake signals are always known, the payload only while it is valid. + `ASSERT_KNOWN(CoredTlDAReadyKnown_A, cored_tl_d_o.a_ready) + `ASSERT_KNOWN(CoredTlDDValidKnown_A, cored_tl_d_o.d_valid) + `ASSERT_KNOWN_IF(CoredTlDPayloadKnown_A, cored_tl_d_o, cored_tl_d_o.d_valid) + `ASSERT_KNOWN(CoredTagD2hKnown_A, cored_tag_d2h_o) + + `ASSERT_KNOWN(CoreRevBmAReadyKnown_A, corerevbm_tl_o.a_ready) + `ASSERT_KNOWN(CoreRevBmDValidKnown_A, corerevbm_tl_o.d_valid) + `ASSERT_KNOWN_IF(CoreRevBmPayloadKnown_A, corerevbm_tl_o, corerevbm_tl_o.d_valid) + + `ASSERT_KNOWN(RevBmTlDAReadyKnown_A, revbm_tl_d_o.a_ready) + `ASSERT_KNOWN(RevBmTlDDValidKnown_A, revbm_tl_d_o.d_valid) + `ASSERT_KNOWN_IF(RevBmTlDPayloadKnown_A, revbm_tl_d_o, revbm_tl_d_o.d_valid) + + // Host ports: handshake signals are always known, the payload only while the request is valid. + `ASSERT_KNOWN(CoredTlHAValidKnown_A, cored_tl_h_o.a_valid) + `ASSERT_KNOWN(CoredTlHDReadyKnown_A, cored_tl_h_o.d_ready) + `ASSERT_KNOWN_IF(CoredTlHPayloadKnown_A, cored_tl_h_o, cored_tl_h_o.a_valid) + + `ASSERT_KNOWN(MetaSramAValidKnown_A, meta_sram_tl_o.a_valid) + `ASSERT_KNOWN(MetaSramDReadyKnown_A, meta_sram_tl_o.d_ready) + `ASSERT_KNOWN_IF(MetaSramPayloadKnown_A, meta_sram_tl_o, meta_sram_tl_o.a_valid) + + `ASSERT_KNOWN(RegsTlDAReadyKnown_A, regs_tl_d_o.a_ready) + `ASSERT_KNOWN(RegsTlDDValidKnown_A, regs_tl_d_o.d_valid) + `ASSERT_KNOWN_IF(RegsTlDPayloadKnown_A, regs_tl_d_o, regs_tl_d_o.d_valid) + + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + + `ASSERT_PRIM_FIFO_SYNC_ERROR_TRIGGERS_ALERT(CheriotTagFilterFifo_A, + u_cheriot_tag_filter.u_prim_fifo_sync_align, + alert_tx_o[0]) + + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegsWeOnehotCheck_A, + u_reg_regs, alert_tx_o[0]) + +endmodule diff --git a/hw/ip/cheriot/rtl/cheriot_access_check.sv b/hw/ip/cheriot/rtl/cheriot_access_check.sv new file mode 100644 index 0000000000000..540cdce810f1c --- /dev/null +++ b/hw/ip/cheriot/rtl/cheriot_access_check.sv @@ -0,0 +1,119 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module cheriot_access_check #( + // TL-UL address type + parameter type addr_t = logic [top_pkg::TL_AW-1:0], + // Start address (inclusive) + parameter addr_t CheriotBaseAddr = 'h0, + // End address (non-inclusive) + parameter addr_t CheriotTopAddr = 'h1, + // Are we allowed to `PutPartialData` in CHERIoT mode? + parameter bit CheriotSubWordAllowed = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + // CHERIoT mode enabled + input prim_mubi_pkg::mubi4_t cheriot_ena_i, + + // TL host port + input tlul_pkg::tl_h2d_t tl_h_i, + output tlul_pkg::tl_d2h_t tl_h_o, + + // TL device port + output tlul_pkg::tl_h2d_t tl_d_o, + input tlul_pkg::tl_d2h_t tl_d_i +); + + import tlul_pkg::*; + + + ///////////// + // Signals // + ///////////// + + tlul_pkg::tl_h2d_t tl_demux_h2d[32'd2]; + tlul_pkg::tl_d2h_t tl_demux_d2h[32'd2]; + + tlul_pkg::tl_h2d_t tl_err_h2d; + tlul_pkg::tl_d2h_t tl_err_d2h; + + logic allow_forward; + logic allowed_operation; + + + //////////////////// + // Access Checker // + //////////////////// + + // SEC_CM: MEM.SW_NOACCESS, INTERSIG.MUBI + always_comb begin: proc_allow_forward + + // Default: do not forward + allow_forward = 1'b0; + allowed_operation = 1'b0; + + // CHERIoT mode enabled + if(prim_mubi_pkg::mubi4_test_true_strict(cheriot_ena_i)) begin + + // Check whether we have a valid operation + allowed_operation = CheriotSubWordAllowed ? + tl_h_i.a_opcode inside {PutFullData, PutPartialData, Get} : + tl_h_i.a_opcode inside {PutFullData, Get}; + + // Forward if address range is valid, operation is allowed, and we can use the device in + // the currently active mode. + allow_forward = tl_h_i.a_address >= CheriotBaseAddr && + tl_h_i.a_address < CheriotTopAddr && + allowed_operation; + + // CHERIoT mode disabled: no access + end else if (prim_mubi_pkg::mubi4_test_false_strict(cheriot_ena_i)) begin + allow_forward = 1'b0; + + // Something else; redirect to error response + end else begin + allow_forward = 1'b0; + end + end + + + /////////////// + // TL Muxing // + /////////////// + + tlul_socket_1n #( + .N(32'd2), + .HReqDepth('h0), + .HRspDepth('h0), + .DReqDepth('h0), + .DRspDepth('h0), + .ExplicitErrs(1'b0) + ) u_tlul_socket_1n ( + .clk_i, + .rst_ni, + .tl_h_i ( tl_h_i ), + .tl_h_o ( tl_h_o ), + .tl_d_o ( tl_demux_h2d ), + .tl_d_i ( tl_demux_d2h ), + .dev_select_i( !allow_forward ) + ); + + assign tl_d_o = tl_demux_h2d[0]; + assign tl_err_h2d = tl_demux_h2d[1]; + + assign tl_demux_d2h[0] = tl_d_i; + assign tl_demux_d2h[1] = tl_err_d2h; + + tlul_err_resp #( + .ReturnBlankResp(1'b0) + ) u_tlul_err_resp ( + .clk_i, + .rst_ni, + .tl_h_i(tl_err_h2d), + .tl_h_o(tl_err_d2h) + ); + +endmodule diff --git a/hw/ip/cheriot/rtl/cheriot_reg_pkg.sv b/hw/ip/cheriot/rtl/cheriot_reg_pkg.sv new file mode 100644 index 0000000000000..1e1a5e0de58d5 --- /dev/null +++ b/hw/ip/cheriot/rtl/cheriot_reg_pkg.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package cheriot_reg_pkg; + + // Param list + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int RegsAw = 2; + + // Number of registers for every interface + parameter int NumRegsRegs = 1; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0 + } cheriot_alert_idx_t; + + /////////////////////////////////////////////// + // Typedefs for registers for regs interface // + /////////////////////////////////////////////// + + typedef struct packed { + logic q; + logic qe; + } cheriot_reg2hw_alert_test_reg_t; + + // Register -> HW type for regs interface + typedef struct packed { + cheriot_reg2hw_alert_test_reg_t alert_test; // [1:0] + } cheriot_regs_reg2hw_t; + + // Register offsets for regs interface + parameter logic [RegsAw-1:0] CHERIOT_ALERT_TEST_OFFSET = 2'h 0; + + // Reset values for hwext registers and their fields for regs interface + parameter logic [0:0] CHERIOT_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] CHERIOT_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + + // Register index for regs interface + typedef enum int { + CHERIOT_ALERT_TEST + } cheriot_regs_id_e; + + // Register width information to check illegal writes for regs interface + parameter logic [3:0] CHERIOT_REGS_PERMIT [1] = '{ + 4'b 0001 // index[0] CHERIOT_ALERT_TEST + }; + +endpackage diff --git a/hw/ip/cheriot/rtl/cheriot_regs_reg_top.sv b/hw/ip/cheriot/rtl/cheriot_regs_reg_top.sv new file mode 100644 index 0000000000000..d3932b97b7bed --- /dev/null +++ b/hw/ip/cheriot/rtl/cheriot_regs_reg_top.sv @@ -0,0 +1,213 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module cheriot_regs_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output cheriot_reg_pkg::cheriot_regs_reg2hw_t reg2hw, // Write + + // Integrity check errors + output logic intg_err_o +); + + import cheriot_reg_pkg::* ; + + localparam int AW = 2; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [0:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(1) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_wd; + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + + logic [0:0] addr_hit; + always_comb begin + addr_hit[0] = (reg_addr == CHERIOT_ALERT_TEST_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[0] & (|(CHERIOT_REGS_PERMIT[0] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = alert_test_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/ip/cheriot/rtl/cheriot_rmw_filter.sv b/hw/ip/cheriot/rtl/cheriot_rmw_filter.sv new file mode 100644 index 0000000000000..ac98c1f2da584 --- /dev/null +++ b/hw/ip/cheriot/rtl/cheriot_rmw_filter.sv @@ -0,0 +1,367 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module cheriot_rmw_filter #( + // TL-UL address type + parameter type addr_t = logic [top_pkg::TL_AW-1:0] +) ( + input logic clk_i, + input logic rst_ni, + + // Host port + input tlul_pkg::tl_h2d_t tl_h_i, + input logic tag_h_i, + input logic [4:0] bit_sel_h_i, + output tlul_pkg::tl_d2h_t tl_h_o, + output logic tag_h_o, + + // Device port + output tlul_pkg::tl_h2d_t tl_d_o, + input tlul_pkg::tl_d2h_t tl_d_i, + + // Error signals + output logic data_intg_error_o, + output logic rsp_intg_error_o, + output logic device_error_o +); + + /////////// + // Types // + /////////// + + // The padding to 57 bit of the BM response fields subject to ECC + localparam int unsigned RspIntgPadding = tlul_pkg::D2HRspMaxWidth - + $bits(tlul_pkg::tl_d2h_rsp_intg_t); + + typedef enum logic [1:0] { + Passthrough = 2'h0, + Fill = 2'h1, + WriteBackReq = 2'h2, + WriteBackAck = 2'h3 + } bit_rmw_state_e; + + + ///////////// + // Signals // + ///////////// + + bit_rmw_state_e state_d, state_q; + + // Signals concerning the multiplexing of the TL-UL H2D requests + logic forward_r_req; + logic emit_r_req; + logic emit_w_req; + + // Signals concerning the multiplexing of the TL-UL H2D responses + logic ack_fill; + logic ack_skip; + logic ack_write_back; + + // We need to keep track of ongoing reads + logic is_read_d, is_read_q; + + // We need to store the metadata address and bit index of the access + addr_t meta_addr_q; + logic [4:0] bit_sel_q; + + // Metadata address of the operation currently driven towards the device + addr_t addr_sel; + + // We need to store whether a capability write had a valid tag bit + logic tag_q; + + // We need to store the word read before writing it back modified + logic [31:0] word_q; + + // Helper signals + logic skip_write_back; + logic update_word; + + // Device response ECC signals + tlul_pkg::tl_d2h_rsp_intg_t rsp_intg; + logic [1:0] rsp_intg_error; + logic [1:0] rsp_data_intg_error; + + + //////////////////// + // Helper Signals // + //////////////////// + + // We can skip the write back operation if the tag to be written matches the current state + assign skip_write_back = tl_d_i.d_data[bit_sel_q] == tag_q; + + + ///////////////// + // Control FSM // + ///////////////// + + always_comb begin : proc_rwm_fsm + + // state stays stable + state_d = state_q; + + forward_r_req = 1'b0; + emit_r_req = 1'b0; + emit_w_req = 1'b0; + + ack_fill = 1'b0; + ack_skip = 1'b0; + ack_write_back = 1'b0; + + is_read_d = 1'b0; + update_word = 1'b0; + + unique case(state_q) + + // The pass-through state allows reads to just be forwarded. Should a properly handshaked + // write arrive request pass, we switch to the Fill state. + Passthrough: begin + if(tl_h_i.a_opcode == tlul_pkg::PutFullData || + tl_h_i.a_opcode == tlul_pkg::PutPartialData) begin + emit_r_req = 1'b1; + if(tl_h_i.a_valid && tl_h_o.a_ready) begin + state_d = Fill; + end + end else if(tl_h_i.a_opcode == tlul_pkg::Get) begin + forward_r_req = 1'b1; + is_read_d = 1'b1; + end + end + + // In fill, we check whether the read data matches the capability bit we intend to write. If + // so, we can omit the write back and return back to pass-through. If not, we have to do + // the modification followed by the write back. + Fill: begin + if(tl_d_i.d_valid) begin + // We don't have to do anything more + if(skip_write_back) begin + ack_skip = 1'b1; + if(tl_h_i.d_ready) begin + state_d = Passthrough; + end + // An update of the SRAM state is required + end else begin + ack_fill = 1'b1; + update_word = 1'b1; + state_d = WriteBackReq; + end + end + end + + // We emit a write request towards the device carrying the updated state. + WriteBackReq: begin + emit_w_req = 1'b1; + if(tl_d_i.a_ready) begin + state_d = WriteBackAck; + end + end + + // We acknowledge the write response from the device and forward it to the host. We are now + // done with the RWM operation and can return to pass-through. + WriteBackAck: begin + ack_write_back = 1'b1; + if(tl_d_i.d_valid && tl_h_i.d_ready) begin + state_d = Passthrough; + end + end + + default:; + endcase + end + + // An enable-FF storing the meta data. This state is updated whenever the host gets a + // request handshaked. + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_request_meta_store + if(!rst_ni) begin + meta_addr_q <= '0; + bit_sel_q <= '0; + tag_q <= 1'b0; + end else begin + if (tl_h_i.a_valid && tl_h_o.a_ready) begin + meta_addr_q <= tl_h_i.a_address; + bit_sel_q <= bit_sel_h_i; + tag_q <= tag_h_i; + end + end + end + + // This enable FF, stores the current state before the modification in the fill state should an + // update be required. + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_word_store + if(!rst_ni) begin + word_q <= '0; + end else begin + if (update_word) begin + word_q <= tl_d_i.d_data; + end + end + end + + // This synchronously clearable, enable FF, stores the state of an ongoing read transaction. + // If clears the state on every completed ack towards the host. It is set on handshaking a + // host read request. + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_read_ongoing_flop + if(!rst_ni) begin + is_read_q <= 1'b0; + end else begin + if (tl_h_o.d_valid && tl_h_i.d_ready) begin + is_read_q <= 1'b0; + end else if (tl_h_i.a_valid && tl_h_o.a_ready) begin + is_read_q <= is_read_d; + end + end + end + + // The state can be updated every cycle + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_fsm_state_store + if(!rst_ni) begin + state_q <= Passthrough; + end else begin + state_q <= state_d; + end + end + + + ///////////////////// + // TL Multiplexing // + ///////////////////// + + // This process is really crammed as a side effect of bundling handshaking and (meta) data signals + // in a single request and response struct. We thus combine here handshaking and data + // multiplexing. + always_comb begin : proc_tl_muxing + + // Default pass-through for all transport signals (except handshaking) + tl_h_o = tl_d_i; + tl_d_o = tl_h_i; + + // Invalid capability as a default + tag_h_o = 1'b0; + + // Inert handshaking is the default + tl_h_o.d_valid = 1'b0; + tl_d_o.a_valid = 1'b0; + tl_h_o.a_ready = 1'b0; + tl_d_o.d_ready = 1'b0; + + // In the case of a read, we just forward the request. We only modify the address to + // point to the word in meta memory holding the capability. + if(forward_r_req) begin + // We are in pass-through case and a request arrives -> we forward it + // but we ensure we divide the address by 64 as one request can track 32 + // capabilities or 64 words. + tl_d_o.a_address = addr_sel; + // Recalculate the command integrity as we have modified the address + tl_d_o.a_user.cmd_intg = tlul_pkg::get_cmd_intg(tl_d_o); + tl_d_o.a_valid = tl_h_i.a_valid; + tl_h_o.a_ready = tl_d_i.a_ready; + + // In the case of a write, we first emit a word read towards meta memory, by forwarding + // a the modified upstream write request, to check whether the corresponding + // capability tag is set. + end else if(emit_r_req) begin + tl_d_o = tlul_pkg::TL_H2D_DEFAULT; + tl_d_o.a_address = addr_sel; + tl_d_o.a_opcode = tlul_pkg::Get; + tl_d_o.a_size = 'd2; + tl_d_o.a_mask = '1; + tl_d_o.a_user.cmd_intg = tlul_pkg::get_cmd_intg(tl_d_o); + tl_d_o.a_user.data_intg = tlul_pkg::get_data_intg(tl_d_o.a_data); + tl_d_o.a_valid = tl_h_i.a_valid; + tl_h_o.a_ready = tl_d_i.a_ready; + + // In the case of a write that modifies state, we eventually need to emit a new write. Here we + // don't have to handshake the upstream host request interface. + end else if(emit_w_req) begin + tl_d_o = tlul_pkg::TL_H2D_DEFAULT; + tl_d_o.a_address = addr_sel; + tl_d_o.a_opcode = tlul_pkg::PutFullData; + tl_d_o.a_size = 'd2; + tl_d_o.a_mask = '1; + tl_d_o.a_data = word_q; + tl_d_o.a_data[bit_sel_q] = tag_q; + tl_d_o.a_user.cmd_intg = tlul_pkg::get_cmd_intg(tl_d_o); + tl_d_o.a_user.data_intg = tlul_pkg::get_data_intg(tl_d_o.a_data); + tl_d_o.a_valid = 1'b1; + end + + // In the read case, we return the read response. The corresponding capability tag bit is + // placed on the host's output tag interface. + if(is_read_q) begin + tl_h_o.d_valid = tl_d_i.d_valid; + tl_d_o.d_ready = tl_h_i.d_ready; + tag_h_o = tl_d_i.d_data[bit_sel_q] && !tl_d_i.d_error; + + // We have translated a write request into a read request to inquire the state of the + // tag word. Checking the capability bit, we notice that we don't have to perform an update. + // We thus translate the read response from the meta device into a write response. + end else if(ack_skip) begin + tl_h_o.d_opcode = tlul_pkg::AccessAck; + tl_d_o.d_ready = tl_h_i.d_ready; + tl_h_o.d_valid = 1'b1; + + // When performing a fill and update, we need to acknowledge the downstream device transaction + // without acknowledging the host's response. + end else if(ack_fill) begin + tl_d_o.d_ready = 1'b1; + + // A write back answer arrives from the device; we forward this to the host. + end else if(ack_write_back) begin + tl_h_o.d_valid = tl_d_i.d_valid; + tl_d_o.d_ready = tl_h_i.d_ready; + end + end + + + /////////////////////////// + // Response ECC Checking // + /////////////////////////// + + // Did we receive a device error? + assign device_error_o = tl_d_i.d_valid && tl_d_o.d_ready && tl_d_i.d_error; + + // Get the response fields subject to ECC + assign rsp_intg = tlul_pkg::extract_d2h_rsp_intg(tl_d_i); + + // Check the bitmap response integrity + // SEC_CM: BUS.INTEGRITY + prim_secded_inv_64_57_dec u_prim_secded_inv_64_57_dec_rsp ( + .data_i ({tl_d_i.d_user.rsp_intg, {RspIntgPadding{1'b0}}, rsp_intg}), + .data_o (/*Not Connected*/), + .syndrome_o(/*Not Connected*/), + .err_o (rsp_intg_error) + ); + + // Mask response integrity error if response is not being handshaked + assign rsp_intg_error_o = tl_d_i.d_valid && tl_d_o.d_ready && (|rsp_intg_error); + + // Check the device response data integrity + // SEC_CM: BUS.INTEGRITY + prim_secded_inv_39_32_dec u_prim_secded_inv_39_32_dec_rsp_data ( + .data_i ({tl_d_i.d_user.data_intg, tl_d_i.d_data}), + .data_o (/*Not Connected*/), + .syndrome_o(/*Not Connected*/), + .err_o (rsp_data_intg_error) + ); + + // Mask response integrity error if response is not being handshaked + assign data_intg_error_o = tl_d_i.d_valid && tl_d_o.d_ready && (|rsp_data_intg_error); + + + //////////////////////// + // Metadata Address // + //////////////////////// + + always_comb begin: proc_addr_sel + // select either the address of the currently active host request or the stored value + addr_sel = '0; + + if(forward_r_req || emit_r_req) begin + addr_sel = tl_h_i.a_address; + end else if(emit_w_req) begin + addr_sel = meta_addr_q; + end + end + +endmodule diff --git a/hw/ip/cheriot/rtl/cheriot_tag_filter.sv b/hw/ip/cheriot/rtl/cheriot_tag_filter.sv new file mode 100644 index 0000000000000..aae6410c0b7e9 --- /dev/null +++ b/hw/ip/cheriot/rtl/cheriot_tag_filter.sv @@ -0,0 +1,306 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "prim_assert.sv" + +module cheriot_tag_filter #( + // The number of outstanding TL transaction the IP supports + parameter int unsigned NumOutstanding = 32'd4, + // TL-UL address type + parameter type addr_t = logic [top_pkg::TL_AW-1:0], + // Memory regions that have a capability tag store + parameter addr_t MainSramBaseAddr = 'h1000_0000, + parameter addr_t MainSramTopAddr = 'h1002_0000, + parameter addr_t NvmBaseAddr = 'h2000_0000, + parameter addr_t NvmTopAddr = 'h2020_0000, + // Base addresses of the corresponding tag regions in the meta SRAM + parameter addr_t MetaMainSramTagBase = 'h0, + parameter addr_t MetaNvmTagBase = 'h0 +)( + input clk_i, + input rst_ni, + + // CHERIoT mode enabled + input prim_mubi_pkg::mubi4_t cheriot_ena_i, + + // Device port + input tlul_pkg::tl_h2d_t tl_d_i, + input logic tag_d_i, + output tlul_pkg::tl_d2h_t tl_d_o, + output logic tag_d_o, + + // Meta port + output tlul_pkg::tl_h2d_t tl_m_o, + output logic tag_m_o, + output logic [4:0] bit_sel_m_o, + input tlul_pkg::tl_d2h_t tl_m_i, + input logic tag_m_i, + + // Host port + output tlul_pkg::tl_h2d_t tl_h_o, + input tlul_pkg::tl_d2h_t tl_h_i, + + output logic fifo_err_o +); + + /////////// + // Types // + /////////// + + // The meta data type handed between the host's request and response channel + typedef struct packed { + logic cap_store; + logic cap; + logic aligned; + logic has_tag; + } req_rsp_meta_t; + + // The fields of an access address that locate its capability tag. + typedef struct packed { + logic [31:8] meta_word; + logic [7:3] bit_sel; + logic [2:0] rsvd; + } meta_addr_t; + + + ///////////// + // Signals // + ///////////// + + // Request handshaking signals + logic tl_d_req_ready; + logic tl_m_req_valid; + logic tl_h_req_valid; + + // Input port of the meta FIFO + logic meta_req_valid; + logic meta_req_ready; + req_rsp_meta_t meta_req; + + // Output port of the meta FIFO + logic meta_rsp_valid; + logic meta_rsp_ready; + req_rsp_meta_t meta_rsp; + + // Whether we need to lookup or fork into the meta memory + logic require_lookup; + // Whether we need to join a meta lookup + logic require_join; + + // Response handshaking signals + logic tl_d_rsp_valid; + logic tl_h_rsp_ready; + logic tl_m_rsp_ready; + + // Unused meta response signals + logic unused_m_rsp; + + // Tag bit store. We only do the lookup on the lower word of a capability to safe + // bandwidth into the meta memory. For the directly following meta word, we store + // the capability + logic tag_d_d, tag_d_q; + + logic tl_d_is_read; + logic tl_d_is_write; + logic tl_d_is_aligned; + + // Offset of the access within its tagged region, and whether it is in one at all + meta_addr_t addr_stem; + addr_t meta_addr; + logic addr_tagged; + + // Unused address signals + logic unused_addr; + + + ////////// + // Fork // + ////////// + + assign tl_d_is_read = tl_d_i.a_opcode == tlul_pkg::Get; + assign tl_d_is_write = tl_d_i.a_opcode == tlul_pkg::PutFullData || + tl_d_i.a_opcode == tlul_pkg::PutPartialData; + assign tl_d_is_aligned = !tl_d_i.a_address[2]; + + /////////////////////// + // Address Remapping // + /////////////////////// + + // Check if access points to a capability-enabled region + always_comb begin: proc_address_remap + // defaults (an access outside every tagged region has no metadata) + addr_stem = '0; + meta_addr = '0; + addr_tagged = 1'b0; + + if(tl_d_i.a_address >= MainSramBaseAddr && tl_d_i.a_address < MainSramTopAddr) begin + addr_stem = tl_d_i.a_address - MainSramBaseAddr; + meta_addr = MetaMainSramTagBase + (addr_t'(addr_stem.meta_word) << 32'd2); + addr_tagged = 1'b1; + end else if(tl_d_i.a_address >= NvmBaseAddr && tl_d_i.a_address < NvmTopAddr) begin + addr_stem = tl_d_i.a_address - NvmBaseAddr; + meta_addr = MetaNvmTagBase + (addr_t'(addr_stem.meta_word) << 32'd2); + addr_tagged = 1'b1; + end + end + + assign bit_sel_m_o = addr_stem.bit_sel; + assign unused_addr = ^addr_stem.rsvd; + + // We need to perform a lookup on 64-bit-aligned reads where the host hints + // us a valid capability load or on any write. A lookup is only required if CHERIoT is enabled. + assign require_lookup = prim_mubi_pkg::mubi4_test_true_strict(cheriot_ena_i) ? + addr_tagged && // CHERIoT dev, + ((tl_d_is_read && // and: Read, + tl_d_is_aligned && // 64-bit-aligned, + tag_d_i) || // hinted cap + tl_d_is_write) : // or write + 1'b0; + + // We only fork the meta channel if a lookup is required + stream_fork_dynamic #( + .N_OUP(32'd3) + ) u_stream_fork_dynamic ( + .clk_i, + .rst_ni, + .valid_i ( tl_d_i.a_valid ), + .ready_o ( tl_d_req_ready ), + .sel_i ( {1'b1, require_lookup, 1'b1} ), + .sel_valid_i( tl_d_i.a_valid ), + .sel_ready_o( /* NOT CONNECTED */ ), + .valid_o ( {meta_req_valid, tl_m_req_valid, tl_h_req_valid} ), + .ready_i ( {meta_req_ready, tl_m_i.a_ready, tl_h_i.a_ready} ) + ); + + + //////////////// + // Meta Store // + //////////////// + + // Assemble meta data between host's request and response channel + assign meta_req = '{ + cap: tag_d_i, + aligned: tl_d_is_aligned, + cap_store: tl_d_is_write, + has_tag: addr_tagged + }; + + // SEC_CM: CTR.REDUN + prim_fifo_sync #( + .Width(32'd4), + .Pass(1'b0), + .Depth(NumOutstanding), + .NeverClears(1'b1), + .Secure(1'b1) + ) u_prim_fifo_sync_align ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .wvalid_i( meta_req_valid ), + .wready_o( meta_req_ready ), + .wdata_i ( meta_req ), + .rvalid_o( meta_rsp_valid ), + .rready_i( meta_rsp_ready ), + .rdata_o ( meta_rsp ), + .full_o ( ), + .depth_o ( ), + .err_o ( fifo_err_o ) + ); + + + ////////// + // Join // + ////////// + + // We need to join in the response from the meta SRAM if CHERIoT is enabled + // Ibex hints capability reads thus a join is requested through the `meta_rsp.cap` signal. + assign require_join = prim_mubi_pkg::mubi4_test_true_strict(cheriot_ena_i) ? + meta_rsp.has_tag && + (meta_rsp.cap_store || (meta_rsp.cap && meta_rsp.aligned)) : + 1'b0; + + stream_join_dynamic #( + .N_INP(32'd3) + ) u_stream_join_dynamic ( + .inp_valid_i( {meta_rsp_valid, tl_m_i.d_valid, tl_h_i.d_valid} ), + .inp_ready_o( {meta_rsp_ready, tl_m_rsp_ready, tl_h_rsp_ready} ), + .sel_i ( {1'b1, require_join, 1'b1} ), + .oup_valid_o( tl_d_rsp_valid ), + .oup_ready_i( tl_d_i.d_ready ) + ); + + + ////////////////////////// + // Stick Capability Tag // + ////////////////////////// + + assign tag_m_o = tag_d_i; + + always_comb begin: proc_sticky_tag_d_o + tag_d_d = tag_d_q; + tag_d_o = tag_d_q; + if(tl_d_o.d_valid && tl_d_i.d_ready) begin + if(meta_rsp.aligned) begin + tag_d_o = meta_rsp.has_tag && tag_m_i; + tag_d_d = meta_rsp.has_tag && tag_m_i; + end else begin + tag_d_d = 1'b0; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_store_r_cap_tag + if(!rst_ni) begin + tag_d_q <= 1'b0; + end else begin + tag_d_q <= tag_d_d; + end + end + + + //////////////////// + // TL connections // + //////////////////// + + // We forward the host requests to both endpoints + always_comb begin: proc_connect_tl_req + tl_h_o = tl_d_i; + tl_h_o.a_valid = tl_h_req_valid; + tl_h_o.d_ready = tl_h_rsp_ready; + + // We inject the meta address here + tl_m_o = tl_d_i; + tl_m_o.a_address = meta_addr; + tl_m_o.a_user.cmd_intg = tlul_pkg::get_cmd_intg(tl_m_o); + tl_m_o.a_valid = tl_m_req_valid; + tl_m_o.d_ready = tl_m_rsp_ready; + end + + // We disregard all of the meta SRAM response except for the tag bit and the error bit + always_comb begin: proc_connect_tl_rsp + tl_d_o = tl_h_i; + tl_d_o.d_error = tl_d_o.d_error || tl_m_i.d_error; + tl_d_o.a_ready = tl_d_req_ready; + tl_d_o.d_valid = tl_d_rsp_valid; + end + + // The response and data integrity is not checked, as both the RMW and the tag filter are + // lock-stepped. + assign unused_m_rsp = ^{tl_m_i.d_data, + tl_m_i.d_opcode, + tl_m_i.d_param, + tl_m_i.d_sink, + tl_m_i.d_size, + tl_m_i.d_source, + tl_m_i.d_user + }; + + //////////////// + // Assertions // + //////////////// + + // Meta FIFO has to be valid when device port handshakes its response + `ASSERT(MetaRspValidOnDHs_A, (tl_d_o.d_valid && tl_d_i.d_ready) |-> meta_rsp_valid) + +endmodule diff --git a/hw/ip/rv_core_ibex/cheriot_switch.core b/hw/ip/rv_core_ibex/cheriot_switch.core new file mode 100644 index 0000000000000..cf29275f80840 --- /dev/null +++ b/hw/ip/rv_core_ibex/cheriot_switch.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:cheriot_switch:0.1" +description: "Write-once ePMP/CHERIoT execution mode switch" +filesets: + files_rtl: + depend: + - lowrisc:prim:all + - lowrisc:prim:mubi + + files: + - rtl/cheriot_switch.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/rv_core_ibex/rtl/cheriot_switch.sv b/hw/ip/rv_core_ibex/rtl/cheriot_switch.sv new file mode 100644 index 0000000000000..84a3f705be0bd --- /dev/null +++ b/hw/ip/rv_core_ibex/rtl/cheriot_switch.sv @@ -0,0 +1,122 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Write-once ePMP/CHERIoT execution mode switch. +// +// The FSM resets unlocked and advances on the first write to the lock register. Once locked it +// reports the selected mode until reset; an invalid lock/enable combination or an invalid state +// encoding lands in the terminal error state, which reports ePMP mode. + +`include "prim_assert.sv" + +module cheriot_switch + import prim_mubi_pkg::*; +( + input logic clk_i, + input logic rst_ni, + + input mubi4_t ena_i, + input mubi4_t lock_i, + input logic lock_access_i, + output mubi4_t ena_o, + + output logic error_o +); + + // Encoding generated at commit feacd8763c using Python 3.12.13 with: + // $ ./util/design/sparse-fsm-encode.py --language=sv \ + // --seed 492361 --distance 4 --states 4 --bits 6 + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: |||||||||||||||||||| (100.00%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 4 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 5 + // + localparam int SwitchStateWidth = 6; + typedef enum logic [SwitchStateWidth-1:0] { + Unlocked = 6'b010110, + LockedEna = 6'b100101, + LockedDis = 6'b111011, + Error = 6'b001000 + } switch_state_e; + + switch_state_e switch_state_d, switch_state_q; + + always_comb begin : proc_switch_fsm + + // Default assignments + switch_state_d = Error; + error_o = 1'b0; + ena_o = MuBi4False; + + unique case (switch_state_q) + + // We reset in unlocked + Unlocked: begin + + // The FSM advanced iff the lock register is written to + if (lock_access_i) begin + // If the proper lock value is written and we enable CHERIoT -> Enable state + if (mubi4_test_true_strict(lock_i) && mubi4_test_true_strict(ena_i)) begin + switch_state_d = LockedEna; + // If the proper lock value is written and we disable CHERIoT -> Disable state + end else if (mubi4_test_true_strict(lock_i) && mubi4_test_false_strict(ena_i)) begin + switch_state_d = LockedDis; + // Otherwise we drop into the error state + end else begin + switch_state_d = Error; + end + + // The lock register is not written to, we remain unlocked + end else begin + switch_state_d = Unlocked; + end + end + + LockedEna: begin + switch_state_d = LockedEna; + ena_o = MuBi4True; + end + + LockedDis: begin + switch_state_d = LockedDis; + ena_o = MuBi4False; + end + + // Enable set to MuBi4False is the proper state on error, this means we remain in ePMP mode + // which is secure at the stage of the switch. + Error: begin + switch_state_d = Error; + ena_o = MuBi4False; + error_o = 1'b1; + end + + default: begin + switch_state_d = Error; + ena_o = MuBi4False; + error_o = 1'b1; + end + endcase + end + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, switch_state_d, switch_state_q, switch_state_e, Unlocked) + + //////////////// + // Assertions // + //////////////// + + `ASSERT_KNOWN(EnaKnown_A, ena_o) + `ASSERT_KNOWN(ErrorKnown_A, error_o) + +endmodule diff --git a/hw/ip/sram_ctrl/data/sram_ctrl.hjson b/hw/ip/sram_ctrl/data/sram_ctrl.hjson index a04ec8e3bd710..56fcfc67833a3 100644 --- a/hw/ip/sram_ctrl/data/sram_ctrl.hjson +++ b/hw/ip/sram_ctrl/data/sram_ctrl.hjson @@ -107,6 +107,13 @@ expose: "true", default: "3" }, + { name: "NumAddrScrRounds", + desc: "Number of address scrambling rounds. 0 disables address scrambling", + type: "int", + local: "false", + expose: "true", + default: "2" + }, { name: "Outstanding", desc: "Number of outstanding TLUL transactions", type: "int", diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv index 5bc503a91b075..4c8dc6f8bef12 100644 --- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv +++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv @@ -26,6 +26,8 @@ module sram_ctrl // PRINCE has 5 half rounds in its original form, which corresponds to 2*5 + 1 effective rounds. // Setting this to 3 lowers this to approximately 7 effective rounds. parameter int NumPrinceRoundsHalf = 3, + // Number of address scrambling rounds. Setting this to 0 disables address scrambling. + parameter int NumAddrScrRounds = 2, // Number of outstanding TLUL transfers parameter int Outstanding = 2, // Enable single-bit error correction and error logging @@ -682,7 +684,8 @@ module sram_ctrl .InstDepth(InstDepth), .EnableParity(0), .DataBitsPerMask(DataWidth), - .NumPrinceRoundsHalf(NumPrinceRoundsHalf) + .NumPrinceRoundsHalf(NumPrinceRoundsHalf), + .NumAddrScrRounds(NumAddrScrRounds) ) u_prim_ram_1p_scr ( .clk_i, .rst_ni, diff --git a/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl b/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl index 41fbd34acaaeb..8ab7a1df4cd5e 100644 --- a/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl +++ b/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl @@ -46,7 +46,9 @@ ], bus_interfaces: [ { protocol: "tlul", direction: "host", name: "corei" } + % if not cheriot_available: { protocol: "tlul", direction: "host", name: "cored" } + % endif % if racl_support: { protocol: "tlul", direction: "device", name: "cfg", racl_support: true } % else: @@ -85,6 +87,53 @@ package: "", }, +% if cheriot_available: + { struct: "mubi4", + type: "uni", + name: "cheriot_ena", + act: "req", + package: "prim_mubi_pkg", + default: "prim_mubi_pkg::MuBi4False", + desc: "CHERIoT mode enable." + }, + + { struct: "tl", + type: "req_rsp", + name: "cored_tl_h", + act: "req", + package: "tlul_pkg", + desc: "Core data host port to CHERIoT subsystem" + }, + + { struct: "logic", + type: "uni", + name: "cored_tag_h2d", + act: "req", + width: "1", + package: "", + default: "1'b0", + desc: "CHERIoT capability tag carried with the A-channel of cored_h." + }, + + { struct: "logic", + type: "uni", + name: "cored_tag_d2h", + act: "rcv", + width: "1", + package: "", + default: "1'b0", + desc: "Capability tag returned on the D-channel of cored_h." + }, + + { struct: "tl", + type: "req_rsp", + name: "corerevbm_tl", + act: "req", + package: "tlul_pkg", + desc: "Core revocation bitmap host port" + }, + +% endif { struct: "ram_1p_cfg", type: "uni", name: "ram_cfg_icache_tag", @@ -357,6 +406,36 @@ local: "false" expose: "true" }, +% if cheriot_available: + { name: "BaseIsa" + type: "ibex_pkg::base_isa_e" + default: "ibex_pkg::BaseIsaRV32I" + desc: "Base ISA" + local: "false" + expose: "true" + }, + { name: "CheriotRevBitmapAddrWidth" + type: "int unsigned" + default: "9" + desc: "Address width of the TRVK revocation bitmap" + local: "false" + expose: "true" + }, + { name: "CheriotRevBitmapBaseAddr" + type: "int unsigned" + default: "0" + desc: "Base address of the TRVK revocation bitmap" + local: "false" + expose: "true" + }, + { name: "CheriotTrvkHeapBaseAddr" + type: "int unsigned" + default: "0" + desc: "Base address of the heap" + local: "false" + expose: "true" + }, +% endif { name: "RV32E" type: "bit" default: "0" @@ -693,6 +772,13 @@ { name: "ICACHE.MEM.INTEGRITY" desc: "ICache memory integrity checking." } +% if cheriot_available: + { name: "CHERIOT_SWITCH.FSM.SPARSE" + desc: ''' + The write-once ePMP/CHERIoT execution mode switch FSM is sparsely encoded. + ''' + } +% endif ] regwidth: "32", @@ -1105,6 +1191,40 @@ ] }, + { name: "CHERIOT_ENA", + desc: ''' + Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). + ''', + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "3:0", + name: "VAL", + resval: "0x0" + desc: ''' + ''' + }, + ] + }, + + { name: "CHERIOT_LOCK", + desc: ''' + Locks the CHERIoT/ePMP mode. + If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. + ''', + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "3:0", + name: "VAL", + desc: ''' + ''' + }, + ] + }, + { name: "FPGA_INFO", desc: ''' FPGA build timestamp info. diff --git a/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.tpldesc.hjson b/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.tpldesc.hjson index 4fa27938a85eb..eac49ae6d3ddc 100644 --- a/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.tpldesc.hjson +++ b/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.tpldesc.hjson @@ -38,5 +38,11 @@ type: "bool" default: false } + { + name: "cheriot_available" + desc: "Whether CHERIoT is enabled" + type: "bool" + default: false + } ] } diff --git a/hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl b/hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl index 57e5121a35fd4..d22a6aff860ed 100644 --- a/hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl +++ b/hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl @@ -3,6 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 `include "prim_assert.sv" +`include "prim_fifo_assert.svh" /** * Ibex RISC-V core @@ -14,6 +15,9 @@ module ${module_instance_name} import rv_core_ibex_pkg::*; import ${module_instance_name}_reg_pkg::*; #( +% if cheriot_available: + parameter ibex_pkg::base_isa_e BaseIsa = ibex_pkg::BaseIsaRV32IorCHERIoT, +% endif parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // Number of cycles a differential skew is tolerated on the alert and escalation signal parameter int unsigned AlertSkewCycles = 1, @@ -64,7 +68,14 @@ module ${module_instance_name} % endif parameter logic [tlul_pkg::RsvdWidth-1:0] TlulHostUserRsvdBits = 0, parameter logic [31:0] CsrMvendorId = 32'b0, +% if cheriot_available: + parameter logic [31:0] CsrMimpId = 32'b0, + parameter int unsigned CheriotRevBitmapAddrWidth = 32'd9, + parameter int unsigned CheriotRevBitmapBaseAddr = 32'h0, + parameter int unsigned CheriotTrvkHeapBaseAddr = 32'h0 +% else: parameter logic [31:0] CsrMimpId = 32'b0 +% endif ) ( // Clock and Reset input logic clk_i, @@ -86,6 +97,10 @@ module ${module_instance_name} input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, +% if cheriot_available: + output prim_mubi_pkg::mubi4_t cheriot_ena_o, + +% endif // Instruction memory interface output tlul_pkg::tl_h2d_t corei_tl_h_o, input tlul_pkg::tl_d2h_t corei_tl_h_i, @@ -94,6 +109,16 @@ module ${module_instance_name} output tlul_pkg::tl_h2d_t cored_tl_h_o, input tlul_pkg::tl_d2h_t cored_tl_h_i, +% if cheriot_available: + // CHERIoT capability tags + output logic cored_tag_h2d_o, + input logic cored_tag_d2h_i, + + // CHERIoT TRVK revocation bitmap (revbm) memory interface + output tlul_pkg::tl_h2d_t corerevbm_tl_o, + input tlul_pkg::tl_d2h_t corerevbm_tl_i, + +% endif // Interrupt inputs input logic irq_software_i, input logic irq_timer_i, @@ -198,6 +223,17 @@ module ${module_instance_name} logic [31:0] shadow_core_data_wdata; logic [6:0] shadow_core_data_wdata_intg; +% if cheriot_available: + // Main core CHERIoT TRVK revocation bitmap (revbm) interface (internal) + logic main_core_revbm_req; + logic main_core_revbm_gnt; + logic [31:0] main_core_revbm_addr; + logic main_core_revbm_rvalid; + logic [31:0] main_core_revbm_rdata; + logic [6:0] main_core_revbm_rdata_intg; + logic main_core_revbm_err; + +% endif // Lockstep interface logic [3:0] core_lockstep_cmp_en; @@ -206,6 +242,10 @@ module ${module_instance_name} tl_d2h_t tl_i_fifo2ibex; tl_h2d_t tl_d_ibex2fifo_main_core; tl_d2h_t tl_d_fifo2ibex; +% if cheriot_available: + tl_h2d_t tl_revbm_ibex2fifo; + tl_d2h_t tl_revbm_fifo2ibex; +% endif // TLUL LC Gate interfaces tl_h2d_t tl_d_fifo2gate; @@ -249,6 +289,11 @@ module ${module_instance_name} // core sleeping logic core_sleep; +% if cheriot_available: + // CHERIoT signals + logic cheriot_switch_error; + +% endif // The following intermediate signals are created to aid in simulations. // // If a parent port is connected directly to a port of sub-modules, the implicit wire connection @@ -266,6 +311,9 @@ module ${module_instance_name} // errors and core alert events logic ibus_intg_err, dbus_intg_err; +% if cheriot_available: + logic revbmbus_intg_err; +% endif logic alert_minor, alert_major_internal, alert_major_bus; logic double_fault; logic fatal_intg_err, fatal_core_err, recov_core_err; @@ -277,7 +325,11 @@ module ${module_instance_name} logic fatal_core_event; logic recov_core_event; // SEC_CM: BUS.INTEGRITY +% if cheriot_available: + assign fatal_intg_event = ibus_intg_err | dbus_intg_err | revbmbus_intg_err | alert_major_bus; +% else: assign fatal_intg_event = ibus_intg_err | dbus_intg_err | alert_major_bus; +% endif assign fatal_core_event = alert_major_internal | double_fault | tlul_lc_gate_core_d_error | @@ -444,6 +496,11 @@ module ${module_instance_name} ibex_pkg::crash_dump_t crash_dump; ibex_top #( +% if cheriot_available: + .BaseIsa ( BaseIsa ), +% else: + .BaseIsa ( ibex_pkg::BaseIsaRV32I ), +% endif .PMPEnable ( PMPEnable ), .PMPGranularity ( PMPGranularity ), .PMPNumRegions ( PMPNumRegions ), @@ -452,6 +509,10 @@ module ${module_instance_name} .PMPRstCfg ( PMPRstCfg ), .PMPRstAddr ( PMPRstAddr ), .PMPRstMsecCfg ( PMPRstMsecCfg ), +% if cheriot_available: + .CheriotRevBitmapAddrWidth ( CheriotRevBitmapAddrWidth), + .CheriotRevBitmapBaseAddr ( CheriotRevBitmapBaseAddr ), +% endif .RV32E ( RV32E ), .RV32M ( RV32M ), .RV32B ( RV32B ), @@ -506,6 +567,12 @@ module ${module_instance_name} .hart_id_i, .boot_addr_i, +% if cheriot_available: + .trvk_heap_base_addr_i(CheriotTrvkHeapBaseAddr), // SRAM base address +% else: + .trvk_heap_base_addr_i('0), // SRAM base address +% endif + .instr_req_o (main_core_instr_req), .instr_gnt_i (main_core_instr_gnt_ibex), .instr_rvalid_i (main_core_instr_rvalid), @@ -522,10 +589,39 @@ module ${module_instance_name} .data_addr_o (main_core_data_addr), .data_wdata_o (main_core_data_wdata), .data_wdata_intg_o (main_core_data_wdata_intg), +% if cheriot_available: + .data_tag_o (cored_tag_h2d_o), +% else: + .data_tag_o (), +% endif .data_rdata_i (main_core_data_rdata), .data_rdata_intg_i (main_core_data_rdata_intg), +% if cheriot_available: + .data_tag_i (cored_tag_d2h_i), +% else: + .data_tag_i ('0), +% endif .data_err_i (main_core_data_err), +% if cheriot_available: + .trvk_revbm_req_o (main_core_revbm_req), + .trvk_revbm_gnt_i (main_core_revbm_gnt), + .trvk_revbm_rvalid_i (main_core_revbm_rvalid), + .trvk_revbm_addr_o (main_core_revbm_addr), + .trvk_revbm_rdata_i (main_core_revbm_rdata), + .trvk_revbm_rdata_intg_i(main_core_revbm_rdata_intg), + .trvk_revbm_err_i (main_core_revbm_err), + +% else: + .trvk_revbm_req_o (), + .trvk_revbm_gnt_i ('0), + .trvk_revbm_rvalid_i ('0), + .trvk_revbm_addr_o (), + .trvk_revbm_rdata_i ('0), + .trvk_revbm_rdata_intg_i('0), + .trvk_revbm_err_i ('0), + +% endif .irq_software_i ( irq_software ), .irq_timer_i ( irq_timer ), .irq_external_i ( irq_external ), @@ -811,6 +907,77 @@ module ${module_instance_name} .err_o (tlul_lc_gate_core_d_error) ); +% if cheriot_available: + if (BaseIsa == ibex_pkg::BaseIsaRV32IorCHERIoT) begin : gen_cheriot_revbm_tl_adapter + + logic [6:0] revbm_wdata_intg; + logic [top_pkg::TL_DW-1:0] unused_revbm_data; + // tl_adapter_host_revbm_ibex only reads revocation bm. a_data is always 0 + assign {revbm_wdata_intg, unused_revbm_data} = prim_secded_pkg::prim_secded_inv_39_32_enc('0); + // SEC_CM: BUS.INTEGRITY + tlul_adapter_host #( + .MAX_REQS(NumOutstandingReqs), + // if secure ibex is not set, data integrity is not generated + // from ibex, therefore generate it in the gasket instead. + .EnableDataIntgGen(~SecureIbex) + ) tl_adapter_host_revbm_ibex ( + .clk_i, + .rst_ni, + .req_i (main_core_revbm_req), + .instr_type_i (prim_mubi_pkg::MuBi4True), + .gnt_o (main_core_revbm_gnt), + .addr_i (main_core_revbm_addr), + .we_i (1'b0), + .wdata_i (32'b0), + .wdata_intg_i (revbm_wdata_intg), + .be_i (4'hF), + .user_rsvd_i (TlulHostUserRsvdBits), + .valid_o (main_core_revbm_rvalid), + .rdata_o (main_core_revbm_rdata), + .rdata_intg_o (main_core_revbm_rdata_intg), + .err_o (main_core_revbm_err), + .intg_err_o (revbmbus_intg_err), + .tl_o (tl_revbm_ibex2fifo), + .tl_i (tl_revbm_fifo2ibex) + ); + + tlul_fifo_sync #( + .ReqPass(FifoPass), + .RspPass(FifoPass), + .ReqDepth(FifoDepth), + .RspDepth(FifoDepth) + ) fifo_revbm ( + .clk_i, + .rst_ni, + .tl_h_i (tl_revbm_ibex2fifo), + .tl_h_o (tl_revbm_fifo2ibex), + .tl_d_o (corerevbm_tl_o), + .tl_d_i (corerevbm_tl_i), + .spare_req_i (1'b0), + .spare_req_o (), + .spare_rsp_i (1'b0), + .spare_rsp_o () + ); + + end else begin : gen_no_cheriot_revbm_tl_adapter + + // Tie-off unused signals + logic unused_cheriot_tl; + assign unused_cheriot_tl = ^{corerevbm_tl_i, + tl_revbm_ibex2fifo, + tl_revbm_fifo2ibex, + main_core_revbm_req, + main_core_revbm_addr + }; + assign corerevbm_tl_o = '0; + assign main_core_revbm_gnt = '0; + assign main_core_revbm_rvalid = '0; + assign main_core_revbm_rdata = '0; + assign main_core_revbm_rdata_intg = '0; + assign main_core_revbm_err = '0; + end + +% endif `ifdef RVFI ibex_tracer ibex_tracer_i ( .clk_i, @@ -947,7 +1114,11 @@ module ${module_instance_name} assign alert_events[0] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_fatal_err.q)); assign alert_events[1] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_recov_err.q)); assign alert_events[2] = cfg_reg_intg_err | cfg_reg_intg_err_shadow | +% if cheriot_available: + fatal_intg_err | fatal_core_err | cheriot_switch_error; +% else: fatal_intg_err | fatal_core_err; +% endif assign alert_events[3] = recov_core_err; logic unused_alert_acks; @@ -1037,6 +1208,37 @@ module ${module_instance_name} assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q; assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q; +% if cheriot_available: + //////////////////// + // CHERIoT switch + //////////////////// + if (BaseIsa == ibex_pkg::BaseIsaRV32IorCHERIoT) begin : gen_cheriot_switch + // SEC_CM: CHERIOT_SWITCH.FSM.SPARSE + cheriot_switch u_cheriot_switch ( + .clk_i, + .rst_ni, + .ena_i (mubi4_t'(reg2hw.cheriot_ena.q)), + .lock_i (mubi4_t'(reg2hw.cheriot_lock.q)), + .lock_access_i(reg2hw.cheriot_lock.qe), + .ena_o (cheriot_ena_o), + .error_o (cheriot_switch_error) + ); + + end else begin : gen_no_cheriot_switch + logic unused_cheriot; + assign cheriot_switch_error = 1'b0; + assign cheriot_ena_o = prim_mubi_pkg::MuBi4False; + assign unused_cheriot = ^{cheriot_switch_error, + reg2hw.cheriot_ena, + reg2hw.cheriot_lock + }; + end + +% else: + logic unused_cheriot; + assign unused_cheriot = ^{reg2hw.cheriot_ena, reg2hw.cheriot_lock}; + +% endif logic unused_reg2hw; assign unused_reg2hw = |reg2hw.rnd_data.q; @@ -1127,7 +1329,8 @@ module ${module_instance_name} assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable, reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data, reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err, - reg2hw_shadow.mcounteren_writable}; + reg2hw_shadow.mcounteren_writable, + reg2hw_shadow.cheriot_ena, reg2hw_shadow.cheriot_lock}; ///////////////////////////////////////////////////////////////// // Shadow Core Data Address Translation Unit and TL-UL Adapter // @@ -1553,5 +1756,10 @@ module ${module_instance_name} `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CoredTlLcGateFsm_A, u_tlul_lc_gate_cored.u_state_regs, alert_tx_o[2]) +% if cheriot_available: + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CheriotSwitchFsm_A, + gen_cheriot_switch.u_cheriot_switch.u_state_regs, alert_tx_o[2]) + +% endif `endif // ifdef INC_ASSERT endmodule diff --git a/hw/ip_templates/rv_core_ibex/rv_core_ibex.core.tpl b/hw/ip_templates/rv_core_ibex/rv_core_ibex.core.tpl index 5a1dc0d38aef1..1f4fc31494f36 100644 --- a/hw/ip_templates/rv_core_ibex/rv_core_ibex.core.tpl +++ b/hw/ip_templates/rv_core_ibex/rv_core_ibex.core.tpl @@ -20,6 +20,9 @@ filesets: - lowrisc:prim:mubi - lowrisc:tlul:adapter_host - lowrisc:ip:rv_core_ibex_pkg + % if cheriot_available: + - lowrisc:ip:cheriot_switch + % endif % if racl_support: - ${instance_vlnv("lowrisc:constants:top_racl_pkg")} % endif diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 62daca2191790..396667ed0cd47 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -4197,6 +4197,15 @@ expose: "true" name_top: SramCtrlRetAonNumPrinceRoundsHalf } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumAddrScrRounds + } { name: Outstanding desc: Number of outstanding TLUL transactions @@ -6752,6 +6761,15 @@ expose: "true" name_top: SramCtrlMainNumPrinceRoundsHalf } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlMainNumAddrScrRounds + } { name: Outstanding desc: Number of outstanding TLUL transactions @@ -7041,6 +7059,15 @@ expose: "true" name_top: SramCtrlMboxNumPrinceRoundsHalf } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlMboxNumAddrScrRounds + } { name: Outstanding desc: Number of outstanding TLUL transactions diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson b/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson index 7693497078771..685bfdd250596 100644 --- a/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson @@ -1079,6 +1079,40 @@ ] }, + { name: "CHERIOT_ENA", + desc: ''' + Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). + ''', + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "3:0", + name: "VAL", + resval: "0x0" + desc: ''' + ''' + }, + ] + }, + + { name: "CHERIOT_LOCK", + desc: ''' + Locks the CHERIoT/ePMP mode. + If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. + ''', + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "3:0", + name: "VAL", + desc: ''' + ''' + }, + ] + }, + { name: "FPGA_INFO", desc: ''' FPGA build timestamp info. diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/top_darjeeling_rv_core_ibex.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/top_darjeeling_rv_core_ibex.ipconfig.hjson index 96ebec200169e..20a7a2575f626 100644 --- a/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/top_darjeeling_rv_core_ibex.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/top_darjeeling_rv_core_ibex.ipconfig.hjson @@ -10,6 +10,7 @@ topname: darjeeling uniquified_modules: {} racl_support: false + cheriot_available: false } dtgen: { diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md b/hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md index c491a6fb5798e..29112607007f3 100644 --- a/hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md +++ b/hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md @@ -5,276 +5,278 @@ A number of memory-mapped registers are available to control Ibex-related functi ## Summary -| Name | Offset | Length | Description | -|:-------------------------------------------------------------------------|:---------|---------:|:------------------------------------------------------------------------------| -| rv_core_ibex.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | -| rv_core_ibex.[`SW_RECOV_ERR`](#sw_recov_err) | 0x4 | 4 | Software recoverable error | -| rv_core_ibex.[`SW_FATAL_ERR`](#sw_fatal_err) | 0x8 | 4 | Software fatal error | -| rv_core_ibex.[`IBUS_REGWEN_0`](#ibus_regwen) | 0xc | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_1`](#ibus_regwen) | 0x10 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_2`](#ibus_regwen) | 0x14 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_3`](#ibus_regwen) | 0x18 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_4`](#ibus_regwen) | 0x1c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_5`](#ibus_regwen) | 0x20 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_6`](#ibus_regwen) | 0x24 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_7`](#ibus_regwen) | 0x28 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_8`](#ibus_regwen) | 0x2c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_9`](#ibus_regwen) | 0x30 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_10`](#ibus_regwen) | 0x34 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_11`](#ibus_regwen) | 0x38 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_12`](#ibus_regwen) | 0x3c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_13`](#ibus_regwen) | 0x40 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_14`](#ibus_regwen) | 0x44 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_15`](#ibus_regwen) | 0x48 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_16`](#ibus_regwen) | 0x4c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_17`](#ibus_regwen) | 0x50 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_18`](#ibus_regwen) | 0x54 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_19`](#ibus_regwen) | 0x58 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_20`](#ibus_regwen) | 0x5c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_21`](#ibus_regwen) | 0x60 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_22`](#ibus_regwen) | 0x64 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_23`](#ibus_regwen) | 0x68 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_24`](#ibus_regwen) | 0x6c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_25`](#ibus_regwen) | 0x70 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_26`](#ibus_regwen) | 0x74 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_27`](#ibus_regwen) | 0x78 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_28`](#ibus_regwen) | 0x7c | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_29`](#ibus_regwen) | 0x80 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_30`](#ibus_regwen) | 0x84 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_31`](#ibus_regwen) | 0x88 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_ADDR_EN_0`](#ibus_addr_en) | 0x8c | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_1`](#ibus_addr_en) | 0x90 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_2`](#ibus_addr_en) | 0x94 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_3`](#ibus_addr_en) | 0x98 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_4`](#ibus_addr_en) | 0x9c | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_5`](#ibus_addr_en) | 0xa0 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_6`](#ibus_addr_en) | 0xa4 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_7`](#ibus_addr_en) | 0xa8 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_8`](#ibus_addr_en) | 0xac | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_9`](#ibus_addr_en) | 0xb0 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_10`](#ibus_addr_en) | 0xb4 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_11`](#ibus_addr_en) | 0xb8 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_12`](#ibus_addr_en) | 0xbc | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_13`](#ibus_addr_en) | 0xc0 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_14`](#ibus_addr_en) | 0xc4 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_15`](#ibus_addr_en) | 0xc8 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_16`](#ibus_addr_en) | 0xcc | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_17`](#ibus_addr_en) | 0xd0 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_18`](#ibus_addr_en) | 0xd4 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_19`](#ibus_addr_en) | 0xd8 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_20`](#ibus_addr_en) | 0xdc | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_21`](#ibus_addr_en) | 0xe0 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_22`](#ibus_addr_en) | 0xe4 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_23`](#ibus_addr_en) | 0xe8 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_24`](#ibus_addr_en) | 0xec | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_25`](#ibus_addr_en) | 0xf0 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_26`](#ibus_addr_en) | 0xf4 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_27`](#ibus_addr_en) | 0xf8 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_28`](#ibus_addr_en) | 0xfc | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_29`](#ibus_addr_en) | 0x100 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_30`](#ibus_addr_en) | 0x104 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_31`](#ibus_addr_en) | 0x108 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching) | 0x10c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_1`](#ibus_addr_matching) | 0x110 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_2`](#ibus_addr_matching) | 0x114 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_3`](#ibus_addr_matching) | 0x118 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_4`](#ibus_addr_matching) | 0x11c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_5`](#ibus_addr_matching) | 0x120 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_6`](#ibus_addr_matching) | 0x124 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_7`](#ibus_addr_matching) | 0x128 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_8`](#ibus_addr_matching) | 0x12c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_9`](#ibus_addr_matching) | 0x130 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_10`](#ibus_addr_matching) | 0x134 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_11`](#ibus_addr_matching) | 0x138 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_12`](#ibus_addr_matching) | 0x13c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_13`](#ibus_addr_matching) | 0x140 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_14`](#ibus_addr_matching) | 0x144 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_15`](#ibus_addr_matching) | 0x148 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_16`](#ibus_addr_matching) | 0x14c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_17`](#ibus_addr_matching) | 0x150 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_18`](#ibus_addr_matching) | 0x154 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_19`](#ibus_addr_matching) | 0x158 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_20`](#ibus_addr_matching) | 0x15c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_21`](#ibus_addr_matching) | 0x160 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_22`](#ibus_addr_matching) | 0x164 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_23`](#ibus_addr_matching) | 0x168 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_24`](#ibus_addr_matching) | 0x16c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_25`](#ibus_addr_matching) | 0x170 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_26`](#ibus_addr_matching) | 0x174 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_27`](#ibus_addr_matching) | 0x178 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_28`](#ibus_addr_matching) | 0x17c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_29`](#ibus_addr_matching) | 0x180 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_30`](#ibus_addr_matching) | 0x184 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_31`](#ibus_addr_matching) | 0x188 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_0`](#ibus_remap_addr) | 0x18c | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_1`](#ibus_remap_addr) | 0x190 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_2`](#ibus_remap_addr) | 0x194 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_3`](#ibus_remap_addr) | 0x198 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_4`](#ibus_remap_addr) | 0x19c | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_5`](#ibus_remap_addr) | 0x1a0 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_6`](#ibus_remap_addr) | 0x1a4 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_7`](#ibus_remap_addr) | 0x1a8 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_8`](#ibus_remap_addr) | 0x1ac | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_9`](#ibus_remap_addr) | 0x1b0 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_10`](#ibus_remap_addr) | 0x1b4 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_11`](#ibus_remap_addr) | 0x1b8 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_12`](#ibus_remap_addr) | 0x1bc | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_13`](#ibus_remap_addr) | 0x1c0 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_14`](#ibus_remap_addr) | 0x1c4 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_15`](#ibus_remap_addr) | 0x1c8 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_16`](#ibus_remap_addr) | 0x1cc | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_17`](#ibus_remap_addr) | 0x1d0 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_18`](#ibus_remap_addr) | 0x1d4 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_19`](#ibus_remap_addr) | 0x1d8 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_20`](#ibus_remap_addr) | 0x1dc | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_21`](#ibus_remap_addr) | 0x1e0 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_22`](#ibus_remap_addr) | 0x1e4 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_23`](#ibus_remap_addr) | 0x1e8 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_24`](#ibus_remap_addr) | 0x1ec | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_25`](#ibus_remap_addr) | 0x1f0 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_26`](#ibus_remap_addr) | 0x1f4 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_27`](#ibus_remap_addr) | 0x1f8 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_28`](#ibus_remap_addr) | 0x1fc | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_29`](#ibus_remap_addr) | 0x200 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_30`](#ibus_remap_addr) | 0x204 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_31`](#ibus_remap_addr) | 0x208 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`DBUS_REGWEN_0`](#dbus_regwen) | 0x20c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_1`](#dbus_regwen) | 0x210 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_2`](#dbus_regwen) | 0x214 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_3`](#dbus_regwen) | 0x218 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_4`](#dbus_regwen) | 0x21c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_5`](#dbus_regwen) | 0x220 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_6`](#dbus_regwen) | 0x224 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_7`](#dbus_regwen) | 0x228 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_8`](#dbus_regwen) | 0x22c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_9`](#dbus_regwen) | 0x230 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_10`](#dbus_regwen) | 0x234 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_11`](#dbus_regwen) | 0x238 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_12`](#dbus_regwen) | 0x23c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_13`](#dbus_regwen) | 0x240 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_14`](#dbus_regwen) | 0x244 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_15`](#dbus_regwen) | 0x248 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_16`](#dbus_regwen) | 0x24c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_17`](#dbus_regwen) | 0x250 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_18`](#dbus_regwen) | 0x254 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_19`](#dbus_regwen) | 0x258 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_20`](#dbus_regwen) | 0x25c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_21`](#dbus_regwen) | 0x260 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_22`](#dbus_regwen) | 0x264 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_23`](#dbus_regwen) | 0x268 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_24`](#dbus_regwen) | 0x26c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_25`](#dbus_regwen) | 0x270 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_26`](#dbus_regwen) | 0x274 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_27`](#dbus_regwen) | 0x278 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_28`](#dbus_regwen) | 0x27c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_29`](#dbus_regwen) | 0x280 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_30`](#dbus_regwen) | 0x284 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_31`](#dbus_regwen) | 0x288 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_ADDR_EN_0`](#dbus_addr_en) | 0x28c | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_1`](#dbus_addr_en) | 0x290 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_2`](#dbus_addr_en) | 0x294 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_3`](#dbus_addr_en) | 0x298 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_4`](#dbus_addr_en) | 0x29c | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_5`](#dbus_addr_en) | 0x2a0 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_6`](#dbus_addr_en) | 0x2a4 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_7`](#dbus_addr_en) | 0x2a8 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_8`](#dbus_addr_en) | 0x2ac | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_9`](#dbus_addr_en) | 0x2b0 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_10`](#dbus_addr_en) | 0x2b4 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_11`](#dbus_addr_en) | 0x2b8 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_12`](#dbus_addr_en) | 0x2bc | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_13`](#dbus_addr_en) | 0x2c0 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_14`](#dbus_addr_en) | 0x2c4 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_15`](#dbus_addr_en) | 0x2c8 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_16`](#dbus_addr_en) | 0x2cc | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_17`](#dbus_addr_en) | 0x2d0 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_18`](#dbus_addr_en) | 0x2d4 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_19`](#dbus_addr_en) | 0x2d8 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_20`](#dbus_addr_en) | 0x2dc | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_21`](#dbus_addr_en) | 0x2e0 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_22`](#dbus_addr_en) | 0x2e4 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_23`](#dbus_addr_en) | 0x2e8 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_24`](#dbus_addr_en) | 0x2ec | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_25`](#dbus_addr_en) | 0x2f0 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_26`](#dbus_addr_en) | 0x2f4 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_27`](#dbus_addr_en) | 0x2f8 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_28`](#dbus_addr_en) | 0x2fc | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_29`](#dbus_addr_en) | 0x300 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_30`](#dbus_addr_en) | 0x304 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_31`](#dbus_addr_en) | 0x308 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_0`](#dbus_addr_matching) | 0x30c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_1`](#dbus_addr_matching) | 0x310 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_2`](#dbus_addr_matching) | 0x314 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_3`](#dbus_addr_matching) | 0x318 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_4`](#dbus_addr_matching) | 0x31c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_5`](#dbus_addr_matching) | 0x320 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_6`](#dbus_addr_matching) | 0x324 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_7`](#dbus_addr_matching) | 0x328 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_8`](#dbus_addr_matching) | 0x32c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_9`](#dbus_addr_matching) | 0x330 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_10`](#dbus_addr_matching) | 0x334 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_11`](#dbus_addr_matching) | 0x338 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_12`](#dbus_addr_matching) | 0x33c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_13`](#dbus_addr_matching) | 0x340 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_14`](#dbus_addr_matching) | 0x344 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_15`](#dbus_addr_matching) | 0x348 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_16`](#dbus_addr_matching) | 0x34c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_17`](#dbus_addr_matching) | 0x350 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_18`](#dbus_addr_matching) | 0x354 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_19`](#dbus_addr_matching) | 0x358 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_20`](#dbus_addr_matching) | 0x35c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_21`](#dbus_addr_matching) | 0x360 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_22`](#dbus_addr_matching) | 0x364 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_23`](#dbus_addr_matching) | 0x368 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_24`](#dbus_addr_matching) | 0x36c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_25`](#dbus_addr_matching) | 0x370 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_26`](#dbus_addr_matching) | 0x374 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_27`](#dbus_addr_matching) | 0x378 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_28`](#dbus_addr_matching) | 0x37c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_29`](#dbus_addr_matching) | 0x380 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_30`](#dbus_addr_matching) | 0x384 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_31`](#dbus_addr_matching) | 0x388 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_0`](#dbus_remap_addr) | 0x38c | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_1`](#dbus_remap_addr) | 0x390 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_2`](#dbus_remap_addr) | 0x394 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_3`](#dbus_remap_addr) | 0x398 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_4`](#dbus_remap_addr) | 0x39c | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_5`](#dbus_remap_addr) | 0x3a0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_6`](#dbus_remap_addr) | 0x3a4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_7`](#dbus_remap_addr) | 0x3a8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_8`](#dbus_remap_addr) | 0x3ac | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_9`](#dbus_remap_addr) | 0x3b0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_10`](#dbus_remap_addr) | 0x3b4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_11`](#dbus_remap_addr) | 0x3b8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_12`](#dbus_remap_addr) | 0x3bc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_13`](#dbus_remap_addr) | 0x3c0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_14`](#dbus_remap_addr) | 0x3c4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_15`](#dbus_remap_addr) | 0x3c8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_16`](#dbus_remap_addr) | 0x3cc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_17`](#dbus_remap_addr) | 0x3d0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_18`](#dbus_remap_addr) | 0x3d4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_19`](#dbus_remap_addr) | 0x3d8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_20`](#dbus_remap_addr) | 0x3dc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_21`](#dbus_remap_addr) | 0x3e0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_22`](#dbus_remap_addr) | 0x3e4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_23`](#dbus_remap_addr) | 0x3e8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_24`](#dbus_remap_addr) | 0x3ec | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_25`](#dbus_remap_addr) | 0x3f0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_26`](#dbus_remap_addr) | 0x3f4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_27`](#dbus_remap_addr) | 0x3f8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_28`](#dbus_remap_addr) | 0x3fc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_29`](#dbus_remap_addr) | 0x400 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_30`](#dbus_remap_addr) | 0x404 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_31`](#dbus_remap_addr) | 0x408 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`NMI_ENABLE`](#nmi_enable) | 0x40c | 4 | Enable mask for NMI. | -| rv_core_ibex.[`NMI_STATE`](#nmi_state) | 0x410 | 4 | Current NMI state | -| rv_core_ibex.[`ERR_STATUS`](#err_status) | 0x414 | 4 | error status | -| rv_core_ibex.[`RND_DATA`](#rnd_data) | 0x418 | 4 | Random data from EDN | -| rv_core_ibex.[`RND_STATUS`](#rnd_status) | 0x41c | 4 | Status of random data in [`RND_DATA`](#rnd_data) | -| rv_core_ibex.[`FPGA_INFO`](#fpga_info) | 0x420 | 4 | FPGA build timestamp info. | -| rv_core_ibex.[`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) | 0x424 | 4 | Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) | -| rv_core_ibex.[`MCOUNTEREN_WRITABLE`](#mcounteren_writable) | 0x428 | 4 | Controls whether Ibex mcounteren CSR is writable by software. | -| rv_core_ibex.[`DV_SIM_WINDOW`](#dv_sim_window) | 0x440 | 32 | Exposed tlul window for DV only purposes. | +| Name | Offset | Length | Description | +|:-------------------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| +| rv_core_ibex.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| rv_core_ibex.[`SW_RECOV_ERR`](#sw_recov_err) | 0x4 | 4 | Software recoverable error | +| rv_core_ibex.[`SW_FATAL_ERR`](#sw_fatal_err) | 0x8 | 4 | Software fatal error | +| rv_core_ibex.[`IBUS_REGWEN_0`](#ibus_regwen) | 0xc | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_1`](#ibus_regwen) | 0x10 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_2`](#ibus_regwen) | 0x14 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_3`](#ibus_regwen) | 0x18 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_4`](#ibus_regwen) | 0x1c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_5`](#ibus_regwen) | 0x20 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_6`](#ibus_regwen) | 0x24 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_7`](#ibus_regwen) | 0x28 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_8`](#ibus_regwen) | 0x2c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_9`](#ibus_regwen) | 0x30 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_10`](#ibus_regwen) | 0x34 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_11`](#ibus_regwen) | 0x38 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_12`](#ibus_regwen) | 0x3c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_13`](#ibus_regwen) | 0x40 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_14`](#ibus_regwen) | 0x44 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_15`](#ibus_regwen) | 0x48 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_16`](#ibus_regwen) | 0x4c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_17`](#ibus_regwen) | 0x50 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_18`](#ibus_regwen) | 0x54 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_19`](#ibus_regwen) | 0x58 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_20`](#ibus_regwen) | 0x5c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_21`](#ibus_regwen) | 0x60 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_22`](#ibus_regwen) | 0x64 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_23`](#ibus_regwen) | 0x68 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_24`](#ibus_regwen) | 0x6c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_25`](#ibus_regwen) | 0x70 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_26`](#ibus_regwen) | 0x74 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_27`](#ibus_regwen) | 0x78 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_28`](#ibus_regwen) | 0x7c | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_29`](#ibus_regwen) | 0x80 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_30`](#ibus_regwen) | 0x84 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_31`](#ibus_regwen) | 0x88 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_ADDR_EN_0`](#ibus_addr_en) | 0x8c | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_1`](#ibus_addr_en) | 0x90 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_2`](#ibus_addr_en) | 0x94 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_3`](#ibus_addr_en) | 0x98 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_4`](#ibus_addr_en) | 0x9c | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_5`](#ibus_addr_en) | 0xa0 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_6`](#ibus_addr_en) | 0xa4 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_7`](#ibus_addr_en) | 0xa8 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_8`](#ibus_addr_en) | 0xac | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_9`](#ibus_addr_en) | 0xb0 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_10`](#ibus_addr_en) | 0xb4 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_11`](#ibus_addr_en) | 0xb8 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_12`](#ibus_addr_en) | 0xbc | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_13`](#ibus_addr_en) | 0xc0 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_14`](#ibus_addr_en) | 0xc4 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_15`](#ibus_addr_en) | 0xc8 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_16`](#ibus_addr_en) | 0xcc | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_17`](#ibus_addr_en) | 0xd0 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_18`](#ibus_addr_en) | 0xd4 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_19`](#ibus_addr_en) | 0xd8 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_20`](#ibus_addr_en) | 0xdc | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_21`](#ibus_addr_en) | 0xe0 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_22`](#ibus_addr_en) | 0xe4 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_23`](#ibus_addr_en) | 0xe8 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_24`](#ibus_addr_en) | 0xec | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_25`](#ibus_addr_en) | 0xf0 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_26`](#ibus_addr_en) | 0xf4 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_27`](#ibus_addr_en) | 0xf8 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_28`](#ibus_addr_en) | 0xfc | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_29`](#ibus_addr_en) | 0x100 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_30`](#ibus_addr_en) | 0x104 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_31`](#ibus_addr_en) | 0x108 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching) | 0x10c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_1`](#ibus_addr_matching) | 0x110 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_2`](#ibus_addr_matching) | 0x114 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_3`](#ibus_addr_matching) | 0x118 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_4`](#ibus_addr_matching) | 0x11c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_5`](#ibus_addr_matching) | 0x120 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_6`](#ibus_addr_matching) | 0x124 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_7`](#ibus_addr_matching) | 0x128 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_8`](#ibus_addr_matching) | 0x12c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_9`](#ibus_addr_matching) | 0x130 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_10`](#ibus_addr_matching) | 0x134 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_11`](#ibus_addr_matching) | 0x138 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_12`](#ibus_addr_matching) | 0x13c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_13`](#ibus_addr_matching) | 0x140 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_14`](#ibus_addr_matching) | 0x144 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_15`](#ibus_addr_matching) | 0x148 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_16`](#ibus_addr_matching) | 0x14c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_17`](#ibus_addr_matching) | 0x150 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_18`](#ibus_addr_matching) | 0x154 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_19`](#ibus_addr_matching) | 0x158 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_20`](#ibus_addr_matching) | 0x15c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_21`](#ibus_addr_matching) | 0x160 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_22`](#ibus_addr_matching) | 0x164 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_23`](#ibus_addr_matching) | 0x168 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_24`](#ibus_addr_matching) | 0x16c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_25`](#ibus_addr_matching) | 0x170 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_26`](#ibus_addr_matching) | 0x174 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_27`](#ibus_addr_matching) | 0x178 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_28`](#ibus_addr_matching) | 0x17c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_29`](#ibus_addr_matching) | 0x180 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_30`](#ibus_addr_matching) | 0x184 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_31`](#ibus_addr_matching) | 0x188 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_0`](#ibus_remap_addr) | 0x18c | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_1`](#ibus_remap_addr) | 0x190 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_2`](#ibus_remap_addr) | 0x194 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_3`](#ibus_remap_addr) | 0x198 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_4`](#ibus_remap_addr) | 0x19c | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_5`](#ibus_remap_addr) | 0x1a0 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_6`](#ibus_remap_addr) | 0x1a4 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_7`](#ibus_remap_addr) | 0x1a8 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_8`](#ibus_remap_addr) | 0x1ac | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_9`](#ibus_remap_addr) | 0x1b0 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_10`](#ibus_remap_addr) | 0x1b4 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_11`](#ibus_remap_addr) | 0x1b8 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_12`](#ibus_remap_addr) | 0x1bc | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_13`](#ibus_remap_addr) | 0x1c0 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_14`](#ibus_remap_addr) | 0x1c4 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_15`](#ibus_remap_addr) | 0x1c8 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_16`](#ibus_remap_addr) | 0x1cc | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_17`](#ibus_remap_addr) | 0x1d0 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_18`](#ibus_remap_addr) | 0x1d4 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_19`](#ibus_remap_addr) | 0x1d8 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_20`](#ibus_remap_addr) | 0x1dc | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_21`](#ibus_remap_addr) | 0x1e0 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_22`](#ibus_remap_addr) | 0x1e4 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_23`](#ibus_remap_addr) | 0x1e8 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_24`](#ibus_remap_addr) | 0x1ec | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_25`](#ibus_remap_addr) | 0x1f0 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_26`](#ibus_remap_addr) | 0x1f4 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_27`](#ibus_remap_addr) | 0x1f8 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_28`](#ibus_remap_addr) | 0x1fc | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_29`](#ibus_remap_addr) | 0x200 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_30`](#ibus_remap_addr) | 0x204 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_31`](#ibus_remap_addr) | 0x208 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`DBUS_REGWEN_0`](#dbus_regwen) | 0x20c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_1`](#dbus_regwen) | 0x210 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_2`](#dbus_regwen) | 0x214 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_3`](#dbus_regwen) | 0x218 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_4`](#dbus_regwen) | 0x21c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_5`](#dbus_regwen) | 0x220 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_6`](#dbus_regwen) | 0x224 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_7`](#dbus_regwen) | 0x228 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_8`](#dbus_regwen) | 0x22c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_9`](#dbus_regwen) | 0x230 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_10`](#dbus_regwen) | 0x234 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_11`](#dbus_regwen) | 0x238 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_12`](#dbus_regwen) | 0x23c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_13`](#dbus_regwen) | 0x240 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_14`](#dbus_regwen) | 0x244 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_15`](#dbus_regwen) | 0x248 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_16`](#dbus_regwen) | 0x24c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_17`](#dbus_regwen) | 0x250 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_18`](#dbus_regwen) | 0x254 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_19`](#dbus_regwen) | 0x258 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_20`](#dbus_regwen) | 0x25c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_21`](#dbus_regwen) | 0x260 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_22`](#dbus_regwen) | 0x264 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_23`](#dbus_regwen) | 0x268 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_24`](#dbus_regwen) | 0x26c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_25`](#dbus_regwen) | 0x270 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_26`](#dbus_regwen) | 0x274 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_27`](#dbus_regwen) | 0x278 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_28`](#dbus_regwen) | 0x27c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_29`](#dbus_regwen) | 0x280 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_30`](#dbus_regwen) | 0x284 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_31`](#dbus_regwen) | 0x288 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_ADDR_EN_0`](#dbus_addr_en) | 0x28c | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_1`](#dbus_addr_en) | 0x290 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_2`](#dbus_addr_en) | 0x294 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_3`](#dbus_addr_en) | 0x298 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_4`](#dbus_addr_en) | 0x29c | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_5`](#dbus_addr_en) | 0x2a0 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_6`](#dbus_addr_en) | 0x2a4 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_7`](#dbus_addr_en) | 0x2a8 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_8`](#dbus_addr_en) | 0x2ac | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_9`](#dbus_addr_en) | 0x2b0 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_10`](#dbus_addr_en) | 0x2b4 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_11`](#dbus_addr_en) | 0x2b8 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_12`](#dbus_addr_en) | 0x2bc | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_13`](#dbus_addr_en) | 0x2c0 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_14`](#dbus_addr_en) | 0x2c4 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_15`](#dbus_addr_en) | 0x2c8 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_16`](#dbus_addr_en) | 0x2cc | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_17`](#dbus_addr_en) | 0x2d0 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_18`](#dbus_addr_en) | 0x2d4 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_19`](#dbus_addr_en) | 0x2d8 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_20`](#dbus_addr_en) | 0x2dc | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_21`](#dbus_addr_en) | 0x2e0 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_22`](#dbus_addr_en) | 0x2e4 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_23`](#dbus_addr_en) | 0x2e8 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_24`](#dbus_addr_en) | 0x2ec | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_25`](#dbus_addr_en) | 0x2f0 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_26`](#dbus_addr_en) | 0x2f4 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_27`](#dbus_addr_en) | 0x2f8 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_28`](#dbus_addr_en) | 0x2fc | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_29`](#dbus_addr_en) | 0x300 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_30`](#dbus_addr_en) | 0x304 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_31`](#dbus_addr_en) | 0x308 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_0`](#dbus_addr_matching) | 0x30c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_1`](#dbus_addr_matching) | 0x310 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_2`](#dbus_addr_matching) | 0x314 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_3`](#dbus_addr_matching) | 0x318 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_4`](#dbus_addr_matching) | 0x31c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_5`](#dbus_addr_matching) | 0x320 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_6`](#dbus_addr_matching) | 0x324 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_7`](#dbus_addr_matching) | 0x328 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_8`](#dbus_addr_matching) | 0x32c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_9`](#dbus_addr_matching) | 0x330 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_10`](#dbus_addr_matching) | 0x334 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_11`](#dbus_addr_matching) | 0x338 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_12`](#dbus_addr_matching) | 0x33c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_13`](#dbus_addr_matching) | 0x340 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_14`](#dbus_addr_matching) | 0x344 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_15`](#dbus_addr_matching) | 0x348 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_16`](#dbus_addr_matching) | 0x34c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_17`](#dbus_addr_matching) | 0x350 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_18`](#dbus_addr_matching) | 0x354 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_19`](#dbus_addr_matching) | 0x358 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_20`](#dbus_addr_matching) | 0x35c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_21`](#dbus_addr_matching) | 0x360 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_22`](#dbus_addr_matching) | 0x364 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_23`](#dbus_addr_matching) | 0x368 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_24`](#dbus_addr_matching) | 0x36c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_25`](#dbus_addr_matching) | 0x370 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_26`](#dbus_addr_matching) | 0x374 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_27`](#dbus_addr_matching) | 0x378 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_28`](#dbus_addr_matching) | 0x37c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_29`](#dbus_addr_matching) | 0x380 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_30`](#dbus_addr_matching) | 0x384 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_31`](#dbus_addr_matching) | 0x388 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_0`](#dbus_remap_addr) | 0x38c | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_1`](#dbus_remap_addr) | 0x390 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_2`](#dbus_remap_addr) | 0x394 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_3`](#dbus_remap_addr) | 0x398 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_4`](#dbus_remap_addr) | 0x39c | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_5`](#dbus_remap_addr) | 0x3a0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_6`](#dbus_remap_addr) | 0x3a4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_7`](#dbus_remap_addr) | 0x3a8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_8`](#dbus_remap_addr) | 0x3ac | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_9`](#dbus_remap_addr) | 0x3b0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_10`](#dbus_remap_addr) | 0x3b4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_11`](#dbus_remap_addr) | 0x3b8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_12`](#dbus_remap_addr) | 0x3bc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_13`](#dbus_remap_addr) | 0x3c0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_14`](#dbus_remap_addr) | 0x3c4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_15`](#dbus_remap_addr) | 0x3c8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_16`](#dbus_remap_addr) | 0x3cc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_17`](#dbus_remap_addr) | 0x3d0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_18`](#dbus_remap_addr) | 0x3d4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_19`](#dbus_remap_addr) | 0x3d8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_20`](#dbus_remap_addr) | 0x3dc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_21`](#dbus_remap_addr) | 0x3e0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_22`](#dbus_remap_addr) | 0x3e4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_23`](#dbus_remap_addr) | 0x3e8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_24`](#dbus_remap_addr) | 0x3ec | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_25`](#dbus_remap_addr) | 0x3f0 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_26`](#dbus_remap_addr) | 0x3f4 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_27`](#dbus_remap_addr) | 0x3f8 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_28`](#dbus_remap_addr) | 0x3fc | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_29`](#dbus_remap_addr) | 0x400 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_30`](#dbus_remap_addr) | 0x404 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_31`](#dbus_remap_addr) | 0x408 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`NMI_ENABLE`](#nmi_enable) | 0x40c | 4 | Enable mask for NMI. | +| rv_core_ibex.[`NMI_STATE`](#nmi_state) | 0x410 | 4 | Current NMI state | +| rv_core_ibex.[`ERR_STATUS`](#err_status) | 0x414 | 4 | error status | +| rv_core_ibex.[`RND_DATA`](#rnd_data) | 0x418 | 4 | Random data from EDN | +| rv_core_ibex.[`RND_STATUS`](#rnd_status) | 0x41c | 4 | Status of random data in [`RND_DATA`](#rnd_data) | +| rv_core_ibex.[`CHERIOT_ENA`](#cheriot_ena) | 0x420 | 4 | Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). | +| rv_core_ibex.[`CHERIOT_LOCK`](#cheriot_lock) | 0x424 | 4 | Locks the CHERIoT/ePMP mode. | +| rv_core_ibex.[`FPGA_INFO`](#fpga_info) | 0x428 | 4 | FPGA build timestamp info. | +| rv_core_ibex.[`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) | 0x42c | 4 | Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) | +| rv_core_ibex.[`MCOUNTEREN_WRITABLE`](#mcounteren_writable) | 0x430 | 4 | Controls whether Ibex mcounteren CSR is writable by software. | +| rv_core_ibex.[`DV_SIM_WINDOW`](#dv_sim_window) | 0x440 | 32 | Exposed tlul window for DV only purposes. | ## ALERT_TEST Alert Test Register @@ -901,10 +903,45 @@ Status of random data in [`RND_DATA`](#rnd_data) | 1 | ro | 0x0 | RND_DATA_FIPS | When [`RND_STATUS.RND_DATA_VALID`](#rnd_status) is 1, this bit indicates whether [`RND_DATA`](#rnd_data) is fips quality. When [`RND_STATUS.RND_DATA_VALID`](#rnd_status) is 0, this bit has no meaning. | | 0 | ro | 0x0 | RND_DATA_VALID | When set, the data in [`RND_DATA`](#rnd_data) is valid. When clear an EDN request for new data for [`RND_DATA`](#rnd_data) is pending. | +## CHERIOT_ENA +Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). +- Offset: `0x420` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["wo"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:4 | | | | Reserved | +| 3:0 | wo | 0x0 | VAL | | + +## CHERIOT_LOCK +Locks the CHERIoT/ePMP mode. +If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. +- Offset: `0x424` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["wo"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:4 | | | | Reserved | +| 3:0 | wo | x | VAL | | + ## FPGA_INFO FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0. -- Offset: `0x420` +- Offset: `0x428` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -920,7 +957,7 @@ This register only contains valid data for fpga, for all other variants it is si ## MCOUNTEREN_WRITABLE_REGWEN Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) -- Offset: `0x424` +- Offset: `0x42c` - Reset default: `0x1` - Reset mask: `0x1` @@ -946,7 +983,7 @@ Write enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) Once set to 0, i ## MCOUNTEREN_WRITABLE Controls whether Ibex mcounteren CSR is writable by software. -- Offset: `0x428` +- Offset: `0x430` - Reset default: `0x6` - Reset mask: `0xf` - Register enable: [`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv index eddb743aeed2e..9dddd35946990 100644 --- a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv @@ -3,6 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 `include "prim_assert.sv" +`include "prim_fifo_assert.svh" /** * Ibex RISC-V core @@ -431,6 +432,7 @@ module rv_core_ibex ibex_pkg::crash_dump_t crash_dump; ibex_top #( + .BaseIsa ( ibex_pkg::BaseIsaRV32I ), .PMPEnable ( PMPEnable ), .PMPGranularity ( PMPGranularity ), .PMPNumRegions ( PMPNumRegions ), @@ -493,6 +495,8 @@ module rv_core_ibex .hart_id_i, .boot_addr_i, + .trvk_heap_base_addr_i('0), // SRAM base address + .instr_req_o (main_core_instr_req), .instr_gnt_i (main_core_instr_gnt_ibex), .instr_rvalid_i (main_core_instr_rvalid), @@ -509,10 +513,20 @@ module rv_core_ibex .data_addr_o (main_core_data_addr), .data_wdata_o (main_core_data_wdata), .data_wdata_intg_o (main_core_data_wdata_intg), + .data_tag_o (), .data_rdata_i (main_core_data_rdata), .data_rdata_intg_i (main_core_data_rdata_intg), + .data_tag_i ('0), .data_err_i (main_core_data_err), + .trvk_revbm_req_o (), + .trvk_revbm_gnt_i ('0), + .trvk_revbm_rvalid_i ('0), + .trvk_revbm_addr_o (), + .trvk_revbm_rdata_i ('0), + .trvk_revbm_rdata_intg_i('0), + .trvk_revbm_err_i ('0), + .irq_software_i ( irq_software ), .irq_timer_i ( irq_timer ), .irq_external_i ( irq_external ), @@ -1012,6 +1026,9 @@ module rv_core_ibex assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q; assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q; + logic unused_cheriot; + assign unused_cheriot = ^{reg2hw.cheriot_ena, reg2hw.cheriot_lock}; + logic unused_reg2hw; assign unused_reg2hw = |reg2hw.rnd_data.q; @@ -1102,7 +1119,8 @@ module rv_core_ibex assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable, reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data, reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err, - reg2hw_shadow.mcounteren_writable}; + reg2hw_shadow.mcounteren_writable, + reg2hw_shadow.cheriot_ena, reg2hw_shadow.cheriot_lock}; ///////////////////////////////////////////////////////////////// // Shadow Core Data Address Translation Unit and TL-UL Adapter // diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv index d7a4734b070cb..ad90d29cf3940 100644 --- a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv +++ b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv @@ -57,9 +57,9 @@ module rv_core_ibex_cfg_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [266:0] reg_we_check; + logic [268:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(267) + .OneHotWidth(269) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -973,6 +973,10 @@ module rv_core_ibex_cfg_reg_top ( logic rnd_status_re; logic rnd_status_rnd_data_valid_qs; logic rnd_status_rnd_data_fips_qs; + logic cheriot_ena_we; + logic [3:0] cheriot_ena_wd; + logic cheriot_lock_we; + logic [3:0] cheriot_lock_wd; logic fpga_info_re; logic [31:0] fpga_info_qs; logic mcounteren_writable_regwen_we; @@ -11682,6 +11686,54 @@ module rv_core_ibex_cfg_reg_top ( ); + // R[cheriot_ena]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessWO), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cheriot_ena ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cheriot_ena_we), + .wd (cheriot_ena_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cheriot_ena.q), + .ds (), + + // to register interface (read) + .qs () + ); + + + // R[cheriot_lock]: V(True) + logic cheriot_lock_qe; + logic [0:0] cheriot_lock_flds_we; + assign cheriot_lock_qe = &cheriot_lock_flds_we; + prim_subreg_ext #( + .DW (4) + ) u_cheriot_lock ( + .re (1'b0), + .we (cheriot_lock_we), + .wd (cheriot_lock_wd), + .d ('0), + .qre (), + .qe (cheriot_lock_flds_we[0]), + .q (reg2hw.cheriot_lock.q), + .ds (), + .qs () + ); + assign reg2hw.cheriot_lock.qe = cheriot_lock_qe; + + // R[fpga_info]: V(True) prim_subreg_ext #( .DW (32) @@ -11758,7 +11810,7 @@ module rv_core_ibex_cfg_reg_top ( - logic [266:0] addr_hit; + logic [268:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RV_CORE_IBEX_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == RV_CORE_IBEX_SW_RECOV_ERR_OFFSET); @@ -12024,9 +12076,11 @@ module rv_core_ibex_cfg_reg_top ( addr_hit[261] = (reg_addr == RV_CORE_IBEX_ERR_STATUS_OFFSET); addr_hit[262] = (reg_addr == RV_CORE_IBEX_RND_DATA_OFFSET); addr_hit[263] = (reg_addr == RV_CORE_IBEX_RND_STATUS_OFFSET); - addr_hit[264] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET); - addr_hit[265] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET); - addr_hit[266] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET); + addr_hit[264] = (reg_addr == RV_CORE_IBEX_CHERIOT_ENA_OFFSET); + addr_hit[265] = (reg_addr == RV_CORE_IBEX_CHERIOT_LOCK_OFFSET); + addr_hit[266] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET); + addr_hit[267] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET); + addr_hit[268] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -12300,7 +12354,9 @@ module rv_core_ibex_cfg_reg_top ( (addr_hit[263] & (|(RV_CORE_IBEX_CFG_PERMIT[263] & ~reg_be))) | (addr_hit[264] & (|(RV_CORE_IBEX_CFG_PERMIT[264] & ~reg_be))) | (addr_hit[265] & (|(RV_CORE_IBEX_CFG_PERMIT[265] & ~reg_be))) | - (addr_hit[266] & (|(RV_CORE_IBEX_CFG_PERMIT[266] & ~reg_be))))); + (addr_hit[266] & (|(RV_CORE_IBEX_CFG_PERMIT[266] & ~reg_be))) | + (addr_hit[267] & (|(RV_CORE_IBEX_CFG_PERMIT[267] & ~reg_be))) | + (addr_hit[268] & (|(RV_CORE_IBEX_CFG_PERMIT[268] & ~reg_be))))); end // Generate write-enables @@ -13108,11 +13164,17 @@ module rv_core_ibex_cfg_reg_top ( assign err_status_recov_core_err_wd = reg_wdata[10]; assign rnd_data_re = addr_hit[262] & reg_re & !reg_error; assign rnd_status_re = addr_hit[263] & reg_re & !reg_error; - assign fpga_info_re = addr_hit[264] & reg_re & !reg_error; - assign mcounteren_writable_regwen_we = addr_hit[265] & reg_we & !reg_error; + assign cheriot_ena_we = addr_hit[264] & reg_we & !reg_error; + + assign cheriot_ena_wd = reg_wdata[3:0]; + assign cheriot_lock_we = addr_hit[265] & reg_we & !reg_error; + + assign cheriot_lock_wd = reg_wdata[3:0]; + assign fpga_info_re = addr_hit[266] & reg_re & !reg_error; + assign mcounteren_writable_regwen_we = addr_hit[267] & reg_we & !reg_error; assign mcounteren_writable_regwen_wd = reg_wdata[0]; - assign mcounteren_writable_we = addr_hit[266] & reg_we & !reg_error; + assign mcounteren_writable_we = addr_hit[268] & reg_we & !reg_error; assign mcounteren_writable_wd = reg_wdata[3:0]; @@ -13382,9 +13444,11 @@ module rv_core_ibex_cfg_reg_top ( reg_we_check[261] = err_status_we; reg_we_check[262] = 1'b0; reg_we_check[263] = 1'b0; - reg_we_check[264] = 1'b0; - reg_we_check[265] = mcounteren_writable_regwen_we; - reg_we_check[266] = mcounteren_writable_gated_we; + reg_we_check[264] = cheriot_ena_we; + reg_we_check[265] = cheriot_lock_we; + reg_we_check[266] = 1'b0; + reg_we_check[267] = mcounteren_writable_regwen_we; + reg_we_check[268] = mcounteren_writable_gated_we; end // Read data return @@ -14457,14 +14521,22 @@ module rv_core_ibex_cfg_reg_top ( end addr_hit[264]: begin - reg_rdata_next[31:0] = fpga_info_qs; + reg_rdata_next[3:0] = '0; end addr_hit[265]: begin - reg_rdata_next[0] = mcounteren_writable_regwen_qs; + reg_rdata_next[3:0] = '0; end addr_hit[266]: begin + reg_rdata_next[31:0] = fpga_info_qs; + end + + addr_hit[267]: begin + reg_rdata_next[0] = mcounteren_writable_regwen_qs; + end + + addr_hit[268]: begin reg_rdata_next[3:0] = mcounteren_writable_qs; end diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv index 9506730750015..2de65c5013154 100644 --- a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv @@ -16,7 +16,7 @@ package rv_core_ibex_reg_pkg; parameter int CfgAw = 11; // Number of registers for every interface - parameter int NumRegsCfg = 267; + parameter int NumRegsCfg = 269; // Alert indices typedef enum int { @@ -110,6 +110,15 @@ package rv_core_ibex_reg_pkg; logic re; } rv_core_ibex_reg2hw_rnd_data_reg_t; + typedef struct packed { + logic [3:0] q; + } rv_core_ibex_reg2hw_cheriot_ena_reg_t; + + typedef struct packed { + logic [3:0] q; + logic qe; + } rv_core_ibex_reg2hw_cheriot_lock_reg_t; + typedef struct packed { logic [3:0] q; } rv_core_ibex_reg2hw_mcounteren_writable_reg_t; @@ -168,18 +177,20 @@ package rv_core_ibex_reg_pkg; // Register -> HW type for cfg interface typedef struct packed { - rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [4408:4401] - rv_core_ibex_reg2hw_sw_recov_err_reg_t sw_recov_err; // [4400:4397] - rv_core_ibex_reg2hw_sw_fatal_err_reg_t sw_fatal_err; // [4396:4393] - rv_core_ibex_reg2hw_ibus_addr_en_mreg_t [31:0] ibus_addr_en; // [4392:4329] - rv_core_ibex_reg2hw_ibus_addr_matching_mreg_t [31:0] ibus_addr_matching; // [4328:3273] - rv_core_ibex_reg2hw_ibus_remap_addr_mreg_t [31:0] ibus_remap_addr; // [3272:2217] - rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [31:0] dbus_addr_en; // [2216:2153] - rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [31:0] dbus_addr_matching; // [2152:1097] - rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [31:0] dbus_remap_addr; // [1096:41] - rv_core_ibex_reg2hw_nmi_enable_reg_t nmi_enable; // [40:39] - rv_core_ibex_reg2hw_nmi_state_reg_t nmi_state; // [38:37] - rv_core_ibex_reg2hw_rnd_data_reg_t rnd_data; // [36:4] + rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [4417:4410] + rv_core_ibex_reg2hw_sw_recov_err_reg_t sw_recov_err; // [4409:4406] + rv_core_ibex_reg2hw_sw_fatal_err_reg_t sw_fatal_err; // [4405:4402] + rv_core_ibex_reg2hw_ibus_addr_en_mreg_t [31:0] ibus_addr_en; // [4401:4338] + rv_core_ibex_reg2hw_ibus_addr_matching_mreg_t [31:0] ibus_addr_matching; // [4337:3282] + rv_core_ibex_reg2hw_ibus_remap_addr_mreg_t [31:0] ibus_remap_addr; // [3281:2226] + rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [31:0] dbus_addr_en; // [2225:2162] + rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [31:0] dbus_addr_matching; // [2161:1106] + rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [31:0] dbus_remap_addr; // [1105:50] + rv_core_ibex_reg2hw_nmi_enable_reg_t nmi_enable; // [49:48] + rv_core_ibex_reg2hw_nmi_state_reg_t nmi_state; // [47:46] + rv_core_ibex_reg2hw_rnd_data_reg_t rnd_data; // [45:13] + rv_core_ibex_reg2hw_cheriot_ena_reg_t cheriot_ena; // [12:9] + rv_core_ibex_reg2hw_cheriot_lock_reg_t cheriot_lock; // [8:4] rv_core_ibex_reg2hw_mcounteren_writable_reg_t mcounteren_writable; // [3:0] } rv_core_ibex_cfg_reg2hw_t; @@ -458,9 +469,11 @@ package rv_core_ibex_reg_pkg; parameter logic [CfgAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 11'h 414; parameter logic [CfgAw-1:0] RV_CORE_IBEX_RND_DATA_OFFSET = 11'h 418; parameter logic [CfgAw-1:0] RV_CORE_IBEX_RND_STATUS_OFFSET = 11'h 41c; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_FPGA_INFO_OFFSET = 11'h 420; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET = 11'h 424; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET = 11'h 428; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_CHERIOT_ENA_OFFSET = 11'h 420; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_CHERIOT_LOCK_OFFSET = 11'h 424; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_FPGA_INFO_OFFSET = 11'h 428; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET = 11'h 42c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET = 11'h 430; // Reset values for hwext registers and their fields for cfg interface parameter logic [3:0] RV_CORE_IBEX_ALERT_TEST_RESVAL = 4'h 0; @@ -473,6 +486,7 @@ package rv_core_ibex_reg_pkg; parameter logic [1:0] RV_CORE_IBEX_RND_STATUS_RESVAL = 2'h 0; parameter logic [0:0] RV_CORE_IBEX_RND_STATUS_RND_DATA_VALID_RESVAL = 1'h 0; parameter logic [0:0] RV_CORE_IBEX_RND_STATUS_RND_DATA_FIPS_RESVAL = 1'h 0; + parameter logic [3:0] RV_CORE_IBEX_CHERIOT_LOCK_RESVAL = 4'h 0; parameter logic [31:0] RV_CORE_IBEX_FPGA_INFO_RESVAL = 32'h 0; parameter logic [31:0] RV_CORE_IBEX_FPGA_INFO_VAL_RESVAL = 32'h 0; @@ -747,13 +761,15 @@ package rv_core_ibex_reg_pkg; RV_CORE_IBEX_ERR_STATUS, RV_CORE_IBEX_RND_DATA, RV_CORE_IBEX_RND_STATUS, + RV_CORE_IBEX_CHERIOT_ENA, + RV_CORE_IBEX_CHERIOT_LOCK, RV_CORE_IBEX_FPGA_INFO, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN, RV_CORE_IBEX_MCOUNTEREN_WRITABLE } rv_core_ibex_cfg_id_e; // Register width information to check illegal writes for cfg interface - parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [267] = '{ + parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [269] = '{ 4'b 0001, // index[ 0] RV_CORE_IBEX_ALERT_TEST 4'b 0001, // index[ 1] RV_CORE_IBEX_SW_RECOV_ERR 4'b 0001, // index[ 2] RV_CORE_IBEX_SW_FATAL_ERR @@ -1018,9 +1034,11 @@ package rv_core_ibex_reg_pkg; 4'b 0011, // index[261] RV_CORE_IBEX_ERR_STATUS 4'b 1111, // index[262] RV_CORE_IBEX_RND_DATA 4'b 0001, // index[263] RV_CORE_IBEX_RND_STATUS - 4'b 1111, // index[264] RV_CORE_IBEX_FPGA_INFO - 4'b 0001, // index[265] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN - 4'b 0001 // index[266] RV_CORE_IBEX_MCOUNTEREN_WRITABLE + 4'b 0001, // index[264] RV_CORE_IBEX_CHERIOT_ENA + 4'b 0001, // index[265] RV_CORE_IBEX_CHERIOT_LOCK + 4'b 1111, // index[266] RV_CORE_IBEX_FPGA_INFO + 4'b 0001, // index[267] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN + 4'b 0001 // index[268] RV_CORE_IBEX_MCOUNTEREN_WRITABLE }; endpackage diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 949658d7af224..be0b5e47f4d9d 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -85,12 +85,14 @@ module top_darjeeling #( parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 3, + parameter int SramCtrlMainNumAddrScrRounds = 2, parameter bit SramCtrlMainEccCorrection = 0, // parameters for sram_ctrl_mbox parameter int SramCtrlMboxInstSize = 4096, parameter int SramCtrlMboxNumRamInst = 1, parameter bit SramCtrlMboxInstrExec = 0, parameter int SramCtrlMboxNumPrinceRoundsHalf = 3, + parameter int SramCtrlMboxNumAddrScrRounds = 2, parameter bit SramCtrlMboxEccCorrection = 0, // parameters for rom_ctrl0 parameter RomCtrl0BootRomInitFile = "", @@ -1874,6 +1876,7 @@ module top_darjeeling #( .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlMainNumAddrScrRounds), .Outstanding(SramCtrlMainOutstanding), .EccCorrection(SramCtrlMainEccCorrection) ) u_sram_ctrl_main ( @@ -1919,6 +1922,7 @@ module top_darjeeling #( .NumRamInst(SramCtrlMboxNumRamInst), .InstrExec(SramCtrlMboxInstrExec), .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlMboxNumAddrScrRounds), .Outstanding(SramCtrlMboxOutstanding), .EccCorrection(SramCtrlMboxEccCorrection) ) u_sram_ctrl_mbox ( diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pd_aon.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pd_aon.sv index 17021bbc3d7a7..5cd0bb66ef39b 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pd_aon.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pd_aon.sv @@ -27,6 +27,7 @@ module top_darjeeling_pd_aon #( parameter int SramCtrlRetAonNumRamInst = 1, parameter bit SramCtrlRetAonInstrExec = 0, parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, + parameter int SramCtrlRetAonNumAddrScrRounds = 2, parameter bit SramCtrlRetAonEccCorrection = 0 ) ( // Inter-module Signal External type @@ -384,6 +385,7 @@ module top_darjeeling_pd_aon #( .NumRamInst(SramCtrlRetAonNumRamInst), .InstrExec(SramCtrlRetAonInstrExec), .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlRetAonNumAddrScrRounds), .Outstanding(SramCtrlRetAonOutstanding), .EccCorrection(SramCtrlRetAonEccCorrection) ) u_sram_ctrl_ret_aon ( diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index 5517072070b03..ccb2296e138e1 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -12,6 +12,7 @@ load("//hw/ip/aes:defs.bzl", "AES") load("//hw/top_earlgrey/ip_autogen/alert_handler:defs.bzl", "ALERT_HANDLER") load("//hw/ip/aon_timer:defs.bzl", "AON_TIMER") load("//hw/top_earlgrey/ip/ast:defs.bzl", "AST") +load("//hw/ip/cheriot:defs.bzl", "CHERIOT") load("//hw/top_earlgrey/ip_autogen/clkmgr:defs.bzl", "CLKMGR") load("//hw/ip/csrng:defs.bzl", "CSRNG") load("//hw/ip/edn:defs.bzl", "EDN") @@ -48,6 +49,7 @@ EARLGREY_IPS = [ ALERT_HANDLER, AON_TIMER, AST, + CHERIOT, CLKMGR, CSRNG, EDN, @@ -143,4 +145,6 @@ EARLGREY_ALERTS = [ "rv_core_ibex_recov_sw_err", "rv_core_ibex_fatal_hw_err", "rv_core_ibex_recov_hw_err", + "cheriot_fatal_fault", + "sram_ctrl_meta_fatal_error", ] diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index c2ee4b7eca050..bac31a51ae9b3 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -604,8 +604,10 @@ edn0 edn1 sram_ctrl_main.regs + sram_ctrl_meta.regs rom_ctrl.regs rv_core_ibex + cheriot.regs ] } ] @@ -1986,8 +1988,8 @@ width: 4 default: "'0" inst_name: otp_ctrl - end_idx: 3 - top_type: partial-one-to-N + end_idx: -1 + top_type: one-to-N top_signame: otp_ctrl_sram_otp_key index: 1 external: true @@ -5860,6 +5862,15 @@ expose: "true" name_top: SramCtrlRetAonNumPrinceRoundsHalf } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumAddrScrRounds + } { name: Outstanding desc: Number of outstanding TLUL transactions @@ -8811,6 +8822,15 @@ expose: "true" name_top: SramCtrlMainNumPrinceRoundsHalf } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlMainNumAddrScrRounds + } { name: Outstanding desc: Number of outstanding TLUL transactions @@ -9190,9 +9210,11 @@ ipgen_params: { num_regions: 2 + cheriot_available: true } param_decl: { + BaseIsa: ibex_pkg::BaseIsaRV32IorCHERIoT PMPEnable: "1" PMPGranularity: "0" PMPNumRegions: "16" @@ -9201,6 +9223,9 @@ PMPRstCfg: ibex_pmp_reset_pkg::PmpCfgRst PMPRstAddr: ibex_pmp_reset_pkg::PmpAddrRst PMPRstMsecCfg: ibex_pmp_reset_pkg::PmpMseccfgRst + CheriotRevBitmapAddrWidth: "9" + CheriotRevBitmapBaseAddr: 32'h1100_0000 + CheriotTrvkHeapBaseAddr: 32'h1000_0000 RV32E: "0" RV32M: ibex_pkg::RV32MSingleCycle RV32B: ibex_pkg::RV32BOTEarlGrey @@ -9364,6 +9389,42 @@ expose: "true" name_top: RvCoreIbexPMPRstMsecCfg } + { + name: BaseIsa + desc: Base ISA + type: ibex_pkg::base_isa_e + default: ibex_pkg::BaseIsaRV32IorCHERIoT + local: "false" + expose: "true" + name_top: RvCoreIbexBaseIsa + } + { + name: CheriotRevBitmapAddrWidth + desc: Address width of the TRVK revocation bitmap + type: int unsigned + default: "9" + local: "false" + expose: "true" + name_top: RvCoreIbexCheriotRevBitmapAddrWidth + } + { + name: CheriotRevBitmapBaseAddr + desc: Base address of the TRVK revocation bitmap + type: int unsigned + default: 32'h1100_0000 + local: "false" + expose: "true" + name_top: RvCoreIbexCheriotRevBitmapBaseAddr + } + { + name: CheriotTrvkHeapBaseAddr + desc: Base address of the heap + type: int unsigned + default: 32'h1000_0000 + local: "false" + expose: "true" + name_top: RvCoreIbexCheriotTrvkHeapBaseAddr + } { name: RV32E desc: RV32E @@ -9602,6 +9663,80 @@ inst_name: rv_core_ibex index: -1 } + { + name: cheriot_ena + desc: CHERIoT mode enable. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + default: prim_mubi_pkg::MuBi4False + inst_name: rv_core_ibex + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_cheriot_ena + index: -1 + } + { + name: cored_tl_h + desc: Core data host port to CHERIoT subsystem + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rv_core_ibex_cored_tl_h + index: -1 + } + { + name: cored_tag_h2d + desc: CHERIoT capability tag carried with the A-channel of cored_h. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: rv_core_ibex + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_cored_tag_h2d + index: -1 + } + { + name: cored_tag_d2h + desc: Capability tag returned on the D-channel of cored_h. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_core_ibex + package: "" + domain: Main + top_signame: cheriot_cored_tag_d2h + index: -1 + } + { + name: corerevbm_tl + desc: Core revocation bitmap host port + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rv_core_ibex_corerevbm_tl + index: -1 + } { name: ram_cfg_icache_tag struct: ram_1p_cfg @@ -9868,7 +10003,7 @@ default: "" domain: Main top_signame: otp_ctrl_sram_otp_key - index: 2 + index: 3 } { name: fpga_info @@ -9897,19 +10032,6 @@ top_signame: main_tl_rv_core_ibex__corei index: -1 } - { - name: cored_tl_h - struct: tl - package: tlul_pkg - type: req_rsp - act: req - width: 1 - inst_name: rv_core_ibex - default: "" - domain: Main - top_signame: main_tl_rv_core_ibex__cored - index: -1 - } { name: cfg_tl_d struct: tl @@ -9935,106 +10057,633 @@ generate_dif: true domain: Main } - ] - port: - [ { - name: ast + name: cheriot + type: cheriot + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: Main + } + } + param_decl: + { + MainSramBaseAddr: 32'h1000_0000 + MainSramTopAddr: 32'h1002_0000 + NvmBaseAddr: 32'h2000_0000 + NvmTopAddr: 32'h2020_0000 + MetaSramBaseAddr: 32'h1100_0000 + } + base_addrs: + { + regs: + { + hart: 0x411B0000 + } + revbm: + { + hart: 0x11000000 + } + } + memory: + { + revbm: + { + label: cheriot_revbm + swaccess: rw + data_intg_passthru: True + exec: False + byte_write: False + size: 0x800 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks_i.clk_main_infra + } + param_list: + [ + { + name: MainSramBaseAddr + desc: Base address of the main SRAM region (inclusive) + type: logic [top_pkg::TL_AW-1:0] + default: 32'h1000_0000 + local: "false" + expose: "true" + name_top: CheriotMainSramBaseAddr + } + { + name: MainSramTopAddr + desc: Top address of the main SRAM region (exclusive). + type: logic [top_pkg::TL_AW-1:0] + default: 32'h1002_0000 + local: "false" + expose: "true" + name_top: CheriotMainSramTopAddr + } + { + name: NvmBaseAddr + desc: Base address of the NVM region (inclusive). + type: logic [top_pkg::TL_AW-1:0] + default: 32'h2000_0000 + local: "false" + expose: "true" + name_top: CheriotNvmBaseAddr + } + { + name: NvmTopAddr + desc: Top address of the NVM region (exclusive). + type: logic [top_pkg::TL_AW-1:0] + default: 32'h2020_0000 + local: "false" + expose: "true" + name_top: CheriotNvmTopAddr + } + { + name: MetaSramBaseAddr + desc: Base address of the CHERIoT meta SRAM region. + type: logic [top_pkg::TL_AW-1:0] + default: 32'h1100_0000 + local: "false" + expose: "true" + name_top: CheriotMetaSramBaseAddr + } + ] inter_signal_list: [ { - struct: edn - type: req_rsp - name: edn - act: rsp - package: edn_pkg - inst_name: ast + name: cheriot_ena + desc: CHERIoT mode enable. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv width: 1 - default: "" + default: prim_mubi_pkg::MuBi4False + inst_name: cheriot domain: Main - top_signame: edn0_edn - index: 2 - external: true - conn_type: true + top_signame: rv_core_ibex_cheriot_ena + index: -1 } { - struct: lc_tx - type: uni - name: lc_dft_en - act: req - package: lc_ctrl_pkg - inst_name: ast + name: cored_tl_d + desc: Data port from the core. + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp width: 1 + inst_name: cheriot default: "" domain: Main - top_signame: lc_ctrl_lc_dft_en + top_signame: rv_core_ibex_cored_tl_h index: -1 - external: true - conn_type: true } { - struct: ram_1p_cfg - package: prim_ram_1p_pkg + name: cored_tag_h2d + desc: CHERIoT capability tag carried with the A-channel of cored_h. + struct: logic type: uni - name: ram_1p_cfg act: rcv - inst_name: ast width: 1 - default: "" - end_idx: -1 - top_type: broadcast - top_signame: ast_ram_1p_cfg + default: 1'b0 + inst_name: cheriot + package: "" + domain: Main + top_signame: rv_core_ibex_cored_tag_h2d index: -1 - external: true - conn_type: true } { - struct: ram_2p_cfg - package: prim_ram_2p_pkg + name: cored_tag_d2h + desc: Capability tag returned on the D-channel of cored_h. + struct: logic type: uni - name: spi_ram_2p_cfg - act: rcv - inst_name: ast + act: req width: 1 - default: "" + default: 1'b0 + inst_name: cheriot + package: "" end_idx: -1 top_type: broadcast - top_signame: ast_spi_ram_2p_cfg + top_signame: cheriot_cored_tag_d2h index: -1 - external: true - conn_type: true } { - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - name: usb_ram_1p_cfg - act: rcv - inst_name: ast + name: corerevbm_tl + desc: TRVK (tag revocation) revocation bitmap port from the core. + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp width: 1 + inst_name: cheriot default: "" - end_idx: -1 - top_type: broadcast - top_signame: ast_usb_ram_1p_cfg + domain: Main + top_signame: rv_core_ibex_corerevbm_tl index: -1 - external: true - conn_type: true } { - struct: rom_cfg - package: prim_rom_pkg - type: uni - name: rom_cfg - act: rcv - inst_name: ast + name: meta_sram_tl + desc: Host TL-UL port to the external meta SRAM controller's RAM interface. + struct: tl + package: tlul_pkg + type: req_rsp + act: req width: 1 + inst_name: cheriot default: "" end_idx: -1 - top_type: broadcast - top_signame: ast_rom_cfg + top_type: one-to-one + top_signame: cheriot_meta_sram_tl index: -1 - external: true - conn_type: true + } + { + name: cored_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: cheriot + default: "" + domain: Main + top_signame: main_tl_cheriot__cored + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: cheriot + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: cheriot_regs_tl_d + index: -1 + } + { + name: revbm_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: cheriot + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: cheriot_revbm_tl_d + index: -1 + } + ] + generate_dif: true + domain: Main + } + { + name: sram_ctrl_meta + type: sram_ctrl + clock_srcs: + { + clk_i: main + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: Main + } + rst_otp_ni: + { + name: lc_io_div4 + domain: Main + } + } + param_decl: + { + InstrExec: "0" + NumAddrScrRounds: "0" + NumPrinceRoundsHalf: "2" + InstSize: "36864" + } + base_addrs: + { + regs: + { + hart: 0x411D0000 + } + ram: + { + hart: 0x11000000 + } + } + memory: + { + ram: + { + label: ram_cheriot_meta + swaccess: rw + data_intg_passthru: "true" + exec: False + byte_write: False + size: 0x9000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks_i.clk_main_infra + clk_otp_i: clkmgr_aon_clocks_i.clk_io_div4_infra + } + param_list: + [ + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlMetaRam + default: 36864 + } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: "36864" + local: "false" + expose: "true" + name_top: SramCtrlMetaInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMetaNumRamInst + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMetaInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlMetaNumPrinceRoundsHalf + } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMetaNumAddrScrRounds + } + { + name: Outstanding + desc: Number of outstanding TLUL transactions + type: int + default: "2" + local: "true" + expose: "true" + name_top: SramCtrlMetaOutstanding + } + { + name: EccCorrection + desc: Enable single-bit error correction and error logging + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMetaEccCorrection + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_meta + default: "" + domain: Main + top_signame: otp_ctrl_sram_otp_key + index: 2 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMetaNumRamInst + } + inst_name: sram_ctrl_meta + default: "" + external: true + conn_type: false + index: -1 + top_signame: sram_ctrl_meta_cfg + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMetaNumRamInst + } + default: "'0" + inst_name: sram_ctrl_meta + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_meta + domain: Main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_meta + domain: Main + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_meta + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_meta + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_meta + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_meta + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_meta + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: sram_ctrl_meta_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_meta + default: "" + domain: Main + top_signame: cheriot_meta_sram_tl + index: -1 + } + ] + generate_dif: true + domain: Main + } + ] + port: + [ + { + name: ast + inter_signal_list: + [ + { + struct: edn + type: req_rsp + name: edn + act: rsp + package: edn_pkg + inst_name: ast + width: 1 + default: "" + domain: Main + top_signame: edn0_edn + index: 2 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_dft_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + domain: Main + top_signame: lc_ctrl_lc_dft_en + index: -1 + external: true + conn_type: true + } + { + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + name: ram_1p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_ram_1p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + name: spi_ram_2p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_spi_ram_2p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + name: usb_ram_1p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_usb_ram_1p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: rom_cfg + package: prim_rom_pkg + type: uni + name: rom_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_rom_cfg + index: -1 + external: true + conn_type: true } { struct: ast_obs_ctrl @@ -10134,6 +10783,7 @@ [ sram_ctrl_main.sram_otp_key sram_ctrl_ret_aon.sram_otp_key + sram_ctrl_meta.sram_otp_key rv_core_ibex.icache_otp_key ] pwrmgr_aon.pwr_nvm: @@ -10328,6 +10978,7 @@ lc_ctrl.lc_hw_debug_en: [ sram_ctrl_main.lc_hw_debug_en + sram_ctrl_meta.lc_hw_debug_en pinmux_aon.lc_hw_debug_en csrng.lc_hw_debug_en rv_dm.lc_hw_debug_en @@ -10350,6 +11001,7 @@ otp_ctrl.lc_escalate_en sram_ctrl_main.lc_escalate_en sram_ctrl_ret_aon.lc_escalate_en + sram_ctrl_meta.lc_escalate_en aon_timer_aon.lc_escalate_en flash_ctrl.lc_escalate_en pinmux_aon.lc_escalate_en @@ -10417,6 +11069,18 @@ [ pwrmgr_aon.pwr_cpu ] + rv_core_ibex.cored_tl_h: + [ + cheriot.cored_tl_d + ] + rv_core_ibex.corerevbm_tl: + [ + cheriot.corerevbm_tl + ] + rv_core_ibex.cored_tag_h2d: + [ + cheriot.cored_tag_h2d + ] spi_device.passthrough: [ spi_host0.passthrough @@ -10429,6 +11093,18 @@ [ pwrmgr_aon.sw_rst_req ] + cheriot.meta_sram_tl: + [ + sram_ctrl_meta.ram_tl + ] + cheriot.cored_tag_d2h: + [ + rv_core_ibex.cored_tag_d2h + ] + rv_core_ibex.cheriot_ena: + [ + cheriot.cheriot_ena + ] pwrmgr_aon.wakeups: [ sysrst_ctrl_aon.wkup_req @@ -10447,9 +11123,9 @@ [ rv_core_ibex.corei_tl_h ] - main.tl_rv_core_ibex__cored: + main.tl_cheriot__cored: [ - rv_core_ibex.cored_tl_h + cheriot.cored_tl_h ] main.tl_rv_dm__sba: [ @@ -10551,6 +11227,18 @@ [ main.tl_sram_ctrl_main__ram ] + sram_ctrl_meta.regs_tl: + [ + main.tl_sram_ctrl_meta__regs + ] + cheriot.regs_tl_d: + [ + main.tl_cheriot__regs + ] + cheriot.revbm_tl_d: + [ + main.tl_cheriot__revbm + ] uart0.tl: [ peri.tl_uart0 @@ -10675,6 +11363,7 @@ ast.ram_1p_cfg: ram_1p_cfg sram_ctrl_main.cfg: "" sram_ctrl_ret_aon.cfg: "" + sram_ctrl_meta.cfg: "" ast.spi_ram_2p_cfg: spi_ram_2p_cfg ast.usb_ram_1p_cfg: usb_ram_1p_cfg ast.rom_cfg: rom_cfg @@ -10787,7 +11476,7 @@ sram_ctrl_main.ram flash_ctrl.mem ] - rv_core_ibex.cored: + cheriot.cored: [ rom_ctrl.rom rom_ctrl.regs @@ -10813,6 +11502,9 @@ kmac sram_ctrl_main.regs rv_core_ibex.cfg + sram_ctrl_meta.regs + cheriot.regs + cheriot.revbm ] rv_dm.sba: [ @@ -10840,6 +11532,9 @@ kmac sram_ctrl_main.regs rv_core_ibex.cfg + sram_ctrl_meta.regs + cheriot.regs + cheriot.revbm ] } nodes: @@ -10858,7 +11553,7 @@ rsp_fifo_pass: true } { - name: rv_core_ibex.cored + name: cheriot.cored type: host addr_space: hart clock: clk_main_i @@ -11417,6 +12112,72 @@ stub: false req_fifo_pass: true } + { + name: sram_ctrl_meta.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x411d0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: cheriot.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: cheriot + addr_range: + [ + { + base_addrs: + { + hart: 0x411b0000 + } + size_byte: 0x4 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: cheriot.revbm + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: cheriot + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + pipeline: true + } ] addr_spaces: [ @@ -11441,7 +12202,7 @@ index: -1 } { - name: tl_rv_core_ibex__cored + name: tl_cheriot__cored struct: tl package: tlul_pkg type: req_rsp @@ -11451,7 +12212,7 @@ default: "" end_idx: -1 top_type: one-to-one - top_signame: main_tl_rv_core_ibex__cored + top_signame: main_tl_cheriot__cored index: -1 } { @@ -11781,6 +12542,45 @@ top_signame: sram_ctrl_main_ram_tl index: -1 } + { + name: tl_sram_ctrl_meta__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: sram_ctrl_meta_regs_tl + index: -1 + } + { + name: tl_cheriot__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: cheriot_regs_tl_d + index: -1 + } + { + name: tl_cheriot__revbm + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: cheriot_revbm_tl_d + index: -1 + } ] } { @@ -14925,6 +15725,10 @@ { signal: "'{ram_1p_cfg}" } + sram_ctrl_meta.cfg: + { + signal: "'{ram_1p_cfg}" + } clkmgr_aon.calib_rdy: { signal: ast_init_done @@ -15092,6 +15896,10 @@ { unused: true } + sram_ctrl_meta.cfg: + { + unused: true + } pinmux_aon.dft_hold_tap_sel: { unused: true @@ -16080,6 +16888,28 @@ lpg_name: infra_lc_Main lpg_idx: 17 } + { + name: cheriot_fatal_fault + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: cheriot + desc: cheriot fatal_fault alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } + { + name: sram_ctrl_meta_fatal_error + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: sram_ctrl_meta + desc: sram_ctrl_meta fatal_error alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } ] outgoing_alert: {} interrupt: @@ -18173,7 +19003,7 @@ signame: otp_ctrl_sram_otp_key_req width: 1 type: req_rsp - end_idx: 3 + end_idx: -1 act: rsp suffix: req default: "'0" @@ -18185,7 +19015,7 @@ signame: otp_ctrl_sram_otp_key_rsp width: 1 type: req_rsp - end_idx: 3 + end_idx: -1 act: rsp suffix: rsp default: "'0" @@ -18989,6 +19819,8 @@ sram_ctrl_main rom_ctrl rv_core_ibex + cheriot + sram_ctrl_meta ] alert_connections: { @@ -19406,17 +20238,37 @@ alert_handler[62]: recov_hw_err ] } + module_cheriot: + { + tx_expr: alert_tx[63] + rx_expr: alert_rx[63] + async_expr: alert_handler_reg_pkg::AsyncOn[63] + comments: + [ + alert_handler[63]: fatal_fault + ] + } + module_sram_ctrl_meta: + { + tx_expr: alert_tx[64] + rx_expr: alert_rx[64] + async_expr: alert_handler_reg_pkg::AsyncOn[64] + comments: + [ + alert_handler[64]: fatal_error + ] + } } alert_handler_info: { alert_handler: { domain: Main - count_tot: 63 + count_tot: 65 count_pd: { Aon: 11 - Main: 52 + Main: 54 } connect_pd: { @@ -21015,8 +21867,8 @@ width: 4 default: "'0" inst_name: otp_ctrl - end_idx: 3 - top_type: partial-one-to-N + end_idx: -1 + top_type: one-to-N top_signame: otp_ctrl_sram_otp_key index: 1 external: true @@ -25735,26 +26587,100 @@ index: -1 } { - name: rom_tl + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rom_ctrl_rom_tl + index: -1 + } + { + name: rst_cpu_n + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + index: -1 + } + { + name: cheriot_ena + desc: CHERIoT mode enable. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + default: prim_mubi_pkg::MuBi4False + inst_name: rv_core_ibex + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_cheriot_ena + index: -1 + } + { + name: cored_tl_h + desc: Core data host port to CHERIoT subsystem + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rv_core_ibex_cored_tl_h + index: -1 + } + { + name: cored_tag_h2d + desc: CHERIoT capability tag carried with the A-channel of cored_h. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: rv_core_ibex + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_cored_tag_h2d + index: -1 + } + { + name: cored_tag_d2h + desc: Capability tag returned on the D-channel of cored_h. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_core_ibex + package: "" + domain: Main + top_signame: cheriot_cored_tag_d2h + index: -1 + } + { + name: corerevbm_tl + desc: Core revocation bitmap host port struct: tl package: tlul_pkg type: req_rsp - act: rsp + act: req width: 1 - inst_name: rom_ctrl + inst_name: rv_core_ibex default: "" end_idx: -1 top_type: one-to-one - top_signame: rom_ctrl_rom_tl - index: -1 - } - { - name: rst_cpu_n - struct: logic - type: uni - act: req - width: 1 - inst_name: rv_core_ibex + top_signame: rv_core_ibex_corerevbm_tl index: -1 } { @@ -26023,7 +26949,7 @@ default: "" domain: Main top_signame: otp_ctrl_sram_otp_key - index: 2 + index: 3 } { name: fpga_info @@ -26037,46 +26963,319 @@ external: true conn_type: false index: -1 - top_signame: fpga_info + top_signame: fpga_info + } + { + name: corei_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + domain: Main + top_signame: main_tl_rv_core_ibex__corei + index: -1 + } + { + name: cfg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rv_core_ibex_cfg_tl_d + index: -1 + } + { + name: cheriot_ena + desc: CHERIoT mode enable. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4False + inst_name: cheriot + domain: Main + top_signame: rv_core_ibex_cheriot_ena + index: -1 + } + { + name: cored_tl_d + desc: Data port from the core. + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: cheriot + default: "" + domain: Main + top_signame: rv_core_ibex_cored_tl_h + index: -1 + } + { + name: cored_tag_h2d + desc: CHERIoT capability tag carried with the A-channel of cored_h. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: cheriot + package: "" + domain: Main + top_signame: rv_core_ibex_cored_tag_h2d + index: -1 + } + { + name: cored_tag_d2h + desc: Capability tag returned on the D-channel of cored_h. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: cheriot + package: "" + end_idx: -1 + top_type: broadcast + top_signame: cheriot_cored_tag_d2h + index: -1 + } + { + name: corerevbm_tl + desc: TRVK (tag revocation) revocation bitmap port from the core. + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: cheriot + default: "" + domain: Main + top_signame: rv_core_ibex_corerevbm_tl + index: -1 + } + { + name: meta_sram_tl + desc: Host TL-UL port to the external meta SRAM controller's RAM interface. + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: cheriot + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: cheriot_meta_sram_tl + index: -1 + } + { + name: cored_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: cheriot + default: "" + domain: Main + top_signame: main_tl_cheriot__cored + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: cheriot + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: cheriot_regs_tl_d + index: -1 + } + { + name: revbm_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: cheriot + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: cheriot_revbm_tl_d + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_meta + default: "" + domain: Main + top_signame: otp_ctrl_sram_otp_key + index: 2 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMetaNumRamInst + } + inst_name: sram_ctrl_meta + default: "" + external: true + conn_type: false + index: -1 + top_signame: sram_ctrl_meta_cfg + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMetaNumRamInst + } + default: "'0" + inst_name: sram_ctrl_meta + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_meta + domain: Main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_meta + domain: Main + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_meta + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_meta + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_meta + index: -1 } { - name: corei_tl_h - struct: tl - package: tlul_pkg - type: req_rsp + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni act: req width: 1 - inst_name: rv_core_ibex - default: "" - domain: Main - top_signame: main_tl_rv_core_ibex__corei + inst_name: sram_ctrl_meta index: -1 } { - name: cored_tl_h + name: regs_tl struct: tl package: tlul_pkg type: req_rsp - act: req + act: rsp width: 1 - inst_name: rv_core_ibex + inst_name: sram_ctrl_meta default: "" - domain: Main - top_signame: main_tl_rv_core_ibex__cored + end_idx: -1 + top_type: one-to-one + top_signame: sram_ctrl_meta_regs_tl index: -1 } { - name: cfg_tl_d + name: ram_tl struct: tl package: tlul_pkg type: req_rsp act: rsp width: 1 - inst_name: rv_core_ibex + inst_name: sram_ctrl_meta default: "" - end_idx: -1 - top_type: one-to-one - top_signame: rv_core_ibex_cfg_tl_d + domain: Main + top_signame: cheriot_meta_sram_tl index: -1 } { @@ -26094,7 +27293,7 @@ index: -1 } { - name: tl_rv_core_ibex__cored + name: tl_cheriot__cored struct: tl package: tlul_pkg type: req_rsp @@ -26104,7 +27303,7 @@ default: "" end_idx: -1 top_type: one-to-one - top_signame: main_tl_rv_core_ibex__cored + top_signame: main_tl_cheriot__cored index: -1 } { @@ -26434,6 +27633,45 @@ top_signame: sram_ctrl_main_ram_tl index: -1 } + { + name: tl_sram_ctrl_meta__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: sram_ctrl_meta_regs_tl + index: -1 + } + { + name: tl_cheriot__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: cheriot_regs_tl_d + index: -1 + } + { + name: tl_cheriot__revbm + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: cheriot_revbm_tl_d + index: -1 + } { name: tl_main struct: tl @@ -28737,6 +29975,35 @@ index: -1 netname: sram_ctrl_ret_aon_cfg } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + domain: Main + inter_pd: false + signame: sram_ctrl_meta_cfg_i + signame_chip: + { + asic: "'{ram_1p_cfg}" + cw340: "'{prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT}" + } + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMetaNumRamInst + } + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_meta_cfg + } { package: prim_ram_2p_pkg struct: ram_2p_cfg @@ -30937,7 +32204,7 @@ signame: otp_ctrl_sram_otp_key_req width: 4 type: req_rsp - end_idx: 3 + end_idx: -1 act: rsp suffix: req default: "'0" @@ -30949,7 +32216,7 @@ signame: otp_ctrl_sram_otp_key_rsp width: 4 type: req_rsp - end_idx: 3 + end_idx: -1 act: rsp suffix: rsp default: "'0" @@ -31746,6 +33013,66 @@ suffix: "" default: "'0" } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: rv_core_ibex_cored_tl_h_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: rv_core_ibex_cored_tl_h_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: rv_core_ibex_corerevbm_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: rv_core_ibex_corerevbm_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: "" + struct: logic + domain: Main + signame: rv_core_ibex_cored_tag_h2d + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: 1'b0 + } { package: spi_device_pkg struct: passthrough_req @@ -31782,6 +33109,54 @@ suffix: "" default: prim_mubi_pkg::MUBI4_DEFAULT } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: cheriot_meta_sram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: cheriot_meta_sram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: "" + struct: logic + domain: Main + signame: cheriot_cored_tag_d2h + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: 1'b0 + } + { + package: prim_mubi_pkg + struct: mubi4 + domain: Main + signame: rv_core_ibex_cheriot_ena + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: prim_mubi_pkg::MuBi4False + } { package: "" struct: logic @@ -31834,7 +33209,7 @@ package: tlul_pkg struct: tl_h2d domain: Main - signame: main_tl_rv_core_ibex__cored_req + signame: main_tl_cheriot__cored_req width: 1 type: req_rsp end_idx: -1 @@ -31846,7 +33221,7 @@ package: tlul_pkg struct: tl_d2h domain: Main - signame: main_tl_rv_core_ibex__cored_rsp + signame: main_tl_cheriot__cored_rsp width: 1 type: req_rsp end_idx: -1 @@ -32454,6 +33829,78 @@ suffix: rsp default: "" } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: sram_ctrl_meta_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: sram_ctrl_meta_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: cheriot_regs_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: cheriot_regs_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: cheriot_revbm_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: cheriot_revbm_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } { package: tlul_pkg struct: tl_h2d diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson index 7276299151c9b..ca380212401b8 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson @@ -47,7 +47,7 @@ randcount: 40 randtype: data name_top: RndCnstOtpCtrlLfsrSeed - default: 0x9caa47e5ce + default: 0xce1cf9e202 randwidth: 40 } { @@ -57,7 +57,7 @@ randcount: 40 randtype: perm name_top: RndCnstOtpCtrlLfsrPerm - default: 0x92008344a54d5df3076e61840052592ce89221c7908416255948d33dd6a7 + default: 0x2db9a04931427083d612779888a74600c8c752135925f9500d55d168e064 randwidth: 240 } { @@ -67,7 +67,7 @@ randcount: 256 randtype: data name_top: RndCnstOtpCtrlScrmblKeyInit - default: 0x2a71d66b5953dbc603379da9efb2069bd79815b2f8d99a40e7fdc4fb13143d77 + default: 0xa7f8b17fa88fee02e3f0864223a2e23a8cc31e2de5e578d43d2dce49e360cfb5 randwidth: 256 } { @@ -2935,7 +2935,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivInvalid - default: 0x53ce1cf9e2029207396945c95c9b54ba + default: 0x94acddf170684f6ead2b7febfe895523 randwidth: 128 } { @@ -2945,7 +2945,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked - default: 0xe6aef30d8577834ccc6caaa63a8e6604 + default: 0xd7bc4846a485956c7f904b9eded09b89 randwidth: 128 } { @@ -2955,7 +2955,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivDev - default: 0x338151b9a23c08f9eed04ca1ebb0bdd3 + default: 0xa75433566f4963d9dc27f3ecb11ce3b8 randwidth: 128 } { @@ -2965,7 +2965,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivProduction - default: 0x5ffb6c4818054e0e0edb0acd0b040fc + default: 0x7aaa7abc85920b1881083aff7bde18ea randwidth: 128 } { @@ -2975,7 +2975,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivRma - default: 0x629ea7f8b17fa88fee02e3f0864223a2 + default: 0xcff85679453da77d92a176b87118af11 randwidth: 128 } { @@ -2985,7 +2985,7 @@ randcount: 1024 randtype: data name_top: RndCnstLcCtrlInvalidTokens - default: 0xe23a8cc31e2de5e578d43d2dce49e360cfb594acddf170684f6ead2b7febfe895523d7bc4846a485956c7f904b9eded09b89a75433566f4963d9dc27f3ecb11ce3b87aaa7abc85920b1881083aff7bde18eacff85679453da77d92a176b87118af11cdbe78d67060615a20b9c0740f07969ccd2d10a1a6e7988fa528ac032e0a + default: 0xcdbe78d67060615a20b9c0740f07969ccd2d10a1a6e7988fa528ac032e0a6138cb8316ff95c65cd7a1a768b06e0106d60eda0f1bc67adf85bd9a56ea088d33ffaa6a1155afb0169ab2de3973d027ee30b8f901f644ec7cd3e56c8ed1ec38739f1d0deb7c774199cf6dd057f44c13e25c7a5877bc5242e6ee63ecdf458ae6596e randwidth: 1024 } ] @@ -3010,7 +3010,7 @@ randcount: 32 randtype: data name_top: RndCnstAlertHandlerLfsrSeed - default: 0x6138cb83 + default: 0x87f9f973 randwidth: 32 } { @@ -3020,7 +3020,7 @@ randcount: 32 randtype: perm name_top: RndCnstAlertHandlerLfsrPerm - default: 0x21bfe532078bb254f11778e61a83b66ee9a5e242 + default: 0x973a43f9d7248bb1cd76e050f7d801c552a567b randwidth: 160 } ] @@ -3061,7 +3061,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetAonSramKey - default: 0x169ab2de3973d027ee30b8f901f644ec + default: 0x1ff0189b04a4f7fba960fe098a4fb9d4 randwidth: 128 } { @@ -3071,7 +3071,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetAonSramNonce - default: 0x7cd3e56c8ed1ec38739f1d0deb7c7741 + default: 0x69171b950e364b0dac5469568e661498 randwidth: 128 } { @@ -3081,7 +3081,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlRetAonLfsrSeed - default: 0x99cf6dd057f44c13 + default: 0xfd89197ccae8ea08 randwidth: 64 } { @@ -3091,7 +3091,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlRetAonLfsrPerm - default: 0x96c1f7f8d3bf2419cb13ddb9ae94f53f3ec27ca330488d32c6e0dae8582d6401a3564a2a99c85bf22458414bdd59e5f8 + default: 0x8084a61e3f7ace5382676e0d70ca7224a0275a457c4e111edcbd456b4a14622ac6b81b5f743f916cfe57ab1b2fc3b43f randwidth: 384 } ] @@ -3145,7 +3145,7 @@ randcount: 128 randtype: data name_top: RndCnstFlashCtrlAddrKey - default: 0x69568e661498fd89197ccae8ea08ff43 + default: 0x57c22c884ed49d87a5b56ba7353c5321 randwidth: 128 } { @@ -3155,7 +3155,7 @@ randcount: 128 randtype: data name_top: RndCnstFlashCtrlDataKey - default: 0xefc2bfb1c6ab5cc63e6f4741e80f777c + default: 0x42f50667e220c5b724c3fdb6d060653b randwidth: 128 } { @@ -3165,7 +3165,7 @@ randcount: 512 randtype: data name_top: RndCnstFlashCtrlAllSeeds - default: 0xb7fc05041a1b896350c9636d6814d23e2f5ff1275ef19959aaa8b6a004d5574984ded1cc79bd6787d6663aa5e622682a6525e083ccddbd2a1b008057c22c884e + default: 0x42a96f88b574e4d3814f5116b3e6f3e331da1182dbc29c894f1800edecf7b17682d2ce3db9b12e1af4339e1f45164a418ebc52210d58dc65508e869af565c1b8 randwidth: 512 } { @@ -3175,7 +3175,7 @@ randcount: 32 randtype: data name_top: RndCnstFlashCtrlLfsrSeed - default: 0xd49d87a5 + default: 0x7d687ee8 randwidth: 32 } { @@ -3185,7 +3185,7 @@ randcount: 32 randtype: perm name_top: RndCnstFlashCtrlLfsrPerm - default: 0x4b862905f72f7d15c39ac6e7fae58041147351b6 + default: 0x4412aadb8cfb5e5ee69b093c706871c49d75cc46 randwidth: 160 } ] @@ -3211,7 +3211,7 @@ randcount: 64 randtype: data name_top: RndCnstAesClearingLfsrSeed - default: 0x4f1800edecf7b176 + default: 0x7d513aea01e9ee42 randwidth: 64 } { @@ -3221,7 +3221,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingLfsrPerm - default: 0xc6824af1d7b6e2b6fdde9895b41fc2d4073af98972397e5310d91a7ea9a1c3b6560c852f8d04854479cc18bb2e3f3d20 + default: 0xb62a538f363d42fafb9f820bd85125911e667dd33f83067c5dc6c2541a0d86a39e1d2eb1faeb3424ad771b201a3d4583 randwidth: 384 } { @@ -3231,7 +3231,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingSharePerm - default: 0x128e70ad3d98bb121d15b8238aa46970ce17b752e6ff49190950653619fd7874b3decbc9286cbb68ff960d0f00e8e51f + default: 0x7fe7abf6d1d4755961ffc8ec34870e2b4a8c450bc24b8eb2c1b5976991b3a4f127ba683b26214b035c68db94c3918dc1 randwidth: 384 } { @@ -3241,7 +3241,7 @@ randcount: 288 randtype: data name_top: RndCnstAesMaskingLfsrSeed - default: 0xdf0a4f7dff07db05de63910e4ee4d8a2c7d4022f16ed8a24f80eebcf8299839c103eae3c + default: 0x5c0cae7ed7fe6c45d1534fd390c7b068cfe8968794de88e8ff4adc3d02ebfa0a1d5faa5e randwidth: 288 } { @@ -3251,7 +3251,7 @@ randcount: 160 randtype: perm name_top: RndCnstAesMaskingLfsrPerm - default: 0x60190a71809b6a5a2864990446967288875d3712311f95425638901b8b767d3a099a8f412d93533c628351494c78333b654f2a7a4e47107f79027b23395c77352b307c146f070c9e4d5b17507389450d213e1c245f548408328c15206e03110b741a527e9d55970e05861e984485434b67345863488227296822369c8a8e062e0f706992914a013d2c133f6d4075570026618d811d16949f256c595e6b66182f + default: 0x3a4b95836675195f84465a2d54244d269a8a727e6d023c672f59118f8d9748516a1d824c63583d61773e077a6e50884e7b7114333f324498761f1e255c8000793b2c4f3794299b8613089e3670435e93575b6962150922381264019c0a1c9d0490600353999f0b6f7892681b7c6c55210f31205d7445054a477396526b2b56857f28890e18308c412e8e0d278b1a427d394916351065812a408706231791340c randwidth: 1280 } ] @@ -3276,7 +3276,7 @@ randcount: 288 randtype: data name_top: RndCnstKmacLfsrSeed - default: 0x2c229957b7d159740ca72ce50c55920ba14e126dcd0a3f6c9b71d03e571bee0e47e5b49 + default: 0x23f40e358f1bf4fe1d5a50b10232a8b3c33a6017b97036561aa26231042404e5ef74645b randwidth: 288 } { @@ -3286,7 +3286,7 @@ randcount: 800 randtype: perm name_top: RndCnstKmacLfsrPerm - default: 0x1ddf635e4e89ada52cd5389f165d0c8d42fa9ea0260ca4f6d5596af1a1c00141e334a3a65b6829499d0747ee9076c258fe56c2a316dd74b307b1bca1a1a3044224401eb5ea95a38e778d177b54c5c493b79d883cf08b95b026603d1466e1c15ccf530cc0bc2b4b4c44b7020af1bec6d15131c67a646bb17fa51f2ae08b816677e65b29dfea69858409fbba5f06cdd12f0f425d988145aede10b20e5ae4187d0d4d4c1378fe7b8f1b627b940077354043c6b549f441ec872ab56f2fb8aad94ea13c44309911fa21ec8f54401a7d1b9ad3edb57831d70c1c415ce48eed576b735222342cb6a40e912ff845025ec9eb04b63eabac50ee569a36fde859e5250ddf19d6c1c45c49dc29663e6b8f21f803c0e3655e9f91cd80a4017ea02b35838cdc9b85bd190025f6e4869a8960780528f4517866804999c817c9a5a0179747273f0b3a11d1897292196acb0e480aea36db2593caacb86115e53cdb92c289febda00908dc3e3a9797dd8d8129178a8491411a6eaa266b344a345bd55a72be48a3937db45d67794c0b38cf8779f8468aa73315928ed7f5c42dece856f610d1e4ec3abd21c5c0dcba126bf5d24d02dae5da169866300c460ba7fec38953fa4b1275018412934065a1b4324de709ceadc4ea188e1251ed126e5733182140c4bde6dc712a598352b4b08226374e5c5b47c0b8b9649e4c3201638a4541943fcb108d87b58b2b157c586f869e4f3f4e59c81690ca6a0e75666b0c69b3472283dc56c12f160426b42a30fd2e6aa0c2466c11d0a908f35dcab68a19b7d9036908a26f558b0da08ecb11fcb2671931dc3452c696d2210c6200d62cee223083bbe2d7594dc06a4252a8996e33991134abf19a7ea94522743c95431155312362185eb18007d214415581d324a057d933208ab530818c5d1b27c2b26b0dceb8609c09e8a139f3054769461621aa9a99067bda41c07f9a1399e81f181b0be44500159c02c0b9e034a569c19b163d030a98a44ca99e5e602a382a11b124cfb9b198b249b085b6e469adb091610b5911962e6a560246ca61064796e8e18bce4505d72bd0e5514a15c5e04822c0a1b6ec614e2092fdea3f20b74316520484d8398ad2f0f42b48481570a2ba846745a0b1f180ec889517e7960d16434c7916b821e29685654730db0720a814cd284adf5ab0955d8c7b74bd9b84a6ad6e03ee9239af670c5c14331447a819248eda1979c721ce04c21d249322ee97c419d2f865c7ccb102f2935512d6fa8a4ce108bc03698aba87a7a14bf9639d99b3bd535831734e07a31899884f72d3e716ca699ac9bd25085d56781a5aa9d9028b539e713598baed767e9664413041881a8d9b9580a8808508758f03823ec625efc2d23a150897c0c2b3ce98c8533e52d89e78bcddd9a4f6 + default: 0x98252c01f83b9df1dd1048eea73d9675aa193246801790b1f2b4d5b9f2e08a18d909c99cdbf3348f8b6f127d556684baa9ce17d8c5bded8845545c017d27db6507bf983286d622d276b89d766a2bda9189ec229eb614b0830de474d7b0147b3542544580402577b9fa775fe8716b05175a7d056dd45408d26e18665ec9adf06a52dc2621276df968c20435dc9a92080474b56b1bff079206f35e10c2f103f978aa215aa5821127b7801b9928028ef0bdf19450932166d37464b8e745b0c00a43c19ada3eaa4c500739d92532ec1aedfb96753426c548d47a1da37ab85feb35195722430a12365a0f225302019091b9ca05ecea5713959407841c43e86c46507fd353d23e5e9b67180e6a17d8e50c38a08650b6305bc98ef39e1c11c9c07b0caad49a7dd3c53e1819d431c45cb8531a4a5b7d91d47c7e3c4038e9a959ead994d800adb1a0043c0091302f732f83a20518988999b387cb483cae8094d259159ea8d2e14b5c97136eb00a2a0a98e6242530f8ea78d3d91573969c2975b4046bcb4899c7512926de61165afae248a3d37dd29caf55100b38cf82308dbe4aa7ace99fced1f5e22def2a3949c6aef10d1e4ef180ea4f8dd85371bd498137c55a4d02db75fb1695d70f0c7a40c460ba5c15e106e79053fad2c7afc18412a7405d81b5de0c937a424eb40c2b0d748fe9951eba26e559de0cbf450311b5a4e22973054a9660d4ad2c268a0f128c64b5b47c0b8b96b4d925e1aa3d8e839509471b69cff2c42361efa2cae95f161c3dc485cfd3963c05a6129aa584599b5243a8d1c910f76f856b103160426bd3030fd2e6aa25246b211d0a97cf35de1368a34881903690872204b2d62645f03b2e8866ed8926b8c1fd750d14b20ab448431880358b3a09fc8d6d8abefcaaebd07ac5279cd6962a332c12913a1e31f88cab468f53eec620d56074c92815f64cc822ac09c0631746cc54acc5c373ae3327027ab04e8b9f3a24151da718588689accb21067bda41c07fa2139a6c1f181b0bec45001591aae4bba034a569509b163d030a98a44ca9a6a477980a8e0a846c49928cfc292d8b267b985b6e4699667e0e05842d649611962e8a560246cabb064796e8e18bce4505d72bd0e5514a15c5e04822c261b6ec614e2092fdea3f20b9e5d08c948121360e62b4bc3d0ad212055c28b0e119d1a71a0c70f90ec889517e7960d164349a516c121e29685654730d87520a814cd284adf5b3c955d8c7c04bd9b84a6ad6eae40fc348e6bd9c31408b34331447a819248eda1979c721ce04c21d249322ee971519d2f8653d8cb10316935512d71e8a4ce108bc03698aba87a7a14041639d99b3bd535805334e07a31899884f72d3e716ca699ac9bd25085d56781a5aa9d9028b539e713598baed767e96 randwidth: 8000 } { @@ -3296,7 +3296,7 @@ randcount: 800 randtype: data name_top: RndCnstKmacBufferLfsrSeed - default: 0xadcdfc5c5f76d4a8e259d88dfe9b670aa0dd992bfe5d2e12489d22504aa7ac1c67f59cba5482c1e35e6e3335c20cc778fc309917b9c870abe0895d76f862ef81f419e3c6cdc8662c71eac141666e443c6492d9bcf7a82420750e5dfc5e3ed4f2907532e1 + default: 0x3335c20cc778fc309917b9c870abe0895d76f862ef81f419e3c6cdc8662c71eac141666e443c6492d9bcf7a82420750e5dfc5e3ed4f2907532e179ebec7ed7d3a5ef4982f73ed91c4b1cd0c85ec5e548b40184a69eb1e54396460e36c55c459efe9e4383 randwidth: 800 } { @@ -3306,7 +3306,7 @@ randcount: 64 randtype: perm name_top: RndCnstKmacMsgPerm - default: 0x6413b04d41226a3ac89962ef089605b8a93ccdd56cd8631cfdbdeaa31343465427e6102df97cbde073e04a9d357fbe9e + default: 0xb3b8145b84219701bd602251d1a7280cf1f7c7f213d9d985ab28c0a57b8b373927112d4a06d562f0efabbdf319e5ee9b randwidth: 384 } ] @@ -3331,7 +3331,7 @@ randcount: 288 randtype: data name_top: RndCnstOtbnUrndPrngSeed - default: 0xdd57022c77ede8609c409d905b3c7819b26a674328819928c5d79bf1db63d11e1c31bbc9 + default: 0xca6bc0b96812de7c775a54ff19343cb32040b3490768889d27e0ba8588d34c05bcf127da randwidth: 288 } { @@ -3341,7 +3341,7 @@ randcount: 256 randtype: perm name_top: RndCnstOtbnBnMacUrndPerm - default: 0xeb13709f16df872123f810902ad0740a3972b4d876a0f957bdc21cb27b310c0960a9bb798eae36fd2dc1ac32e94192450b825b4e1da3667524be9aec2fdd9358ed7f2b8f33043ee4f5a71135efc8a54baa1e01c68c17c5f3ce3763f653f7cd46b89818156d02ff6cd1f2fc422cd20fd9db00738d26c306afd76496c9f04dfa61ee699b2852a41f8a486fe8f14fa1255d3acfab2e945edaa61b6259ad67296a0e55d644869eb722430ddcb5b0d5898197fe3b7e7d38565c6e30917ae24a78d4e6509cb683bf4784cb035f951afbb1e571e799800851a2658be1bc054cd3e385bae0279d88f40749ea4020b33c3419545a777cde1268b9c06bca143dccc43fc7a8 + default: 0xcba9d4daf76d68e2c51263231d79f8bc88d05773c25a27f42d72ad6175d1068213bd45102120461c0993b0ecff4e140af253fe98b9ef87b8a63996326c174d3c642cea743126c776a5df9aaeb4bb36a18e9041d334db16f39f7faa3f8da7c93d7092d77b196bf6c066d2abe44233e68ceec13e1800c411355b15ede7dd4be91e022f240f9b2b8f776037d92a04b2b58558a0014ce00cd50bdc5469a32852ba8a1fa4486f407c4fbe255d3af5c82e945e05c3ac1b6259afca67296a0e55a8fd44869ed822430df9fce3fb898197b7e8eb3b7e7dcd38ce565c6e3091c67a9d4a78faf149e1509cb683bf4784f0de035f951acfccb10771b399800851a2d6658be5 randwidth: 2048 } { @@ -3351,7 +3351,7 @@ randcount: 128 randtype: data name_top: RndCnstOtbnOtbnKey - default: 0xbef1f0b924c470ac5a99809985dc415b + default: 0x2030621a4d3d73871fdaf5ad0c1dd1e randwidth: 128 } { @@ -3361,7 +3361,7 @@ randcount: 64 randtype: data name_top: RndCnstOtbnOtbnNonce - default: 0xa1eaced382d54c9e + default: 0x95f99d7129ca6861 randwidth: 64 } ] @@ -3386,7 +3386,7 @@ randcount: 64 randtype: data name_top: RndCnstKeymgrLfsrSeed - default: 0x378d030ea5d37665 + default: 0xa4425b9cc42edba8 randwidth: 64 } { @@ -3396,7 +3396,7 @@ randcount: 64 randtype: perm name_top: RndCnstKeymgrLfsrPerm - default: 0x6f2f25138426806ba968f86ac76091bde2eb50c359174ed21d673f23a9f705dce4c2c0e27d5b498fe2bd639a135c03b5 + default: 0x6b87978462c36608c73d622ab25d09cf507fda8c50540f7b3ba73947eaca7c2c92353de96c475832fc249ae9fc52d162 randwidth: 384 } { @@ -3406,7 +3406,7 @@ randcount: 32 randtype: perm name_top: RndCnstKeymgrRandPerm - default: 0x5ce46d907d6fa3665558800fafde88124b9e3c2e + default: 0x85e8b7f63bf28a310247d131c9e59677ea9305a8 randwidth: 160 } { @@ -3416,7 +3416,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrRevisionSeed - default: 0x6d07801b027bd4e9bf578b146f616b6082465e44680ce93649a84575b465479f + default: 0x227a978179aa2e6adc5ea5fd83777d387766ba9e8c77a65b1aad174dd41aca70 randwidth: 256 } { @@ -3426,7 +3426,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrCreatorIdentitySeed - default: 0x31a975234377e00d28ec32fa5850e8a7f607a49b2cade12af0dd48b9227a9781 + default: 0xd3807ba54e793023fa711994ccf5d2f42daffa84621ab157014b70509da8413d randwidth: 256 } { @@ -3436,7 +3436,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOwnerIntIdentitySeed - default: 0x79aa2e6adc5ea5fd83777d387766ba9e8c77a65b1aad174dd41aca70d3807ba5 + default: 0xda43fecdd6c1a58693232d1c3e361d856ab2d1dc6455d87f13c9a4671446bea8 randwidth: 256 } { @@ -3446,7 +3446,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOwnerIdentitySeed - default: 0x4e793023fa711994ccf5d2f42daffa84621ab157014b70509da8413dda43fecd + default: 0x56d5fbb54bb5b253a70bc372cfc9bb0ab38a5edabee7d224d1a668378437dd24 randwidth: 256 } { @@ -3456,7 +3456,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrSoftOutputSeed - default: 0xd6c1a58693232d1c3e361d856ab2d1dc6455d87f13c9a4671446bea856d5fbb5 + default: 0x797b602b068c0a1aeca298c96a8130ab336462cee1bf8c653fde5a40a24df78e randwidth: 256 } { @@ -3466,7 +3466,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrHardOutputSeed - default: 0x4bb5b253a70bc372cfc9bb0ab38a5edabee7d224d1a668378437dd24797b602b + default: 0x146916dc55f8ce6dbfaad08910fbe1822c22a17a376fa1315c0cb3c29cf4d10a randwidth: 256 } { @@ -3476,7 +3476,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrAesSeed - default: 0x68c0a1aeca298c96a8130ab336462cee1bf8c653fde5a40a24df78e146916dc + default: 0xe5c8f0c7b034bf23c9068e307d8513b7734aa78cc36f947a2737bbc0acd1447b randwidth: 256 } { @@ -3486,7 +3486,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrKmacSeed - default: 0x55f8ce6dbfaad08910fbe1822c22a17a376fa1315c0cb3c29cf4d10ae5c8f0c7 + default: 0xaa83c3fc818bb3b4a840ad3214ceb3f354ca2e089302c3ee1d695aa616283205 randwidth: 256 } { @@ -3496,7 +3496,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOtbnSeed - default: 0xb034bf23c9068e307d8513b7734aa78cc36f947a2737bbc0acd1447baa83c3fc + default: 0xdb05cd6c18888ad01fe046eafd8bf298db7d5fe0fd32a29689a0c1549c28c210 randwidth: 256 } { @@ -3506,7 +3506,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrCdi - default: 0x818bb3b4a840ad3214ceb3f354ca2e089302c3ee1d695aa616283205db05cd6c + default: 0xc01ff7e6e6d20e0404e7b51d020aa3695df42597cacaea4e16ef75a4823ee1bf randwidth: 256 } { @@ -3516,7 +3516,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrNoneSeed - default: 0x18888ad01fe046eafd8bf298db7d5fe0fd32a29689a0c1549c28c210c01ff7e6 + default: 0x100b50c3a2c1ba79a60bd0d947c26d8d3c3874c6b8e34a85925ce73b8f155098 randwidth: 256 } ] @@ -3541,7 +3541,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivNonProduction - default: 0xe6d20e0404e7b51d020aa3695df42597cacaea4e16ef75a4823ee1bf100b50c3a2c1ba79a60bd0d947c26d8d3c3874c6 + default: 0x5eb503e8e40713152d132e9e94da720a712d7d6b7326f3102ba57ab12f0c11e464e613088d6df2cc4352aa62df6b0719 randwidth: 384 } { @@ -3551,7 +3551,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivProduction - default: 0xb8e34a85925ce73b8f1550985eb503e8e40713152d132e9e94da720a712d7d6b7326f3102ba57ab12f0c11e464e61308 + default: 0x9ea6c6782ad9bb2e78fa04c68991de3b57a9b61206e6c0a2afa6a3c56d97128c7811e36a2829db025ec69547062345c4 randwidth: 384 } ] @@ -3591,7 +3591,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramKey - default: 0x8d6df2cc4352aa62df6b07199ea6c678 + default: 0xf5ef1b06a119650a85c30237536dc3 randwidth: 128 } { @@ -3601,7 +3601,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramNonce - default: 0x2ad9bb2e78fa04c68991de3b57a9b612 + default: 0xe35040de9ac1a6f2b35c99fb71e1aaab randwidth: 128 } { @@ -3611,7 +3611,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlMainLfsrSeed - default: 0x6e6c0a2afa6a3c5 + default: 0x3c208383adf50311 randwidth: 64 } { @@ -3621,7 +3621,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlMainLfsrPerm - default: 0xd85e43b8c91da6f4ab25c7cf9f2aa0e87d153bb2d69984e243cfd436d84266ca301b5cc8051fb15c0dca6b8f5e8c495b + default: 0xc4564278f7ef9e8275134f5d3ba60a4e5b79422b94f0bf973164abdb88601f237ba40543681b309b76e3cea20691173f randwidth: 384 } ] @@ -3661,7 +3661,7 @@ randcount: 64 randtype: data name_top: RndCnstRomCtrlScrNonce - default: 0xd35500e5a51bba34 + default: 0xae3157b7279a2bd0 randwidth: 64 } { @@ -3671,7 +3671,7 @@ randcount: 128 randtype: data name_top: RndCnstRomCtrlScrKey - default: 0xa71d81e9eb876b6f1996b2be4b58dfcf + default: 0xf45178add4099b463a9bfadeb0a249e6 randwidth: 128 } ] @@ -3696,7 +3696,7 @@ randcount: 32 randtype: data name_top: RndCnstRvCoreIbexLfsrSeed - default: 0xb830b9e2 + default: 0x7a25feea randwidth: 32 } { @@ -3706,7 +3706,7 @@ randcount: 32 randtype: perm name_top: RndCnstRvCoreIbexLfsrPerm - default: 0xd77e228d8f0e22749897b391954fc06c255e536b + default: 0x1bfb401d1ff454c2cccbae6fa4c2cec09bb20792 randwidth: 160 } { @@ -3716,7 +3716,7 @@ randcount: 128 randtype: data name_top: RndCnstRvCoreIbexIbexKeyDefault - default: 0xb7279a2bd0f45178add4099b463a9bfa + default: 0x57a6a15faa577395193cde4a6705bd11 randwidth: 128 } { @@ -3726,11 +3726,81 @@ randcount: 64 randtype: data name_top: RndCnstRvCoreIbexIbexNonceDefault - default: 0xdeb0a249e67a25fe + default: 0x203330a927a8ce1a randwidth: 64 } ] template_type: rv_core_ibex } + { + name: sram_ctrl_meta + type: sram_ctrl + base_addrs: + { + regs: + { + hart: 0x411D0000 + } + ram: + { + hart: 0x11000000 + } + } + memory: + { + ram: + { + label: ram_cheriot_meta + swaccess: rw + data_intg_passthru: "true" + exec: False + byte_write: False + size: 0x9000 + } + } + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMetaSramKey + default: 0xc88224a441c4192abe1dc426feee2c9b + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMetaSramNonce + default: 0x1c8b34b1a821afe522e11c4049d9b85f + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstSramCtrlMetaLfsrSeed + default: 0x9dc3c99a37868579 + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstSramCtrlMetaLfsrPerm + default: 0x1e9e0fd27066eb555141332258a788677ef98fdb2efb6f332df18e030fc492851bc98bcd49d26572bc43160a970a16ad + randwidth: 384 + } + ] + } ] } diff --git a/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson b/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson index 4a779431a79c6..4f5a11908a6e7 100644 --- a/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson +++ b/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson @@ -112,6 +112,7 @@ "0x94949494", "0x94949494", "0x94949494", + "0x94949494", ], }, { @@ -162,19 +163,19 @@ }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", - value: "0x6db5ced", + value: "0x18cbd487", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", - value: "0x68737b02", + value: "0x7663f368", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", - value: "0x9c389f87", + value: "0x822817ed", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", - value: "0xc20dd3a6", + value: "0xdc1d5bcc", }, { name: "OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG", diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 4f5cf143b85b0..ab263cdb6fd76 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -243,8 +243,10 @@ "edn0" "edn1", "sram_ctrl_main.regs" + "sram_ctrl_meta.regs" "rom_ctrl.regs", - "rv_core_ibex" + "rv_core_ibex", + "cheriot.regs" ] } ] @@ -989,8 +991,10 @@ attr: "ipgen", ipgen_params: { num_regions: 2 + cheriot_available: true } - param_decl: {PMPEnable: "1", + param_decl: {BaseIsa: "ibex_pkg::BaseIsaRV32IorCHERIoT", + PMPEnable: "1", PMPGranularity: "0", PMPNumRegions: "16", MHPMCounterNum: "2", @@ -998,6 +1002,9 @@ PMPRstCfg: "ibex_pmp_reset_pkg::PmpCfgRst", PMPRstAddr: "ibex_pmp_reset_pkg::PmpAddrRst", PMPRstMsecCfg: "ibex_pmp_reset_pkg::PmpMseccfgRst", + CheriotRevBitmapAddrWidth: "9", + CheriotRevBitmapBaseAddr: "32'h1100_0000", + CheriotTrvkHeapBaseAddr: "32'h1000_0000", RV32E: "0", RV32M: "ibex_pkg::RV32MSingleCycle", RV32B: "ibex_pkg::RV32BOTEarlGrey", @@ -1041,6 +1048,62 @@ hart: "0x411F0000", }, }, + { name: "cheriot", + type: "cheriot", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + param_decl: { + MainSramBaseAddr: "32'h1000_0000", + MainSramTopAddr: "32'h1002_0000", + NvmBaseAddr: "32'h2000_0000", + NvmTopAddr: "32'h2020_0000", + MetaSramBaseAddr: "32'h1100_0000", + }, + base_addrs: { + regs: {hart: "0x411B0000"}, + revbm: {hart: "0x11000000"}, + }, + memory: { + revbm: { + label: "cheriot_revbm", + swaccess: "rw", + data_intg_passthru: "True", + exec: "False", + byte_write: "False", + size: "0x800" + } + }, + }, + { name: "sram_ctrl_meta", + type: "sram_ctrl", + clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, + param_decl: { + InstrExec: "0", + // Temporarily disabled to support non-power-of-two depth + NumAddrScrRounds: "0", + NumPrinceRoundsHalf: "2", + InstSize: "36864", + }, + base_addrs: { + regs: {hart: "0x411D0000"}, + ram: {hart: "0x11000000"} + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_cheriot_meta", + swaccess: "rw", + data_intg_passthru: "true", + exec: "False", + byte_write: "False", + size: "0x9000" + } + } + }, ], // The port data structure is not something that should be used liberally. @@ -1154,6 +1217,7 @@ 'lc_ctrl.lc_nvm_rma_seed' : ['flash_ctrl.rma_seed'], 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', 'sram_ctrl_ret_aon.sram_otp_key', + 'sram_ctrl_meta.sram_otp_key', 'rv_core_ibex.icache_otp_key'], 'pwrmgr_aon.pwr_nvm' : ['flash_ctrl.pwrmgr'], 'pwrmgr_aon.pwr_rst' : ['rstmgr_aon.pwr'], @@ -1243,6 +1307,7 @@ 'rv_dm.lc_hw_debug_clr'], 'lc_ctrl.lc_init_done' : ['rv_dm.lc_init_done'], 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', + 'sram_ctrl_meta.lc_hw_debug_en', 'pinmux_aon.lc_hw_debug_en', 'csrng.lc_hw_debug_en', 'rv_dm.lc_hw_debug_en', @@ -1256,6 +1321,7 @@ 'otp_ctrl.lc_escalate_en', 'sram_ctrl_main.lc_escalate_en', 'sram_ctrl_ret_aon.lc_escalate_en', + 'sram_ctrl_meta.lc_escalate_en', 'aon_timer_aon.lc_escalate_en', 'flash_ctrl.lc_escalate_en', 'pinmux_aon.lc_escalate_en'], @@ -1289,8 +1355,11 @@ // rv core ibex connections - 'rv_core_ibex.crash_dump' : ['rstmgr_aon.cpu_dump'], - 'rv_core_ibex.pwrmgr' : ['pwrmgr_aon.pwr_cpu'], + 'rv_core_ibex.crash_dump' : ['rstmgr_aon.cpu_dump'], + 'rv_core_ibex.pwrmgr' : ['pwrmgr_aon.pwr_cpu'], + 'rv_core_ibex.cored_tl_h' : ['cheriot.cored_tl_d'], + 'rv_core_ibex.corerevbm_tl' : ['cheriot.corerevbm_tl'], + 'rv_core_ibex.cored_tag_h2d' : ['cheriot.cored_tag_h2d'], // spi passthrough connection 'spi_device.passthrough' : ['spi_host0.passthrough'], @@ -1300,6 +1369,11 @@ // Reset manager software reset request to pwrmgr 'rstmgr_aon.sw_rst_req' : ['pwrmgr_aon.sw_rst_req'], + + // CHERIoT connections + 'cheriot.meta_sram_tl' : ['sram_ctrl_meta.ram_tl'], + 'cheriot.cored_tag_d2h' : ['rv_core_ibex.cored_tag_d2h'], + 'rv_core_ibex.cheriot_ena' : ['cheriot.cheriot_ena'], }, // top is to connect to top net/struct. @@ -1350,6 +1424,7 @@ 'ast.ram_1p_cfg' : 'ram_1p_cfg', 'sram_ctrl_main.cfg' : '', 'sram_ctrl_ret_aon.cfg' : '', + 'sram_ctrl_meta.cfg' : '', 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', 'ast.usb_ram_1p_cfg' : 'usb_ram_1p_cfg', 'ast.rom_cfg' : 'rom_cfg', @@ -1652,6 +1727,7 @@ 'ast.lc_dft_en' : { signal: 'lc_dft_en' }, 'sram_ctrl_main.cfg' : { signal: "'{ram_1p_cfg}" }, 'sram_ctrl_ret_aon.cfg' : { signal: "'{ram_1p_cfg}" }, + 'sram_ctrl_meta.cfg' : { signal: "'{ram_1p_cfg}" }, 'clkmgr_aon.calib_rdy' : { signal: 'ast_init_done' }, 'flash_ctrl.flash_test_mode_a' : { signal: "{FLASH_TEST_MODE1, FLASH_TEST_MODE0}"}, 'flash_ctrl.flash_test_voltage_h' : { signal: 'FLASH_TEST_VOLT' }, @@ -1741,6 +1817,7 @@ 'clkmgr_aon.calib_rdy' : { signal: 'ast_init_done' }, 'sram_ctrl_main.cfg' : { unused: true }, 'sram_ctrl_ret_aon.cfg' : { unused: true }, + 'sram_ctrl_meta.cfg' : { unused: true }, 'pinmux_aon.dft_hold_tap_sel' : { unused: true }, 'pinmux_aon.usb_dnpullup_en' : { unused: true }, 'pinmux_aon.dft_strap_test' : { unused: true }, diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index 717b7b9e3c5c1..e9f69c2a5b7cb 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson @@ -31,7 +31,7 @@ reset: "rst_main_ni", pipeline: false }, - { name: "rv_core_ibex.cored", + { name: "cheriot.cored", type: "host", addr_space: "hart", clock: "clk_main_i", @@ -216,16 +216,38 @@ reset: "rst_main_ni", pipeline: false }, + { name: "sram_ctrl_meta.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "cheriot.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "cheriot.revbm", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, ], connections: { rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.mem", "sram_ctrl_main.ram", "flash_ctrl.mem"], - rv_core_ibex.cored: [ + cheriot.cored: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev", "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", - "rv_core_ibex.cfg" + "rv_core_ibex.cfg", "sram_ctrl_meta.regs", "cheriot.regs", + "cheriot.revbm" ], rv_dm.sba: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", @@ -233,7 +255,8 @@ "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", - "rv_core_ibex.cfg", + "rv_core_ibex.cfg", "sram_ctrl_meta.regs", "cheriot.regs", + "cheriot.revbm" ], }, } diff --git a/hw/top_earlgrey/doc/memory_map.md b/hw/top_earlgrey/doc/memory_map.md index 38b9419aff08a..883e285dd53b1 100644 --- a/hw/top_earlgrey/doc/memory_map.md +++ b/hw/top_earlgrey/doc/memory_map.md @@ -58,6 +58,8 @@ The main address space, shared between the CPU and DM | sram_ctrl_main | regs | `0x411C0000` | `0x40` | `0x10` | regs device on sram_ctrl_main | | rom_ctrl | regs | `0x411E0000` | `0x80` | `0x20` | regs device on rom_ctrl | | rv_core_ibex | cfg | `0x411F0000` | `0x100` | `0x40` | cfg device on rv_core_ibex | +| cheriot | regs | `0x411B0000` | `0x4` | `0x1` | regs device on cheriot | +| sram_ctrl_meta | regs | `0x411D0000` | `0x40` | `0x10` | regs device on sram_ctrl_meta | ### Memory Blocks @@ -67,3 +69,5 @@ The main address space, shared between the CPU and DM | flash_ctrl | mem | `0x20000000` | `0x100000` | `0x40000` | | sram_ctrl_main | ram | `0x10000000` | `0x20000` | `0x8000` | | rom_ctrl | rom | `0x8000` | `0x8000` | `0x2000` | +| cheriot | revbm | `0x11000000` | `0x800` | `0x200` | +| sram_ctrl_meta | ram | `0x11000000` | `0x9000` | `0x2400` | diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index c3b78899aad5b..67a8a0f6178eb 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv @@ -67,3 +67,5 @@ assign alert_if[59].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0]; assign alert_if[60].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1]; assign alert_if[61].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2]; assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3]; +assign alert_if[63].alert_tx = `CHIP_HIER.u_cheriot.alert_tx_o[0]; +assign alert_if[64].alert_tx = `CHIP_HIER.u_sram_ctrl_meta.alert_tx_o[0]; diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index 633f71d4d3877..b1b232cf8a850 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv @@ -38,7 +38,7 @@ wire clk_io_div4; clk_rst_if clk_rst_if_io_div4(.clk(clk_io_div4), .rst_n(rst_n)); tl_if rv_core_ibex__corei_tl_if(clk_main, rst_n); -tl_if rv_core_ibex__cored_tl_if(clk_main, rst_n); +tl_if cheriot__cored_tl_if(clk_main, rst_n); tl_if rv_dm__sba_tl_if(clk_main, rst_n); tl_if rv_dm__regs_tl_if(clk_main, rst_n); @@ -64,6 +64,9 @@ tl_if keymgr_tl_if(clk_main, rst_n); tl_if rv_core_ibex__cfg_tl_if(clk_main, rst_n); tl_if sram_ctrl_main__regs_tl_if(clk_main, rst_n); tl_if sram_ctrl_main__ram_tl_if(clk_main, rst_n); +tl_if sram_ctrl_meta__regs_tl_if(clk_main, rst_n); +tl_if cheriot__regs_tl_if(clk_main, rst_n); +tl_if cheriot__revbm_tl_if(clk_main, rst_n); tl_if uart0_tl_if(clk_io_div4, rst_n); tl_if uart1_tl_if(clk_io_div4, rst_n); tl_if uart2_tl_if(clk_io_div4, rst_n); @@ -119,7 +122,7 @@ initial begin `ifndef GATE_LEVEL `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__corei, rv_core_ibex, corei_tl_h) - `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__cored, rv_core_ibex, cored_tl_h) + `DRIVE_CHIP_TL_HOST_IF(cheriot__cored, cheriot, cored_tl_h) `DRIVE_CHIP_TL_HOST_IF(rv_dm__sba, rv_dm, sba_tl_h) `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__regs, rv_dm, regs_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__mem, rv_dm, mem_tl_d) @@ -144,6 +147,9 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex__cfg, rv_core_ibex, cfg_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__regs, sram_ctrl_main, regs_tl) `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__ram, sram_ctrl_main, ram_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_meta__regs, sram_ctrl_meta, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(cheriot__regs, cheriot, regs_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(cheriot__revbm, cheriot, revbm_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(uart0, uart0, tl) `DRIVE_CHIP_TL_DEVICE_IF(uart1, uart1, tl) `DRIVE_CHIP_TL_DEVICE_IF(uart2, uart2, tl) diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index c8490de6787e5..fdbcc8261a77b 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -76,6 +76,15 @@ tl_device_t xbar_devices[$] = '{ '{"sram_ctrl_main__ram", '{ '{32'h10000000, 32'h1001ffff} }}, + '{"sram_ctrl_meta__regs", '{ + '{32'h411d0000, 32'h411d003f} + }}, + '{"cheriot__regs", '{ + '{32'h411b0000, 32'h411b0003} + }}, + '{"cheriot__revbm", '{ + '{32'h11000000, 32'h110007ff} + }}, '{"uart0", '{ '{32'h40000000, 32'h4000003f} }}, @@ -160,7 +169,7 @@ tl_host_t xbar_hosts[$] = '{ "sram_ctrl_main__ram", "flash_ctrl__mem"}} , - '{"rv_core_ibex__cored", 1, '{ + '{"cheriot__cored", 1, '{ "rom_ctrl__rom", "rom_ctrl__regs", "rv_dm__mem", @@ -208,7 +217,10 @@ tl_host_t xbar_hosts[$] = '{ "keymgr", "kmac", "sram_ctrl_main__regs", - "rv_core_ibex__cfg"}} + "rv_core_ibex__cfg", + "sram_ctrl_meta__regs", + "cheriot__regs", + "cheriot__revbm"}} , '{"rv_dm__sba", 2, '{ "rom_ctrl__rom", @@ -258,5 +270,8 @@ tl_host_t xbar_hosts[$] = '{ "keymgr", "kmac", "sram_ctrl_main__regs", - "rv_core_ibex__cfg"}} + "rv_core_ibex__cfg", + "sram_ctrl_meta__regs", + "cheriot__regs", + "cheriot__revbm"}} }; diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 7bad143feef58..cae0e6708c63b 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -111,6 +111,19 @@ -node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[31:31] -node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[27:17] -node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[31:29] +-node tb.dut*.u_sram_ctrl_meta regs_tl_*i.a_address[15:6] +-node tb.dut*.u_sram_ctrl_meta regs_tl_*i.a_address[17:17] +-node tb.dut*.u_sram_ctrl_meta regs_tl_*i.a_address[23:21] +-node tb.dut*.u_sram_ctrl_meta regs_tl_*i.a_address[29:25] +-node tb.dut*.u_sram_ctrl_meta regs_tl_*i.a_address[31:31] +-node tb.dut*.u_cheriot regs_tl_*i.a_address[15:2] +-node tb.dut*.u_cheriot regs_tl_*i.a_address[18:18] +-node tb.dut*.u_cheriot regs_tl_*i.a_address[23:21] +-node tb.dut*.u_cheriot regs_tl_*i.a_address[29:25] +-node tb.dut*.u_cheriot regs_tl_*i.a_address[31:31] +-node tb.dut*.u_cheriot revbm_tl_*i.a_address[23:11] +-node tb.dut*.u_cheriot revbm_tl_*i.a_address[27:25] +-node tb.dut*.u_cheriot revbm_tl_*i.a_address[31:29] -node tb.dut*.u_uart0 tl_*i.a_address[29:6] -node tb.dut*.u_uart0 tl_*i.a_address[31:31] -node tb.dut*.u_uart1 tl_*i.a_address[15:6] diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 35532d856f373..54c5d9d1043b3 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv @@ -4,7 +4,7 @@ // Generated by topgen.py -parameter uint NUM_ALERTS = 63; +parameter uint NUM_ALERTS = 65; parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "uart0_fatal_fault", "uart1_fatal_fault", @@ -68,5 +68,7 @@ parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "rv_core_ibex_fatal_sw_err", "rv_core_ibex_recov_sw_err", "rv_core_ibex_fatal_hw_err", - "rv_core_ibex_recov_hw_err" + "rv_core_ibex_recov_hw_err", + "cheriot_fatal_fault", + "sram_ctrl_meta_fatal_error" }; diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv index 5e8e7671e0034..f58883f293456 100644 --- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv +++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv @@ -265,8 +265,13 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base // Disable functional coverage of comportable IP-specific specialized registers. // Chip level testbench does not sample these coverpoints. protected virtual function void pre_build_ral_settings(dv_base_reg_block ral); + RAL_T chip_ral; super.pre_build_ral_settings(ral); ral.set_en_dv_reg_cov(0); + // sram_ctrl_meta.ram is not on the main XBAR - it is only reachable via + // the cheriot.revbm port, which is already mapped at the same address. + // Registering both causes a UVM_WARNING (overlap) that fails the test. + if ($cast(chip_ral, ral)) chip_ral.create_sram_ctrl_meta_ram = 1'b0; endfunction // Apply RAL fixes before it is locked. diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv index aa86f4a77ffc0..e8d1769e266f0 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv @@ -579,14 +579,14 @@ class chip_sw_rv_core_ibex_lockstep_glitch_vseq extends chip_sw_base_vseq; "data_addr_o", "data_wdata_o": begin $assertoff(0, - "tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_rv_core_ibex__cored.gen_device"); + "tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cheriot__cored.gen_device"); end // The RF read data obtained on Port b may feed into data_wdata_o even if Ibex isn't doing // a store. "rf_rdata_b_ecc_i": begin if (glitched_inp_used) begin $assertoff(0, - "tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_rv_core_ibex__cored.gen_device"); + "tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cheriot__cored.gen_device"); end end // There are several SVAs inside ibex_top ensuring correct behavior of crash dump. When diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 5ade736dec398..831f801926bd6 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -64,7 +64,7 @@ sram_ctrl_main.ram flash_ctrl.mem ] - rv_core_ibex.cored: + cheriot.cored: [ rom_ctrl.rom rom_ctrl.regs @@ -90,6 +90,9 @@ kmac sram_ctrl_main.regs rv_core_ibex.cfg + sram_ctrl_meta.regs + cheriot.regs + cheriot.revbm ] rv_dm.sba: [ @@ -117,6 +120,9 @@ kmac sram_ctrl_main.regs rv_core_ibex.cfg + sram_ctrl_meta.regs + cheriot.regs + cheriot.revbm ] } nodes: @@ -135,7 +141,7 @@ rsp_fifo_pass: true } { - name: rv_core_ibex.cored + name: cheriot.cored type: host addr_space: hart clock: clk_main_i @@ -694,6 +700,72 @@ stub: false req_fifo_pass: true } + { + name: sram_ctrl_meta.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x411d0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: cheriot.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: cheriot + addr_range: + [ + { + base_addrs: + { + hart: 0x411b0000 + } + size_byte: 0x4 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: cheriot.revbm + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: cheriot + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + pipeline: true + } ] addr_spaces: [ @@ -718,7 +790,7 @@ index: -1 } { - name: tl_rv_core_ibex__cored + name: tl_cheriot__cored struct: tl package: tlul_pkg type: req_rsp @@ -728,7 +800,7 @@ default: "" end_idx: -1 top_type: one-to-one - top_signame: main_tl_rv_core_ibex__cored + top_signame: main_tl_cheriot__cored index: -1 } { @@ -1058,5 +1130,44 @@ top_signame: sram_ctrl_main_ram_tl index: -1 } + { + name: tl_sram_ctrl_meta__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: sram_ctrl_meta_regs_tl + index: -1 + } + { + name: tl_cheriot__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: cheriot_regs_tl_d + index: -1 + } + { + name: tl_cheriot__revbm + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: cheriot_revbm_tl_d + index: -1 + } ] } diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 06b9379039341..c69d821c52bd2 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson @@ -20,7 +20,7 @@ } { struct: "tl" type: "req_rsp" - name: "tl_rv_core_ibex__cored" + name: "tl_cheriot__cored" act: "rsp" package: "tlul_pkg" } @@ -175,5 +175,23 @@ act: "req" package: "tlul_pkg" } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_meta__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_cheriot__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_cheriot__revbm" + act: "req" + package: "tlul_pkg" + } ] } diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 84f165db01cbb..db57bf1582f79 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -27,7 +27,7 @@ initial force dut.rst_spi_host1_ni = rst_n; // Host TileLink interface connections `CONNECT_TL_HOST_IF(rv_core_ibex__corei, dut, clk_main_i, rst_n) -`CONNECT_TL_HOST_IF(rv_core_ibex__cored, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(cheriot__cored, dut, clk_main_i, rst_n) `CONNECT_TL_HOST_IF(rv_dm__sba, dut, clk_main_i, rst_n) // Device TileLink interface connections @@ -55,3 +55,6 @@ initial force dut.rst_spi_host1_ni = rst_n; `CONNECT_TL_DEVICE_IF(rv_core_ibex__cfg, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(sram_ctrl_main__regs, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(sram_ctrl_main__ram, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_meta__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(cheriot__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(cheriot__revbm, dut, clk_main_i, rst_n) diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index 528f79c929b33..61bac6d9e9247 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -109,6 +109,19 @@ -node tb.dut tl_sram_ctrl_main__regs_o.a_address[31:31] -node tb.dut tl_sram_ctrl_main__ram_o.a_address[27:17] -node tb.dut tl_sram_ctrl_main__ram_o.a_address[31:29] +-node tb.dut tl_sram_ctrl_meta__regs_o.a_address[15:6] +-node tb.dut tl_sram_ctrl_meta__regs_o.a_address[17:17] +-node tb.dut tl_sram_ctrl_meta__regs_o.a_address[23:21] +-node tb.dut tl_sram_ctrl_meta__regs_o.a_address[29:25] +-node tb.dut tl_sram_ctrl_meta__regs_o.a_address[31:31] +-node tb.dut tl_cheriot__regs_o.a_address[15:2] +-node tb.dut tl_cheriot__regs_o.a_address[18:18] +-node tb.dut tl_cheriot__regs_o.a_address[23:21] +-node tb.dut tl_cheriot__regs_o.a_address[29:25] +-node tb.dut tl_cheriot__regs_o.a_address[31:31] +-node tb.dut tl_cheriot__revbm_o.a_address[23:11] +-node tb.dut tl_cheriot__revbm_o.a_address[27:25] +-node tb.dut tl_cheriot__revbm_o.a_address[31:29] -node tb.dut tl_*.a_source[7:6] -node tb.dut tl_*.d_source[7:6] diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index a6c1a5357b391..eb0e74aeb6ee6 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -79,6 +79,15 @@ tl_device_t xbar_devices[$] = '{ }}, '{"sram_ctrl_main__ram", '{ '{32'h10000000, 32'h1001ffff} + }}, + '{"sram_ctrl_meta__regs", '{ + '{32'h411d0000, 32'h411d003f} + }}, + '{"cheriot__regs", '{ + '{32'h411b0000, 32'h411b0003} + }}, + '{"cheriot__revbm", '{ + '{32'h11000000, 32'h110007ff} }}}; // List of Xbar hosts @@ -89,7 +98,7 @@ tl_host_t xbar_hosts[$] = '{ "sram_ctrl_main__ram", "flash_ctrl__mem"}} , - '{"rv_core_ibex__cored", 1, '{ + '{"cheriot__cored", 1, '{ "rom_ctrl__rom", "rom_ctrl__regs", "rv_dm__mem", @@ -113,7 +122,10 @@ tl_host_t xbar_hosts[$] = '{ "keymgr", "kmac", "sram_ctrl_main__regs", - "rv_core_ibex__cfg"}} + "rv_core_ibex__cfg", + "sram_ctrl_meta__regs", + "cheriot__regs", + "cheriot__revbm"}} , '{"rv_dm__sba", 2, '{ "rom_ctrl__rom", @@ -139,5 +151,8 @@ tl_host_t xbar_hosts[$] = '{ "keymgr", "kmac", "sram_ctrl_main__regs", - "rv_core_ibex__cfg"}} + "rv_core_ibex__cfg", + "sram_ctrl_meta__regs", + "cheriot__regs", + "cheriot__revbm"}} }; diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index fe56a65c6db69..f3af5ba903623 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -12,11 +12,11 @@ module xbar_main_bind; .h2d (tl_rv_core_ibex__corei_i), .d2h (tl_rv_core_ibex__corei_o) ); - bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex__cored ( + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_cheriot__cored ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_rv_core_ibex__cored_i), - .d2h (tl_rv_core_ibex__cored_o) + .h2d (tl_cheriot__cored_i), + .d2h (tl_cheriot__cored_o) ); bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_dm__sba ( .clk_i (clk_main_i), @@ -170,5 +170,23 @@ module xbar_main_bind; .h2d (tl_sram_ctrl_main__ram_o), .d2h (tl_sram_ctrl_main__ram_i) ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_meta__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_meta__regs_o), + .d2h (tl_sram_ctrl_meta__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_cheriot__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_cheriot__regs_o), + .d2h (tl_cheriot__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_cheriot__revbm ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_cheriot__revbm_o), + .d2h (tl_cheriot__revbm_i) + ); `endif endmodule diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 22a1a4bcaf6ac..222a86ec8e7a7 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -33,6 +33,9 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX__CFG = 32'h 411f0000; localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__REGS = 32'h 411c0000; localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__RAM = 32'h 10000000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_META__REGS = 32'h 411d0000; + localparam logic [31:0] ADDR_SPACE_CHERIOT__REGS = 32'h 411b0000; + localparam logic [31:0] ADDR_SPACE_CHERIOT__REVBM = 32'h 11000000; localparam logic [31:0] ADDR_MASK_RV_DM__REGS = 32'h 0000000f; localparam logic [31:0] ADDR_MASK_RV_DM__MEM = 32'h 00000fff; @@ -61,9 +64,12 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 000000ff; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0001ffff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_META__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_CHERIOT__REGS = 32'h 00000003; + localparam logic [31:0] ADDR_MASK_CHERIOT__REVBM = 32'h 000007ff; localparam int N_HOST = 3; - localparam int N_DEVICE = 24; + localparam int N_DEVICE = 27; typedef enum int { TlRvDmRegs = 0, @@ -89,12 +95,15 @@ package tl_main_pkg; TlKeymgr = 20, TlRvCoreIbexCfg = 21, TlSramCtrlMainRegs = 22, - TlSramCtrlMainRam = 23 + TlSramCtrlMainRam = 23, + TlSramCtrlMetaRegs = 24, + TlCheriotRegs = 25, + TlCheriotRevbm = 26 } tl_device_e; typedef enum int { TlRvCoreIbexCorei = 0, - TlRvCoreIbexCored = 1, + TlCheriotCored = 1, TlRvDmSba = 2 } tl_host_e; diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index a5bee7720f922..edc6c4e0938c2 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -7,123 +7,135 @@ // // Interconnect // rv_core_ibex.corei -// -> s1n_27 -// -> sm1_28 +// -> s1n_30 +// -> sm1_31 // -> rom_ctrl.rom -// -> sm1_29 +// -> sm1_32 // -> rv_dm.mem -// -> sm1_30 +// -> sm1_33 // -> sram_ctrl_main.ram -// -> sm1_31 +// -> sm1_34 // -> flash_ctrl.mem -// rv_core_ibex.cored -// -> s1n_32 -// -> sm1_28 +// cheriot.cored +// -> s1n_35 +// -> sm1_31 // -> rom_ctrl.rom -// -> sm1_33 +// -> sm1_36 // -> rom_ctrl.regs -// -> sm1_29 +// -> sm1_32 // -> rv_dm.mem -// -> sm1_34 +// -> sm1_37 // -> rv_dm.regs -// -> sm1_30 +// -> sm1_33 // -> sram_ctrl_main.ram -// -> sm1_36 -// -> asf_35 +// -> sm1_39 +// -> asf_38 // -> peri -// -> sm1_38 -// -> asf_37 +// -> sm1_41 +// -> asf_40 // -> spi_host0 -// -> sm1_40 -// -> asf_39 +// -> sm1_43 +// -> asf_42 // -> spi_host1 -// -> sm1_42 -// -> asf_41 +// -> sm1_45 +// -> asf_44 // -> usbdev -// -> sm1_43 +// -> sm1_46 // -> flash_ctrl.core -// -> sm1_44 +// -> sm1_47 // -> flash_ctrl.prim -// -> sm1_31 +// -> sm1_34 // -> flash_ctrl.mem -// -> sm1_45 +// -> sm1_48 // -> aes -// -> sm1_46 +// -> sm1_49 // -> entropy_src -// -> sm1_47 +// -> sm1_50 // -> csrng -// -> sm1_48 +// -> sm1_51 // -> edn0 -// -> sm1_49 +// -> sm1_52 // -> edn1 -// -> sm1_50 +// -> sm1_53 // -> hmac -// -> sm1_51 +// -> sm1_54 // -> rv_plic -// -> sm1_52 +// -> sm1_55 // -> otbn -// -> sm1_53 +// -> sm1_56 // -> keymgr -// -> sm1_54 +// -> sm1_57 // -> kmac -// -> sm1_55 +// -> sm1_58 // -> sram_ctrl_main.regs -// -> sm1_56 +// -> sm1_59 // -> rv_core_ibex.cfg +// -> sm1_60 +// -> sram_ctrl_meta.regs +// -> sm1_61 +// -> cheriot.regs +// -> sm1_62 +// -> cheriot.revbm // rv_dm.sba -// -> s1n_57 -// -> sm1_28 +// -> s1n_63 +// -> sm1_31 // -> rom_ctrl.rom -// -> sm1_33 +// -> sm1_36 // -> rom_ctrl.regs -// -> sm1_29 +// -> sm1_32 // -> rv_dm.mem -// -> sm1_34 +// -> sm1_37 // -> rv_dm.regs -// -> sm1_30 +// -> sm1_33 // -> sram_ctrl_main.ram -// -> sm1_36 -// -> asf_35 +// -> sm1_39 +// -> asf_38 // -> peri -// -> sm1_38 -// -> asf_37 +// -> sm1_41 +// -> asf_40 // -> spi_host0 -// -> sm1_40 -// -> asf_39 +// -> sm1_43 +// -> asf_42 // -> spi_host1 -// -> sm1_42 -// -> asf_41 +// -> sm1_45 +// -> asf_44 // -> usbdev -// -> sm1_43 +// -> sm1_46 // -> flash_ctrl.core -// -> sm1_44 +// -> sm1_47 // -> flash_ctrl.prim -// -> sm1_31 +// -> sm1_34 // -> flash_ctrl.mem -// -> sm1_45 +// -> sm1_48 // -> aes -// -> sm1_46 +// -> sm1_49 // -> entropy_src -// -> sm1_47 +// -> sm1_50 // -> csrng -// -> sm1_48 +// -> sm1_51 // -> edn0 -// -> sm1_49 +// -> sm1_52 // -> edn1 -// -> sm1_50 +// -> sm1_53 // -> hmac -// -> sm1_51 +// -> sm1_54 // -> rv_plic -// -> sm1_52 +// -> sm1_55 // -> otbn -// -> sm1_53 +// -> sm1_56 // -> keymgr -// -> sm1_54 +// -> sm1_57 // -> kmac -// -> sm1_55 +// -> sm1_58 // -> sram_ctrl_main.regs -// -> sm1_56 +// -> sm1_59 // -> rv_core_ibex.cfg +// -> sm1_60 +// -> sram_ctrl_meta.regs +// -> sm1_61 +// -> cheriot.regs +// -> sm1_62 +// -> cheriot.revbm module xbar_main ( input clk_main_i, @@ -140,8 +152,8 @@ module xbar_main ( // Host interfaces input tlul_pkg::tl_h2d_t tl_rv_core_ibex__corei_i, output tlul_pkg::tl_d2h_t tl_rv_core_ibex__corei_o, - input tlul_pkg::tl_h2d_t tl_rv_core_ibex__cored_i, - output tlul_pkg::tl_d2h_t tl_rv_core_ibex__cored_o, + input tlul_pkg::tl_h2d_t tl_cheriot__cored_i, + output tlul_pkg::tl_d2h_t tl_cheriot__cored_o, input tlul_pkg::tl_h2d_t tl_rv_dm__sba_i, output tlul_pkg::tl_d2h_t tl_rv_dm__sba_o, @@ -194,6 +206,12 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__regs_i, output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__ram_o, input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__ram_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_meta__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_meta__regs_i, + output tlul_pkg::tl_h2d_t tl_cheriot__regs_o, + input tlul_pkg::tl_d2h_t tl_cheriot__regs_i, + output tlul_pkg::tl_h2d_t tl_cheriot__revbm_o, + input tlul_pkg::tl_d2h_t tl_cheriot__revbm_i, input prim_mubi_pkg::mubi4_t scanmode_i ); @@ -206,36 +224,15 @@ module xbar_main ( logic unused_scanmode; assign unused_scanmode = ^scanmode_i; - tl_h2d_t tl_s1n_27_us_h2d ; - tl_d2h_t tl_s1n_27_us_d2h ; + tl_h2d_t tl_s1n_30_us_h2d ; + tl_d2h_t tl_s1n_30_us_d2h ; - tl_h2d_t tl_s1n_27_ds_h2d [4]; - tl_d2h_t tl_s1n_27_ds_d2h [4]; + tl_h2d_t tl_s1n_30_ds_h2d [4]; + tl_d2h_t tl_s1n_30_ds_d2h [4]; // Create steering signal - logic [2:0] dev_sel_s1n_27; - - - tl_h2d_t tl_sm1_28_us_h2d [3]; - tl_d2h_t tl_sm1_28_us_d2h [3]; - - tl_h2d_t tl_sm1_28_ds_h2d ; - tl_d2h_t tl_sm1_28_ds_d2h ; - - - tl_h2d_t tl_sm1_29_us_h2d [3]; - tl_d2h_t tl_sm1_29_us_d2h [3]; - - tl_h2d_t tl_sm1_29_ds_h2d ; - tl_d2h_t tl_sm1_29_ds_d2h ; - - - tl_h2d_t tl_sm1_30_us_h2d [3]; - tl_d2h_t tl_sm1_30_us_d2h [3]; - - tl_h2d_t tl_sm1_30_ds_h2d ; - tl_d2h_t tl_sm1_30_ds_d2h ; + logic [2:0] dev_sel_s1n_30; tl_h2d_t tl_sm1_31_us_h2d [3]; @@ -244,34 +241,36 @@ module xbar_main ( tl_h2d_t tl_sm1_31_ds_h2d ; tl_d2h_t tl_sm1_31_ds_d2h ; - tl_h2d_t tl_s1n_32_us_h2d ; - tl_d2h_t tl_s1n_32_us_d2h ; - - tl_h2d_t tl_s1n_32_ds_h2d [24]; - tl_d2h_t tl_s1n_32_ds_d2h [24]; + tl_h2d_t tl_sm1_32_us_h2d [3]; + tl_d2h_t tl_sm1_32_us_d2h [3]; - // Create steering signal - logic [4:0] dev_sel_s1n_32; + tl_h2d_t tl_sm1_32_ds_h2d ; + tl_d2h_t tl_sm1_32_ds_d2h ; - tl_h2d_t tl_sm1_33_us_h2d [2]; - tl_d2h_t tl_sm1_33_us_d2h [2]; + tl_h2d_t tl_sm1_33_us_h2d [3]; + tl_d2h_t tl_sm1_33_us_d2h [3]; tl_h2d_t tl_sm1_33_ds_h2d ; tl_d2h_t tl_sm1_33_ds_d2h ; - tl_h2d_t tl_sm1_34_us_h2d [2]; - tl_d2h_t tl_sm1_34_us_d2h [2]; + tl_h2d_t tl_sm1_34_us_h2d [3]; + tl_d2h_t tl_sm1_34_us_d2h [3]; tl_h2d_t tl_sm1_34_ds_h2d ; tl_d2h_t tl_sm1_34_ds_d2h ; - tl_h2d_t tl_asf_35_us_h2d ; - tl_d2h_t tl_asf_35_us_d2h ; - tl_h2d_t tl_asf_35_ds_h2d ; - tl_d2h_t tl_asf_35_ds_d2h ; + tl_h2d_t tl_s1n_35_us_h2d ; + tl_d2h_t tl_s1n_35_us_d2h ; + + + tl_h2d_t tl_s1n_35_ds_h2d [27]; + tl_d2h_t tl_s1n_35_ds_d2h [27]; + + // Create steering signal + logic [4:0] dev_sel_s1n_35; tl_h2d_t tl_sm1_36_us_h2d [2]; @@ -280,41 +279,41 @@ module xbar_main ( tl_h2d_t tl_sm1_36_ds_h2d ; tl_d2h_t tl_sm1_36_ds_d2h ; - tl_h2d_t tl_asf_37_us_h2d ; - tl_d2h_t tl_asf_37_us_d2h ; - tl_h2d_t tl_asf_37_ds_h2d ; - tl_d2h_t tl_asf_37_ds_d2h ; + tl_h2d_t tl_sm1_37_us_h2d [2]; + tl_d2h_t tl_sm1_37_us_d2h [2]; - tl_h2d_t tl_sm1_38_us_h2d [2]; - tl_d2h_t tl_sm1_38_us_d2h [2]; + tl_h2d_t tl_sm1_37_ds_h2d ; + tl_d2h_t tl_sm1_37_ds_d2h ; - tl_h2d_t tl_sm1_38_ds_h2d ; - tl_d2h_t tl_sm1_38_ds_d2h ; + tl_h2d_t tl_asf_38_us_h2d ; + tl_d2h_t tl_asf_38_us_d2h ; + tl_h2d_t tl_asf_38_ds_h2d ; + tl_d2h_t tl_asf_38_ds_d2h ; - tl_h2d_t tl_asf_39_us_h2d ; - tl_d2h_t tl_asf_39_us_d2h ; - tl_h2d_t tl_asf_39_ds_h2d ; - tl_d2h_t tl_asf_39_ds_d2h ; + tl_h2d_t tl_sm1_39_us_h2d [2]; + tl_d2h_t tl_sm1_39_us_d2h [2]; - tl_h2d_t tl_sm1_40_us_h2d [2]; - tl_d2h_t tl_sm1_40_us_d2h [2]; + tl_h2d_t tl_sm1_39_ds_h2d ; + tl_d2h_t tl_sm1_39_ds_d2h ; - tl_h2d_t tl_sm1_40_ds_h2d ; - tl_d2h_t tl_sm1_40_ds_d2h ; + tl_h2d_t tl_asf_40_us_h2d ; + tl_d2h_t tl_asf_40_us_d2h ; + tl_h2d_t tl_asf_40_ds_h2d ; + tl_d2h_t tl_asf_40_ds_d2h ; - tl_h2d_t tl_asf_41_us_h2d ; - tl_d2h_t tl_asf_41_us_d2h ; - tl_h2d_t tl_asf_41_ds_h2d ; - tl_d2h_t tl_asf_41_ds_d2h ; + tl_h2d_t tl_sm1_41_us_h2d [2]; + tl_d2h_t tl_sm1_41_us_d2h [2]; - tl_h2d_t tl_sm1_42_us_h2d [2]; - tl_d2h_t tl_sm1_42_us_d2h [2]; + tl_h2d_t tl_sm1_41_ds_h2d ; + tl_d2h_t tl_sm1_41_ds_d2h ; - tl_h2d_t tl_sm1_42_ds_h2d ; - tl_d2h_t tl_sm1_42_ds_d2h ; + tl_h2d_t tl_asf_42_us_h2d ; + tl_d2h_t tl_asf_42_us_d2h ; + tl_h2d_t tl_asf_42_ds_h2d ; + tl_d2h_t tl_asf_42_ds_d2h ; tl_h2d_t tl_sm1_43_us_h2d [2]; @@ -323,12 +322,10 @@ module xbar_main ( tl_h2d_t tl_sm1_43_ds_h2d ; tl_d2h_t tl_sm1_43_ds_d2h ; - - tl_h2d_t tl_sm1_44_us_h2d [2]; - tl_d2h_t tl_sm1_44_us_d2h [2]; - - tl_h2d_t tl_sm1_44_ds_h2d ; - tl_d2h_t tl_sm1_44_ds_d2h ; + tl_h2d_t tl_asf_44_us_h2d ; + tl_d2h_t tl_asf_44_us_d2h ; + tl_h2d_t tl_asf_44_ds_h2d ; + tl_d2h_t tl_asf_44_ds_d2h ; tl_h2d_t tl_sm1_45_us_h2d [2]; @@ -414,491 +411,584 @@ module xbar_main ( tl_h2d_t tl_sm1_56_ds_h2d ; tl_d2h_t tl_sm1_56_ds_d2h ; - tl_h2d_t tl_s1n_57_us_h2d ; - tl_d2h_t tl_s1n_57_us_d2h ; + tl_h2d_t tl_sm1_57_us_h2d [2]; + tl_d2h_t tl_sm1_57_us_d2h [2]; + + tl_h2d_t tl_sm1_57_ds_h2d ; + tl_d2h_t tl_sm1_57_ds_d2h ; + + + tl_h2d_t tl_sm1_58_us_h2d [2]; + tl_d2h_t tl_sm1_58_us_d2h [2]; + + tl_h2d_t tl_sm1_58_ds_h2d ; + tl_d2h_t tl_sm1_58_ds_d2h ; + + + tl_h2d_t tl_sm1_59_us_h2d [2]; + tl_d2h_t tl_sm1_59_us_d2h [2]; + + tl_h2d_t tl_sm1_59_ds_h2d ; + tl_d2h_t tl_sm1_59_ds_d2h ; - tl_h2d_t tl_s1n_57_ds_h2d [24]; - tl_d2h_t tl_s1n_57_ds_d2h [24]; + + tl_h2d_t tl_sm1_60_us_h2d [2]; + tl_d2h_t tl_sm1_60_us_d2h [2]; + + tl_h2d_t tl_sm1_60_ds_h2d ; + tl_d2h_t tl_sm1_60_ds_d2h ; + + + tl_h2d_t tl_sm1_61_us_h2d [2]; + tl_d2h_t tl_sm1_61_us_d2h [2]; + + tl_h2d_t tl_sm1_61_ds_h2d ; + tl_d2h_t tl_sm1_61_ds_d2h ; + + + tl_h2d_t tl_sm1_62_us_h2d [2]; + tl_d2h_t tl_sm1_62_us_d2h [2]; + + tl_h2d_t tl_sm1_62_ds_h2d ; + tl_d2h_t tl_sm1_62_ds_d2h ; + + tl_h2d_t tl_s1n_63_us_h2d ; + tl_d2h_t tl_s1n_63_us_d2h ; + + + tl_h2d_t tl_s1n_63_ds_h2d [27]; + tl_d2h_t tl_s1n_63_ds_d2h [27]; // Create steering signal - logic [4:0] dev_sel_s1n_57; + logic [4:0] dev_sel_s1n_63; + + + + assign tl_sm1_31_us_h2d[0] = tl_s1n_30_ds_h2d[0]; + assign tl_s1n_30_ds_d2h[0] = tl_sm1_31_us_d2h[0]; + + assign tl_sm1_32_us_h2d[0] = tl_s1n_30_ds_h2d[1]; + assign tl_s1n_30_ds_d2h[1] = tl_sm1_32_us_d2h[0]; + + assign tl_sm1_33_us_h2d[0] = tl_s1n_30_ds_h2d[2]; + assign tl_s1n_30_ds_d2h[2] = tl_sm1_33_us_d2h[0]; + assign tl_sm1_34_us_h2d[0] = tl_s1n_30_ds_h2d[3]; + assign tl_s1n_30_ds_d2h[3] = tl_sm1_34_us_d2h[0]; + assign tl_sm1_31_us_h2d[1] = tl_s1n_35_ds_h2d[0]; + assign tl_s1n_35_ds_d2h[0] = tl_sm1_31_us_d2h[1]; - assign tl_sm1_28_us_h2d[0] = tl_s1n_27_ds_h2d[0]; - assign tl_s1n_27_ds_d2h[0] = tl_sm1_28_us_d2h[0]; + assign tl_sm1_36_us_h2d[0] = tl_s1n_35_ds_h2d[1]; + assign tl_s1n_35_ds_d2h[1] = tl_sm1_36_us_d2h[0]; - assign tl_sm1_29_us_h2d[0] = tl_s1n_27_ds_h2d[1]; - assign tl_s1n_27_ds_d2h[1] = tl_sm1_29_us_d2h[0]; + assign tl_sm1_32_us_h2d[1] = tl_s1n_35_ds_h2d[2]; + assign tl_s1n_35_ds_d2h[2] = tl_sm1_32_us_d2h[1]; - assign tl_sm1_30_us_h2d[0] = tl_s1n_27_ds_h2d[2]; - assign tl_s1n_27_ds_d2h[2] = tl_sm1_30_us_d2h[0]; + assign tl_sm1_37_us_h2d[0] = tl_s1n_35_ds_h2d[3]; + assign tl_s1n_35_ds_d2h[3] = tl_sm1_37_us_d2h[0]; - assign tl_sm1_31_us_h2d[0] = tl_s1n_27_ds_h2d[3]; - assign tl_s1n_27_ds_d2h[3] = tl_sm1_31_us_d2h[0]; + assign tl_sm1_33_us_h2d[1] = tl_s1n_35_ds_h2d[4]; + assign tl_s1n_35_ds_d2h[4] = tl_sm1_33_us_d2h[1]; - assign tl_sm1_28_us_h2d[1] = tl_s1n_32_ds_h2d[0]; - assign tl_s1n_32_ds_d2h[0] = tl_sm1_28_us_d2h[1]; + assign tl_sm1_39_us_h2d[0] = tl_s1n_35_ds_h2d[5]; + assign tl_s1n_35_ds_d2h[5] = tl_sm1_39_us_d2h[0]; - assign tl_sm1_33_us_h2d[0] = tl_s1n_32_ds_h2d[1]; - assign tl_s1n_32_ds_d2h[1] = tl_sm1_33_us_d2h[0]; + assign tl_sm1_41_us_h2d[0] = tl_s1n_35_ds_h2d[6]; + assign tl_s1n_35_ds_d2h[6] = tl_sm1_41_us_d2h[0]; - assign tl_sm1_29_us_h2d[1] = tl_s1n_32_ds_h2d[2]; - assign tl_s1n_32_ds_d2h[2] = tl_sm1_29_us_d2h[1]; + assign tl_sm1_43_us_h2d[0] = tl_s1n_35_ds_h2d[7]; + assign tl_s1n_35_ds_d2h[7] = tl_sm1_43_us_d2h[0]; - assign tl_sm1_34_us_h2d[0] = tl_s1n_32_ds_h2d[3]; - assign tl_s1n_32_ds_d2h[3] = tl_sm1_34_us_d2h[0]; + assign tl_sm1_45_us_h2d[0] = tl_s1n_35_ds_h2d[8]; + assign tl_s1n_35_ds_d2h[8] = tl_sm1_45_us_d2h[0]; - assign tl_sm1_30_us_h2d[1] = tl_s1n_32_ds_h2d[4]; - assign tl_s1n_32_ds_d2h[4] = tl_sm1_30_us_d2h[1]; + assign tl_sm1_46_us_h2d[0] = tl_s1n_35_ds_h2d[9]; + assign tl_s1n_35_ds_d2h[9] = tl_sm1_46_us_d2h[0]; - assign tl_sm1_36_us_h2d[0] = tl_s1n_32_ds_h2d[5]; - assign tl_s1n_32_ds_d2h[5] = tl_sm1_36_us_d2h[0]; + assign tl_sm1_47_us_h2d[0] = tl_s1n_35_ds_h2d[10]; + assign tl_s1n_35_ds_d2h[10] = tl_sm1_47_us_d2h[0]; - assign tl_sm1_38_us_h2d[0] = tl_s1n_32_ds_h2d[6]; - assign tl_s1n_32_ds_d2h[6] = tl_sm1_38_us_d2h[0]; + assign tl_sm1_34_us_h2d[1] = tl_s1n_35_ds_h2d[11]; + assign tl_s1n_35_ds_d2h[11] = tl_sm1_34_us_d2h[1]; - assign tl_sm1_40_us_h2d[0] = tl_s1n_32_ds_h2d[7]; - assign tl_s1n_32_ds_d2h[7] = tl_sm1_40_us_d2h[0]; + assign tl_sm1_48_us_h2d[0] = tl_s1n_35_ds_h2d[12]; + assign tl_s1n_35_ds_d2h[12] = tl_sm1_48_us_d2h[0]; - assign tl_sm1_42_us_h2d[0] = tl_s1n_32_ds_h2d[8]; - assign tl_s1n_32_ds_d2h[8] = tl_sm1_42_us_d2h[0]; + assign tl_sm1_49_us_h2d[0] = tl_s1n_35_ds_h2d[13]; + assign tl_s1n_35_ds_d2h[13] = tl_sm1_49_us_d2h[0]; - assign tl_sm1_43_us_h2d[0] = tl_s1n_32_ds_h2d[9]; - assign tl_s1n_32_ds_d2h[9] = tl_sm1_43_us_d2h[0]; + assign tl_sm1_50_us_h2d[0] = tl_s1n_35_ds_h2d[14]; + assign tl_s1n_35_ds_d2h[14] = tl_sm1_50_us_d2h[0]; - assign tl_sm1_44_us_h2d[0] = tl_s1n_32_ds_h2d[10]; - assign tl_s1n_32_ds_d2h[10] = tl_sm1_44_us_d2h[0]; + assign tl_sm1_51_us_h2d[0] = tl_s1n_35_ds_h2d[15]; + assign tl_s1n_35_ds_d2h[15] = tl_sm1_51_us_d2h[0]; - assign tl_sm1_31_us_h2d[1] = tl_s1n_32_ds_h2d[11]; - assign tl_s1n_32_ds_d2h[11] = tl_sm1_31_us_d2h[1]; + assign tl_sm1_52_us_h2d[0] = tl_s1n_35_ds_h2d[16]; + assign tl_s1n_35_ds_d2h[16] = tl_sm1_52_us_d2h[0]; - assign tl_sm1_45_us_h2d[0] = tl_s1n_32_ds_h2d[12]; - assign tl_s1n_32_ds_d2h[12] = tl_sm1_45_us_d2h[0]; + assign tl_sm1_53_us_h2d[0] = tl_s1n_35_ds_h2d[17]; + assign tl_s1n_35_ds_d2h[17] = tl_sm1_53_us_d2h[0]; - assign tl_sm1_46_us_h2d[0] = tl_s1n_32_ds_h2d[13]; - assign tl_s1n_32_ds_d2h[13] = tl_sm1_46_us_d2h[0]; + assign tl_sm1_54_us_h2d[0] = tl_s1n_35_ds_h2d[18]; + assign tl_s1n_35_ds_d2h[18] = tl_sm1_54_us_d2h[0]; - assign tl_sm1_47_us_h2d[0] = tl_s1n_32_ds_h2d[14]; - assign tl_s1n_32_ds_d2h[14] = tl_sm1_47_us_d2h[0]; + assign tl_sm1_55_us_h2d[0] = tl_s1n_35_ds_h2d[19]; + assign tl_s1n_35_ds_d2h[19] = tl_sm1_55_us_d2h[0]; - assign tl_sm1_48_us_h2d[0] = tl_s1n_32_ds_h2d[15]; - assign tl_s1n_32_ds_d2h[15] = tl_sm1_48_us_d2h[0]; + assign tl_sm1_56_us_h2d[0] = tl_s1n_35_ds_h2d[20]; + assign tl_s1n_35_ds_d2h[20] = tl_sm1_56_us_d2h[0]; - assign tl_sm1_49_us_h2d[0] = tl_s1n_32_ds_h2d[16]; - assign tl_s1n_32_ds_d2h[16] = tl_sm1_49_us_d2h[0]; + assign tl_sm1_57_us_h2d[0] = tl_s1n_35_ds_h2d[21]; + assign tl_s1n_35_ds_d2h[21] = tl_sm1_57_us_d2h[0]; - assign tl_sm1_50_us_h2d[0] = tl_s1n_32_ds_h2d[17]; - assign tl_s1n_32_ds_d2h[17] = tl_sm1_50_us_d2h[0]; + assign tl_sm1_58_us_h2d[0] = tl_s1n_35_ds_h2d[22]; + assign tl_s1n_35_ds_d2h[22] = tl_sm1_58_us_d2h[0]; - assign tl_sm1_51_us_h2d[0] = tl_s1n_32_ds_h2d[18]; - assign tl_s1n_32_ds_d2h[18] = tl_sm1_51_us_d2h[0]; + assign tl_sm1_59_us_h2d[0] = tl_s1n_35_ds_h2d[23]; + assign tl_s1n_35_ds_d2h[23] = tl_sm1_59_us_d2h[0]; - assign tl_sm1_52_us_h2d[0] = tl_s1n_32_ds_h2d[19]; - assign tl_s1n_32_ds_d2h[19] = tl_sm1_52_us_d2h[0]; + assign tl_sm1_60_us_h2d[0] = tl_s1n_35_ds_h2d[24]; + assign tl_s1n_35_ds_d2h[24] = tl_sm1_60_us_d2h[0]; - assign tl_sm1_53_us_h2d[0] = tl_s1n_32_ds_h2d[20]; - assign tl_s1n_32_ds_d2h[20] = tl_sm1_53_us_d2h[0]; + assign tl_sm1_61_us_h2d[0] = tl_s1n_35_ds_h2d[25]; + assign tl_s1n_35_ds_d2h[25] = tl_sm1_61_us_d2h[0]; - assign tl_sm1_54_us_h2d[0] = tl_s1n_32_ds_h2d[21]; - assign tl_s1n_32_ds_d2h[21] = tl_sm1_54_us_d2h[0]; + assign tl_sm1_62_us_h2d[0] = tl_s1n_35_ds_h2d[26]; + assign tl_s1n_35_ds_d2h[26] = tl_sm1_62_us_d2h[0]; - assign tl_sm1_55_us_h2d[0] = tl_s1n_32_ds_h2d[22]; - assign tl_s1n_32_ds_d2h[22] = tl_sm1_55_us_d2h[0]; + assign tl_sm1_31_us_h2d[2] = tl_s1n_63_ds_h2d[0]; + assign tl_s1n_63_ds_d2h[0] = tl_sm1_31_us_d2h[2]; - assign tl_sm1_56_us_h2d[0] = tl_s1n_32_ds_h2d[23]; - assign tl_s1n_32_ds_d2h[23] = tl_sm1_56_us_d2h[0]; + assign tl_sm1_36_us_h2d[1] = tl_s1n_63_ds_h2d[1]; + assign tl_s1n_63_ds_d2h[1] = tl_sm1_36_us_d2h[1]; - assign tl_sm1_28_us_h2d[2] = tl_s1n_57_ds_h2d[0]; - assign tl_s1n_57_ds_d2h[0] = tl_sm1_28_us_d2h[2]; + assign tl_sm1_32_us_h2d[2] = tl_s1n_63_ds_h2d[2]; + assign tl_s1n_63_ds_d2h[2] = tl_sm1_32_us_d2h[2]; - assign tl_sm1_33_us_h2d[1] = tl_s1n_57_ds_h2d[1]; - assign tl_s1n_57_ds_d2h[1] = tl_sm1_33_us_d2h[1]; + assign tl_sm1_37_us_h2d[1] = tl_s1n_63_ds_h2d[3]; + assign tl_s1n_63_ds_d2h[3] = tl_sm1_37_us_d2h[1]; - assign tl_sm1_29_us_h2d[2] = tl_s1n_57_ds_h2d[2]; - assign tl_s1n_57_ds_d2h[2] = tl_sm1_29_us_d2h[2]; + assign tl_sm1_33_us_h2d[2] = tl_s1n_63_ds_h2d[4]; + assign tl_s1n_63_ds_d2h[4] = tl_sm1_33_us_d2h[2]; - assign tl_sm1_34_us_h2d[1] = tl_s1n_57_ds_h2d[3]; - assign tl_s1n_57_ds_d2h[3] = tl_sm1_34_us_d2h[1]; + assign tl_sm1_39_us_h2d[1] = tl_s1n_63_ds_h2d[5]; + assign tl_s1n_63_ds_d2h[5] = tl_sm1_39_us_d2h[1]; - assign tl_sm1_30_us_h2d[2] = tl_s1n_57_ds_h2d[4]; - assign tl_s1n_57_ds_d2h[4] = tl_sm1_30_us_d2h[2]; + assign tl_sm1_41_us_h2d[1] = tl_s1n_63_ds_h2d[6]; + assign tl_s1n_63_ds_d2h[6] = tl_sm1_41_us_d2h[1]; - assign tl_sm1_36_us_h2d[1] = tl_s1n_57_ds_h2d[5]; - assign tl_s1n_57_ds_d2h[5] = tl_sm1_36_us_d2h[1]; + assign tl_sm1_43_us_h2d[1] = tl_s1n_63_ds_h2d[7]; + assign tl_s1n_63_ds_d2h[7] = tl_sm1_43_us_d2h[1]; - assign tl_sm1_38_us_h2d[1] = tl_s1n_57_ds_h2d[6]; - assign tl_s1n_57_ds_d2h[6] = tl_sm1_38_us_d2h[1]; + assign tl_sm1_45_us_h2d[1] = tl_s1n_63_ds_h2d[8]; + assign tl_s1n_63_ds_d2h[8] = tl_sm1_45_us_d2h[1]; - assign tl_sm1_40_us_h2d[1] = tl_s1n_57_ds_h2d[7]; - assign tl_s1n_57_ds_d2h[7] = tl_sm1_40_us_d2h[1]; + assign tl_sm1_46_us_h2d[1] = tl_s1n_63_ds_h2d[9]; + assign tl_s1n_63_ds_d2h[9] = tl_sm1_46_us_d2h[1]; - assign tl_sm1_42_us_h2d[1] = tl_s1n_57_ds_h2d[8]; - assign tl_s1n_57_ds_d2h[8] = tl_sm1_42_us_d2h[1]; + assign tl_sm1_47_us_h2d[1] = tl_s1n_63_ds_h2d[10]; + assign tl_s1n_63_ds_d2h[10] = tl_sm1_47_us_d2h[1]; - assign tl_sm1_43_us_h2d[1] = tl_s1n_57_ds_h2d[9]; - assign tl_s1n_57_ds_d2h[9] = tl_sm1_43_us_d2h[1]; + assign tl_sm1_34_us_h2d[2] = tl_s1n_63_ds_h2d[11]; + assign tl_s1n_63_ds_d2h[11] = tl_sm1_34_us_d2h[2]; - assign tl_sm1_44_us_h2d[1] = tl_s1n_57_ds_h2d[10]; - assign tl_s1n_57_ds_d2h[10] = tl_sm1_44_us_d2h[1]; + assign tl_sm1_48_us_h2d[1] = tl_s1n_63_ds_h2d[12]; + assign tl_s1n_63_ds_d2h[12] = tl_sm1_48_us_d2h[1]; - assign tl_sm1_31_us_h2d[2] = tl_s1n_57_ds_h2d[11]; - assign tl_s1n_57_ds_d2h[11] = tl_sm1_31_us_d2h[2]; + assign tl_sm1_49_us_h2d[1] = tl_s1n_63_ds_h2d[13]; + assign tl_s1n_63_ds_d2h[13] = tl_sm1_49_us_d2h[1]; - assign tl_sm1_45_us_h2d[1] = tl_s1n_57_ds_h2d[12]; - assign tl_s1n_57_ds_d2h[12] = tl_sm1_45_us_d2h[1]; + assign tl_sm1_50_us_h2d[1] = tl_s1n_63_ds_h2d[14]; + assign tl_s1n_63_ds_d2h[14] = tl_sm1_50_us_d2h[1]; - assign tl_sm1_46_us_h2d[1] = tl_s1n_57_ds_h2d[13]; - assign tl_s1n_57_ds_d2h[13] = tl_sm1_46_us_d2h[1]; + assign tl_sm1_51_us_h2d[1] = tl_s1n_63_ds_h2d[15]; + assign tl_s1n_63_ds_d2h[15] = tl_sm1_51_us_d2h[1]; - assign tl_sm1_47_us_h2d[1] = tl_s1n_57_ds_h2d[14]; - assign tl_s1n_57_ds_d2h[14] = tl_sm1_47_us_d2h[1]; + assign tl_sm1_52_us_h2d[1] = tl_s1n_63_ds_h2d[16]; + assign tl_s1n_63_ds_d2h[16] = tl_sm1_52_us_d2h[1]; - assign tl_sm1_48_us_h2d[1] = tl_s1n_57_ds_h2d[15]; - assign tl_s1n_57_ds_d2h[15] = tl_sm1_48_us_d2h[1]; + assign tl_sm1_53_us_h2d[1] = tl_s1n_63_ds_h2d[17]; + assign tl_s1n_63_ds_d2h[17] = tl_sm1_53_us_d2h[1]; - assign tl_sm1_49_us_h2d[1] = tl_s1n_57_ds_h2d[16]; - assign tl_s1n_57_ds_d2h[16] = tl_sm1_49_us_d2h[1]; + assign tl_sm1_54_us_h2d[1] = tl_s1n_63_ds_h2d[18]; + assign tl_s1n_63_ds_d2h[18] = tl_sm1_54_us_d2h[1]; - assign tl_sm1_50_us_h2d[1] = tl_s1n_57_ds_h2d[17]; - assign tl_s1n_57_ds_d2h[17] = tl_sm1_50_us_d2h[1]; + assign tl_sm1_55_us_h2d[1] = tl_s1n_63_ds_h2d[19]; + assign tl_s1n_63_ds_d2h[19] = tl_sm1_55_us_d2h[1]; - assign tl_sm1_51_us_h2d[1] = tl_s1n_57_ds_h2d[18]; - assign tl_s1n_57_ds_d2h[18] = tl_sm1_51_us_d2h[1]; + assign tl_sm1_56_us_h2d[1] = tl_s1n_63_ds_h2d[20]; + assign tl_s1n_63_ds_d2h[20] = tl_sm1_56_us_d2h[1]; - assign tl_sm1_52_us_h2d[1] = tl_s1n_57_ds_h2d[19]; - assign tl_s1n_57_ds_d2h[19] = tl_sm1_52_us_d2h[1]; + assign tl_sm1_57_us_h2d[1] = tl_s1n_63_ds_h2d[21]; + assign tl_s1n_63_ds_d2h[21] = tl_sm1_57_us_d2h[1]; - assign tl_sm1_53_us_h2d[1] = tl_s1n_57_ds_h2d[20]; - assign tl_s1n_57_ds_d2h[20] = tl_sm1_53_us_d2h[1]; + assign tl_sm1_58_us_h2d[1] = tl_s1n_63_ds_h2d[22]; + assign tl_s1n_63_ds_d2h[22] = tl_sm1_58_us_d2h[1]; - assign tl_sm1_54_us_h2d[1] = tl_s1n_57_ds_h2d[21]; - assign tl_s1n_57_ds_d2h[21] = tl_sm1_54_us_d2h[1]; + assign tl_sm1_59_us_h2d[1] = tl_s1n_63_ds_h2d[23]; + assign tl_s1n_63_ds_d2h[23] = tl_sm1_59_us_d2h[1]; - assign tl_sm1_55_us_h2d[1] = tl_s1n_57_ds_h2d[22]; - assign tl_s1n_57_ds_d2h[22] = tl_sm1_55_us_d2h[1]; + assign tl_sm1_60_us_h2d[1] = tl_s1n_63_ds_h2d[24]; + assign tl_s1n_63_ds_d2h[24] = tl_sm1_60_us_d2h[1]; - assign tl_sm1_56_us_h2d[1] = tl_s1n_57_ds_h2d[23]; - assign tl_s1n_57_ds_d2h[23] = tl_sm1_56_us_d2h[1]; + assign tl_sm1_61_us_h2d[1] = tl_s1n_63_ds_h2d[25]; + assign tl_s1n_63_ds_d2h[25] = tl_sm1_61_us_d2h[1]; - assign tl_s1n_27_us_h2d = tl_rv_core_ibex__corei_i; - assign tl_rv_core_ibex__corei_o = tl_s1n_27_us_d2h; + assign tl_sm1_62_us_h2d[1] = tl_s1n_63_ds_h2d[26]; + assign tl_s1n_63_ds_d2h[26] = tl_sm1_62_us_d2h[1]; - assign tl_rom_ctrl__rom_o = tl_sm1_28_ds_h2d; - assign tl_sm1_28_ds_d2h = tl_rom_ctrl__rom_i; + assign tl_s1n_30_us_h2d = tl_rv_core_ibex__corei_i; + assign tl_rv_core_ibex__corei_o = tl_s1n_30_us_d2h; - assign tl_rv_dm__mem_o = tl_sm1_29_ds_h2d; - assign tl_sm1_29_ds_d2h = tl_rv_dm__mem_i; + assign tl_rom_ctrl__rom_o = tl_sm1_31_ds_h2d; + assign tl_sm1_31_ds_d2h = tl_rom_ctrl__rom_i; - assign tl_sram_ctrl_main__ram_o = tl_sm1_30_ds_h2d; - assign tl_sm1_30_ds_d2h = tl_sram_ctrl_main__ram_i; + assign tl_rv_dm__mem_o = tl_sm1_32_ds_h2d; + assign tl_sm1_32_ds_d2h = tl_rv_dm__mem_i; - assign tl_flash_ctrl__mem_o = tl_sm1_31_ds_h2d; - assign tl_sm1_31_ds_d2h = tl_flash_ctrl__mem_i; + assign tl_sram_ctrl_main__ram_o = tl_sm1_33_ds_h2d; + assign tl_sm1_33_ds_d2h = tl_sram_ctrl_main__ram_i; - assign tl_s1n_32_us_h2d = tl_rv_core_ibex__cored_i; - assign tl_rv_core_ibex__cored_o = tl_s1n_32_us_d2h; + assign tl_flash_ctrl__mem_o = tl_sm1_34_ds_h2d; + assign tl_sm1_34_ds_d2h = tl_flash_ctrl__mem_i; - assign tl_rom_ctrl__regs_o = tl_sm1_33_ds_h2d; - assign tl_sm1_33_ds_d2h = tl_rom_ctrl__regs_i; + assign tl_s1n_35_us_h2d = tl_cheriot__cored_i; + assign tl_cheriot__cored_o = tl_s1n_35_us_d2h; - assign tl_rv_dm__regs_o = tl_sm1_34_ds_h2d; - assign tl_sm1_34_ds_d2h = tl_rv_dm__regs_i; + assign tl_rom_ctrl__regs_o = tl_sm1_36_ds_h2d; + assign tl_sm1_36_ds_d2h = tl_rom_ctrl__regs_i; - assign tl_peri_o = tl_asf_35_ds_h2d; - assign tl_asf_35_ds_d2h = tl_peri_i; + assign tl_rv_dm__regs_o = tl_sm1_37_ds_h2d; + assign tl_sm1_37_ds_d2h = tl_rv_dm__regs_i; - assign tl_asf_35_us_h2d = tl_sm1_36_ds_h2d; - assign tl_sm1_36_ds_d2h = tl_asf_35_us_d2h; + assign tl_peri_o = tl_asf_38_ds_h2d; + assign tl_asf_38_ds_d2h = tl_peri_i; - assign tl_spi_host0_o = tl_asf_37_ds_h2d; - assign tl_asf_37_ds_d2h = tl_spi_host0_i; + assign tl_asf_38_us_h2d = tl_sm1_39_ds_h2d; + assign tl_sm1_39_ds_d2h = tl_asf_38_us_d2h; - assign tl_asf_37_us_h2d = tl_sm1_38_ds_h2d; - assign tl_sm1_38_ds_d2h = tl_asf_37_us_d2h; + assign tl_spi_host0_o = tl_asf_40_ds_h2d; + assign tl_asf_40_ds_d2h = tl_spi_host0_i; - assign tl_spi_host1_o = tl_asf_39_ds_h2d; - assign tl_asf_39_ds_d2h = tl_spi_host1_i; + assign tl_asf_40_us_h2d = tl_sm1_41_ds_h2d; + assign tl_sm1_41_ds_d2h = tl_asf_40_us_d2h; - assign tl_asf_39_us_h2d = tl_sm1_40_ds_h2d; - assign tl_sm1_40_ds_d2h = tl_asf_39_us_d2h; + assign tl_spi_host1_o = tl_asf_42_ds_h2d; + assign tl_asf_42_ds_d2h = tl_spi_host1_i; - assign tl_usbdev_o = tl_asf_41_ds_h2d; - assign tl_asf_41_ds_d2h = tl_usbdev_i; + assign tl_asf_42_us_h2d = tl_sm1_43_ds_h2d; + assign tl_sm1_43_ds_d2h = tl_asf_42_us_d2h; - assign tl_asf_41_us_h2d = tl_sm1_42_ds_h2d; - assign tl_sm1_42_ds_d2h = tl_asf_41_us_d2h; + assign tl_usbdev_o = tl_asf_44_ds_h2d; + assign tl_asf_44_ds_d2h = tl_usbdev_i; - assign tl_flash_ctrl__core_o = tl_sm1_43_ds_h2d; - assign tl_sm1_43_ds_d2h = tl_flash_ctrl__core_i; + assign tl_asf_44_us_h2d = tl_sm1_45_ds_h2d; + assign tl_sm1_45_ds_d2h = tl_asf_44_us_d2h; - assign tl_flash_ctrl__prim_o = tl_sm1_44_ds_h2d; - assign tl_sm1_44_ds_d2h = tl_flash_ctrl__prim_i; + assign tl_flash_ctrl__core_o = tl_sm1_46_ds_h2d; + assign tl_sm1_46_ds_d2h = tl_flash_ctrl__core_i; - assign tl_aes_o = tl_sm1_45_ds_h2d; - assign tl_sm1_45_ds_d2h = tl_aes_i; + assign tl_flash_ctrl__prim_o = tl_sm1_47_ds_h2d; + assign tl_sm1_47_ds_d2h = tl_flash_ctrl__prim_i; - assign tl_entropy_src_o = tl_sm1_46_ds_h2d; - assign tl_sm1_46_ds_d2h = tl_entropy_src_i; + assign tl_aes_o = tl_sm1_48_ds_h2d; + assign tl_sm1_48_ds_d2h = tl_aes_i; - assign tl_csrng_o = tl_sm1_47_ds_h2d; - assign tl_sm1_47_ds_d2h = tl_csrng_i; + assign tl_entropy_src_o = tl_sm1_49_ds_h2d; + assign tl_sm1_49_ds_d2h = tl_entropy_src_i; - assign tl_edn0_o = tl_sm1_48_ds_h2d; - assign tl_sm1_48_ds_d2h = tl_edn0_i; + assign tl_csrng_o = tl_sm1_50_ds_h2d; + assign tl_sm1_50_ds_d2h = tl_csrng_i; - assign tl_edn1_o = tl_sm1_49_ds_h2d; - assign tl_sm1_49_ds_d2h = tl_edn1_i; + assign tl_edn0_o = tl_sm1_51_ds_h2d; + assign tl_sm1_51_ds_d2h = tl_edn0_i; - assign tl_hmac_o = tl_sm1_50_ds_h2d; - assign tl_sm1_50_ds_d2h = tl_hmac_i; + assign tl_edn1_o = tl_sm1_52_ds_h2d; + assign tl_sm1_52_ds_d2h = tl_edn1_i; - assign tl_rv_plic_o = tl_sm1_51_ds_h2d; - assign tl_sm1_51_ds_d2h = tl_rv_plic_i; + assign tl_hmac_o = tl_sm1_53_ds_h2d; + assign tl_sm1_53_ds_d2h = tl_hmac_i; - assign tl_otbn_o = tl_sm1_52_ds_h2d; - assign tl_sm1_52_ds_d2h = tl_otbn_i; + assign tl_rv_plic_o = tl_sm1_54_ds_h2d; + assign tl_sm1_54_ds_d2h = tl_rv_plic_i; - assign tl_keymgr_o = tl_sm1_53_ds_h2d; - assign tl_sm1_53_ds_d2h = tl_keymgr_i; + assign tl_otbn_o = tl_sm1_55_ds_h2d; + assign tl_sm1_55_ds_d2h = tl_otbn_i; - assign tl_kmac_o = tl_sm1_54_ds_h2d; - assign tl_sm1_54_ds_d2h = tl_kmac_i; + assign tl_keymgr_o = tl_sm1_56_ds_h2d; + assign tl_sm1_56_ds_d2h = tl_keymgr_i; - assign tl_sram_ctrl_main__regs_o = tl_sm1_55_ds_h2d; - assign tl_sm1_55_ds_d2h = tl_sram_ctrl_main__regs_i; + assign tl_kmac_o = tl_sm1_57_ds_h2d; + assign tl_sm1_57_ds_d2h = tl_kmac_i; - assign tl_rv_core_ibex__cfg_o = tl_sm1_56_ds_h2d; - assign tl_sm1_56_ds_d2h = tl_rv_core_ibex__cfg_i; + assign tl_sram_ctrl_main__regs_o = tl_sm1_58_ds_h2d; + assign tl_sm1_58_ds_d2h = tl_sram_ctrl_main__regs_i; - assign tl_s1n_57_us_h2d = tl_rv_dm__sba_i; - assign tl_rv_dm__sba_o = tl_s1n_57_us_d2h; + assign tl_rv_core_ibex__cfg_o = tl_sm1_59_ds_h2d; + assign tl_sm1_59_ds_d2h = tl_rv_core_ibex__cfg_i; + + assign tl_sram_ctrl_meta__regs_o = tl_sm1_60_ds_h2d; + assign tl_sm1_60_ds_d2h = tl_sram_ctrl_meta__regs_i; + + assign tl_cheriot__regs_o = tl_sm1_61_ds_h2d; + assign tl_sm1_61_ds_d2h = tl_cheriot__regs_i; + + assign tl_cheriot__revbm_o = tl_sm1_62_ds_h2d; + assign tl_sm1_62_ds_d2h = tl_cheriot__revbm_i; + + assign tl_s1n_63_us_h2d = tl_rv_dm__sba_i; + assign tl_rv_dm__sba_o = tl_s1n_63_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_27 = 3'd4; - if ((tl_s1n_27_us_h2d.a_address & + dev_sel_s1n_30 = 3'd4; + if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin - dev_sel_s1n_27 = 3'd0; + dev_sel_s1n_30 = 3'd0; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_27 = 3'd1; + dev_sel_s1n_30 = 3'd1; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_27 = 3'd2; + dev_sel_s1n_30 = 3'd2; - end else if ((tl_s1n_27_us_h2d.a_address & + end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_27 = 3'd3; + dev_sel_s1n_30 = 3'd3; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_32 = 5'd24; - if ((tl_s1n_32_us_h2d.a_address & + dev_sel_s1n_35 = 5'd27; + if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin - dev_sel_s1n_32 = 5'd0; + dev_sel_s1n_35 = 5'd0; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_32 = 5'd1; + dev_sel_s1n_35 = 5'd1; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_32 = 5'd2; + dev_sel_s1n_35 = 5'd2; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin - dev_sel_s1n_32 = 5'd3; + dev_sel_s1n_35 = 5'd3; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_32 = 5'd4; + dev_sel_s1n_35 = 5'd4; end else if ( - ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || - ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) + ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || + ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) ) begin - dev_sel_s1n_32 = 5'd5; + dev_sel_s1n_35 = 5'd5; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin - dev_sel_s1n_32 = 5'd6; + dev_sel_s1n_35 = 5'd6; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin - dev_sel_s1n_32 = 5'd7; + dev_sel_s1n_35 = 5'd7; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_32 = 5'd8; + dev_sel_s1n_35 = 5'd8; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_32 = 5'd9; + dev_sel_s1n_35 = 5'd9; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_32 = 5'd10; + dev_sel_s1n_35 = 5'd10; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_32 = 5'd11; + dev_sel_s1n_35 = 5'd11; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_32 = 5'd12; + dev_sel_s1n_35 = 5'd12; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_32 = 5'd13; + dev_sel_s1n_35 = 5'd13; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_32 = 5'd14; + dev_sel_s1n_35 = 5'd14; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_32 = 5'd15; + dev_sel_s1n_35 = 5'd15; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_32 = 5'd16; + dev_sel_s1n_35 = 5'd16; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_32 = 5'd17; + dev_sel_s1n_35 = 5'd17; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_32 = 5'd18; + dev_sel_s1n_35 = 5'd18; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_32 = 5'd19; + dev_sel_s1n_35 = 5'd19; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin - dev_sel_s1n_32 = 5'd20; + dev_sel_s1n_35 = 5'd20; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_32 = 5'd21; + dev_sel_s1n_35 = 5'd21; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin - dev_sel_s1n_32 = 5'd22; + dev_sel_s1n_35 = 5'd22; - end else if ((tl_s1n_32_us_h2d.a_address & + end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin - dev_sel_s1n_32 = 5'd23; + dev_sel_s1n_35 = 5'd23; + + end else if ((tl_s1n_35_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_META__REGS)) == ADDR_SPACE_SRAM_CTRL_META__REGS) begin + dev_sel_s1n_35 = 5'd24; + + end else if ((tl_s1n_35_us_h2d.a_address & + ~(ADDR_MASK_CHERIOT__REGS)) == ADDR_SPACE_CHERIOT__REGS) begin + dev_sel_s1n_35 = 5'd25; + + end else if ((tl_s1n_35_us_h2d.a_address & + ~(ADDR_MASK_CHERIOT__REVBM)) == ADDR_SPACE_CHERIOT__REVBM) begin + dev_sel_s1n_35 = 5'd26; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_57 = 5'd24; - if ((tl_s1n_57_us_h2d.a_address & + dev_sel_s1n_63 = 5'd27; + if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin - dev_sel_s1n_57 = 5'd0; + dev_sel_s1n_63 = 5'd0; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_57 = 5'd1; + dev_sel_s1n_63 = 5'd1; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_57 = 5'd2; + dev_sel_s1n_63 = 5'd2; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin - dev_sel_s1n_57 = 5'd3; + dev_sel_s1n_63 = 5'd3; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_57 = 5'd4; + dev_sel_s1n_63 = 5'd4; end else if ( - ((tl_s1n_57_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || - ((tl_s1n_57_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) + ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || + ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) ) begin - dev_sel_s1n_57 = 5'd5; + dev_sel_s1n_63 = 5'd5; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin - dev_sel_s1n_57 = 5'd6; + dev_sel_s1n_63 = 5'd6; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin - dev_sel_s1n_57 = 5'd7; + dev_sel_s1n_63 = 5'd7; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_57 = 5'd8; + dev_sel_s1n_63 = 5'd8; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_57 = 5'd9; + dev_sel_s1n_63 = 5'd9; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_57 = 5'd10; + dev_sel_s1n_63 = 5'd10; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_57 = 5'd11; + dev_sel_s1n_63 = 5'd11; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_57 = 5'd12; + dev_sel_s1n_63 = 5'd12; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_57 = 5'd13; + dev_sel_s1n_63 = 5'd13; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_57 = 5'd14; + dev_sel_s1n_63 = 5'd14; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_57 = 5'd15; + dev_sel_s1n_63 = 5'd15; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_57 = 5'd16; + dev_sel_s1n_63 = 5'd16; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_57 = 5'd17; + dev_sel_s1n_63 = 5'd17; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_57 = 5'd18; + dev_sel_s1n_63 = 5'd18; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_57 = 5'd19; + dev_sel_s1n_63 = 5'd19; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin - dev_sel_s1n_57 = 5'd20; + dev_sel_s1n_63 = 5'd20; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_57 = 5'd21; + dev_sel_s1n_63 = 5'd21; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin - dev_sel_s1n_57 = 5'd22; + dev_sel_s1n_63 = 5'd22; - end else if ((tl_s1n_57_us_h2d.a_address & + end else if ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin - dev_sel_s1n_57 = 5'd23; + dev_sel_s1n_63 = 5'd23; + + end else if ((tl_s1n_63_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_META__REGS)) == ADDR_SPACE_SRAM_CTRL_META__REGS) begin + dev_sel_s1n_63 = 5'd24; + + end else if ((tl_s1n_63_us_h2d.a_address & + ~(ADDR_MASK_CHERIOT__REGS)) == ADDR_SPACE_CHERIOT__REGS) begin + dev_sel_s1n_63 = 5'd25; + + end else if ((tl_s1n_63_us_h2d.a_address & + ~(ADDR_MASK_CHERIOT__REVBM)) == ADDR_SPACE_CHERIOT__REVBM) begin + dev_sel_s1n_63 = 5'd26; end end @@ -910,27 +1000,27 @@ end .DReqDepth (16'h0), .DRspDepth (16'h0), .N (4) - ) u_s1n_27 ( + ) u_s1n_30 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_27_us_h2d), - .tl_h_o (tl_s1n_27_us_d2h), - .tl_d_o (tl_s1n_27_ds_h2d), - .tl_d_i (tl_s1n_27_ds_d2h), - .dev_select_i (dev_sel_s1n_27) + .tl_h_i (tl_s1n_30_us_h2d), + .tl_h_o (tl_s1n_30_us_d2h), + .tl_d_o (tl_s1n_30_ds_h2d), + .tl_d_i (tl_s1n_30_ds_d2h), + .dev_select_i (dev_sel_s1n_30) ); tlul_socket_m1 #( .HReqDepth (12'h0), .HRspDepth (12'h0), .DRspPass (1'b0), .M (3) - ) u_sm1_28 ( + ) u_sm1_31 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_28_us_h2d), - .tl_h_o (tl_sm1_28_us_d2h), - .tl_d_o (tl_sm1_28_ds_h2d), - .tl_d_i (tl_sm1_28_ds_d2h) + .tl_h_i (tl_sm1_31_us_h2d), + .tl_h_o (tl_sm1_31_us_d2h), + .tl_d_o (tl_sm1_31_ds_h2d), + .tl_d_i (tl_sm1_31_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -938,13 +1028,13 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (3) - ) u_sm1_29 ( + ) u_sm1_32 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_29_us_h2d), - .tl_h_o (tl_sm1_29_us_d2h), - .tl_d_o (tl_sm1_29_ds_h2d), - .tl_d_i (tl_sm1_29_ds_d2h) + .tl_h_i (tl_sm1_32_us_h2d), + .tl_h_o (tl_sm1_32_us_d2h), + .tl_d_o (tl_sm1_32_ds_h2d), + .tl_d_i (tl_sm1_32_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -952,13 +1042,13 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_30 ( + ) u_sm1_33 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_30_us_h2d), - .tl_h_o (tl_sm1_30_us_d2h), - .tl_d_o (tl_sm1_30_ds_h2d), - .tl_d_i (tl_sm1_30_ds_d2h) + .tl_h_i (tl_sm1_33_us_h2d), + .tl_h_o (tl_sm1_33_us_d2h), + .tl_d_o (tl_sm1_33_ds_h2d), + .tl_d_i (tl_sm1_33_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -966,28 +1056,28 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (3) - ) u_sm1_31 ( + ) u_sm1_34 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_31_us_h2d), - .tl_h_o (tl_sm1_31_us_d2h), - .tl_d_o (tl_sm1_31_ds_h2d), - .tl_d_i (tl_sm1_31_ds_d2h) + .tl_h_i (tl_sm1_34_us_h2d), + .tl_h_o (tl_sm1_34_us_d2h), + .tl_d_o (tl_sm1_34_ds_h2d), + .tl_d_i (tl_sm1_34_ds_d2h) ); tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (96'h0), - .DRspDepth (96'h0), - .N (24) - ) u_s1n_32 ( + .DReqDepth (108'h0), + .DRspDepth (108'h0), + .N (27) + ) u_s1n_35 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_32_us_h2d), - .tl_h_o (tl_s1n_32_us_d2h), - .tl_d_o (tl_s1n_32_ds_h2d), - .tl_d_i (tl_s1n_32_ds_d2h), - .dev_select_i (dev_sel_s1n_32) + .tl_h_i (tl_s1n_35_us_h2d), + .tl_h_o (tl_s1n_35_us_d2h), + .tl_d_o (tl_s1n_35_ds_h2d), + .tl_d_i (tl_s1n_35_ds_d2h), + .dev_select_i (dev_sel_s1n_35) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -995,13 +1085,13 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (2) - ) u_sm1_33 ( + ) u_sm1_36 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_33_us_h2d), - .tl_h_o (tl_sm1_33_us_d2h), - .tl_d_o (tl_sm1_33_ds_h2d), - .tl_d_i (tl_sm1_33_ds_d2h) + .tl_h_i (tl_sm1_36_us_h2d), + .tl_h_o (tl_sm1_36_us_d2h), + .tl_d_o (tl_sm1_36_ds_h2d), + .tl_d_i (tl_sm1_36_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1009,26 +1099,26 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (2) - ) u_sm1_34 ( + ) u_sm1_37 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_34_us_h2d), - .tl_h_o (tl_sm1_34_us_d2h), - .tl_d_o (tl_sm1_34_ds_h2d), - .tl_d_i (tl_sm1_34_ds_d2h) + .tl_h_i (tl_sm1_37_us_h2d), + .tl_h_o (tl_sm1_37_us_d2h), + .tl_d_o (tl_sm1_37_ds_h2d), + .tl_d_i (tl_sm1_37_ds_d2h) ); tlul_fifo_async #( .ReqDepth (1), .RspDepth (1) - ) u_asf_35 ( + ) u_asf_38 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), .clk_d_i (clk_fixed_i), .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_35_us_h2d), - .tl_h_o (tl_asf_35_us_d2h), - .tl_d_o (tl_asf_35_ds_h2d), - .tl_d_i (tl_asf_35_ds_d2h) + .tl_h_i (tl_asf_38_us_h2d), + .tl_h_o (tl_asf_38_us_d2h), + .tl_d_o (tl_asf_38_ds_h2d), + .tl_d_i (tl_asf_38_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1036,26 +1126,26 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (2) - ) u_sm1_36 ( + ) u_sm1_39 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_36_us_h2d), - .tl_h_o (tl_sm1_36_us_d2h), - .tl_d_o (tl_sm1_36_ds_h2d), - .tl_d_i (tl_sm1_36_ds_d2h) + .tl_h_i (tl_sm1_39_us_h2d), + .tl_h_o (tl_sm1_39_us_d2h), + .tl_d_o (tl_sm1_39_ds_h2d), + .tl_d_i (tl_sm1_39_ds_d2h) ); tlul_fifo_async #( .ReqDepth (1), .RspDepth (1) - ) u_asf_37 ( + ) u_asf_40 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), .clk_d_i (clk_spi_host0_i), .rst_d_ni (rst_spi_host0_ni), - .tl_h_i (tl_asf_37_us_h2d), - .tl_h_o (tl_asf_37_us_d2h), - .tl_d_o (tl_asf_37_ds_h2d), - .tl_d_i (tl_asf_37_ds_d2h) + .tl_h_i (tl_asf_40_us_h2d), + .tl_h_o (tl_asf_40_us_d2h), + .tl_d_o (tl_asf_40_ds_h2d), + .tl_d_i (tl_asf_40_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1063,26 +1153,26 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (2) - ) u_sm1_38 ( + ) u_sm1_41 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_38_us_h2d), - .tl_h_o (tl_sm1_38_us_d2h), - .tl_d_o (tl_sm1_38_ds_h2d), - .tl_d_i (tl_sm1_38_ds_d2h) + .tl_h_i (tl_sm1_41_us_h2d), + .tl_h_o (tl_sm1_41_us_d2h), + .tl_d_o (tl_sm1_41_ds_h2d), + .tl_d_i (tl_sm1_41_ds_d2h) ); tlul_fifo_async #( .ReqDepth (1), .RspDepth (1) - ) u_asf_39 ( + ) u_asf_42 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), .clk_d_i (clk_spi_host1_i), .rst_d_ni (rst_spi_host1_ni), - .tl_h_i (tl_asf_39_us_h2d), - .tl_h_o (tl_asf_39_us_d2h), - .tl_d_o (tl_asf_39_ds_h2d), - .tl_d_i (tl_asf_39_ds_d2h) + .tl_h_i (tl_asf_42_us_h2d), + .tl_h_o (tl_asf_42_us_d2h), + .tl_d_o (tl_asf_42_ds_h2d), + .tl_d_i (tl_asf_42_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1090,26 +1180,26 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (2) - ) u_sm1_40 ( + ) u_sm1_43 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_40_us_h2d), - .tl_h_o (tl_sm1_40_us_d2h), - .tl_d_o (tl_sm1_40_ds_h2d), - .tl_d_i (tl_sm1_40_ds_d2h) + .tl_h_i (tl_sm1_43_us_h2d), + .tl_h_o (tl_sm1_43_us_d2h), + .tl_d_o (tl_sm1_43_ds_h2d), + .tl_d_i (tl_sm1_43_ds_d2h) ); tlul_fifo_async #( .ReqDepth (1), .RspDepth (1) - ) u_asf_41 ( + ) u_asf_44 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), .clk_d_i (clk_usb_i), .rst_d_ni (rst_usb_ni), - .tl_h_i (tl_asf_41_us_h2d), - .tl_h_o (tl_asf_41_us_d2h), - .tl_d_o (tl_asf_41_ds_h2d), - .tl_d_i (tl_asf_41_ds_d2h) + .tl_h_i (tl_asf_44_us_h2d), + .tl_h_o (tl_asf_44_us_d2h), + .tl_d_o (tl_asf_44_ds_h2d), + .tl_d_i (tl_asf_44_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1117,48 +1207,6 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (2) - ) u_sm1_42 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_42_us_h2d), - .tl_h_o (tl_sm1_42_us_d2h), - .tl_d_o (tl_sm1_42_ds_h2d), - .tl_d_i (tl_sm1_42_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_43 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_43_us_h2d), - .tl_h_o (tl_sm1_43_us_d2h), - .tl_d_o (tl_sm1_43_ds_h2d), - .tl_d_i (tl_sm1_43_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_44 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_44_us_h2d), - .tl_h_o (tl_sm1_44_us_d2h), - .tl_d_o (tl_sm1_44_ds_h2d), - .tl_d_i (tl_sm1_44_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) ) u_sm1_45 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -1321,20 +1369,104 @@ end .tl_d_o (tl_sm1_56_ds_h2d), .tl_d_i (tl_sm1_56_ds_d2h) ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_57 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_57_us_h2d), + .tl_h_o (tl_sm1_57_us_d2h), + .tl_d_o (tl_sm1_57_ds_h2d), + .tl_d_i (tl_sm1_57_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_58 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_58_us_h2d), + .tl_h_o (tl_sm1_58_us_d2h), + .tl_d_o (tl_sm1_58_ds_h2d), + .tl_d_i (tl_sm1_58_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_59 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_59_us_h2d), + .tl_h_o (tl_sm1_59_us_d2h), + .tl_d_o (tl_sm1_59_ds_h2d), + .tl_d_i (tl_sm1_59_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_60 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_60_us_h2d), + .tl_h_o (tl_sm1_60_us_d2h), + .tl_d_o (tl_sm1_60_ds_h2d), + .tl_d_i (tl_sm1_60_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_61 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_61_us_h2d), + .tl_h_o (tl_sm1_61_us_d2h), + .tl_d_o (tl_sm1_61_ds_h2d), + .tl_d_i (tl_sm1_61_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_62 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_62_us_h2d), + .tl_h_o (tl_sm1_62_us_d2h), + .tl_d_o (tl_sm1_62_ds_h2d), + .tl_d_i (tl_sm1_62_ds_d2h) + ); tlul_socket_1n #( .HReqPass (1'b0), .HRspPass (1'b0), - .DReqDepth (96'h0), - .DRspDepth (96'h0), - .N (24) - ) u_s1n_57 ( + .DReqDepth (108'h0), + .DRspDepth (108'h0), + .N (27) + ) u_s1n_63 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_57_us_h2d), - .tl_h_o (tl_s1n_57_us_d2h), - .tl_d_o (tl_s1n_57_ds_h2d), - .tl_d_i (tl_s1n_57_ds_d2h), - .dev_select_i (dev_sel_s1n_57) + .tl_h_i (tl_s1n_63_us_h2d), + .tl_h_o (tl_s1n_63_us_d2h), + .tl_d_o (tl_s1n_63_ds_h2d), + .tl_d_i (tl_s1n_63_ds_d2h), + .dev_select_i (dev_sel_s1n_63) ); endmodule diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson index 7f59ba7b95f8b..208fd03e9d46f 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson @@ -49,7 +49,7 @@ { name: "NAlerts", desc: "Number of alert channels.", type: "int", - default: "63", + default: "65", local: "true" }, { name: "NLpg", @@ -77,6 +77,8 @@ 5'd17, 5'd17, 5'd17, + 5'd17, + 5'd17, 5'd19, 5'd19, 5'd19, @@ -220,6 +222,8 @@ 1'b1, 1'b1, 1'b1, + 1'b1, + 1'b1, 1'b1 } ''' diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index 40d443c49ceea..a72b51cf31eb2 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -6,7 +6,7 @@ param_values: { module_instance_name: alert_handler - n_alerts: 63 + n_alerts: 65 esc_cnt_dw: 32 accu_cnt_dw: 16 async_on: @@ -74,6 +74,8 @@ 1'b1 1'b1 1'b1 + 1'b1 + 1'b1 ] n_classes: 4 n_esc_sev: 4 @@ -144,6 +146,8 @@ 5'd17 5'd17 5'd17 + 5'd17 + 5'd17 ] topname: earlgrey uniquified_modules: {} diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md index f2e1856cd658c..70e33441ed16d 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md +++ b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md @@ -24,7 +24,7 @@ The parameterization rules are explained in more detail in the architectural des Localparam | Default (Max) | This Core | Description ---------------|-----------------------|----------------|--------------- -`NAlerts` | 8 (248) | 63 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. +`NAlerts` | 8 (248) | 65 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. `NLpg` | 1 | 24 | Number of unique low-power groups as determined by topgen. `LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen. `EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit. diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv index e38de9d2add7e..a2d291b385d89 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -7,7 +7,7 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 63; + parameter int NAlerts = 65; parameter int NLpg = 24; parameter int NLpgWidth = 5; parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { @@ -17,6 +17,8 @@ package alert_handler_reg_pkg; 5'd17, 5'd17, 5'd17, + 5'd17, + 5'd17, 5'd19, 5'd19, 5'd19, @@ -140,6 +142,8 @@ package alert_handler_reg_pkg; 1'b1, 1'b1, 1'b1, + 1'b1, + 1'b1, 1'b1 }; parameter int N_CLASSES = 4; @@ -162,7 +166,7 @@ package alert_handler_reg_pkg; parameter int BlockAw = 11; // Number of registers for every interface - parameter int NumRegs = 342; + parameter int NumRegs = 350; //////////////////////////// // Typedefs for registers // @@ -616,15 +620,15 @@ package alert_handler_reg_pkg; // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [1151:1148] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1147:1144] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [1143:1136] - alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1135:1120] - alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1119:1119] - alert_handler_reg2hw_alert_regwen_mreg_t [62:0] alert_regwen; // [1118:1056] - alert_handler_reg2hw_alert_en_shadowed_mreg_t [62:0] alert_en_shadowed; // [1055:993] - alert_handler_reg2hw_alert_class_shadowed_mreg_t [62:0] alert_class_shadowed; // [992:867] - alert_handler_reg2hw_alert_cause_mreg_t [62:0] alert_cause; // [866:804] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1161:1158] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1157:1154] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1153:1146] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1145:1130] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1129:1129] + alert_handler_reg2hw_alert_regwen_mreg_t [64:0] alert_regwen; // [1128:1064] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [64:0] alert_en_shadowed; // [1063:999] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [64:0] alert_class_shadowed; // [998:869] + alert_handler_reg2hw_alert_cause_mreg_t [64:0] alert_cause; // [868:804] alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] loc_alert_class_shadowed; // [796:783] @@ -677,8 +681,8 @@ package alert_handler_reg_pkg; // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [359:352] - alert_handler_hw2reg_alert_cause_mreg_t [62:0] alert_cause; // [351:226] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [363:356] + alert_handler_hw2reg_alert_cause_mreg_t [64:0] alert_cause; // [355:226] alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -768,279 +772,287 @@ package alert_handler_reg_pkg; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 114; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 118; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 11c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 460; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 464; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 468; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 46c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 470; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 474; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 478; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 47c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 480; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 484; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 488; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 48c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 490; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 494; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 498; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 49c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 500; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 504; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 508; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 50c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 510; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 514; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 518; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 51c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 520; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 524; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 528; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 52c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 530; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 534; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 538; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 53c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 540; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 544; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 548; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 54c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 550; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 574; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -1132,6 +1144,8 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_REGWEN_60, ALERT_HANDLER_ALERT_REGWEN_61, ALERT_HANDLER_ALERT_REGWEN_62, + ALERT_HANDLER_ALERT_REGWEN_63, + ALERT_HANDLER_ALERT_REGWEN_64, ALERT_HANDLER_ALERT_EN_SHADOWED_0, ALERT_HANDLER_ALERT_EN_SHADOWED_1, ALERT_HANDLER_ALERT_EN_SHADOWED_2, @@ -1195,6 +1209,8 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_EN_SHADOWED_60, ALERT_HANDLER_ALERT_EN_SHADOWED_61, ALERT_HANDLER_ALERT_EN_SHADOWED_62, + ALERT_HANDLER_ALERT_EN_SHADOWED_63, + ALERT_HANDLER_ALERT_EN_SHADOWED_64, ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, @@ -1258,6 +1274,8 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CLASS_SHADOWED_60, ALERT_HANDLER_ALERT_CLASS_SHADOWED_61, ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -1321,6 +1339,8 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CAUSE_60, ALERT_HANDLER_ALERT_CAUSE_61, ALERT_HANDLER_ALERT_CAUSE_62, + ALERT_HANDLER_ALERT_CAUSE_63, + ALERT_HANDLER_ALERT_CAUSE_64, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -1408,7 +1428,7 @@ package alert_handler_reg_pkg; } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [342] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [350] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1478,279 +1498,287 @@ package alert_handler_reg_pkg; 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 - 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_7 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_8 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_9 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_10 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_11 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_12 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_13 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_14 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_15 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_16 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_17 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_18 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_19 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_20 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_21 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_22 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_23 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_24 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_25 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_26 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_27 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_28 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_29 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_30 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_31 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_32 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_33 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_34 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_35 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_36 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_37 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_38 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_39 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_40 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_41 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_42 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_43 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_44 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_45 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_46 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_47 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_48 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_49 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_50 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_51 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_52 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_53 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_54 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_55 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_56 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_57 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_58 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_59 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_60 - 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_61 - 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_62 - 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 - 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 - 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 - 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 - 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 - 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 - 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 - 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 - 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 - 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 - 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 - 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 - 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 - 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 - 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 - 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 - 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 - 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 - 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 - 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 - 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 - 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 - 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 - 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 - 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 - 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 - 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 - 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 - 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 - 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 - 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 - 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 - 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 - 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 - 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 - 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 - 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 - 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 - 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 - 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 - 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 - 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 - 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 - 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 - 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 - 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 - 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 - 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 - 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 - 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 - 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 - 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 - 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 - 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 - 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 - 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 - 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_31 - 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_32 - 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_33 - 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_34 - 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_35 - 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_36 - 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_37 - 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_38 - 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_39 - 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_40 - 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_41 - 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_42 - 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_43 - 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_44 - 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_45 - 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_46 - 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_47 - 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_48 - 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_49 - 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_50 - 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_51 - 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_52 - 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_53 - 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_54 - 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_55 - 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_56 - 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_57 - 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_58 - 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_59 - 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_60 - 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_61 - 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_62 - 4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_REGWEN_5 - 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_REGWEN_6 - 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CAUSE_4 - 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CAUSE_5 - 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CAUSE_6 - 4'b 0001, // index[286] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[287] ALERT_HANDLER_CLASSA_CTRL_SHADOWED - 4'b 0001, // index[288] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[289] ALERT_HANDLER_CLASSA_CLR_SHADOWED - 4'b 0011, // index[290] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[291] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[292] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[293] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[294] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED - 4'b 1111, // index[295] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED - 4'b 1111, // index[296] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED - 4'b 1111, // index[297] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED - 4'b 1111, // index[298] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[299] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[300] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[301] ALERT_HANDLER_CLASSB_CTRL_SHADOWED - 4'b 0001, // index[302] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[303] ALERT_HANDLER_CLASSB_CLR_SHADOWED - 4'b 0011, // index[304] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[305] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[306] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[307] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[308] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED - 4'b 1111, // index[309] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED - 4'b 1111, // index[310] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED - 4'b 1111, // index[311] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED - 4'b 1111, // index[312] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[313] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[314] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[315] ALERT_HANDLER_CLASSC_CTRL_SHADOWED - 4'b 0001, // index[316] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[317] ALERT_HANDLER_CLASSC_CLR_SHADOWED - 4'b 0011, // index[318] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[319] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[320] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[321] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[322] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED - 4'b 1111, // index[323] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED - 4'b 1111, // index[324] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED - 4'b 1111, // index[325] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED - 4'b 1111, // index[326] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[327] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[328] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[329] ALERT_HANDLER_CLASSD_CTRL_SHADOWED - 4'b 0001, // index[330] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[331] ALERT_HANDLER_CLASSD_CLR_SHADOWED - 4'b 0011, // index[332] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[333] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[334] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[335] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[336] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED - 4'b 1111, // index[337] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED - 4'b 1111, // index[338] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED - 4'b 1111, // index[339] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED - 4'b 1111, // index[340] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[341] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_64 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[294] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[296] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[298] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[301] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[303] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[305] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[306] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[307] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[308] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[309] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[310] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[311] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[312] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[313] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[315] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[317] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[319] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[320] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[321] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[322] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[323] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[324] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[325] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[326] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[327] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[329] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[331] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[332] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[333] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[334] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[335] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[336] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[338] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[340] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[341] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[343] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[345] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[346] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[347] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[348] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[349] ALERT_HANDLER_CLASSD_STATE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv index 57970b9f6b05d..bfd63f483984c 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv @@ -56,9 +56,9 @@ module alert_handler_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [341:0] reg_we_check; + logic [349:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(342) + .OneHotWidth(350) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -352,6 +352,12 @@ module alert_handler_reg_top ( logic alert_regwen_62_we; logic alert_regwen_62_qs; logic alert_regwen_62_wd; + logic alert_regwen_63_we; + logic alert_regwen_63_qs; + logic alert_regwen_63_wd; + logic alert_regwen_64_we; + logic alert_regwen_64_qs; + logic alert_regwen_64_wd; logic alert_en_shadowed_0_re; logic alert_en_shadowed_0_we; logic alert_en_shadowed_0_qs; @@ -730,6 +736,18 @@ module alert_handler_reg_top ( logic alert_en_shadowed_62_wd; logic alert_en_shadowed_62_storage_err; logic alert_en_shadowed_62_update_err; + logic alert_en_shadowed_63_re; + logic alert_en_shadowed_63_we; + logic alert_en_shadowed_63_qs; + logic alert_en_shadowed_63_wd; + logic alert_en_shadowed_63_storage_err; + logic alert_en_shadowed_63_update_err; + logic alert_en_shadowed_64_re; + logic alert_en_shadowed_64_we; + logic alert_en_shadowed_64_qs; + logic alert_en_shadowed_64_wd; + logic alert_en_shadowed_64_storage_err; + logic alert_en_shadowed_64_update_err; logic alert_class_shadowed_0_re; logic alert_class_shadowed_0_we; logic [1:0] alert_class_shadowed_0_qs; @@ -1108,6 +1126,18 @@ module alert_handler_reg_top ( logic [1:0] alert_class_shadowed_62_wd; logic alert_class_shadowed_62_storage_err; logic alert_class_shadowed_62_update_err; + logic alert_class_shadowed_63_re; + logic alert_class_shadowed_63_we; + logic [1:0] alert_class_shadowed_63_qs; + logic [1:0] alert_class_shadowed_63_wd; + logic alert_class_shadowed_63_storage_err; + logic alert_class_shadowed_63_update_err; + logic alert_class_shadowed_64_re; + logic alert_class_shadowed_64_we; + logic [1:0] alert_class_shadowed_64_qs; + logic [1:0] alert_class_shadowed_64_wd; + logic alert_class_shadowed_64_storage_err; + logic alert_class_shadowed_64_update_err; logic alert_cause_0_we; logic alert_cause_0_qs; logic alert_cause_0_wd; @@ -1297,6 +1327,12 @@ module alert_handler_reg_top ( logic alert_cause_62_we; logic alert_cause_62_qs; logic alert_cause_62_wd; + logic alert_cause_63_we; + logic alert_cause_63_qs; + logic alert_cause_63_wd; + logic alert_cause_64_we; + logic alert_cause_64_qs; + logic alert_cause_64_wd; logic loc_alert_regwen_0_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; @@ -4057,6 +4093,64 @@ module alert_handler_reg_top ( ); + // Subregister 63 of Multireg alert_regwen + // R[alert_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_63_we), + .wd (alert_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[63].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_63_qs) + ); + + + // Subregister 64 of Multireg alert_regwen + // R[alert_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_64_we), + .wd (alert_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[64].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_64_qs) + ); + + // Subregister 0 of Multireg alert_en_shadowed // R[alert_en_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -6640,6 +6734,88 @@ module alert_handler_reg_top ( ); + // Subregister 63 of Multireg alert_en_shadowed + // R[alert_en_shadowed_63]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_63_gated_we; + assign alert_en_shadowed_63_gated_we = alert_en_shadowed_63_we & alert_regwen_63_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_63_re), + .we (alert_en_shadowed_63_gated_we), + .wd (alert_en_shadowed_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[63].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_63_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_63_update_err), + .err_storage (alert_en_shadowed_63_storage_err) + ); + + + // Subregister 64 of Multireg alert_en_shadowed + // R[alert_en_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_64_gated_we; + assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_64_re), + .we (alert_en_shadowed_64_gated_we), + .wd (alert_en_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_64_update_err), + .err_storage (alert_en_shadowed_64_storage_err) + ); + + // Subregister 0 of Multireg alert_class_shadowed // R[alert_class_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -9223,6 +9399,88 @@ module alert_handler_reg_top ( ); + // Subregister 63 of Multireg alert_class_shadowed + // R[alert_class_shadowed_63]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_63_gated_we; + assign alert_class_shadowed_63_gated_we = alert_class_shadowed_63_we & alert_regwen_63_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_63_re), + .we (alert_class_shadowed_63_gated_we), + .wd (alert_class_shadowed_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[63].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_63_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_63_update_err), + .err_storage (alert_class_shadowed_63_storage_err) + ); + + + // Subregister 64 of Multireg alert_class_shadowed + // R[alert_class_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_64_gated_we; + assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_64_re), + .we (alert_class_shadowed_64_gated_we), + .wd (alert_class_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_64_update_err), + .err_storage (alert_class_shadowed_64_storage_err) + ); + + // Subregister 0 of Multireg alert_cause // R[alert_cause_0]: V(False) prim_subreg #( @@ -11050,6 +11308,64 @@ module alert_handler_reg_top ( ); + // Subregister 63 of Multireg alert_cause + // R[alert_cause_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_63_we), + .wd (alert_cause_63_wd), + + // from internal hardware + .de (hw2reg.alert_cause[63].de), + .d (hw2reg.alert_cause[63].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[63].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_63_qs) + ); + + + // Subregister 64 of Multireg alert_cause + // R[alert_cause_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_64_we), + .wd (alert_cause_64_wd), + + // from internal hardware + .de (hw2reg.alert_cause[64].de), + .d (hw2reg.alert_cause[64].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[64].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_64_qs) + ); + + // Subregister 0 of Multireg loc_alert_regwen // R[loc_alert_regwen_0]: V(False) prim_subreg #( @@ -15246,7 +15562,7 @@ module alert_handler_reg_top ( - logic [341:0] addr_hit; + logic [349:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET); @@ -15317,279 +15633,287 @@ module alert_handler_reg_top ( addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET); addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET); addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET); - addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); - addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); - addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); - addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); - addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); - addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); - addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); - addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); - addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); - addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); - addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); - addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); - addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); - addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); - addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); - addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); - addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); - addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); - addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); - addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); - addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); - addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); - addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); - addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); - addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); - addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); - addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); - addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); - addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); - addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); - addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); - addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); - addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); - addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); - addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); - addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); - addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); - addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); - addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); - addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); - addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); - addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); - addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); - addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); - addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); - addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); + addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -15938,7 +16262,15 @@ module alert_handler_reg_top ( (addr_hit[338] & (|(ALERT_HANDLER_PERMIT[338] & ~reg_be))) | (addr_hit[339] & (|(ALERT_HANDLER_PERMIT[339] & ~reg_be))) | (addr_hit[340] & (|(ALERT_HANDLER_PERMIT[340] & ~reg_be))) | - (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))))); + (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))) | + (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) | + (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) | + (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) | + (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) | + (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) | + (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) | + (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) | + (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))))); end // Generate write-enables @@ -16169,802 +16501,830 @@ module alert_handler_reg_top ( assign alert_regwen_62_we = addr_hit[68] & reg_we & !reg_error; assign alert_regwen_62_wd = reg_wdata[0]; - assign alert_en_shadowed_0_re = addr_hit[69] & reg_re & !reg_error; - assign alert_en_shadowed_0_we = addr_hit[69] & reg_we & !reg_error; + assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error; + + assign alert_regwen_63_wd = reg_wdata[0]; + assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error; + + assign alert_regwen_64_wd = reg_wdata[0]; + assign alert_en_shadowed_0_re = addr_hit[71] & reg_re & !reg_error; + assign alert_en_shadowed_0_we = addr_hit[71] & reg_we & !reg_error; assign alert_en_shadowed_0_wd = reg_wdata[0]; - assign alert_en_shadowed_1_re = addr_hit[70] & reg_re & !reg_error; - assign alert_en_shadowed_1_we = addr_hit[70] & reg_we & !reg_error; + assign alert_en_shadowed_1_re = addr_hit[72] & reg_re & !reg_error; + assign alert_en_shadowed_1_we = addr_hit[72] & reg_we & !reg_error; assign alert_en_shadowed_1_wd = reg_wdata[0]; - assign alert_en_shadowed_2_re = addr_hit[71] & reg_re & !reg_error; - assign alert_en_shadowed_2_we = addr_hit[71] & reg_we & !reg_error; + assign alert_en_shadowed_2_re = addr_hit[73] & reg_re & !reg_error; + assign alert_en_shadowed_2_we = addr_hit[73] & reg_we & !reg_error; assign alert_en_shadowed_2_wd = reg_wdata[0]; - assign alert_en_shadowed_3_re = addr_hit[72] & reg_re & !reg_error; - assign alert_en_shadowed_3_we = addr_hit[72] & reg_we & !reg_error; + assign alert_en_shadowed_3_re = addr_hit[74] & reg_re & !reg_error; + assign alert_en_shadowed_3_we = addr_hit[74] & reg_we & !reg_error; assign alert_en_shadowed_3_wd = reg_wdata[0]; - assign alert_en_shadowed_4_re = addr_hit[73] & reg_re & !reg_error; - assign alert_en_shadowed_4_we = addr_hit[73] & reg_we & !reg_error; + assign alert_en_shadowed_4_re = addr_hit[75] & reg_re & !reg_error; + assign alert_en_shadowed_4_we = addr_hit[75] & reg_we & !reg_error; assign alert_en_shadowed_4_wd = reg_wdata[0]; - assign alert_en_shadowed_5_re = addr_hit[74] & reg_re & !reg_error; - assign alert_en_shadowed_5_we = addr_hit[74] & reg_we & !reg_error; + assign alert_en_shadowed_5_re = addr_hit[76] & reg_re & !reg_error; + assign alert_en_shadowed_5_we = addr_hit[76] & reg_we & !reg_error; assign alert_en_shadowed_5_wd = reg_wdata[0]; - assign alert_en_shadowed_6_re = addr_hit[75] & reg_re & !reg_error; - assign alert_en_shadowed_6_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_shadowed_6_re = addr_hit[77] & reg_re & !reg_error; + assign alert_en_shadowed_6_we = addr_hit[77] & reg_we & !reg_error; assign alert_en_shadowed_6_wd = reg_wdata[0]; - assign alert_en_shadowed_7_re = addr_hit[76] & reg_re & !reg_error; - assign alert_en_shadowed_7_we = addr_hit[76] & reg_we & !reg_error; + assign alert_en_shadowed_7_re = addr_hit[78] & reg_re & !reg_error; + assign alert_en_shadowed_7_we = addr_hit[78] & reg_we & !reg_error; assign alert_en_shadowed_7_wd = reg_wdata[0]; - assign alert_en_shadowed_8_re = addr_hit[77] & reg_re & !reg_error; - assign alert_en_shadowed_8_we = addr_hit[77] & reg_we & !reg_error; + assign alert_en_shadowed_8_re = addr_hit[79] & reg_re & !reg_error; + assign alert_en_shadowed_8_we = addr_hit[79] & reg_we & !reg_error; assign alert_en_shadowed_8_wd = reg_wdata[0]; - assign alert_en_shadowed_9_re = addr_hit[78] & reg_re & !reg_error; - assign alert_en_shadowed_9_we = addr_hit[78] & reg_we & !reg_error; + assign alert_en_shadowed_9_re = addr_hit[80] & reg_re & !reg_error; + assign alert_en_shadowed_9_we = addr_hit[80] & reg_we & !reg_error; assign alert_en_shadowed_9_wd = reg_wdata[0]; - assign alert_en_shadowed_10_re = addr_hit[79] & reg_re & !reg_error; - assign alert_en_shadowed_10_we = addr_hit[79] & reg_we & !reg_error; + assign alert_en_shadowed_10_re = addr_hit[81] & reg_re & !reg_error; + assign alert_en_shadowed_10_we = addr_hit[81] & reg_we & !reg_error; assign alert_en_shadowed_10_wd = reg_wdata[0]; - assign alert_en_shadowed_11_re = addr_hit[80] & reg_re & !reg_error; - assign alert_en_shadowed_11_we = addr_hit[80] & reg_we & !reg_error; + assign alert_en_shadowed_11_re = addr_hit[82] & reg_re & !reg_error; + assign alert_en_shadowed_11_we = addr_hit[82] & reg_we & !reg_error; assign alert_en_shadowed_11_wd = reg_wdata[0]; - assign alert_en_shadowed_12_re = addr_hit[81] & reg_re & !reg_error; - assign alert_en_shadowed_12_we = addr_hit[81] & reg_we & !reg_error; + assign alert_en_shadowed_12_re = addr_hit[83] & reg_re & !reg_error; + assign alert_en_shadowed_12_we = addr_hit[83] & reg_we & !reg_error; assign alert_en_shadowed_12_wd = reg_wdata[0]; - assign alert_en_shadowed_13_re = addr_hit[82] & reg_re & !reg_error; - assign alert_en_shadowed_13_we = addr_hit[82] & reg_we & !reg_error; + assign alert_en_shadowed_13_re = addr_hit[84] & reg_re & !reg_error; + assign alert_en_shadowed_13_we = addr_hit[84] & reg_we & !reg_error; assign alert_en_shadowed_13_wd = reg_wdata[0]; - assign alert_en_shadowed_14_re = addr_hit[83] & reg_re & !reg_error; - assign alert_en_shadowed_14_we = addr_hit[83] & reg_we & !reg_error; + assign alert_en_shadowed_14_re = addr_hit[85] & reg_re & !reg_error; + assign alert_en_shadowed_14_we = addr_hit[85] & reg_we & !reg_error; assign alert_en_shadowed_14_wd = reg_wdata[0]; - assign alert_en_shadowed_15_re = addr_hit[84] & reg_re & !reg_error; - assign alert_en_shadowed_15_we = addr_hit[84] & reg_we & !reg_error; + assign alert_en_shadowed_15_re = addr_hit[86] & reg_re & !reg_error; + assign alert_en_shadowed_15_we = addr_hit[86] & reg_we & !reg_error; assign alert_en_shadowed_15_wd = reg_wdata[0]; - assign alert_en_shadowed_16_re = addr_hit[85] & reg_re & !reg_error; - assign alert_en_shadowed_16_we = addr_hit[85] & reg_we & !reg_error; + assign alert_en_shadowed_16_re = addr_hit[87] & reg_re & !reg_error; + assign alert_en_shadowed_16_we = addr_hit[87] & reg_we & !reg_error; assign alert_en_shadowed_16_wd = reg_wdata[0]; - assign alert_en_shadowed_17_re = addr_hit[86] & reg_re & !reg_error; - assign alert_en_shadowed_17_we = addr_hit[86] & reg_we & !reg_error; + assign alert_en_shadowed_17_re = addr_hit[88] & reg_re & !reg_error; + assign alert_en_shadowed_17_we = addr_hit[88] & reg_we & !reg_error; assign alert_en_shadowed_17_wd = reg_wdata[0]; - assign alert_en_shadowed_18_re = addr_hit[87] & reg_re & !reg_error; - assign alert_en_shadowed_18_we = addr_hit[87] & reg_we & !reg_error; + assign alert_en_shadowed_18_re = addr_hit[89] & reg_re & !reg_error; + assign alert_en_shadowed_18_we = addr_hit[89] & reg_we & !reg_error; assign alert_en_shadowed_18_wd = reg_wdata[0]; - assign alert_en_shadowed_19_re = addr_hit[88] & reg_re & !reg_error; - assign alert_en_shadowed_19_we = addr_hit[88] & reg_we & !reg_error; + assign alert_en_shadowed_19_re = addr_hit[90] & reg_re & !reg_error; + assign alert_en_shadowed_19_we = addr_hit[90] & reg_we & !reg_error; assign alert_en_shadowed_19_wd = reg_wdata[0]; - assign alert_en_shadowed_20_re = addr_hit[89] & reg_re & !reg_error; - assign alert_en_shadowed_20_we = addr_hit[89] & reg_we & !reg_error; + assign alert_en_shadowed_20_re = addr_hit[91] & reg_re & !reg_error; + assign alert_en_shadowed_20_we = addr_hit[91] & reg_we & !reg_error; assign alert_en_shadowed_20_wd = reg_wdata[0]; - assign alert_en_shadowed_21_re = addr_hit[90] & reg_re & !reg_error; - assign alert_en_shadowed_21_we = addr_hit[90] & reg_we & !reg_error; + assign alert_en_shadowed_21_re = addr_hit[92] & reg_re & !reg_error; + assign alert_en_shadowed_21_we = addr_hit[92] & reg_we & !reg_error; assign alert_en_shadowed_21_wd = reg_wdata[0]; - assign alert_en_shadowed_22_re = addr_hit[91] & reg_re & !reg_error; - assign alert_en_shadowed_22_we = addr_hit[91] & reg_we & !reg_error; + assign alert_en_shadowed_22_re = addr_hit[93] & reg_re & !reg_error; + assign alert_en_shadowed_22_we = addr_hit[93] & reg_we & !reg_error; assign alert_en_shadowed_22_wd = reg_wdata[0]; - assign alert_en_shadowed_23_re = addr_hit[92] & reg_re & !reg_error; - assign alert_en_shadowed_23_we = addr_hit[92] & reg_we & !reg_error; + assign alert_en_shadowed_23_re = addr_hit[94] & reg_re & !reg_error; + assign alert_en_shadowed_23_we = addr_hit[94] & reg_we & !reg_error; assign alert_en_shadowed_23_wd = reg_wdata[0]; - assign alert_en_shadowed_24_re = addr_hit[93] & reg_re & !reg_error; - assign alert_en_shadowed_24_we = addr_hit[93] & reg_we & !reg_error; + assign alert_en_shadowed_24_re = addr_hit[95] & reg_re & !reg_error; + assign alert_en_shadowed_24_we = addr_hit[95] & reg_we & !reg_error; assign alert_en_shadowed_24_wd = reg_wdata[0]; - assign alert_en_shadowed_25_re = addr_hit[94] & reg_re & !reg_error; - assign alert_en_shadowed_25_we = addr_hit[94] & reg_we & !reg_error; + assign alert_en_shadowed_25_re = addr_hit[96] & reg_re & !reg_error; + assign alert_en_shadowed_25_we = addr_hit[96] & reg_we & !reg_error; assign alert_en_shadowed_25_wd = reg_wdata[0]; - assign alert_en_shadowed_26_re = addr_hit[95] & reg_re & !reg_error; - assign alert_en_shadowed_26_we = addr_hit[95] & reg_we & !reg_error; + assign alert_en_shadowed_26_re = addr_hit[97] & reg_re & !reg_error; + assign alert_en_shadowed_26_we = addr_hit[97] & reg_we & !reg_error; assign alert_en_shadowed_26_wd = reg_wdata[0]; - assign alert_en_shadowed_27_re = addr_hit[96] & reg_re & !reg_error; - assign alert_en_shadowed_27_we = addr_hit[96] & reg_we & !reg_error; + assign alert_en_shadowed_27_re = addr_hit[98] & reg_re & !reg_error; + assign alert_en_shadowed_27_we = addr_hit[98] & reg_we & !reg_error; assign alert_en_shadowed_27_wd = reg_wdata[0]; - assign alert_en_shadowed_28_re = addr_hit[97] & reg_re & !reg_error; - assign alert_en_shadowed_28_we = addr_hit[97] & reg_we & !reg_error; + assign alert_en_shadowed_28_re = addr_hit[99] & reg_re & !reg_error; + assign alert_en_shadowed_28_we = addr_hit[99] & reg_we & !reg_error; assign alert_en_shadowed_28_wd = reg_wdata[0]; - assign alert_en_shadowed_29_re = addr_hit[98] & reg_re & !reg_error; - assign alert_en_shadowed_29_we = addr_hit[98] & reg_we & !reg_error; + assign alert_en_shadowed_29_re = addr_hit[100] & reg_re & !reg_error; + assign alert_en_shadowed_29_we = addr_hit[100] & reg_we & !reg_error; assign alert_en_shadowed_29_wd = reg_wdata[0]; - assign alert_en_shadowed_30_re = addr_hit[99] & reg_re & !reg_error; - assign alert_en_shadowed_30_we = addr_hit[99] & reg_we & !reg_error; + assign alert_en_shadowed_30_re = addr_hit[101] & reg_re & !reg_error; + assign alert_en_shadowed_30_we = addr_hit[101] & reg_we & !reg_error; assign alert_en_shadowed_30_wd = reg_wdata[0]; - assign alert_en_shadowed_31_re = addr_hit[100] & reg_re & !reg_error; - assign alert_en_shadowed_31_we = addr_hit[100] & reg_we & !reg_error; + assign alert_en_shadowed_31_re = addr_hit[102] & reg_re & !reg_error; + assign alert_en_shadowed_31_we = addr_hit[102] & reg_we & !reg_error; assign alert_en_shadowed_31_wd = reg_wdata[0]; - assign alert_en_shadowed_32_re = addr_hit[101] & reg_re & !reg_error; - assign alert_en_shadowed_32_we = addr_hit[101] & reg_we & !reg_error; + assign alert_en_shadowed_32_re = addr_hit[103] & reg_re & !reg_error; + assign alert_en_shadowed_32_we = addr_hit[103] & reg_we & !reg_error; assign alert_en_shadowed_32_wd = reg_wdata[0]; - assign alert_en_shadowed_33_re = addr_hit[102] & reg_re & !reg_error; - assign alert_en_shadowed_33_we = addr_hit[102] & reg_we & !reg_error; + assign alert_en_shadowed_33_re = addr_hit[104] & reg_re & !reg_error; + assign alert_en_shadowed_33_we = addr_hit[104] & reg_we & !reg_error; assign alert_en_shadowed_33_wd = reg_wdata[0]; - assign alert_en_shadowed_34_re = addr_hit[103] & reg_re & !reg_error; - assign alert_en_shadowed_34_we = addr_hit[103] & reg_we & !reg_error; + assign alert_en_shadowed_34_re = addr_hit[105] & reg_re & !reg_error; + assign alert_en_shadowed_34_we = addr_hit[105] & reg_we & !reg_error; assign alert_en_shadowed_34_wd = reg_wdata[0]; - assign alert_en_shadowed_35_re = addr_hit[104] & reg_re & !reg_error; - assign alert_en_shadowed_35_we = addr_hit[104] & reg_we & !reg_error; + assign alert_en_shadowed_35_re = addr_hit[106] & reg_re & !reg_error; + assign alert_en_shadowed_35_we = addr_hit[106] & reg_we & !reg_error; assign alert_en_shadowed_35_wd = reg_wdata[0]; - assign alert_en_shadowed_36_re = addr_hit[105] & reg_re & !reg_error; - assign alert_en_shadowed_36_we = addr_hit[105] & reg_we & !reg_error; + assign alert_en_shadowed_36_re = addr_hit[107] & reg_re & !reg_error; + assign alert_en_shadowed_36_we = addr_hit[107] & reg_we & !reg_error; assign alert_en_shadowed_36_wd = reg_wdata[0]; - assign alert_en_shadowed_37_re = addr_hit[106] & reg_re & !reg_error; - assign alert_en_shadowed_37_we = addr_hit[106] & reg_we & !reg_error; + assign alert_en_shadowed_37_re = addr_hit[108] & reg_re & !reg_error; + assign alert_en_shadowed_37_we = addr_hit[108] & reg_we & !reg_error; assign alert_en_shadowed_37_wd = reg_wdata[0]; - assign alert_en_shadowed_38_re = addr_hit[107] & reg_re & !reg_error; - assign alert_en_shadowed_38_we = addr_hit[107] & reg_we & !reg_error; + assign alert_en_shadowed_38_re = addr_hit[109] & reg_re & !reg_error; + assign alert_en_shadowed_38_we = addr_hit[109] & reg_we & !reg_error; assign alert_en_shadowed_38_wd = reg_wdata[0]; - assign alert_en_shadowed_39_re = addr_hit[108] & reg_re & !reg_error; - assign alert_en_shadowed_39_we = addr_hit[108] & reg_we & !reg_error; + assign alert_en_shadowed_39_re = addr_hit[110] & reg_re & !reg_error; + assign alert_en_shadowed_39_we = addr_hit[110] & reg_we & !reg_error; assign alert_en_shadowed_39_wd = reg_wdata[0]; - assign alert_en_shadowed_40_re = addr_hit[109] & reg_re & !reg_error; - assign alert_en_shadowed_40_we = addr_hit[109] & reg_we & !reg_error; + assign alert_en_shadowed_40_re = addr_hit[111] & reg_re & !reg_error; + assign alert_en_shadowed_40_we = addr_hit[111] & reg_we & !reg_error; assign alert_en_shadowed_40_wd = reg_wdata[0]; - assign alert_en_shadowed_41_re = addr_hit[110] & reg_re & !reg_error; - assign alert_en_shadowed_41_we = addr_hit[110] & reg_we & !reg_error; + assign alert_en_shadowed_41_re = addr_hit[112] & reg_re & !reg_error; + assign alert_en_shadowed_41_we = addr_hit[112] & reg_we & !reg_error; assign alert_en_shadowed_41_wd = reg_wdata[0]; - assign alert_en_shadowed_42_re = addr_hit[111] & reg_re & !reg_error; - assign alert_en_shadowed_42_we = addr_hit[111] & reg_we & !reg_error; + assign alert_en_shadowed_42_re = addr_hit[113] & reg_re & !reg_error; + assign alert_en_shadowed_42_we = addr_hit[113] & reg_we & !reg_error; assign alert_en_shadowed_42_wd = reg_wdata[0]; - assign alert_en_shadowed_43_re = addr_hit[112] & reg_re & !reg_error; - assign alert_en_shadowed_43_we = addr_hit[112] & reg_we & !reg_error; + assign alert_en_shadowed_43_re = addr_hit[114] & reg_re & !reg_error; + assign alert_en_shadowed_43_we = addr_hit[114] & reg_we & !reg_error; assign alert_en_shadowed_43_wd = reg_wdata[0]; - assign alert_en_shadowed_44_re = addr_hit[113] & reg_re & !reg_error; - assign alert_en_shadowed_44_we = addr_hit[113] & reg_we & !reg_error; + assign alert_en_shadowed_44_re = addr_hit[115] & reg_re & !reg_error; + assign alert_en_shadowed_44_we = addr_hit[115] & reg_we & !reg_error; assign alert_en_shadowed_44_wd = reg_wdata[0]; - assign alert_en_shadowed_45_re = addr_hit[114] & reg_re & !reg_error; - assign alert_en_shadowed_45_we = addr_hit[114] & reg_we & !reg_error; + assign alert_en_shadowed_45_re = addr_hit[116] & reg_re & !reg_error; + assign alert_en_shadowed_45_we = addr_hit[116] & reg_we & !reg_error; assign alert_en_shadowed_45_wd = reg_wdata[0]; - assign alert_en_shadowed_46_re = addr_hit[115] & reg_re & !reg_error; - assign alert_en_shadowed_46_we = addr_hit[115] & reg_we & !reg_error; + assign alert_en_shadowed_46_re = addr_hit[117] & reg_re & !reg_error; + assign alert_en_shadowed_46_we = addr_hit[117] & reg_we & !reg_error; assign alert_en_shadowed_46_wd = reg_wdata[0]; - assign alert_en_shadowed_47_re = addr_hit[116] & reg_re & !reg_error; - assign alert_en_shadowed_47_we = addr_hit[116] & reg_we & !reg_error; + assign alert_en_shadowed_47_re = addr_hit[118] & reg_re & !reg_error; + assign alert_en_shadowed_47_we = addr_hit[118] & reg_we & !reg_error; assign alert_en_shadowed_47_wd = reg_wdata[0]; - assign alert_en_shadowed_48_re = addr_hit[117] & reg_re & !reg_error; - assign alert_en_shadowed_48_we = addr_hit[117] & reg_we & !reg_error; + assign alert_en_shadowed_48_re = addr_hit[119] & reg_re & !reg_error; + assign alert_en_shadowed_48_we = addr_hit[119] & reg_we & !reg_error; assign alert_en_shadowed_48_wd = reg_wdata[0]; - assign alert_en_shadowed_49_re = addr_hit[118] & reg_re & !reg_error; - assign alert_en_shadowed_49_we = addr_hit[118] & reg_we & !reg_error; + assign alert_en_shadowed_49_re = addr_hit[120] & reg_re & !reg_error; + assign alert_en_shadowed_49_we = addr_hit[120] & reg_we & !reg_error; assign alert_en_shadowed_49_wd = reg_wdata[0]; - assign alert_en_shadowed_50_re = addr_hit[119] & reg_re & !reg_error; - assign alert_en_shadowed_50_we = addr_hit[119] & reg_we & !reg_error; + assign alert_en_shadowed_50_re = addr_hit[121] & reg_re & !reg_error; + assign alert_en_shadowed_50_we = addr_hit[121] & reg_we & !reg_error; assign alert_en_shadowed_50_wd = reg_wdata[0]; - assign alert_en_shadowed_51_re = addr_hit[120] & reg_re & !reg_error; - assign alert_en_shadowed_51_we = addr_hit[120] & reg_we & !reg_error; + assign alert_en_shadowed_51_re = addr_hit[122] & reg_re & !reg_error; + assign alert_en_shadowed_51_we = addr_hit[122] & reg_we & !reg_error; assign alert_en_shadowed_51_wd = reg_wdata[0]; - assign alert_en_shadowed_52_re = addr_hit[121] & reg_re & !reg_error; - assign alert_en_shadowed_52_we = addr_hit[121] & reg_we & !reg_error; + assign alert_en_shadowed_52_re = addr_hit[123] & reg_re & !reg_error; + assign alert_en_shadowed_52_we = addr_hit[123] & reg_we & !reg_error; assign alert_en_shadowed_52_wd = reg_wdata[0]; - assign alert_en_shadowed_53_re = addr_hit[122] & reg_re & !reg_error; - assign alert_en_shadowed_53_we = addr_hit[122] & reg_we & !reg_error; + assign alert_en_shadowed_53_re = addr_hit[124] & reg_re & !reg_error; + assign alert_en_shadowed_53_we = addr_hit[124] & reg_we & !reg_error; assign alert_en_shadowed_53_wd = reg_wdata[0]; - assign alert_en_shadowed_54_re = addr_hit[123] & reg_re & !reg_error; - assign alert_en_shadowed_54_we = addr_hit[123] & reg_we & !reg_error; + assign alert_en_shadowed_54_re = addr_hit[125] & reg_re & !reg_error; + assign alert_en_shadowed_54_we = addr_hit[125] & reg_we & !reg_error; assign alert_en_shadowed_54_wd = reg_wdata[0]; - assign alert_en_shadowed_55_re = addr_hit[124] & reg_re & !reg_error; - assign alert_en_shadowed_55_we = addr_hit[124] & reg_we & !reg_error; + assign alert_en_shadowed_55_re = addr_hit[126] & reg_re & !reg_error; + assign alert_en_shadowed_55_we = addr_hit[126] & reg_we & !reg_error; assign alert_en_shadowed_55_wd = reg_wdata[0]; - assign alert_en_shadowed_56_re = addr_hit[125] & reg_re & !reg_error; - assign alert_en_shadowed_56_we = addr_hit[125] & reg_we & !reg_error; + assign alert_en_shadowed_56_re = addr_hit[127] & reg_re & !reg_error; + assign alert_en_shadowed_56_we = addr_hit[127] & reg_we & !reg_error; assign alert_en_shadowed_56_wd = reg_wdata[0]; - assign alert_en_shadowed_57_re = addr_hit[126] & reg_re & !reg_error; - assign alert_en_shadowed_57_we = addr_hit[126] & reg_we & !reg_error; + assign alert_en_shadowed_57_re = addr_hit[128] & reg_re & !reg_error; + assign alert_en_shadowed_57_we = addr_hit[128] & reg_we & !reg_error; assign alert_en_shadowed_57_wd = reg_wdata[0]; - assign alert_en_shadowed_58_re = addr_hit[127] & reg_re & !reg_error; - assign alert_en_shadowed_58_we = addr_hit[127] & reg_we & !reg_error; + assign alert_en_shadowed_58_re = addr_hit[129] & reg_re & !reg_error; + assign alert_en_shadowed_58_we = addr_hit[129] & reg_we & !reg_error; assign alert_en_shadowed_58_wd = reg_wdata[0]; - assign alert_en_shadowed_59_re = addr_hit[128] & reg_re & !reg_error; - assign alert_en_shadowed_59_we = addr_hit[128] & reg_we & !reg_error; + assign alert_en_shadowed_59_re = addr_hit[130] & reg_re & !reg_error; + assign alert_en_shadowed_59_we = addr_hit[130] & reg_we & !reg_error; assign alert_en_shadowed_59_wd = reg_wdata[0]; - assign alert_en_shadowed_60_re = addr_hit[129] & reg_re & !reg_error; - assign alert_en_shadowed_60_we = addr_hit[129] & reg_we & !reg_error; + assign alert_en_shadowed_60_re = addr_hit[131] & reg_re & !reg_error; + assign alert_en_shadowed_60_we = addr_hit[131] & reg_we & !reg_error; assign alert_en_shadowed_60_wd = reg_wdata[0]; - assign alert_en_shadowed_61_re = addr_hit[130] & reg_re & !reg_error; - assign alert_en_shadowed_61_we = addr_hit[130] & reg_we & !reg_error; + assign alert_en_shadowed_61_re = addr_hit[132] & reg_re & !reg_error; + assign alert_en_shadowed_61_we = addr_hit[132] & reg_we & !reg_error; assign alert_en_shadowed_61_wd = reg_wdata[0]; - assign alert_en_shadowed_62_re = addr_hit[131] & reg_re & !reg_error; - assign alert_en_shadowed_62_we = addr_hit[131] & reg_we & !reg_error; + assign alert_en_shadowed_62_re = addr_hit[133] & reg_re & !reg_error; + assign alert_en_shadowed_62_we = addr_hit[133] & reg_we & !reg_error; assign alert_en_shadowed_62_wd = reg_wdata[0]; - assign alert_class_shadowed_0_re = addr_hit[132] & reg_re & !reg_error; - assign alert_class_shadowed_0_we = addr_hit[132] & reg_we & !reg_error; + assign alert_en_shadowed_63_re = addr_hit[134] & reg_re & !reg_error; + assign alert_en_shadowed_63_we = addr_hit[134] & reg_we & !reg_error; + + assign alert_en_shadowed_63_wd = reg_wdata[0]; + assign alert_en_shadowed_64_re = addr_hit[135] & reg_re & !reg_error; + assign alert_en_shadowed_64_we = addr_hit[135] & reg_we & !reg_error; + + assign alert_en_shadowed_64_wd = reg_wdata[0]; + assign alert_class_shadowed_0_re = addr_hit[136] & reg_re & !reg_error; + assign alert_class_shadowed_0_we = addr_hit[136] & reg_we & !reg_error; assign alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign alert_class_shadowed_1_re = addr_hit[133] & reg_re & !reg_error; - assign alert_class_shadowed_1_we = addr_hit[133] & reg_we & !reg_error; + assign alert_class_shadowed_1_re = addr_hit[137] & reg_re & !reg_error; + assign alert_class_shadowed_1_we = addr_hit[137] & reg_we & !reg_error; assign alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign alert_class_shadowed_2_re = addr_hit[134] & reg_re & !reg_error; - assign alert_class_shadowed_2_we = addr_hit[134] & reg_we & !reg_error; + assign alert_class_shadowed_2_re = addr_hit[138] & reg_re & !reg_error; + assign alert_class_shadowed_2_we = addr_hit[138] & reg_we & !reg_error; assign alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign alert_class_shadowed_3_re = addr_hit[135] & reg_re & !reg_error; - assign alert_class_shadowed_3_we = addr_hit[135] & reg_we & !reg_error; + assign alert_class_shadowed_3_re = addr_hit[139] & reg_re & !reg_error; + assign alert_class_shadowed_3_we = addr_hit[139] & reg_we & !reg_error; assign alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign alert_class_shadowed_4_re = addr_hit[136] & reg_re & !reg_error; - assign alert_class_shadowed_4_we = addr_hit[136] & reg_we & !reg_error; + assign alert_class_shadowed_4_re = addr_hit[140] & reg_re & !reg_error; + assign alert_class_shadowed_4_we = addr_hit[140] & reg_we & !reg_error; assign alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign alert_class_shadowed_5_re = addr_hit[137] & reg_re & !reg_error; - assign alert_class_shadowed_5_we = addr_hit[137] & reg_we & !reg_error; + assign alert_class_shadowed_5_re = addr_hit[141] & reg_re & !reg_error; + assign alert_class_shadowed_5_we = addr_hit[141] & reg_we & !reg_error; assign alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign alert_class_shadowed_6_re = addr_hit[138] & reg_re & !reg_error; - assign alert_class_shadowed_6_we = addr_hit[138] & reg_we & !reg_error; + assign alert_class_shadowed_6_re = addr_hit[142] & reg_re & !reg_error; + assign alert_class_shadowed_6_we = addr_hit[142] & reg_we & !reg_error; assign alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign alert_class_shadowed_7_re = addr_hit[139] & reg_re & !reg_error; - assign alert_class_shadowed_7_we = addr_hit[139] & reg_we & !reg_error; + assign alert_class_shadowed_7_re = addr_hit[143] & reg_re & !reg_error; + assign alert_class_shadowed_7_we = addr_hit[143] & reg_we & !reg_error; assign alert_class_shadowed_7_wd = reg_wdata[1:0]; - assign alert_class_shadowed_8_re = addr_hit[140] & reg_re & !reg_error; - assign alert_class_shadowed_8_we = addr_hit[140] & reg_we & !reg_error; + assign alert_class_shadowed_8_re = addr_hit[144] & reg_re & !reg_error; + assign alert_class_shadowed_8_we = addr_hit[144] & reg_we & !reg_error; assign alert_class_shadowed_8_wd = reg_wdata[1:0]; - assign alert_class_shadowed_9_re = addr_hit[141] & reg_re & !reg_error; - assign alert_class_shadowed_9_we = addr_hit[141] & reg_we & !reg_error; + assign alert_class_shadowed_9_re = addr_hit[145] & reg_re & !reg_error; + assign alert_class_shadowed_9_we = addr_hit[145] & reg_we & !reg_error; assign alert_class_shadowed_9_wd = reg_wdata[1:0]; - assign alert_class_shadowed_10_re = addr_hit[142] & reg_re & !reg_error; - assign alert_class_shadowed_10_we = addr_hit[142] & reg_we & !reg_error; + assign alert_class_shadowed_10_re = addr_hit[146] & reg_re & !reg_error; + assign alert_class_shadowed_10_we = addr_hit[146] & reg_we & !reg_error; assign alert_class_shadowed_10_wd = reg_wdata[1:0]; - assign alert_class_shadowed_11_re = addr_hit[143] & reg_re & !reg_error; - assign alert_class_shadowed_11_we = addr_hit[143] & reg_we & !reg_error; + assign alert_class_shadowed_11_re = addr_hit[147] & reg_re & !reg_error; + assign alert_class_shadowed_11_we = addr_hit[147] & reg_we & !reg_error; assign alert_class_shadowed_11_wd = reg_wdata[1:0]; - assign alert_class_shadowed_12_re = addr_hit[144] & reg_re & !reg_error; - assign alert_class_shadowed_12_we = addr_hit[144] & reg_we & !reg_error; + assign alert_class_shadowed_12_re = addr_hit[148] & reg_re & !reg_error; + assign alert_class_shadowed_12_we = addr_hit[148] & reg_we & !reg_error; assign alert_class_shadowed_12_wd = reg_wdata[1:0]; - assign alert_class_shadowed_13_re = addr_hit[145] & reg_re & !reg_error; - assign alert_class_shadowed_13_we = addr_hit[145] & reg_we & !reg_error; + assign alert_class_shadowed_13_re = addr_hit[149] & reg_re & !reg_error; + assign alert_class_shadowed_13_we = addr_hit[149] & reg_we & !reg_error; assign alert_class_shadowed_13_wd = reg_wdata[1:0]; - assign alert_class_shadowed_14_re = addr_hit[146] & reg_re & !reg_error; - assign alert_class_shadowed_14_we = addr_hit[146] & reg_we & !reg_error; + assign alert_class_shadowed_14_re = addr_hit[150] & reg_re & !reg_error; + assign alert_class_shadowed_14_we = addr_hit[150] & reg_we & !reg_error; assign alert_class_shadowed_14_wd = reg_wdata[1:0]; - assign alert_class_shadowed_15_re = addr_hit[147] & reg_re & !reg_error; - assign alert_class_shadowed_15_we = addr_hit[147] & reg_we & !reg_error; + assign alert_class_shadowed_15_re = addr_hit[151] & reg_re & !reg_error; + assign alert_class_shadowed_15_we = addr_hit[151] & reg_we & !reg_error; assign alert_class_shadowed_15_wd = reg_wdata[1:0]; - assign alert_class_shadowed_16_re = addr_hit[148] & reg_re & !reg_error; - assign alert_class_shadowed_16_we = addr_hit[148] & reg_we & !reg_error; + assign alert_class_shadowed_16_re = addr_hit[152] & reg_re & !reg_error; + assign alert_class_shadowed_16_we = addr_hit[152] & reg_we & !reg_error; assign alert_class_shadowed_16_wd = reg_wdata[1:0]; - assign alert_class_shadowed_17_re = addr_hit[149] & reg_re & !reg_error; - assign alert_class_shadowed_17_we = addr_hit[149] & reg_we & !reg_error; + assign alert_class_shadowed_17_re = addr_hit[153] & reg_re & !reg_error; + assign alert_class_shadowed_17_we = addr_hit[153] & reg_we & !reg_error; assign alert_class_shadowed_17_wd = reg_wdata[1:0]; - assign alert_class_shadowed_18_re = addr_hit[150] & reg_re & !reg_error; - assign alert_class_shadowed_18_we = addr_hit[150] & reg_we & !reg_error; + assign alert_class_shadowed_18_re = addr_hit[154] & reg_re & !reg_error; + assign alert_class_shadowed_18_we = addr_hit[154] & reg_we & !reg_error; assign alert_class_shadowed_18_wd = reg_wdata[1:0]; - assign alert_class_shadowed_19_re = addr_hit[151] & reg_re & !reg_error; - assign alert_class_shadowed_19_we = addr_hit[151] & reg_we & !reg_error; + assign alert_class_shadowed_19_re = addr_hit[155] & reg_re & !reg_error; + assign alert_class_shadowed_19_we = addr_hit[155] & reg_we & !reg_error; assign alert_class_shadowed_19_wd = reg_wdata[1:0]; - assign alert_class_shadowed_20_re = addr_hit[152] & reg_re & !reg_error; - assign alert_class_shadowed_20_we = addr_hit[152] & reg_we & !reg_error; + assign alert_class_shadowed_20_re = addr_hit[156] & reg_re & !reg_error; + assign alert_class_shadowed_20_we = addr_hit[156] & reg_we & !reg_error; assign alert_class_shadowed_20_wd = reg_wdata[1:0]; - assign alert_class_shadowed_21_re = addr_hit[153] & reg_re & !reg_error; - assign alert_class_shadowed_21_we = addr_hit[153] & reg_we & !reg_error; + assign alert_class_shadowed_21_re = addr_hit[157] & reg_re & !reg_error; + assign alert_class_shadowed_21_we = addr_hit[157] & reg_we & !reg_error; assign alert_class_shadowed_21_wd = reg_wdata[1:0]; - assign alert_class_shadowed_22_re = addr_hit[154] & reg_re & !reg_error; - assign alert_class_shadowed_22_we = addr_hit[154] & reg_we & !reg_error; + assign alert_class_shadowed_22_re = addr_hit[158] & reg_re & !reg_error; + assign alert_class_shadowed_22_we = addr_hit[158] & reg_we & !reg_error; assign alert_class_shadowed_22_wd = reg_wdata[1:0]; - assign alert_class_shadowed_23_re = addr_hit[155] & reg_re & !reg_error; - assign alert_class_shadowed_23_we = addr_hit[155] & reg_we & !reg_error; + assign alert_class_shadowed_23_re = addr_hit[159] & reg_re & !reg_error; + assign alert_class_shadowed_23_we = addr_hit[159] & reg_we & !reg_error; assign alert_class_shadowed_23_wd = reg_wdata[1:0]; - assign alert_class_shadowed_24_re = addr_hit[156] & reg_re & !reg_error; - assign alert_class_shadowed_24_we = addr_hit[156] & reg_we & !reg_error; + assign alert_class_shadowed_24_re = addr_hit[160] & reg_re & !reg_error; + assign alert_class_shadowed_24_we = addr_hit[160] & reg_we & !reg_error; assign alert_class_shadowed_24_wd = reg_wdata[1:0]; - assign alert_class_shadowed_25_re = addr_hit[157] & reg_re & !reg_error; - assign alert_class_shadowed_25_we = addr_hit[157] & reg_we & !reg_error; + assign alert_class_shadowed_25_re = addr_hit[161] & reg_re & !reg_error; + assign alert_class_shadowed_25_we = addr_hit[161] & reg_we & !reg_error; assign alert_class_shadowed_25_wd = reg_wdata[1:0]; - assign alert_class_shadowed_26_re = addr_hit[158] & reg_re & !reg_error; - assign alert_class_shadowed_26_we = addr_hit[158] & reg_we & !reg_error; + assign alert_class_shadowed_26_re = addr_hit[162] & reg_re & !reg_error; + assign alert_class_shadowed_26_we = addr_hit[162] & reg_we & !reg_error; assign alert_class_shadowed_26_wd = reg_wdata[1:0]; - assign alert_class_shadowed_27_re = addr_hit[159] & reg_re & !reg_error; - assign alert_class_shadowed_27_we = addr_hit[159] & reg_we & !reg_error; + assign alert_class_shadowed_27_re = addr_hit[163] & reg_re & !reg_error; + assign alert_class_shadowed_27_we = addr_hit[163] & reg_we & !reg_error; assign alert_class_shadowed_27_wd = reg_wdata[1:0]; - assign alert_class_shadowed_28_re = addr_hit[160] & reg_re & !reg_error; - assign alert_class_shadowed_28_we = addr_hit[160] & reg_we & !reg_error; + assign alert_class_shadowed_28_re = addr_hit[164] & reg_re & !reg_error; + assign alert_class_shadowed_28_we = addr_hit[164] & reg_we & !reg_error; assign alert_class_shadowed_28_wd = reg_wdata[1:0]; - assign alert_class_shadowed_29_re = addr_hit[161] & reg_re & !reg_error; - assign alert_class_shadowed_29_we = addr_hit[161] & reg_we & !reg_error; + assign alert_class_shadowed_29_re = addr_hit[165] & reg_re & !reg_error; + assign alert_class_shadowed_29_we = addr_hit[165] & reg_we & !reg_error; assign alert_class_shadowed_29_wd = reg_wdata[1:0]; - assign alert_class_shadowed_30_re = addr_hit[162] & reg_re & !reg_error; - assign alert_class_shadowed_30_we = addr_hit[162] & reg_we & !reg_error; + assign alert_class_shadowed_30_re = addr_hit[166] & reg_re & !reg_error; + assign alert_class_shadowed_30_we = addr_hit[166] & reg_we & !reg_error; assign alert_class_shadowed_30_wd = reg_wdata[1:0]; - assign alert_class_shadowed_31_re = addr_hit[163] & reg_re & !reg_error; - assign alert_class_shadowed_31_we = addr_hit[163] & reg_we & !reg_error; + assign alert_class_shadowed_31_re = addr_hit[167] & reg_re & !reg_error; + assign alert_class_shadowed_31_we = addr_hit[167] & reg_we & !reg_error; assign alert_class_shadowed_31_wd = reg_wdata[1:0]; - assign alert_class_shadowed_32_re = addr_hit[164] & reg_re & !reg_error; - assign alert_class_shadowed_32_we = addr_hit[164] & reg_we & !reg_error; + assign alert_class_shadowed_32_re = addr_hit[168] & reg_re & !reg_error; + assign alert_class_shadowed_32_we = addr_hit[168] & reg_we & !reg_error; assign alert_class_shadowed_32_wd = reg_wdata[1:0]; - assign alert_class_shadowed_33_re = addr_hit[165] & reg_re & !reg_error; - assign alert_class_shadowed_33_we = addr_hit[165] & reg_we & !reg_error; + assign alert_class_shadowed_33_re = addr_hit[169] & reg_re & !reg_error; + assign alert_class_shadowed_33_we = addr_hit[169] & reg_we & !reg_error; assign alert_class_shadowed_33_wd = reg_wdata[1:0]; - assign alert_class_shadowed_34_re = addr_hit[166] & reg_re & !reg_error; - assign alert_class_shadowed_34_we = addr_hit[166] & reg_we & !reg_error; + assign alert_class_shadowed_34_re = addr_hit[170] & reg_re & !reg_error; + assign alert_class_shadowed_34_we = addr_hit[170] & reg_we & !reg_error; assign alert_class_shadowed_34_wd = reg_wdata[1:0]; - assign alert_class_shadowed_35_re = addr_hit[167] & reg_re & !reg_error; - assign alert_class_shadowed_35_we = addr_hit[167] & reg_we & !reg_error; + assign alert_class_shadowed_35_re = addr_hit[171] & reg_re & !reg_error; + assign alert_class_shadowed_35_we = addr_hit[171] & reg_we & !reg_error; assign alert_class_shadowed_35_wd = reg_wdata[1:0]; - assign alert_class_shadowed_36_re = addr_hit[168] & reg_re & !reg_error; - assign alert_class_shadowed_36_we = addr_hit[168] & reg_we & !reg_error; + assign alert_class_shadowed_36_re = addr_hit[172] & reg_re & !reg_error; + assign alert_class_shadowed_36_we = addr_hit[172] & reg_we & !reg_error; assign alert_class_shadowed_36_wd = reg_wdata[1:0]; - assign alert_class_shadowed_37_re = addr_hit[169] & reg_re & !reg_error; - assign alert_class_shadowed_37_we = addr_hit[169] & reg_we & !reg_error; + assign alert_class_shadowed_37_re = addr_hit[173] & reg_re & !reg_error; + assign alert_class_shadowed_37_we = addr_hit[173] & reg_we & !reg_error; assign alert_class_shadowed_37_wd = reg_wdata[1:0]; - assign alert_class_shadowed_38_re = addr_hit[170] & reg_re & !reg_error; - assign alert_class_shadowed_38_we = addr_hit[170] & reg_we & !reg_error; + assign alert_class_shadowed_38_re = addr_hit[174] & reg_re & !reg_error; + assign alert_class_shadowed_38_we = addr_hit[174] & reg_we & !reg_error; assign alert_class_shadowed_38_wd = reg_wdata[1:0]; - assign alert_class_shadowed_39_re = addr_hit[171] & reg_re & !reg_error; - assign alert_class_shadowed_39_we = addr_hit[171] & reg_we & !reg_error; + assign alert_class_shadowed_39_re = addr_hit[175] & reg_re & !reg_error; + assign alert_class_shadowed_39_we = addr_hit[175] & reg_we & !reg_error; assign alert_class_shadowed_39_wd = reg_wdata[1:0]; - assign alert_class_shadowed_40_re = addr_hit[172] & reg_re & !reg_error; - assign alert_class_shadowed_40_we = addr_hit[172] & reg_we & !reg_error; + assign alert_class_shadowed_40_re = addr_hit[176] & reg_re & !reg_error; + assign alert_class_shadowed_40_we = addr_hit[176] & reg_we & !reg_error; assign alert_class_shadowed_40_wd = reg_wdata[1:0]; - assign alert_class_shadowed_41_re = addr_hit[173] & reg_re & !reg_error; - assign alert_class_shadowed_41_we = addr_hit[173] & reg_we & !reg_error; + assign alert_class_shadowed_41_re = addr_hit[177] & reg_re & !reg_error; + assign alert_class_shadowed_41_we = addr_hit[177] & reg_we & !reg_error; assign alert_class_shadowed_41_wd = reg_wdata[1:0]; - assign alert_class_shadowed_42_re = addr_hit[174] & reg_re & !reg_error; - assign alert_class_shadowed_42_we = addr_hit[174] & reg_we & !reg_error; + assign alert_class_shadowed_42_re = addr_hit[178] & reg_re & !reg_error; + assign alert_class_shadowed_42_we = addr_hit[178] & reg_we & !reg_error; assign alert_class_shadowed_42_wd = reg_wdata[1:0]; - assign alert_class_shadowed_43_re = addr_hit[175] & reg_re & !reg_error; - assign alert_class_shadowed_43_we = addr_hit[175] & reg_we & !reg_error; + assign alert_class_shadowed_43_re = addr_hit[179] & reg_re & !reg_error; + assign alert_class_shadowed_43_we = addr_hit[179] & reg_we & !reg_error; assign alert_class_shadowed_43_wd = reg_wdata[1:0]; - assign alert_class_shadowed_44_re = addr_hit[176] & reg_re & !reg_error; - assign alert_class_shadowed_44_we = addr_hit[176] & reg_we & !reg_error; + assign alert_class_shadowed_44_re = addr_hit[180] & reg_re & !reg_error; + assign alert_class_shadowed_44_we = addr_hit[180] & reg_we & !reg_error; assign alert_class_shadowed_44_wd = reg_wdata[1:0]; - assign alert_class_shadowed_45_re = addr_hit[177] & reg_re & !reg_error; - assign alert_class_shadowed_45_we = addr_hit[177] & reg_we & !reg_error; + assign alert_class_shadowed_45_re = addr_hit[181] & reg_re & !reg_error; + assign alert_class_shadowed_45_we = addr_hit[181] & reg_we & !reg_error; assign alert_class_shadowed_45_wd = reg_wdata[1:0]; - assign alert_class_shadowed_46_re = addr_hit[178] & reg_re & !reg_error; - assign alert_class_shadowed_46_we = addr_hit[178] & reg_we & !reg_error; + assign alert_class_shadowed_46_re = addr_hit[182] & reg_re & !reg_error; + assign alert_class_shadowed_46_we = addr_hit[182] & reg_we & !reg_error; assign alert_class_shadowed_46_wd = reg_wdata[1:0]; - assign alert_class_shadowed_47_re = addr_hit[179] & reg_re & !reg_error; - assign alert_class_shadowed_47_we = addr_hit[179] & reg_we & !reg_error; + assign alert_class_shadowed_47_re = addr_hit[183] & reg_re & !reg_error; + assign alert_class_shadowed_47_we = addr_hit[183] & reg_we & !reg_error; assign alert_class_shadowed_47_wd = reg_wdata[1:0]; - assign alert_class_shadowed_48_re = addr_hit[180] & reg_re & !reg_error; - assign alert_class_shadowed_48_we = addr_hit[180] & reg_we & !reg_error; + assign alert_class_shadowed_48_re = addr_hit[184] & reg_re & !reg_error; + assign alert_class_shadowed_48_we = addr_hit[184] & reg_we & !reg_error; assign alert_class_shadowed_48_wd = reg_wdata[1:0]; - assign alert_class_shadowed_49_re = addr_hit[181] & reg_re & !reg_error; - assign alert_class_shadowed_49_we = addr_hit[181] & reg_we & !reg_error; + assign alert_class_shadowed_49_re = addr_hit[185] & reg_re & !reg_error; + assign alert_class_shadowed_49_we = addr_hit[185] & reg_we & !reg_error; assign alert_class_shadowed_49_wd = reg_wdata[1:0]; - assign alert_class_shadowed_50_re = addr_hit[182] & reg_re & !reg_error; - assign alert_class_shadowed_50_we = addr_hit[182] & reg_we & !reg_error; + assign alert_class_shadowed_50_re = addr_hit[186] & reg_re & !reg_error; + assign alert_class_shadowed_50_we = addr_hit[186] & reg_we & !reg_error; assign alert_class_shadowed_50_wd = reg_wdata[1:0]; - assign alert_class_shadowed_51_re = addr_hit[183] & reg_re & !reg_error; - assign alert_class_shadowed_51_we = addr_hit[183] & reg_we & !reg_error; + assign alert_class_shadowed_51_re = addr_hit[187] & reg_re & !reg_error; + assign alert_class_shadowed_51_we = addr_hit[187] & reg_we & !reg_error; assign alert_class_shadowed_51_wd = reg_wdata[1:0]; - assign alert_class_shadowed_52_re = addr_hit[184] & reg_re & !reg_error; - assign alert_class_shadowed_52_we = addr_hit[184] & reg_we & !reg_error; + assign alert_class_shadowed_52_re = addr_hit[188] & reg_re & !reg_error; + assign alert_class_shadowed_52_we = addr_hit[188] & reg_we & !reg_error; assign alert_class_shadowed_52_wd = reg_wdata[1:0]; - assign alert_class_shadowed_53_re = addr_hit[185] & reg_re & !reg_error; - assign alert_class_shadowed_53_we = addr_hit[185] & reg_we & !reg_error; + assign alert_class_shadowed_53_re = addr_hit[189] & reg_re & !reg_error; + assign alert_class_shadowed_53_we = addr_hit[189] & reg_we & !reg_error; assign alert_class_shadowed_53_wd = reg_wdata[1:0]; - assign alert_class_shadowed_54_re = addr_hit[186] & reg_re & !reg_error; - assign alert_class_shadowed_54_we = addr_hit[186] & reg_we & !reg_error; + assign alert_class_shadowed_54_re = addr_hit[190] & reg_re & !reg_error; + assign alert_class_shadowed_54_we = addr_hit[190] & reg_we & !reg_error; assign alert_class_shadowed_54_wd = reg_wdata[1:0]; - assign alert_class_shadowed_55_re = addr_hit[187] & reg_re & !reg_error; - assign alert_class_shadowed_55_we = addr_hit[187] & reg_we & !reg_error; + assign alert_class_shadowed_55_re = addr_hit[191] & reg_re & !reg_error; + assign alert_class_shadowed_55_we = addr_hit[191] & reg_we & !reg_error; assign alert_class_shadowed_55_wd = reg_wdata[1:0]; - assign alert_class_shadowed_56_re = addr_hit[188] & reg_re & !reg_error; - assign alert_class_shadowed_56_we = addr_hit[188] & reg_we & !reg_error; + assign alert_class_shadowed_56_re = addr_hit[192] & reg_re & !reg_error; + assign alert_class_shadowed_56_we = addr_hit[192] & reg_we & !reg_error; assign alert_class_shadowed_56_wd = reg_wdata[1:0]; - assign alert_class_shadowed_57_re = addr_hit[189] & reg_re & !reg_error; - assign alert_class_shadowed_57_we = addr_hit[189] & reg_we & !reg_error; + assign alert_class_shadowed_57_re = addr_hit[193] & reg_re & !reg_error; + assign alert_class_shadowed_57_we = addr_hit[193] & reg_we & !reg_error; assign alert_class_shadowed_57_wd = reg_wdata[1:0]; - assign alert_class_shadowed_58_re = addr_hit[190] & reg_re & !reg_error; - assign alert_class_shadowed_58_we = addr_hit[190] & reg_we & !reg_error; + assign alert_class_shadowed_58_re = addr_hit[194] & reg_re & !reg_error; + assign alert_class_shadowed_58_we = addr_hit[194] & reg_we & !reg_error; assign alert_class_shadowed_58_wd = reg_wdata[1:0]; - assign alert_class_shadowed_59_re = addr_hit[191] & reg_re & !reg_error; - assign alert_class_shadowed_59_we = addr_hit[191] & reg_we & !reg_error; + assign alert_class_shadowed_59_re = addr_hit[195] & reg_re & !reg_error; + assign alert_class_shadowed_59_we = addr_hit[195] & reg_we & !reg_error; assign alert_class_shadowed_59_wd = reg_wdata[1:0]; - assign alert_class_shadowed_60_re = addr_hit[192] & reg_re & !reg_error; - assign alert_class_shadowed_60_we = addr_hit[192] & reg_we & !reg_error; + assign alert_class_shadowed_60_re = addr_hit[196] & reg_re & !reg_error; + assign alert_class_shadowed_60_we = addr_hit[196] & reg_we & !reg_error; assign alert_class_shadowed_60_wd = reg_wdata[1:0]; - assign alert_class_shadowed_61_re = addr_hit[193] & reg_re & !reg_error; - assign alert_class_shadowed_61_we = addr_hit[193] & reg_we & !reg_error; + assign alert_class_shadowed_61_re = addr_hit[197] & reg_re & !reg_error; + assign alert_class_shadowed_61_we = addr_hit[197] & reg_we & !reg_error; assign alert_class_shadowed_61_wd = reg_wdata[1:0]; - assign alert_class_shadowed_62_re = addr_hit[194] & reg_re & !reg_error; - assign alert_class_shadowed_62_we = addr_hit[194] & reg_we & !reg_error; + assign alert_class_shadowed_62_re = addr_hit[198] & reg_re & !reg_error; + assign alert_class_shadowed_62_we = addr_hit[198] & reg_we & !reg_error; assign alert_class_shadowed_62_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[195] & reg_we & !reg_error; + assign alert_class_shadowed_63_re = addr_hit[199] & reg_re & !reg_error; + assign alert_class_shadowed_63_we = addr_hit[199] & reg_we & !reg_error; + + assign alert_class_shadowed_63_wd = reg_wdata[1:0]; + assign alert_class_shadowed_64_re = addr_hit[200] & reg_re & !reg_error; + assign alert_class_shadowed_64_we = addr_hit[200] & reg_we & !reg_error; + + assign alert_class_shadowed_64_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[201] & reg_we & !reg_error; assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[196] & reg_we & !reg_error; + assign alert_cause_1_we = addr_hit[202] & reg_we & !reg_error; assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[197] & reg_we & !reg_error; + assign alert_cause_2_we = addr_hit[203] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[198] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[204] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[199] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[205] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[200] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[206] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[201] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[207] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[202] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[208] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[203] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[209] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[204] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[210] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[205] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[211] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[206] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[212] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[207] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[213] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[208] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[214] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[209] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[215] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[210] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[216] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[211] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[217] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[212] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[218] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[213] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[219] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[214] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[220] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[215] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[221] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[216] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[222] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[217] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[223] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[218] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[224] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[219] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[225] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[220] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[226] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[221] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[227] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[222] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[228] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[223] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[229] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[224] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[230] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[225] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[231] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign alert_cause_31_we = addr_hit[226] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[232] & reg_we & !reg_error; assign alert_cause_31_wd = reg_wdata[0]; - assign alert_cause_32_we = addr_hit[227] & reg_we & !reg_error; + assign alert_cause_32_we = addr_hit[233] & reg_we & !reg_error; assign alert_cause_32_wd = reg_wdata[0]; - assign alert_cause_33_we = addr_hit[228] & reg_we & !reg_error; + assign alert_cause_33_we = addr_hit[234] & reg_we & !reg_error; assign alert_cause_33_wd = reg_wdata[0]; - assign alert_cause_34_we = addr_hit[229] & reg_we & !reg_error; + assign alert_cause_34_we = addr_hit[235] & reg_we & !reg_error; assign alert_cause_34_wd = reg_wdata[0]; - assign alert_cause_35_we = addr_hit[230] & reg_we & !reg_error; + assign alert_cause_35_we = addr_hit[236] & reg_we & !reg_error; assign alert_cause_35_wd = reg_wdata[0]; - assign alert_cause_36_we = addr_hit[231] & reg_we & !reg_error; + assign alert_cause_36_we = addr_hit[237] & reg_we & !reg_error; assign alert_cause_36_wd = reg_wdata[0]; - assign alert_cause_37_we = addr_hit[232] & reg_we & !reg_error; + assign alert_cause_37_we = addr_hit[238] & reg_we & !reg_error; assign alert_cause_37_wd = reg_wdata[0]; - assign alert_cause_38_we = addr_hit[233] & reg_we & !reg_error; + assign alert_cause_38_we = addr_hit[239] & reg_we & !reg_error; assign alert_cause_38_wd = reg_wdata[0]; - assign alert_cause_39_we = addr_hit[234] & reg_we & !reg_error; + assign alert_cause_39_we = addr_hit[240] & reg_we & !reg_error; assign alert_cause_39_wd = reg_wdata[0]; - assign alert_cause_40_we = addr_hit[235] & reg_we & !reg_error; + assign alert_cause_40_we = addr_hit[241] & reg_we & !reg_error; assign alert_cause_40_wd = reg_wdata[0]; - assign alert_cause_41_we = addr_hit[236] & reg_we & !reg_error; + assign alert_cause_41_we = addr_hit[242] & reg_we & !reg_error; assign alert_cause_41_wd = reg_wdata[0]; - assign alert_cause_42_we = addr_hit[237] & reg_we & !reg_error; + assign alert_cause_42_we = addr_hit[243] & reg_we & !reg_error; assign alert_cause_42_wd = reg_wdata[0]; - assign alert_cause_43_we = addr_hit[238] & reg_we & !reg_error; + assign alert_cause_43_we = addr_hit[244] & reg_we & !reg_error; assign alert_cause_43_wd = reg_wdata[0]; - assign alert_cause_44_we = addr_hit[239] & reg_we & !reg_error; + assign alert_cause_44_we = addr_hit[245] & reg_we & !reg_error; assign alert_cause_44_wd = reg_wdata[0]; - assign alert_cause_45_we = addr_hit[240] & reg_we & !reg_error; + assign alert_cause_45_we = addr_hit[246] & reg_we & !reg_error; assign alert_cause_45_wd = reg_wdata[0]; - assign alert_cause_46_we = addr_hit[241] & reg_we & !reg_error; + assign alert_cause_46_we = addr_hit[247] & reg_we & !reg_error; assign alert_cause_46_wd = reg_wdata[0]; - assign alert_cause_47_we = addr_hit[242] & reg_we & !reg_error; + assign alert_cause_47_we = addr_hit[248] & reg_we & !reg_error; assign alert_cause_47_wd = reg_wdata[0]; - assign alert_cause_48_we = addr_hit[243] & reg_we & !reg_error; + assign alert_cause_48_we = addr_hit[249] & reg_we & !reg_error; assign alert_cause_48_wd = reg_wdata[0]; - assign alert_cause_49_we = addr_hit[244] & reg_we & !reg_error; + assign alert_cause_49_we = addr_hit[250] & reg_we & !reg_error; assign alert_cause_49_wd = reg_wdata[0]; - assign alert_cause_50_we = addr_hit[245] & reg_we & !reg_error; + assign alert_cause_50_we = addr_hit[251] & reg_we & !reg_error; assign alert_cause_50_wd = reg_wdata[0]; - assign alert_cause_51_we = addr_hit[246] & reg_we & !reg_error; + assign alert_cause_51_we = addr_hit[252] & reg_we & !reg_error; assign alert_cause_51_wd = reg_wdata[0]; - assign alert_cause_52_we = addr_hit[247] & reg_we & !reg_error; + assign alert_cause_52_we = addr_hit[253] & reg_we & !reg_error; assign alert_cause_52_wd = reg_wdata[0]; - assign alert_cause_53_we = addr_hit[248] & reg_we & !reg_error; + assign alert_cause_53_we = addr_hit[254] & reg_we & !reg_error; assign alert_cause_53_wd = reg_wdata[0]; - assign alert_cause_54_we = addr_hit[249] & reg_we & !reg_error; + assign alert_cause_54_we = addr_hit[255] & reg_we & !reg_error; assign alert_cause_54_wd = reg_wdata[0]; - assign alert_cause_55_we = addr_hit[250] & reg_we & !reg_error; + assign alert_cause_55_we = addr_hit[256] & reg_we & !reg_error; assign alert_cause_55_wd = reg_wdata[0]; - assign alert_cause_56_we = addr_hit[251] & reg_we & !reg_error; + assign alert_cause_56_we = addr_hit[257] & reg_we & !reg_error; assign alert_cause_56_wd = reg_wdata[0]; - assign alert_cause_57_we = addr_hit[252] & reg_we & !reg_error; + assign alert_cause_57_we = addr_hit[258] & reg_we & !reg_error; assign alert_cause_57_wd = reg_wdata[0]; - assign alert_cause_58_we = addr_hit[253] & reg_we & !reg_error; + assign alert_cause_58_we = addr_hit[259] & reg_we & !reg_error; assign alert_cause_58_wd = reg_wdata[0]; - assign alert_cause_59_we = addr_hit[254] & reg_we & !reg_error; + assign alert_cause_59_we = addr_hit[260] & reg_we & !reg_error; assign alert_cause_59_wd = reg_wdata[0]; - assign alert_cause_60_we = addr_hit[255] & reg_we & !reg_error; + assign alert_cause_60_we = addr_hit[261] & reg_we & !reg_error; assign alert_cause_60_wd = reg_wdata[0]; - assign alert_cause_61_we = addr_hit[256] & reg_we & !reg_error; + assign alert_cause_61_we = addr_hit[262] & reg_we & !reg_error; assign alert_cause_61_wd = reg_wdata[0]; - assign alert_cause_62_we = addr_hit[257] & reg_we & !reg_error; + assign alert_cause_62_we = addr_hit[263] & reg_we & !reg_error; assign alert_cause_62_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[258] & reg_we & !reg_error; + assign alert_cause_63_we = addr_hit[264] & reg_we & !reg_error; + + assign alert_cause_63_wd = reg_wdata[0]; + assign alert_cause_64_we = addr_hit[265] & reg_we & !reg_error; + + assign alert_cause_64_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[266] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[259] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[267] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[260] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[268] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[261] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[269] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[262] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[270] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_regwen_5_we = addr_hit[263] & reg_we & !reg_error; + assign loc_alert_regwen_5_we = addr_hit[271] & reg_we & !reg_error; assign loc_alert_regwen_5_wd = reg_wdata[0]; - assign loc_alert_regwen_6_we = addr_hit[264] & reg_we & !reg_error; + assign loc_alert_regwen_6_we = addr_hit[272] & reg_we & !reg_error; assign loc_alert_regwen_6_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_0_re = addr_hit[265] & reg_re & !reg_error; - assign loc_alert_en_shadowed_0_we = addr_hit[265] & reg_we & !reg_error; + assign loc_alert_en_shadowed_0_re = addr_hit[273] & reg_re & !reg_error; + assign loc_alert_en_shadowed_0_we = addr_hit[273] & reg_we & !reg_error; assign loc_alert_en_shadowed_0_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_1_re = addr_hit[266] & reg_re & !reg_error; - assign loc_alert_en_shadowed_1_we = addr_hit[266] & reg_we & !reg_error; + assign loc_alert_en_shadowed_1_re = addr_hit[274] & reg_re & !reg_error; + assign loc_alert_en_shadowed_1_we = addr_hit[274] & reg_we & !reg_error; assign loc_alert_en_shadowed_1_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_2_re = addr_hit[267] & reg_re & !reg_error; - assign loc_alert_en_shadowed_2_we = addr_hit[267] & reg_we & !reg_error; + assign loc_alert_en_shadowed_2_re = addr_hit[275] & reg_re & !reg_error; + assign loc_alert_en_shadowed_2_we = addr_hit[275] & reg_we & !reg_error; assign loc_alert_en_shadowed_2_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_3_re = addr_hit[268] & reg_re & !reg_error; - assign loc_alert_en_shadowed_3_we = addr_hit[268] & reg_we & !reg_error; + assign loc_alert_en_shadowed_3_re = addr_hit[276] & reg_re & !reg_error; + assign loc_alert_en_shadowed_3_we = addr_hit[276] & reg_we & !reg_error; assign loc_alert_en_shadowed_3_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_4_re = addr_hit[269] & reg_re & !reg_error; - assign loc_alert_en_shadowed_4_we = addr_hit[269] & reg_we & !reg_error; + assign loc_alert_en_shadowed_4_re = addr_hit[277] & reg_re & !reg_error; + assign loc_alert_en_shadowed_4_we = addr_hit[277] & reg_we & !reg_error; assign loc_alert_en_shadowed_4_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_5_re = addr_hit[270] & reg_re & !reg_error; - assign loc_alert_en_shadowed_5_we = addr_hit[270] & reg_we & !reg_error; + assign loc_alert_en_shadowed_5_re = addr_hit[278] & reg_re & !reg_error; + assign loc_alert_en_shadowed_5_we = addr_hit[278] & reg_we & !reg_error; assign loc_alert_en_shadowed_5_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_6_re = addr_hit[271] & reg_re & !reg_error; - assign loc_alert_en_shadowed_6_we = addr_hit[271] & reg_we & !reg_error; + assign loc_alert_en_shadowed_6_re = addr_hit[279] & reg_re & !reg_error; + assign loc_alert_en_shadowed_6_we = addr_hit[279] & reg_we & !reg_error; assign loc_alert_en_shadowed_6_wd = reg_wdata[0]; - assign loc_alert_class_shadowed_0_re = addr_hit[272] & reg_re & !reg_error; - assign loc_alert_class_shadowed_0_we = addr_hit[272] & reg_we & !reg_error; + assign loc_alert_class_shadowed_0_re = addr_hit[280] & reg_re & !reg_error; + assign loc_alert_class_shadowed_0_we = addr_hit[280] & reg_we & !reg_error; assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_1_re = addr_hit[273] & reg_re & !reg_error; - assign loc_alert_class_shadowed_1_we = addr_hit[273] & reg_we & !reg_error; + assign loc_alert_class_shadowed_1_re = addr_hit[281] & reg_re & !reg_error; + assign loc_alert_class_shadowed_1_we = addr_hit[281] & reg_we & !reg_error; assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_2_re = addr_hit[274] & reg_re & !reg_error; - assign loc_alert_class_shadowed_2_we = addr_hit[274] & reg_we & !reg_error; + assign loc_alert_class_shadowed_2_re = addr_hit[282] & reg_re & !reg_error; + assign loc_alert_class_shadowed_2_we = addr_hit[282] & reg_we & !reg_error; assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_3_re = addr_hit[275] & reg_re & !reg_error; - assign loc_alert_class_shadowed_3_we = addr_hit[275] & reg_we & !reg_error; + assign loc_alert_class_shadowed_3_re = addr_hit[283] & reg_re & !reg_error; + assign loc_alert_class_shadowed_3_we = addr_hit[283] & reg_we & !reg_error; assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_4_re = addr_hit[276] & reg_re & !reg_error; - assign loc_alert_class_shadowed_4_we = addr_hit[276] & reg_we & !reg_error; + assign loc_alert_class_shadowed_4_re = addr_hit[284] & reg_re & !reg_error; + assign loc_alert_class_shadowed_4_we = addr_hit[284] & reg_we & !reg_error; assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_5_re = addr_hit[277] & reg_re & !reg_error; - assign loc_alert_class_shadowed_5_we = addr_hit[277] & reg_we & !reg_error; + assign loc_alert_class_shadowed_5_re = addr_hit[285] & reg_re & !reg_error; + assign loc_alert_class_shadowed_5_we = addr_hit[285] & reg_we & !reg_error; assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_6_re = addr_hit[278] & reg_re & !reg_error; - assign loc_alert_class_shadowed_6_we = addr_hit[278] & reg_we & !reg_error; + assign loc_alert_class_shadowed_6_re = addr_hit[286] & reg_re & !reg_error; + assign loc_alert_class_shadowed_6_we = addr_hit[286] & reg_we & !reg_error; assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[279] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[287] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[280] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[288] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[281] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[289] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[282] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[290] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign loc_alert_cause_4_we = addr_hit[283] & reg_we & !reg_error; + assign loc_alert_cause_4_we = addr_hit[291] & reg_we & !reg_error; assign loc_alert_cause_4_wd = reg_wdata[0]; - assign loc_alert_cause_5_we = addr_hit[284] & reg_we & !reg_error; + assign loc_alert_cause_5_we = addr_hit[292] & reg_we & !reg_error; assign loc_alert_cause_5_wd = reg_wdata[0]; - assign loc_alert_cause_6_we = addr_hit[285] & reg_we & !reg_error; + assign loc_alert_cause_6_we = addr_hit[293] & reg_we & !reg_error; assign loc_alert_cause_6_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[286] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[294] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_shadowed_re = addr_hit[287] & reg_re & !reg_error; - assign classa_ctrl_shadowed_we = addr_hit[287] & reg_we & !reg_error; + assign classa_ctrl_shadowed_re = addr_hit[295] & reg_re & !reg_error; + assign classa_ctrl_shadowed_we = addr_hit[295] & reg_we & !reg_error; assign classa_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -16985,49 +17345,49 @@ module alert_handler_reg_top ( assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[288] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[296] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_shadowed_re = addr_hit[289] & reg_re & !reg_error; - assign classa_clr_shadowed_we = addr_hit[289] & reg_we & !reg_error; + assign classa_clr_shadowed_re = addr_hit[297] & reg_re & !reg_error; + assign classa_clr_shadowed_we = addr_hit[297] & reg_we & !reg_error; assign classa_clr_shadowed_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[290] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_re = addr_hit[291] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_we = addr_hit[291] & reg_we & !reg_error; + assign classa_accum_cnt_re = addr_hit[298] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_re = addr_hit[299] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_we = addr_hit[299] & reg_we & !reg_error; assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_shadowed_re = addr_hit[292] & reg_re & !reg_error; - assign classa_timeout_cyc_shadowed_we = addr_hit[292] & reg_we & !reg_error; + assign classa_timeout_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error; + assign classa_timeout_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error; assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_crashdump_trigger_shadowed_re = addr_hit[293] & reg_re & !reg_error; - assign classa_crashdump_trigger_shadowed_we = addr_hit[293] & reg_we & !reg_error; + assign classa_crashdump_trigger_shadowed_re = addr_hit[301] & reg_re & !reg_error; + assign classa_crashdump_trigger_shadowed_we = addr_hit[301] & reg_we & !reg_error; assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classa_phase0_cyc_shadowed_re = addr_hit[294] & reg_re & !reg_error; - assign classa_phase0_cyc_shadowed_we = addr_hit[294] & reg_we & !reg_error; + assign classa_phase0_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error; + assign classa_phase0_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error; assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_shadowed_re = addr_hit[295] & reg_re & !reg_error; - assign classa_phase1_cyc_shadowed_we = addr_hit[295] & reg_we & !reg_error; + assign classa_phase1_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error; + assign classa_phase1_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error; assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_shadowed_re = addr_hit[296] & reg_re & !reg_error; - assign classa_phase2_cyc_shadowed_we = addr_hit[296] & reg_we & !reg_error; + assign classa_phase2_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error; + assign classa_phase2_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error; assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_shadowed_re = addr_hit[297] & reg_re & !reg_error; - assign classa_phase3_cyc_shadowed_we = addr_hit[297] & reg_we & !reg_error; + assign classa_phase3_cyc_shadowed_re = addr_hit[305] & reg_re & !reg_error; + assign classa_phase3_cyc_shadowed_we = addr_hit[305] & reg_we & !reg_error; assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[298] & reg_re & !reg_error; - assign classa_state_re = addr_hit[299] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[300] & reg_we & !reg_error; + assign classa_esc_cnt_re = addr_hit[306] & reg_re & !reg_error; + assign classa_state_re = addr_hit[307] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[308] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_shadowed_re = addr_hit[301] & reg_re & !reg_error; - assign classb_ctrl_shadowed_we = addr_hit[301] & reg_we & !reg_error; + assign classb_ctrl_shadowed_re = addr_hit[309] & reg_re & !reg_error; + assign classb_ctrl_shadowed_we = addr_hit[309] & reg_we & !reg_error; assign classb_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17048,49 +17408,49 @@ module alert_handler_reg_top ( assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[302] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[310] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_shadowed_re = addr_hit[303] & reg_re & !reg_error; - assign classb_clr_shadowed_we = addr_hit[303] & reg_we & !reg_error; + assign classb_clr_shadowed_re = addr_hit[311] & reg_re & !reg_error; + assign classb_clr_shadowed_we = addr_hit[311] & reg_we & !reg_error; assign classb_clr_shadowed_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[304] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_re = addr_hit[305] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_we = addr_hit[305] & reg_we & !reg_error; + assign classb_accum_cnt_re = addr_hit[312] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_re = addr_hit[313] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_we = addr_hit[313] & reg_we & !reg_error; assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_shadowed_re = addr_hit[306] & reg_re & !reg_error; - assign classb_timeout_cyc_shadowed_we = addr_hit[306] & reg_we & !reg_error; + assign classb_timeout_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error; + assign classb_timeout_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error; assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_crashdump_trigger_shadowed_re = addr_hit[307] & reg_re & !reg_error; - assign classb_crashdump_trigger_shadowed_we = addr_hit[307] & reg_we & !reg_error; + assign classb_crashdump_trigger_shadowed_re = addr_hit[315] & reg_re & !reg_error; + assign classb_crashdump_trigger_shadowed_we = addr_hit[315] & reg_we & !reg_error; assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classb_phase0_cyc_shadowed_re = addr_hit[308] & reg_re & !reg_error; - assign classb_phase0_cyc_shadowed_we = addr_hit[308] & reg_we & !reg_error; + assign classb_phase0_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error; + assign classb_phase0_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error; assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_shadowed_re = addr_hit[309] & reg_re & !reg_error; - assign classb_phase1_cyc_shadowed_we = addr_hit[309] & reg_we & !reg_error; + assign classb_phase1_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error; + assign classb_phase1_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error; assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_shadowed_re = addr_hit[310] & reg_re & !reg_error; - assign classb_phase2_cyc_shadowed_we = addr_hit[310] & reg_we & !reg_error; + assign classb_phase2_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error; + assign classb_phase2_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error; assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_shadowed_re = addr_hit[311] & reg_re & !reg_error; - assign classb_phase3_cyc_shadowed_we = addr_hit[311] & reg_we & !reg_error; + assign classb_phase3_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error; + assign classb_phase3_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error; assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[312] & reg_re & !reg_error; - assign classb_state_re = addr_hit[313] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[314] & reg_we & !reg_error; + assign classb_esc_cnt_re = addr_hit[320] & reg_re & !reg_error; + assign classb_state_re = addr_hit[321] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[322] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_shadowed_re = addr_hit[315] & reg_re & !reg_error; - assign classc_ctrl_shadowed_we = addr_hit[315] & reg_we & !reg_error; + assign classc_ctrl_shadowed_re = addr_hit[323] & reg_re & !reg_error; + assign classc_ctrl_shadowed_we = addr_hit[323] & reg_we & !reg_error; assign classc_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17111,49 +17471,49 @@ module alert_handler_reg_top ( assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[316] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[324] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_shadowed_re = addr_hit[317] & reg_re & !reg_error; - assign classc_clr_shadowed_we = addr_hit[317] & reg_we & !reg_error; + assign classc_clr_shadowed_re = addr_hit[325] & reg_re & !reg_error; + assign classc_clr_shadowed_we = addr_hit[325] & reg_we & !reg_error; assign classc_clr_shadowed_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[318] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_re = addr_hit[319] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_we = addr_hit[319] & reg_we & !reg_error; + assign classc_accum_cnt_re = addr_hit[326] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_re = addr_hit[327] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_we = addr_hit[327] & reg_we & !reg_error; assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_shadowed_re = addr_hit[320] & reg_re & !reg_error; - assign classc_timeout_cyc_shadowed_we = addr_hit[320] & reg_we & !reg_error; + assign classc_timeout_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error; + assign classc_timeout_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error; assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_crashdump_trigger_shadowed_re = addr_hit[321] & reg_re & !reg_error; - assign classc_crashdump_trigger_shadowed_we = addr_hit[321] & reg_we & !reg_error; + assign classc_crashdump_trigger_shadowed_re = addr_hit[329] & reg_re & !reg_error; + assign classc_crashdump_trigger_shadowed_we = addr_hit[329] & reg_we & !reg_error; assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classc_phase0_cyc_shadowed_re = addr_hit[322] & reg_re & !reg_error; - assign classc_phase0_cyc_shadowed_we = addr_hit[322] & reg_we & !reg_error; + assign classc_phase0_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error; + assign classc_phase0_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error; assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_shadowed_re = addr_hit[323] & reg_re & !reg_error; - assign classc_phase1_cyc_shadowed_we = addr_hit[323] & reg_we & !reg_error; + assign classc_phase1_cyc_shadowed_re = addr_hit[331] & reg_re & !reg_error; + assign classc_phase1_cyc_shadowed_we = addr_hit[331] & reg_we & !reg_error; assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_shadowed_re = addr_hit[324] & reg_re & !reg_error; - assign classc_phase2_cyc_shadowed_we = addr_hit[324] & reg_we & !reg_error; + assign classc_phase2_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error; + assign classc_phase2_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error; assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_shadowed_re = addr_hit[325] & reg_re & !reg_error; - assign classc_phase3_cyc_shadowed_we = addr_hit[325] & reg_we & !reg_error; + assign classc_phase3_cyc_shadowed_re = addr_hit[333] & reg_re & !reg_error; + assign classc_phase3_cyc_shadowed_we = addr_hit[333] & reg_we & !reg_error; assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[326] & reg_re & !reg_error; - assign classc_state_re = addr_hit[327] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[328] & reg_we & !reg_error; + assign classc_esc_cnt_re = addr_hit[334] & reg_re & !reg_error; + assign classc_state_re = addr_hit[335] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[336] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_shadowed_re = addr_hit[329] & reg_re & !reg_error; - assign classd_ctrl_shadowed_we = addr_hit[329] & reg_we & !reg_error; + assign classd_ctrl_shadowed_re = addr_hit[337] & reg_re & !reg_error; + assign classd_ctrl_shadowed_we = addr_hit[337] & reg_we & !reg_error; assign classd_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17174,44 +17534,44 @@ module alert_handler_reg_top ( assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[330] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[338] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_shadowed_re = addr_hit[331] & reg_re & !reg_error; - assign classd_clr_shadowed_we = addr_hit[331] & reg_we & !reg_error; + assign classd_clr_shadowed_re = addr_hit[339] & reg_re & !reg_error; + assign classd_clr_shadowed_we = addr_hit[339] & reg_we & !reg_error; assign classd_clr_shadowed_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[332] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_re = addr_hit[333] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_we = addr_hit[333] & reg_we & !reg_error; + assign classd_accum_cnt_re = addr_hit[340] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_re = addr_hit[341] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_we = addr_hit[341] & reg_we & !reg_error; assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_shadowed_re = addr_hit[334] & reg_re & !reg_error; - assign classd_timeout_cyc_shadowed_we = addr_hit[334] & reg_we & !reg_error; + assign classd_timeout_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error; + assign classd_timeout_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error; assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_crashdump_trigger_shadowed_re = addr_hit[335] & reg_re & !reg_error; - assign classd_crashdump_trigger_shadowed_we = addr_hit[335] & reg_we & !reg_error; + assign classd_crashdump_trigger_shadowed_re = addr_hit[343] & reg_re & !reg_error; + assign classd_crashdump_trigger_shadowed_we = addr_hit[343] & reg_we & !reg_error; assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classd_phase0_cyc_shadowed_re = addr_hit[336] & reg_re & !reg_error; - assign classd_phase0_cyc_shadowed_we = addr_hit[336] & reg_we & !reg_error; + assign classd_phase0_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error; + assign classd_phase0_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error; assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_shadowed_re = addr_hit[337] & reg_re & !reg_error; - assign classd_phase1_cyc_shadowed_we = addr_hit[337] & reg_we & !reg_error; + assign classd_phase1_cyc_shadowed_re = addr_hit[345] & reg_re & !reg_error; + assign classd_phase1_cyc_shadowed_we = addr_hit[345] & reg_we & !reg_error; assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_shadowed_re = addr_hit[338] & reg_re & !reg_error; - assign classd_phase2_cyc_shadowed_we = addr_hit[338] & reg_we & !reg_error; + assign classd_phase2_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error; + assign classd_phase2_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error; assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_shadowed_re = addr_hit[339] & reg_re & !reg_error; - assign classd_phase3_cyc_shadowed_we = addr_hit[339] & reg_we & !reg_error; + assign classd_phase3_cyc_shadowed_re = addr_hit[347] & reg_re & !reg_error; + assign classd_phase3_cyc_shadowed_we = addr_hit[347] & reg_we & !reg_error; assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[340] & reg_re & !reg_error; - assign classd_state_re = addr_hit[341] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[348] & reg_re & !reg_error; + assign classd_state_re = addr_hit[349] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -17284,279 +17644,287 @@ module alert_handler_reg_top ( reg_we_check[66] = alert_regwen_60_we; reg_we_check[67] = alert_regwen_61_we; reg_we_check[68] = alert_regwen_62_we; - reg_we_check[69] = alert_en_shadowed_0_gated_we; - reg_we_check[70] = alert_en_shadowed_1_gated_we; - reg_we_check[71] = alert_en_shadowed_2_gated_we; - reg_we_check[72] = alert_en_shadowed_3_gated_we; - reg_we_check[73] = alert_en_shadowed_4_gated_we; - reg_we_check[74] = alert_en_shadowed_5_gated_we; - reg_we_check[75] = alert_en_shadowed_6_gated_we; - reg_we_check[76] = alert_en_shadowed_7_gated_we; - reg_we_check[77] = alert_en_shadowed_8_gated_we; - reg_we_check[78] = alert_en_shadowed_9_gated_we; - reg_we_check[79] = alert_en_shadowed_10_gated_we; - reg_we_check[80] = alert_en_shadowed_11_gated_we; - reg_we_check[81] = alert_en_shadowed_12_gated_we; - reg_we_check[82] = alert_en_shadowed_13_gated_we; - reg_we_check[83] = alert_en_shadowed_14_gated_we; - reg_we_check[84] = alert_en_shadowed_15_gated_we; - reg_we_check[85] = alert_en_shadowed_16_gated_we; - reg_we_check[86] = alert_en_shadowed_17_gated_we; - reg_we_check[87] = alert_en_shadowed_18_gated_we; - reg_we_check[88] = alert_en_shadowed_19_gated_we; - reg_we_check[89] = alert_en_shadowed_20_gated_we; - reg_we_check[90] = alert_en_shadowed_21_gated_we; - reg_we_check[91] = alert_en_shadowed_22_gated_we; - reg_we_check[92] = alert_en_shadowed_23_gated_we; - reg_we_check[93] = alert_en_shadowed_24_gated_we; - reg_we_check[94] = alert_en_shadowed_25_gated_we; - reg_we_check[95] = alert_en_shadowed_26_gated_we; - reg_we_check[96] = alert_en_shadowed_27_gated_we; - reg_we_check[97] = alert_en_shadowed_28_gated_we; - reg_we_check[98] = alert_en_shadowed_29_gated_we; - reg_we_check[99] = alert_en_shadowed_30_gated_we; - reg_we_check[100] = alert_en_shadowed_31_gated_we; - reg_we_check[101] = alert_en_shadowed_32_gated_we; - reg_we_check[102] = alert_en_shadowed_33_gated_we; - reg_we_check[103] = alert_en_shadowed_34_gated_we; - reg_we_check[104] = alert_en_shadowed_35_gated_we; - reg_we_check[105] = alert_en_shadowed_36_gated_we; - reg_we_check[106] = alert_en_shadowed_37_gated_we; - reg_we_check[107] = alert_en_shadowed_38_gated_we; - reg_we_check[108] = alert_en_shadowed_39_gated_we; - reg_we_check[109] = alert_en_shadowed_40_gated_we; - reg_we_check[110] = alert_en_shadowed_41_gated_we; - reg_we_check[111] = alert_en_shadowed_42_gated_we; - reg_we_check[112] = alert_en_shadowed_43_gated_we; - reg_we_check[113] = alert_en_shadowed_44_gated_we; - reg_we_check[114] = alert_en_shadowed_45_gated_we; - reg_we_check[115] = alert_en_shadowed_46_gated_we; - reg_we_check[116] = alert_en_shadowed_47_gated_we; - reg_we_check[117] = alert_en_shadowed_48_gated_we; - reg_we_check[118] = alert_en_shadowed_49_gated_we; - reg_we_check[119] = alert_en_shadowed_50_gated_we; - reg_we_check[120] = alert_en_shadowed_51_gated_we; - reg_we_check[121] = alert_en_shadowed_52_gated_we; - reg_we_check[122] = alert_en_shadowed_53_gated_we; - reg_we_check[123] = alert_en_shadowed_54_gated_we; - reg_we_check[124] = alert_en_shadowed_55_gated_we; - reg_we_check[125] = alert_en_shadowed_56_gated_we; - reg_we_check[126] = alert_en_shadowed_57_gated_we; - reg_we_check[127] = alert_en_shadowed_58_gated_we; - reg_we_check[128] = alert_en_shadowed_59_gated_we; - reg_we_check[129] = alert_en_shadowed_60_gated_we; - reg_we_check[130] = alert_en_shadowed_61_gated_we; - reg_we_check[131] = alert_en_shadowed_62_gated_we; - reg_we_check[132] = alert_class_shadowed_0_gated_we; - reg_we_check[133] = alert_class_shadowed_1_gated_we; - reg_we_check[134] = alert_class_shadowed_2_gated_we; - reg_we_check[135] = alert_class_shadowed_3_gated_we; - reg_we_check[136] = alert_class_shadowed_4_gated_we; - reg_we_check[137] = alert_class_shadowed_5_gated_we; - reg_we_check[138] = alert_class_shadowed_6_gated_we; - reg_we_check[139] = alert_class_shadowed_7_gated_we; - reg_we_check[140] = alert_class_shadowed_8_gated_we; - reg_we_check[141] = alert_class_shadowed_9_gated_we; - reg_we_check[142] = alert_class_shadowed_10_gated_we; - reg_we_check[143] = alert_class_shadowed_11_gated_we; - reg_we_check[144] = alert_class_shadowed_12_gated_we; - reg_we_check[145] = alert_class_shadowed_13_gated_we; - reg_we_check[146] = alert_class_shadowed_14_gated_we; - reg_we_check[147] = alert_class_shadowed_15_gated_we; - reg_we_check[148] = alert_class_shadowed_16_gated_we; - reg_we_check[149] = alert_class_shadowed_17_gated_we; - reg_we_check[150] = alert_class_shadowed_18_gated_we; - reg_we_check[151] = alert_class_shadowed_19_gated_we; - reg_we_check[152] = alert_class_shadowed_20_gated_we; - reg_we_check[153] = alert_class_shadowed_21_gated_we; - reg_we_check[154] = alert_class_shadowed_22_gated_we; - reg_we_check[155] = alert_class_shadowed_23_gated_we; - reg_we_check[156] = alert_class_shadowed_24_gated_we; - reg_we_check[157] = alert_class_shadowed_25_gated_we; - reg_we_check[158] = alert_class_shadowed_26_gated_we; - reg_we_check[159] = alert_class_shadowed_27_gated_we; - reg_we_check[160] = alert_class_shadowed_28_gated_we; - reg_we_check[161] = alert_class_shadowed_29_gated_we; - reg_we_check[162] = alert_class_shadowed_30_gated_we; - reg_we_check[163] = alert_class_shadowed_31_gated_we; - reg_we_check[164] = alert_class_shadowed_32_gated_we; - reg_we_check[165] = alert_class_shadowed_33_gated_we; - reg_we_check[166] = alert_class_shadowed_34_gated_we; - reg_we_check[167] = alert_class_shadowed_35_gated_we; - reg_we_check[168] = alert_class_shadowed_36_gated_we; - reg_we_check[169] = alert_class_shadowed_37_gated_we; - reg_we_check[170] = alert_class_shadowed_38_gated_we; - reg_we_check[171] = alert_class_shadowed_39_gated_we; - reg_we_check[172] = alert_class_shadowed_40_gated_we; - reg_we_check[173] = alert_class_shadowed_41_gated_we; - reg_we_check[174] = alert_class_shadowed_42_gated_we; - reg_we_check[175] = alert_class_shadowed_43_gated_we; - reg_we_check[176] = alert_class_shadowed_44_gated_we; - reg_we_check[177] = alert_class_shadowed_45_gated_we; - reg_we_check[178] = alert_class_shadowed_46_gated_we; - reg_we_check[179] = alert_class_shadowed_47_gated_we; - reg_we_check[180] = alert_class_shadowed_48_gated_we; - reg_we_check[181] = alert_class_shadowed_49_gated_we; - reg_we_check[182] = alert_class_shadowed_50_gated_we; - reg_we_check[183] = alert_class_shadowed_51_gated_we; - reg_we_check[184] = alert_class_shadowed_52_gated_we; - reg_we_check[185] = alert_class_shadowed_53_gated_we; - reg_we_check[186] = alert_class_shadowed_54_gated_we; - reg_we_check[187] = alert_class_shadowed_55_gated_we; - reg_we_check[188] = alert_class_shadowed_56_gated_we; - reg_we_check[189] = alert_class_shadowed_57_gated_we; - reg_we_check[190] = alert_class_shadowed_58_gated_we; - reg_we_check[191] = alert_class_shadowed_59_gated_we; - reg_we_check[192] = alert_class_shadowed_60_gated_we; - reg_we_check[193] = alert_class_shadowed_61_gated_we; - reg_we_check[194] = alert_class_shadowed_62_gated_we; - reg_we_check[195] = alert_cause_0_we; - reg_we_check[196] = alert_cause_1_we; - reg_we_check[197] = alert_cause_2_we; - reg_we_check[198] = alert_cause_3_we; - reg_we_check[199] = alert_cause_4_we; - reg_we_check[200] = alert_cause_5_we; - reg_we_check[201] = alert_cause_6_we; - reg_we_check[202] = alert_cause_7_we; - reg_we_check[203] = alert_cause_8_we; - reg_we_check[204] = alert_cause_9_we; - reg_we_check[205] = alert_cause_10_we; - reg_we_check[206] = alert_cause_11_we; - reg_we_check[207] = alert_cause_12_we; - reg_we_check[208] = alert_cause_13_we; - reg_we_check[209] = alert_cause_14_we; - reg_we_check[210] = alert_cause_15_we; - reg_we_check[211] = alert_cause_16_we; - reg_we_check[212] = alert_cause_17_we; - reg_we_check[213] = alert_cause_18_we; - reg_we_check[214] = alert_cause_19_we; - reg_we_check[215] = alert_cause_20_we; - reg_we_check[216] = alert_cause_21_we; - reg_we_check[217] = alert_cause_22_we; - reg_we_check[218] = alert_cause_23_we; - reg_we_check[219] = alert_cause_24_we; - reg_we_check[220] = alert_cause_25_we; - reg_we_check[221] = alert_cause_26_we; - reg_we_check[222] = alert_cause_27_we; - reg_we_check[223] = alert_cause_28_we; - reg_we_check[224] = alert_cause_29_we; - reg_we_check[225] = alert_cause_30_we; - reg_we_check[226] = alert_cause_31_we; - reg_we_check[227] = alert_cause_32_we; - reg_we_check[228] = alert_cause_33_we; - reg_we_check[229] = alert_cause_34_we; - reg_we_check[230] = alert_cause_35_we; - reg_we_check[231] = alert_cause_36_we; - reg_we_check[232] = alert_cause_37_we; - reg_we_check[233] = alert_cause_38_we; - reg_we_check[234] = alert_cause_39_we; - reg_we_check[235] = alert_cause_40_we; - reg_we_check[236] = alert_cause_41_we; - reg_we_check[237] = alert_cause_42_we; - reg_we_check[238] = alert_cause_43_we; - reg_we_check[239] = alert_cause_44_we; - reg_we_check[240] = alert_cause_45_we; - reg_we_check[241] = alert_cause_46_we; - reg_we_check[242] = alert_cause_47_we; - reg_we_check[243] = alert_cause_48_we; - reg_we_check[244] = alert_cause_49_we; - reg_we_check[245] = alert_cause_50_we; - reg_we_check[246] = alert_cause_51_we; - reg_we_check[247] = alert_cause_52_we; - reg_we_check[248] = alert_cause_53_we; - reg_we_check[249] = alert_cause_54_we; - reg_we_check[250] = alert_cause_55_we; - reg_we_check[251] = alert_cause_56_we; - reg_we_check[252] = alert_cause_57_we; - reg_we_check[253] = alert_cause_58_we; - reg_we_check[254] = alert_cause_59_we; - reg_we_check[255] = alert_cause_60_we; - reg_we_check[256] = alert_cause_61_we; - reg_we_check[257] = alert_cause_62_we; - reg_we_check[258] = loc_alert_regwen_0_we; - reg_we_check[259] = loc_alert_regwen_1_we; - reg_we_check[260] = loc_alert_regwen_2_we; - reg_we_check[261] = loc_alert_regwen_3_we; - reg_we_check[262] = loc_alert_regwen_4_we; - reg_we_check[263] = loc_alert_regwen_5_we; - reg_we_check[264] = loc_alert_regwen_6_we; - reg_we_check[265] = loc_alert_en_shadowed_0_gated_we; - reg_we_check[266] = loc_alert_en_shadowed_1_gated_we; - reg_we_check[267] = loc_alert_en_shadowed_2_gated_we; - reg_we_check[268] = loc_alert_en_shadowed_3_gated_we; - reg_we_check[269] = loc_alert_en_shadowed_4_gated_we; - reg_we_check[270] = loc_alert_en_shadowed_5_gated_we; - reg_we_check[271] = loc_alert_en_shadowed_6_gated_we; - reg_we_check[272] = loc_alert_class_shadowed_0_gated_we; - reg_we_check[273] = loc_alert_class_shadowed_1_gated_we; - reg_we_check[274] = loc_alert_class_shadowed_2_gated_we; - reg_we_check[275] = loc_alert_class_shadowed_3_gated_we; - reg_we_check[276] = loc_alert_class_shadowed_4_gated_we; - reg_we_check[277] = loc_alert_class_shadowed_5_gated_we; - reg_we_check[278] = loc_alert_class_shadowed_6_gated_we; - reg_we_check[279] = loc_alert_cause_0_we; - reg_we_check[280] = loc_alert_cause_1_we; - reg_we_check[281] = loc_alert_cause_2_we; - reg_we_check[282] = loc_alert_cause_3_we; - reg_we_check[283] = loc_alert_cause_4_we; - reg_we_check[284] = loc_alert_cause_5_we; - reg_we_check[285] = loc_alert_cause_6_we; - reg_we_check[286] = classa_regwen_we; - reg_we_check[287] = classa_ctrl_shadowed_gated_we; - reg_we_check[288] = classa_clr_regwen_we; - reg_we_check[289] = classa_clr_shadowed_gated_we; - reg_we_check[290] = 1'b0; - reg_we_check[291] = classa_accum_thresh_shadowed_gated_we; - reg_we_check[292] = classa_timeout_cyc_shadowed_gated_we; - reg_we_check[293] = classa_crashdump_trigger_shadowed_gated_we; - reg_we_check[294] = classa_phase0_cyc_shadowed_gated_we; - reg_we_check[295] = classa_phase1_cyc_shadowed_gated_we; - reg_we_check[296] = classa_phase2_cyc_shadowed_gated_we; - reg_we_check[297] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[69] = alert_regwen_63_we; + reg_we_check[70] = alert_regwen_64_we; + reg_we_check[71] = alert_en_shadowed_0_gated_we; + reg_we_check[72] = alert_en_shadowed_1_gated_we; + reg_we_check[73] = alert_en_shadowed_2_gated_we; + reg_we_check[74] = alert_en_shadowed_3_gated_we; + reg_we_check[75] = alert_en_shadowed_4_gated_we; + reg_we_check[76] = alert_en_shadowed_5_gated_we; + reg_we_check[77] = alert_en_shadowed_6_gated_we; + reg_we_check[78] = alert_en_shadowed_7_gated_we; + reg_we_check[79] = alert_en_shadowed_8_gated_we; + reg_we_check[80] = alert_en_shadowed_9_gated_we; + reg_we_check[81] = alert_en_shadowed_10_gated_we; + reg_we_check[82] = alert_en_shadowed_11_gated_we; + reg_we_check[83] = alert_en_shadowed_12_gated_we; + reg_we_check[84] = alert_en_shadowed_13_gated_we; + reg_we_check[85] = alert_en_shadowed_14_gated_we; + reg_we_check[86] = alert_en_shadowed_15_gated_we; + reg_we_check[87] = alert_en_shadowed_16_gated_we; + reg_we_check[88] = alert_en_shadowed_17_gated_we; + reg_we_check[89] = alert_en_shadowed_18_gated_we; + reg_we_check[90] = alert_en_shadowed_19_gated_we; + reg_we_check[91] = alert_en_shadowed_20_gated_we; + reg_we_check[92] = alert_en_shadowed_21_gated_we; + reg_we_check[93] = alert_en_shadowed_22_gated_we; + reg_we_check[94] = alert_en_shadowed_23_gated_we; + reg_we_check[95] = alert_en_shadowed_24_gated_we; + reg_we_check[96] = alert_en_shadowed_25_gated_we; + reg_we_check[97] = alert_en_shadowed_26_gated_we; + reg_we_check[98] = alert_en_shadowed_27_gated_we; + reg_we_check[99] = alert_en_shadowed_28_gated_we; + reg_we_check[100] = alert_en_shadowed_29_gated_we; + reg_we_check[101] = alert_en_shadowed_30_gated_we; + reg_we_check[102] = alert_en_shadowed_31_gated_we; + reg_we_check[103] = alert_en_shadowed_32_gated_we; + reg_we_check[104] = alert_en_shadowed_33_gated_we; + reg_we_check[105] = alert_en_shadowed_34_gated_we; + reg_we_check[106] = alert_en_shadowed_35_gated_we; + reg_we_check[107] = alert_en_shadowed_36_gated_we; + reg_we_check[108] = alert_en_shadowed_37_gated_we; + reg_we_check[109] = alert_en_shadowed_38_gated_we; + reg_we_check[110] = alert_en_shadowed_39_gated_we; + reg_we_check[111] = alert_en_shadowed_40_gated_we; + reg_we_check[112] = alert_en_shadowed_41_gated_we; + reg_we_check[113] = alert_en_shadowed_42_gated_we; + reg_we_check[114] = alert_en_shadowed_43_gated_we; + reg_we_check[115] = alert_en_shadowed_44_gated_we; + reg_we_check[116] = alert_en_shadowed_45_gated_we; + reg_we_check[117] = alert_en_shadowed_46_gated_we; + reg_we_check[118] = alert_en_shadowed_47_gated_we; + reg_we_check[119] = alert_en_shadowed_48_gated_we; + reg_we_check[120] = alert_en_shadowed_49_gated_we; + reg_we_check[121] = alert_en_shadowed_50_gated_we; + reg_we_check[122] = alert_en_shadowed_51_gated_we; + reg_we_check[123] = alert_en_shadowed_52_gated_we; + reg_we_check[124] = alert_en_shadowed_53_gated_we; + reg_we_check[125] = alert_en_shadowed_54_gated_we; + reg_we_check[126] = alert_en_shadowed_55_gated_we; + reg_we_check[127] = alert_en_shadowed_56_gated_we; + reg_we_check[128] = alert_en_shadowed_57_gated_we; + reg_we_check[129] = alert_en_shadowed_58_gated_we; + reg_we_check[130] = alert_en_shadowed_59_gated_we; + reg_we_check[131] = alert_en_shadowed_60_gated_we; + reg_we_check[132] = alert_en_shadowed_61_gated_we; + reg_we_check[133] = alert_en_shadowed_62_gated_we; + reg_we_check[134] = alert_en_shadowed_63_gated_we; + reg_we_check[135] = alert_en_shadowed_64_gated_we; + reg_we_check[136] = alert_class_shadowed_0_gated_we; + reg_we_check[137] = alert_class_shadowed_1_gated_we; + reg_we_check[138] = alert_class_shadowed_2_gated_we; + reg_we_check[139] = alert_class_shadowed_3_gated_we; + reg_we_check[140] = alert_class_shadowed_4_gated_we; + reg_we_check[141] = alert_class_shadowed_5_gated_we; + reg_we_check[142] = alert_class_shadowed_6_gated_we; + reg_we_check[143] = alert_class_shadowed_7_gated_we; + reg_we_check[144] = alert_class_shadowed_8_gated_we; + reg_we_check[145] = alert_class_shadowed_9_gated_we; + reg_we_check[146] = alert_class_shadowed_10_gated_we; + reg_we_check[147] = alert_class_shadowed_11_gated_we; + reg_we_check[148] = alert_class_shadowed_12_gated_we; + reg_we_check[149] = alert_class_shadowed_13_gated_we; + reg_we_check[150] = alert_class_shadowed_14_gated_we; + reg_we_check[151] = alert_class_shadowed_15_gated_we; + reg_we_check[152] = alert_class_shadowed_16_gated_we; + reg_we_check[153] = alert_class_shadowed_17_gated_we; + reg_we_check[154] = alert_class_shadowed_18_gated_we; + reg_we_check[155] = alert_class_shadowed_19_gated_we; + reg_we_check[156] = alert_class_shadowed_20_gated_we; + reg_we_check[157] = alert_class_shadowed_21_gated_we; + reg_we_check[158] = alert_class_shadowed_22_gated_we; + reg_we_check[159] = alert_class_shadowed_23_gated_we; + reg_we_check[160] = alert_class_shadowed_24_gated_we; + reg_we_check[161] = alert_class_shadowed_25_gated_we; + reg_we_check[162] = alert_class_shadowed_26_gated_we; + reg_we_check[163] = alert_class_shadowed_27_gated_we; + reg_we_check[164] = alert_class_shadowed_28_gated_we; + reg_we_check[165] = alert_class_shadowed_29_gated_we; + reg_we_check[166] = alert_class_shadowed_30_gated_we; + reg_we_check[167] = alert_class_shadowed_31_gated_we; + reg_we_check[168] = alert_class_shadowed_32_gated_we; + reg_we_check[169] = alert_class_shadowed_33_gated_we; + reg_we_check[170] = alert_class_shadowed_34_gated_we; + reg_we_check[171] = alert_class_shadowed_35_gated_we; + reg_we_check[172] = alert_class_shadowed_36_gated_we; + reg_we_check[173] = alert_class_shadowed_37_gated_we; + reg_we_check[174] = alert_class_shadowed_38_gated_we; + reg_we_check[175] = alert_class_shadowed_39_gated_we; + reg_we_check[176] = alert_class_shadowed_40_gated_we; + reg_we_check[177] = alert_class_shadowed_41_gated_we; + reg_we_check[178] = alert_class_shadowed_42_gated_we; + reg_we_check[179] = alert_class_shadowed_43_gated_we; + reg_we_check[180] = alert_class_shadowed_44_gated_we; + reg_we_check[181] = alert_class_shadowed_45_gated_we; + reg_we_check[182] = alert_class_shadowed_46_gated_we; + reg_we_check[183] = alert_class_shadowed_47_gated_we; + reg_we_check[184] = alert_class_shadowed_48_gated_we; + reg_we_check[185] = alert_class_shadowed_49_gated_we; + reg_we_check[186] = alert_class_shadowed_50_gated_we; + reg_we_check[187] = alert_class_shadowed_51_gated_we; + reg_we_check[188] = alert_class_shadowed_52_gated_we; + reg_we_check[189] = alert_class_shadowed_53_gated_we; + reg_we_check[190] = alert_class_shadowed_54_gated_we; + reg_we_check[191] = alert_class_shadowed_55_gated_we; + reg_we_check[192] = alert_class_shadowed_56_gated_we; + reg_we_check[193] = alert_class_shadowed_57_gated_we; + reg_we_check[194] = alert_class_shadowed_58_gated_we; + reg_we_check[195] = alert_class_shadowed_59_gated_we; + reg_we_check[196] = alert_class_shadowed_60_gated_we; + reg_we_check[197] = alert_class_shadowed_61_gated_we; + reg_we_check[198] = alert_class_shadowed_62_gated_we; + reg_we_check[199] = alert_class_shadowed_63_gated_we; + reg_we_check[200] = alert_class_shadowed_64_gated_we; + reg_we_check[201] = alert_cause_0_we; + reg_we_check[202] = alert_cause_1_we; + reg_we_check[203] = alert_cause_2_we; + reg_we_check[204] = alert_cause_3_we; + reg_we_check[205] = alert_cause_4_we; + reg_we_check[206] = alert_cause_5_we; + reg_we_check[207] = alert_cause_6_we; + reg_we_check[208] = alert_cause_7_we; + reg_we_check[209] = alert_cause_8_we; + reg_we_check[210] = alert_cause_9_we; + reg_we_check[211] = alert_cause_10_we; + reg_we_check[212] = alert_cause_11_we; + reg_we_check[213] = alert_cause_12_we; + reg_we_check[214] = alert_cause_13_we; + reg_we_check[215] = alert_cause_14_we; + reg_we_check[216] = alert_cause_15_we; + reg_we_check[217] = alert_cause_16_we; + reg_we_check[218] = alert_cause_17_we; + reg_we_check[219] = alert_cause_18_we; + reg_we_check[220] = alert_cause_19_we; + reg_we_check[221] = alert_cause_20_we; + reg_we_check[222] = alert_cause_21_we; + reg_we_check[223] = alert_cause_22_we; + reg_we_check[224] = alert_cause_23_we; + reg_we_check[225] = alert_cause_24_we; + reg_we_check[226] = alert_cause_25_we; + reg_we_check[227] = alert_cause_26_we; + reg_we_check[228] = alert_cause_27_we; + reg_we_check[229] = alert_cause_28_we; + reg_we_check[230] = alert_cause_29_we; + reg_we_check[231] = alert_cause_30_we; + reg_we_check[232] = alert_cause_31_we; + reg_we_check[233] = alert_cause_32_we; + reg_we_check[234] = alert_cause_33_we; + reg_we_check[235] = alert_cause_34_we; + reg_we_check[236] = alert_cause_35_we; + reg_we_check[237] = alert_cause_36_we; + reg_we_check[238] = alert_cause_37_we; + reg_we_check[239] = alert_cause_38_we; + reg_we_check[240] = alert_cause_39_we; + reg_we_check[241] = alert_cause_40_we; + reg_we_check[242] = alert_cause_41_we; + reg_we_check[243] = alert_cause_42_we; + reg_we_check[244] = alert_cause_43_we; + reg_we_check[245] = alert_cause_44_we; + reg_we_check[246] = alert_cause_45_we; + reg_we_check[247] = alert_cause_46_we; + reg_we_check[248] = alert_cause_47_we; + reg_we_check[249] = alert_cause_48_we; + reg_we_check[250] = alert_cause_49_we; + reg_we_check[251] = alert_cause_50_we; + reg_we_check[252] = alert_cause_51_we; + reg_we_check[253] = alert_cause_52_we; + reg_we_check[254] = alert_cause_53_we; + reg_we_check[255] = alert_cause_54_we; + reg_we_check[256] = alert_cause_55_we; + reg_we_check[257] = alert_cause_56_we; + reg_we_check[258] = alert_cause_57_we; + reg_we_check[259] = alert_cause_58_we; + reg_we_check[260] = alert_cause_59_we; + reg_we_check[261] = alert_cause_60_we; + reg_we_check[262] = alert_cause_61_we; + reg_we_check[263] = alert_cause_62_we; + reg_we_check[264] = alert_cause_63_we; + reg_we_check[265] = alert_cause_64_we; + reg_we_check[266] = loc_alert_regwen_0_we; + reg_we_check[267] = loc_alert_regwen_1_we; + reg_we_check[268] = loc_alert_regwen_2_we; + reg_we_check[269] = loc_alert_regwen_3_we; + reg_we_check[270] = loc_alert_regwen_4_we; + reg_we_check[271] = loc_alert_regwen_5_we; + reg_we_check[272] = loc_alert_regwen_6_we; + reg_we_check[273] = loc_alert_en_shadowed_0_gated_we; + reg_we_check[274] = loc_alert_en_shadowed_1_gated_we; + reg_we_check[275] = loc_alert_en_shadowed_2_gated_we; + reg_we_check[276] = loc_alert_en_shadowed_3_gated_we; + reg_we_check[277] = loc_alert_en_shadowed_4_gated_we; + reg_we_check[278] = loc_alert_en_shadowed_5_gated_we; + reg_we_check[279] = loc_alert_en_shadowed_6_gated_we; + reg_we_check[280] = loc_alert_class_shadowed_0_gated_we; + reg_we_check[281] = loc_alert_class_shadowed_1_gated_we; + reg_we_check[282] = loc_alert_class_shadowed_2_gated_we; + reg_we_check[283] = loc_alert_class_shadowed_3_gated_we; + reg_we_check[284] = loc_alert_class_shadowed_4_gated_we; + reg_we_check[285] = loc_alert_class_shadowed_5_gated_we; + reg_we_check[286] = loc_alert_class_shadowed_6_gated_we; + reg_we_check[287] = loc_alert_cause_0_we; + reg_we_check[288] = loc_alert_cause_1_we; + reg_we_check[289] = loc_alert_cause_2_we; + reg_we_check[290] = loc_alert_cause_3_we; + reg_we_check[291] = loc_alert_cause_4_we; + reg_we_check[292] = loc_alert_cause_5_we; + reg_we_check[293] = loc_alert_cause_6_we; + reg_we_check[294] = classa_regwen_we; + reg_we_check[295] = classa_ctrl_shadowed_gated_we; + reg_we_check[296] = classa_clr_regwen_we; + reg_we_check[297] = classa_clr_shadowed_gated_we; reg_we_check[298] = 1'b0; - reg_we_check[299] = 1'b0; - reg_we_check[300] = classb_regwen_we; - reg_we_check[301] = classb_ctrl_shadowed_gated_we; - reg_we_check[302] = classb_clr_regwen_we; - reg_we_check[303] = classb_clr_shadowed_gated_we; - reg_we_check[304] = 1'b0; - reg_we_check[305] = classb_accum_thresh_shadowed_gated_we; - reg_we_check[306] = classb_timeout_cyc_shadowed_gated_we; - reg_we_check[307] = classb_crashdump_trigger_shadowed_gated_we; - reg_we_check[308] = classb_phase0_cyc_shadowed_gated_we; - reg_we_check[309] = classb_phase1_cyc_shadowed_gated_we; - reg_we_check[310] = classb_phase2_cyc_shadowed_gated_we; - reg_we_check[311] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[299] = classa_accum_thresh_shadowed_gated_we; + reg_we_check[300] = classa_timeout_cyc_shadowed_gated_we; + reg_we_check[301] = classa_crashdump_trigger_shadowed_gated_we; + reg_we_check[302] = classa_phase0_cyc_shadowed_gated_we; + reg_we_check[303] = classa_phase1_cyc_shadowed_gated_we; + reg_we_check[304] = classa_phase2_cyc_shadowed_gated_we; + reg_we_check[305] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[306] = 1'b0; + reg_we_check[307] = 1'b0; + reg_we_check[308] = classb_regwen_we; + reg_we_check[309] = classb_ctrl_shadowed_gated_we; + reg_we_check[310] = classb_clr_regwen_we; + reg_we_check[311] = classb_clr_shadowed_gated_we; reg_we_check[312] = 1'b0; - reg_we_check[313] = 1'b0; - reg_we_check[314] = classc_regwen_we; - reg_we_check[315] = classc_ctrl_shadowed_gated_we; - reg_we_check[316] = classc_clr_regwen_we; - reg_we_check[317] = classc_clr_shadowed_gated_we; - reg_we_check[318] = 1'b0; - reg_we_check[319] = classc_accum_thresh_shadowed_gated_we; - reg_we_check[320] = classc_timeout_cyc_shadowed_gated_we; - reg_we_check[321] = classc_crashdump_trigger_shadowed_gated_we; - reg_we_check[322] = classc_phase0_cyc_shadowed_gated_we; - reg_we_check[323] = classc_phase1_cyc_shadowed_gated_we; - reg_we_check[324] = classc_phase2_cyc_shadowed_gated_we; - reg_we_check[325] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[313] = classb_accum_thresh_shadowed_gated_we; + reg_we_check[314] = classb_timeout_cyc_shadowed_gated_we; + reg_we_check[315] = classb_crashdump_trigger_shadowed_gated_we; + reg_we_check[316] = classb_phase0_cyc_shadowed_gated_we; + reg_we_check[317] = classb_phase1_cyc_shadowed_gated_we; + reg_we_check[318] = classb_phase2_cyc_shadowed_gated_we; + reg_we_check[319] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[320] = 1'b0; + reg_we_check[321] = 1'b0; + reg_we_check[322] = classc_regwen_we; + reg_we_check[323] = classc_ctrl_shadowed_gated_we; + reg_we_check[324] = classc_clr_regwen_we; + reg_we_check[325] = classc_clr_shadowed_gated_we; reg_we_check[326] = 1'b0; - reg_we_check[327] = 1'b0; - reg_we_check[328] = classd_regwen_we; - reg_we_check[329] = classd_ctrl_shadowed_gated_we; - reg_we_check[330] = classd_clr_regwen_we; - reg_we_check[331] = classd_clr_shadowed_gated_we; - reg_we_check[332] = 1'b0; - reg_we_check[333] = classd_accum_thresh_shadowed_gated_we; - reg_we_check[334] = classd_timeout_cyc_shadowed_gated_we; - reg_we_check[335] = classd_crashdump_trigger_shadowed_gated_we; - reg_we_check[336] = classd_phase0_cyc_shadowed_gated_we; - reg_we_check[337] = classd_phase1_cyc_shadowed_gated_we; - reg_we_check[338] = classd_phase2_cyc_shadowed_gated_we; - reg_we_check[339] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[327] = classc_accum_thresh_shadowed_gated_we; + reg_we_check[328] = classc_timeout_cyc_shadowed_gated_we; + reg_we_check[329] = classc_crashdump_trigger_shadowed_gated_we; + reg_we_check[330] = classc_phase0_cyc_shadowed_gated_we; + reg_we_check[331] = classc_phase1_cyc_shadowed_gated_we; + reg_we_check[332] = classc_phase2_cyc_shadowed_gated_we; + reg_we_check[333] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[334] = 1'b0; + reg_we_check[335] = 1'b0; + reg_we_check[336] = classd_regwen_we; + reg_we_check[337] = classd_ctrl_shadowed_gated_we; + reg_we_check[338] = classd_clr_regwen_we; + reg_we_check[339] = classd_clr_shadowed_gated_we; reg_we_check[340] = 1'b0; - reg_we_check[341] = 1'b0; + reg_we_check[341] = classd_accum_thresh_shadowed_gated_we; + reg_we_check[342] = classd_timeout_cyc_shadowed_gated_we; + reg_we_check[343] = classd_crashdump_trigger_shadowed_gated_we; + reg_we_check[344] = classd_phase0_cyc_shadowed_gated_we; + reg_we_check[345] = classd_phase1_cyc_shadowed_gated_we; + reg_we_check[346] = classd_phase2_cyc_shadowed_gated_we; + reg_we_check[347] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[348] = 1'b0; + reg_we_check[349] = 1'b0; end // Read data return @@ -17849,878 +18217,910 @@ module alert_handler_reg_top ( end addr_hit[69]: begin - reg_rdata_next[0] = alert_en_shadowed_0_qs; + reg_rdata_next[0] = alert_regwen_63_qs; end addr_hit[70]: begin - reg_rdata_next[0] = alert_en_shadowed_1_qs; + reg_rdata_next[0] = alert_regwen_64_qs; end addr_hit[71]: begin - reg_rdata_next[0] = alert_en_shadowed_2_qs; + reg_rdata_next[0] = alert_en_shadowed_0_qs; end addr_hit[72]: begin - reg_rdata_next[0] = alert_en_shadowed_3_qs; + reg_rdata_next[0] = alert_en_shadowed_1_qs; end addr_hit[73]: begin - reg_rdata_next[0] = alert_en_shadowed_4_qs; + reg_rdata_next[0] = alert_en_shadowed_2_qs; end addr_hit[74]: begin - reg_rdata_next[0] = alert_en_shadowed_5_qs; + reg_rdata_next[0] = alert_en_shadowed_3_qs; end addr_hit[75]: begin - reg_rdata_next[0] = alert_en_shadowed_6_qs; + reg_rdata_next[0] = alert_en_shadowed_4_qs; end addr_hit[76]: begin - reg_rdata_next[0] = alert_en_shadowed_7_qs; + reg_rdata_next[0] = alert_en_shadowed_5_qs; end addr_hit[77]: begin - reg_rdata_next[0] = alert_en_shadowed_8_qs; + reg_rdata_next[0] = alert_en_shadowed_6_qs; end addr_hit[78]: begin - reg_rdata_next[0] = alert_en_shadowed_9_qs; + reg_rdata_next[0] = alert_en_shadowed_7_qs; end addr_hit[79]: begin - reg_rdata_next[0] = alert_en_shadowed_10_qs; + reg_rdata_next[0] = alert_en_shadowed_8_qs; end addr_hit[80]: begin - reg_rdata_next[0] = alert_en_shadowed_11_qs; + reg_rdata_next[0] = alert_en_shadowed_9_qs; end addr_hit[81]: begin - reg_rdata_next[0] = alert_en_shadowed_12_qs; + reg_rdata_next[0] = alert_en_shadowed_10_qs; end addr_hit[82]: begin - reg_rdata_next[0] = alert_en_shadowed_13_qs; + reg_rdata_next[0] = alert_en_shadowed_11_qs; end addr_hit[83]: begin - reg_rdata_next[0] = alert_en_shadowed_14_qs; + reg_rdata_next[0] = alert_en_shadowed_12_qs; end addr_hit[84]: begin - reg_rdata_next[0] = alert_en_shadowed_15_qs; + reg_rdata_next[0] = alert_en_shadowed_13_qs; end addr_hit[85]: begin - reg_rdata_next[0] = alert_en_shadowed_16_qs; + reg_rdata_next[0] = alert_en_shadowed_14_qs; end addr_hit[86]: begin - reg_rdata_next[0] = alert_en_shadowed_17_qs; + reg_rdata_next[0] = alert_en_shadowed_15_qs; end addr_hit[87]: begin - reg_rdata_next[0] = alert_en_shadowed_18_qs; + reg_rdata_next[0] = alert_en_shadowed_16_qs; end addr_hit[88]: begin - reg_rdata_next[0] = alert_en_shadowed_19_qs; + reg_rdata_next[0] = alert_en_shadowed_17_qs; end addr_hit[89]: begin - reg_rdata_next[0] = alert_en_shadowed_20_qs; + reg_rdata_next[0] = alert_en_shadowed_18_qs; end addr_hit[90]: begin - reg_rdata_next[0] = alert_en_shadowed_21_qs; + reg_rdata_next[0] = alert_en_shadowed_19_qs; end addr_hit[91]: begin - reg_rdata_next[0] = alert_en_shadowed_22_qs; + reg_rdata_next[0] = alert_en_shadowed_20_qs; end addr_hit[92]: begin - reg_rdata_next[0] = alert_en_shadowed_23_qs; + reg_rdata_next[0] = alert_en_shadowed_21_qs; end addr_hit[93]: begin - reg_rdata_next[0] = alert_en_shadowed_24_qs; + reg_rdata_next[0] = alert_en_shadowed_22_qs; end addr_hit[94]: begin - reg_rdata_next[0] = alert_en_shadowed_25_qs; + reg_rdata_next[0] = alert_en_shadowed_23_qs; end addr_hit[95]: begin - reg_rdata_next[0] = alert_en_shadowed_26_qs; + reg_rdata_next[0] = alert_en_shadowed_24_qs; end addr_hit[96]: begin - reg_rdata_next[0] = alert_en_shadowed_27_qs; + reg_rdata_next[0] = alert_en_shadowed_25_qs; end addr_hit[97]: begin - reg_rdata_next[0] = alert_en_shadowed_28_qs; + reg_rdata_next[0] = alert_en_shadowed_26_qs; end addr_hit[98]: begin - reg_rdata_next[0] = alert_en_shadowed_29_qs; + reg_rdata_next[0] = alert_en_shadowed_27_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_en_shadowed_30_qs; + reg_rdata_next[0] = alert_en_shadowed_28_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_en_shadowed_31_qs; + reg_rdata_next[0] = alert_en_shadowed_29_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_en_shadowed_32_qs; + reg_rdata_next[0] = alert_en_shadowed_30_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_en_shadowed_33_qs; + reg_rdata_next[0] = alert_en_shadowed_31_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_en_shadowed_34_qs; + reg_rdata_next[0] = alert_en_shadowed_32_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_en_shadowed_35_qs; + reg_rdata_next[0] = alert_en_shadowed_33_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_en_shadowed_36_qs; + reg_rdata_next[0] = alert_en_shadowed_34_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_en_shadowed_37_qs; + reg_rdata_next[0] = alert_en_shadowed_35_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_en_shadowed_38_qs; + reg_rdata_next[0] = alert_en_shadowed_36_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_en_shadowed_39_qs; + reg_rdata_next[0] = alert_en_shadowed_37_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_en_shadowed_40_qs; + reg_rdata_next[0] = alert_en_shadowed_38_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_en_shadowed_41_qs; + reg_rdata_next[0] = alert_en_shadowed_39_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_en_shadowed_42_qs; + reg_rdata_next[0] = alert_en_shadowed_40_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_en_shadowed_43_qs; + reg_rdata_next[0] = alert_en_shadowed_41_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_en_shadowed_44_qs; + reg_rdata_next[0] = alert_en_shadowed_42_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_en_shadowed_45_qs; + reg_rdata_next[0] = alert_en_shadowed_43_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_en_shadowed_46_qs; + reg_rdata_next[0] = alert_en_shadowed_44_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_en_shadowed_47_qs; + reg_rdata_next[0] = alert_en_shadowed_45_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_en_shadowed_48_qs; + reg_rdata_next[0] = alert_en_shadowed_46_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_en_shadowed_49_qs; + reg_rdata_next[0] = alert_en_shadowed_47_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_en_shadowed_50_qs; + reg_rdata_next[0] = alert_en_shadowed_48_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_en_shadowed_51_qs; + reg_rdata_next[0] = alert_en_shadowed_49_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_en_shadowed_52_qs; + reg_rdata_next[0] = alert_en_shadowed_50_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_en_shadowed_53_qs; + reg_rdata_next[0] = alert_en_shadowed_51_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_en_shadowed_54_qs; + reg_rdata_next[0] = alert_en_shadowed_52_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_en_shadowed_55_qs; + reg_rdata_next[0] = alert_en_shadowed_53_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_en_shadowed_56_qs; + reg_rdata_next[0] = alert_en_shadowed_54_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_en_shadowed_57_qs; + reg_rdata_next[0] = alert_en_shadowed_55_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_en_shadowed_58_qs; + reg_rdata_next[0] = alert_en_shadowed_56_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_en_shadowed_59_qs; + reg_rdata_next[0] = alert_en_shadowed_57_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_en_shadowed_60_qs; + reg_rdata_next[0] = alert_en_shadowed_58_qs; end addr_hit[130]: begin - reg_rdata_next[0] = alert_en_shadowed_61_qs; + reg_rdata_next[0] = alert_en_shadowed_59_qs; end addr_hit[131]: begin - reg_rdata_next[0] = alert_en_shadowed_62_qs; + reg_rdata_next[0] = alert_en_shadowed_60_qs; end addr_hit[132]: begin - reg_rdata_next[1:0] = alert_class_shadowed_0_qs; + reg_rdata_next[0] = alert_en_shadowed_61_qs; end addr_hit[133]: begin - reg_rdata_next[1:0] = alert_class_shadowed_1_qs; + reg_rdata_next[0] = alert_en_shadowed_62_qs; end addr_hit[134]: begin - reg_rdata_next[1:0] = alert_class_shadowed_2_qs; + reg_rdata_next[0] = alert_en_shadowed_63_qs; end addr_hit[135]: begin - reg_rdata_next[1:0] = alert_class_shadowed_3_qs; + reg_rdata_next[0] = alert_en_shadowed_64_qs; end addr_hit[136]: begin - reg_rdata_next[1:0] = alert_class_shadowed_4_qs; + reg_rdata_next[1:0] = alert_class_shadowed_0_qs; end addr_hit[137]: begin - reg_rdata_next[1:0] = alert_class_shadowed_5_qs; + reg_rdata_next[1:0] = alert_class_shadowed_1_qs; end addr_hit[138]: begin - reg_rdata_next[1:0] = alert_class_shadowed_6_qs; + reg_rdata_next[1:0] = alert_class_shadowed_2_qs; end addr_hit[139]: begin - reg_rdata_next[1:0] = alert_class_shadowed_7_qs; + reg_rdata_next[1:0] = alert_class_shadowed_3_qs; end addr_hit[140]: begin - reg_rdata_next[1:0] = alert_class_shadowed_8_qs; + reg_rdata_next[1:0] = alert_class_shadowed_4_qs; end addr_hit[141]: begin - reg_rdata_next[1:0] = alert_class_shadowed_9_qs; + reg_rdata_next[1:0] = alert_class_shadowed_5_qs; end addr_hit[142]: begin - reg_rdata_next[1:0] = alert_class_shadowed_10_qs; + reg_rdata_next[1:0] = alert_class_shadowed_6_qs; end addr_hit[143]: begin - reg_rdata_next[1:0] = alert_class_shadowed_11_qs; + reg_rdata_next[1:0] = alert_class_shadowed_7_qs; end addr_hit[144]: begin - reg_rdata_next[1:0] = alert_class_shadowed_12_qs; + reg_rdata_next[1:0] = alert_class_shadowed_8_qs; end addr_hit[145]: begin - reg_rdata_next[1:0] = alert_class_shadowed_13_qs; + reg_rdata_next[1:0] = alert_class_shadowed_9_qs; end addr_hit[146]: begin - reg_rdata_next[1:0] = alert_class_shadowed_14_qs; + reg_rdata_next[1:0] = alert_class_shadowed_10_qs; end addr_hit[147]: begin - reg_rdata_next[1:0] = alert_class_shadowed_15_qs; + reg_rdata_next[1:0] = alert_class_shadowed_11_qs; end addr_hit[148]: begin - reg_rdata_next[1:0] = alert_class_shadowed_16_qs; + reg_rdata_next[1:0] = alert_class_shadowed_12_qs; end addr_hit[149]: begin - reg_rdata_next[1:0] = alert_class_shadowed_17_qs; + reg_rdata_next[1:0] = alert_class_shadowed_13_qs; end addr_hit[150]: begin - reg_rdata_next[1:0] = alert_class_shadowed_18_qs; + reg_rdata_next[1:0] = alert_class_shadowed_14_qs; end addr_hit[151]: begin - reg_rdata_next[1:0] = alert_class_shadowed_19_qs; + reg_rdata_next[1:0] = alert_class_shadowed_15_qs; end addr_hit[152]: begin - reg_rdata_next[1:0] = alert_class_shadowed_20_qs; + reg_rdata_next[1:0] = alert_class_shadowed_16_qs; end addr_hit[153]: begin - reg_rdata_next[1:0] = alert_class_shadowed_21_qs; + reg_rdata_next[1:0] = alert_class_shadowed_17_qs; end addr_hit[154]: begin - reg_rdata_next[1:0] = alert_class_shadowed_22_qs; + reg_rdata_next[1:0] = alert_class_shadowed_18_qs; end addr_hit[155]: begin - reg_rdata_next[1:0] = alert_class_shadowed_23_qs; + reg_rdata_next[1:0] = alert_class_shadowed_19_qs; end addr_hit[156]: begin - reg_rdata_next[1:0] = alert_class_shadowed_24_qs; + reg_rdata_next[1:0] = alert_class_shadowed_20_qs; end addr_hit[157]: begin - reg_rdata_next[1:0] = alert_class_shadowed_25_qs; + reg_rdata_next[1:0] = alert_class_shadowed_21_qs; end addr_hit[158]: begin - reg_rdata_next[1:0] = alert_class_shadowed_26_qs; + reg_rdata_next[1:0] = alert_class_shadowed_22_qs; end addr_hit[159]: begin - reg_rdata_next[1:0] = alert_class_shadowed_27_qs; + reg_rdata_next[1:0] = alert_class_shadowed_23_qs; end addr_hit[160]: begin - reg_rdata_next[1:0] = alert_class_shadowed_28_qs; + reg_rdata_next[1:0] = alert_class_shadowed_24_qs; end addr_hit[161]: begin - reg_rdata_next[1:0] = alert_class_shadowed_29_qs; + reg_rdata_next[1:0] = alert_class_shadowed_25_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = alert_class_shadowed_30_qs; + reg_rdata_next[1:0] = alert_class_shadowed_26_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = alert_class_shadowed_31_qs; + reg_rdata_next[1:0] = alert_class_shadowed_27_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = alert_class_shadowed_32_qs; + reg_rdata_next[1:0] = alert_class_shadowed_28_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = alert_class_shadowed_33_qs; + reg_rdata_next[1:0] = alert_class_shadowed_29_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = alert_class_shadowed_34_qs; + reg_rdata_next[1:0] = alert_class_shadowed_30_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = alert_class_shadowed_35_qs; + reg_rdata_next[1:0] = alert_class_shadowed_31_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = alert_class_shadowed_36_qs; + reg_rdata_next[1:0] = alert_class_shadowed_32_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = alert_class_shadowed_37_qs; + reg_rdata_next[1:0] = alert_class_shadowed_33_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = alert_class_shadowed_38_qs; + reg_rdata_next[1:0] = alert_class_shadowed_34_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = alert_class_shadowed_39_qs; + reg_rdata_next[1:0] = alert_class_shadowed_35_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = alert_class_shadowed_40_qs; + reg_rdata_next[1:0] = alert_class_shadowed_36_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = alert_class_shadowed_41_qs; + reg_rdata_next[1:0] = alert_class_shadowed_37_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = alert_class_shadowed_42_qs; + reg_rdata_next[1:0] = alert_class_shadowed_38_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = alert_class_shadowed_43_qs; + reg_rdata_next[1:0] = alert_class_shadowed_39_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = alert_class_shadowed_44_qs; + reg_rdata_next[1:0] = alert_class_shadowed_40_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = alert_class_shadowed_45_qs; + reg_rdata_next[1:0] = alert_class_shadowed_41_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = alert_class_shadowed_46_qs; + reg_rdata_next[1:0] = alert_class_shadowed_42_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = alert_class_shadowed_47_qs; + reg_rdata_next[1:0] = alert_class_shadowed_43_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = alert_class_shadowed_48_qs; + reg_rdata_next[1:0] = alert_class_shadowed_44_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = alert_class_shadowed_49_qs; + reg_rdata_next[1:0] = alert_class_shadowed_45_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = alert_class_shadowed_50_qs; + reg_rdata_next[1:0] = alert_class_shadowed_46_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = alert_class_shadowed_51_qs; + reg_rdata_next[1:0] = alert_class_shadowed_47_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = alert_class_shadowed_52_qs; + reg_rdata_next[1:0] = alert_class_shadowed_48_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = alert_class_shadowed_53_qs; + reg_rdata_next[1:0] = alert_class_shadowed_49_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = alert_class_shadowed_54_qs; + reg_rdata_next[1:0] = alert_class_shadowed_50_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = alert_class_shadowed_55_qs; + reg_rdata_next[1:0] = alert_class_shadowed_51_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = alert_class_shadowed_56_qs; + reg_rdata_next[1:0] = alert_class_shadowed_52_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = alert_class_shadowed_57_qs; + reg_rdata_next[1:0] = alert_class_shadowed_53_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = alert_class_shadowed_58_qs; + reg_rdata_next[1:0] = alert_class_shadowed_54_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = alert_class_shadowed_59_qs; + reg_rdata_next[1:0] = alert_class_shadowed_55_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = alert_class_shadowed_60_qs; + reg_rdata_next[1:0] = alert_class_shadowed_56_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = alert_class_shadowed_61_qs; + reg_rdata_next[1:0] = alert_class_shadowed_57_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = alert_class_shadowed_62_qs; + reg_rdata_next[1:0] = alert_class_shadowed_58_qs; end addr_hit[195]: begin - reg_rdata_next[0] = alert_cause_0_qs; + reg_rdata_next[1:0] = alert_class_shadowed_59_qs; end addr_hit[196]: begin - reg_rdata_next[0] = alert_cause_1_qs; + reg_rdata_next[1:0] = alert_class_shadowed_60_qs; end addr_hit[197]: begin - reg_rdata_next[0] = alert_cause_2_qs; + reg_rdata_next[1:0] = alert_class_shadowed_61_qs; end addr_hit[198]: begin - reg_rdata_next[0] = alert_cause_3_qs; + reg_rdata_next[1:0] = alert_class_shadowed_62_qs; end addr_hit[199]: begin - reg_rdata_next[0] = alert_cause_4_qs; + reg_rdata_next[1:0] = alert_class_shadowed_63_qs; end addr_hit[200]: begin - reg_rdata_next[0] = alert_cause_5_qs; + reg_rdata_next[1:0] = alert_class_shadowed_64_qs; end addr_hit[201]: begin - reg_rdata_next[0] = alert_cause_6_qs; + reg_rdata_next[0] = alert_cause_0_qs; end addr_hit[202]: begin - reg_rdata_next[0] = alert_cause_7_qs; + reg_rdata_next[0] = alert_cause_1_qs; end addr_hit[203]: begin - reg_rdata_next[0] = alert_cause_8_qs; + reg_rdata_next[0] = alert_cause_2_qs; end addr_hit[204]: begin - reg_rdata_next[0] = alert_cause_9_qs; + reg_rdata_next[0] = alert_cause_3_qs; end addr_hit[205]: begin - reg_rdata_next[0] = alert_cause_10_qs; + reg_rdata_next[0] = alert_cause_4_qs; end addr_hit[206]: begin - reg_rdata_next[0] = alert_cause_11_qs; + reg_rdata_next[0] = alert_cause_5_qs; end addr_hit[207]: begin - reg_rdata_next[0] = alert_cause_12_qs; + reg_rdata_next[0] = alert_cause_6_qs; end addr_hit[208]: begin - reg_rdata_next[0] = alert_cause_13_qs; + reg_rdata_next[0] = alert_cause_7_qs; end addr_hit[209]: begin - reg_rdata_next[0] = alert_cause_14_qs; + reg_rdata_next[0] = alert_cause_8_qs; end addr_hit[210]: begin - reg_rdata_next[0] = alert_cause_15_qs; + reg_rdata_next[0] = alert_cause_9_qs; end addr_hit[211]: begin - reg_rdata_next[0] = alert_cause_16_qs; + reg_rdata_next[0] = alert_cause_10_qs; end addr_hit[212]: begin - reg_rdata_next[0] = alert_cause_17_qs; + reg_rdata_next[0] = alert_cause_11_qs; end addr_hit[213]: begin - reg_rdata_next[0] = alert_cause_18_qs; + reg_rdata_next[0] = alert_cause_12_qs; end addr_hit[214]: begin - reg_rdata_next[0] = alert_cause_19_qs; + reg_rdata_next[0] = alert_cause_13_qs; end addr_hit[215]: begin - reg_rdata_next[0] = alert_cause_20_qs; + reg_rdata_next[0] = alert_cause_14_qs; end addr_hit[216]: begin - reg_rdata_next[0] = alert_cause_21_qs; + reg_rdata_next[0] = alert_cause_15_qs; end addr_hit[217]: begin - reg_rdata_next[0] = alert_cause_22_qs; + reg_rdata_next[0] = alert_cause_16_qs; end addr_hit[218]: begin - reg_rdata_next[0] = alert_cause_23_qs; + reg_rdata_next[0] = alert_cause_17_qs; end addr_hit[219]: begin - reg_rdata_next[0] = alert_cause_24_qs; + reg_rdata_next[0] = alert_cause_18_qs; end addr_hit[220]: begin - reg_rdata_next[0] = alert_cause_25_qs; + reg_rdata_next[0] = alert_cause_19_qs; end addr_hit[221]: begin - reg_rdata_next[0] = alert_cause_26_qs; + reg_rdata_next[0] = alert_cause_20_qs; end addr_hit[222]: begin - reg_rdata_next[0] = alert_cause_27_qs; + reg_rdata_next[0] = alert_cause_21_qs; end addr_hit[223]: begin - reg_rdata_next[0] = alert_cause_28_qs; + reg_rdata_next[0] = alert_cause_22_qs; end addr_hit[224]: begin - reg_rdata_next[0] = alert_cause_29_qs; + reg_rdata_next[0] = alert_cause_23_qs; end addr_hit[225]: begin - reg_rdata_next[0] = alert_cause_30_qs; + reg_rdata_next[0] = alert_cause_24_qs; end addr_hit[226]: begin - reg_rdata_next[0] = alert_cause_31_qs; + reg_rdata_next[0] = alert_cause_25_qs; end addr_hit[227]: begin - reg_rdata_next[0] = alert_cause_32_qs; + reg_rdata_next[0] = alert_cause_26_qs; end addr_hit[228]: begin - reg_rdata_next[0] = alert_cause_33_qs; + reg_rdata_next[0] = alert_cause_27_qs; end addr_hit[229]: begin - reg_rdata_next[0] = alert_cause_34_qs; + reg_rdata_next[0] = alert_cause_28_qs; end addr_hit[230]: begin - reg_rdata_next[0] = alert_cause_35_qs; + reg_rdata_next[0] = alert_cause_29_qs; end addr_hit[231]: begin - reg_rdata_next[0] = alert_cause_36_qs; + reg_rdata_next[0] = alert_cause_30_qs; end addr_hit[232]: begin - reg_rdata_next[0] = alert_cause_37_qs; + reg_rdata_next[0] = alert_cause_31_qs; end addr_hit[233]: begin - reg_rdata_next[0] = alert_cause_38_qs; + reg_rdata_next[0] = alert_cause_32_qs; end addr_hit[234]: begin - reg_rdata_next[0] = alert_cause_39_qs; + reg_rdata_next[0] = alert_cause_33_qs; end addr_hit[235]: begin - reg_rdata_next[0] = alert_cause_40_qs; + reg_rdata_next[0] = alert_cause_34_qs; end addr_hit[236]: begin - reg_rdata_next[0] = alert_cause_41_qs; + reg_rdata_next[0] = alert_cause_35_qs; end addr_hit[237]: begin - reg_rdata_next[0] = alert_cause_42_qs; + reg_rdata_next[0] = alert_cause_36_qs; end addr_hit[238]: begin - reg_rdata_next[0] = alert_cause_43_qs; + reg_rdata_next[0] = alert_cause_37_qs; end addr_hit[239]: begin - reg_rdata_next[0] = alert_cause_44_qs; + reg_rdata_next[0] = alert_cause_38_qs; end addr_hit[240]: begin - reg_rdata_next[0] = alert_cause_45_qs; + reg_rdata_next[0] = alert_cause_39_qs; end addr_hit[241]: begin - reg_rdata_next[0] = alert_cause_46_qs; + reg_rdata_next[0] = alert_cause_40_qs; end addr_hit[242]: begin - reg_rdata_next[0] = alert_cause_47_qs; + reg_rdata_next[0] = alert_cause_41_qs; end addr_hit[243]: begin - reg_rdata_next[0] = alert_cause_48_qs; + reg_rdata_next[0] = alert_cause_42_qs; end addr_hit[244]: begin - reg_rdata_next[0] = alert_cause_49_qs; + reg_rdata_next[0] = alert_cause_43_qs; end addr_hit[245]: begin - reg_rdata_next[0] = alert_cause_50_qs; + reg_rdata_next[0] = alert_cause_44_qs; end addr_hit[246]: begin - reg_rdata_next[0] = alert_cause_51_qs; + reg_rdata_next[0] = alert_cause_45_qs; end addr_hit[247]: begin - reg_rdata_next[0] = alert_cause_52_qs; + reg_rdata_next[0] = alert_cause_46_qs; end addr_hit[248]: begin - reg_rdata_next[0] = alert_cause_53_qs; + reg_rdata_next[0] = alert_cause_47_qs; end addr_hit[249]: begin - reg_rdata_next[0] = alert_cause_54_qs; + reg_rdata_next[0] = alert_cause_48_qs; end addr_hit[250]: begin - reg_rdata_next[0] = alert_cause_55_qs; + reg_rdata_next[0] = alert_cause_49_qs; end addr_hit[251]: begin - reg_rdata_next[0] = alert_cause_56_qs; + reg_rdata_next[0] = alert_cause_50_qs; end addr_hit[252]: begin - reg_rdata_next[0] = alert_cause_57_qs; + reg_rdata_next[0] = alert_cause_51_qs; end addr_hit[253]: begin - reg_rdata_next[0] = alert_cause_58_qs; + reg_rdata_next[0] = alert_cause_52_qs; end addr_hit[254]: begin - reg_rdata_next[0] = alert_cause_59_qs; + reg_rdata_next[0] = alert_cause_53_qs; end addr_hit[255]: begin - reg_rdata_next[0] = alert_cause_60_qs; + reg_rdata_next[0] = alert_cause_54_qs; end addr_hit[256]: begin - reg_rdata_next[0] = alert_cause_61_qs; + reg_rdata_next[0] = alert_cause_55_qs; end addr_hit[257]: begin - reg_rdata_next[0] = alert_cause_62_qs; + reg_rdata_next[0] = alert_cause_56_qs; end addr_hit[258]: begin - reg_rdata_next[0] = loc_alert_regwen_0_qs; + reg_rdata_next[0] = alert_cause_57_qs; end addr_hit[259]: begin - reg_rdata_next[0] = loc_alert_regwen_1_qs; + reg_rdata_next[0] = alert_cause_58_qs; end addr_hit[260]: begin - reg_rdata_next[0] = loc_alert_regwen_2_qs; + reg_rdata_next[0] = alert_cause_59_qs; end addr_hit[261]: begin - reg_rdata_next[0] = loc_alert_regwen_3_qs; + reg_rdata_next[0] = alert_cause_60_qs; end addr_hit[262]: begin - reg_rdata_next[0] = loc_alert_regwen_4_qs; + reg_rdata_next[0] = alert_cause_61_qs; end addr_hit[263]: begin - reg_rdata_next[0] = loc_alert_regwen_5_qs; + reg_rdata_next[0] = alert_cause_62_qs; end addr_hit[264]: begin - reg_rdata_next[0] = loc_alert_regwen_6_qs; + reg_rdata_next[0] = alert_cause_63_qs; end addr_hit[265]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; + reg_rdata_next[0] = alert_cause_64_qs; end addr_hit[266]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; + reg_rdata_next[0] = loc_alert_regwen_0_qs; end addr_hit[267]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; + reg_rdata_next[0] = loc_alert_regwen_1_qs; end addr_hit[268]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; + reg_rdata_next[0] = loc_alert_regwen_2_qs; end addr_hit[269]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; + reg_rdata_next[0] = loc_alert_regwen_3_qs; end addr_hit[270]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; + reg_rdata_next[0] = loc_alert_regwen_4_qs; end addr_hit[271]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; + reg_rdata_next[0] = loc_alert_regwen_5_qs; end addr_hit[272]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; + reg_rdata_next[0] = loc_alert_regwen_6_qs; end addr_hit[273]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; end addr_hit[274]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; end addr_hit[275]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; end addr_hit[276]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; end addr_hit[277]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; end addr_hit[278]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; end addr_hit[279]: begin - reg_rdata_next[0] = loc_alert_cause_0_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; end addr_hit[280]: begin - reg_rdata_next[0] = loc_alert_cause_1_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; end addr_hit[281]: begin - reg_rdata_next[0] = loc_alert_cause_2_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; end addr_hit[282]: begin - reg_rdata_next[0] = loc_alert_cause_3_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; end addr_hit[283]: begin - reg_rdata_next[0] = loc_alert_cause_4_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; end addr_hit[284]: begin - reg_rdata_next[0] = loc_alert_cause_5_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; end addr_hit[285]: begin - reg_rdata_next[0] = loc_alert_cause_6_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; end addr_hit[286]: begin - reg_rdata_next[0] = classa_regwen_qs; + reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; end addr_hit[287]: begin + reg_rdata_next[0] = loc_alert_cause_0_qs; + end + + addr_hit[288]: begin + reg_rdata_next[0] = loc_alert_cause_1_qs; + end + + addr_hit[289]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[290]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[291]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[292]: begin + reg_rdata_next[0] = loc_alert_cause_5_qs; + end + + addr_hit[293]: begin + reg_rdata_next[0] = loc_alert_cause_6_qs; + end + + addr_hit[294]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[295]: begin reg_rdata_next[0] = classa_ctrl_shadowed_en_qs; reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs; @@ -18733,59 +19133,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs; end - addr_hit[288]: begin + addr_hit[296]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[289]: begin + addr_hit[297]: begin reg_rdata_next[0] = classa_clr_shadowed_qs; end - addr_hit[290]: begin + addr_hit[298]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[291]: begin + addr_hit[299]: begin reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs; end - addr_hit[292]: begin + addr_hit[300]: begin reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs; end - addr_hit[293]: begin + addr_hit[301]: begin reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs; end - addr_hit[294]: begin + addr_hit[302]: begin reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs; end - addr_hit[295]: begin + addr_hit[303]: begin reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs; end - addr_hit[296]: begin + addr_hit[304]: begin reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs; end - addr_hit[297]: begin + addr_hit[305]: begin reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs; end - addr_hit[298]: begin + addr_hit[306]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[299]: begin + addr_hit[307]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[300]: begin + addr_hit[308]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[301]: begin + addr_hit[309]: begin reg_rdata_next[0] = classb_ctrl_shadowed_en_qs; reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs; @@ -18798,59 +19198,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs; end - addr_hit[302]: begin + addr_hit[310]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[303]: begin + addr_hit[311]: begin reg_rdata_next[0] = classb_clr_shadowed_qs; end - addr_hit[304]: begin + addr_hit[312]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[305]: begin + addr_hit[313]: begin reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs; end - addr_hit[306]: begin + addr_hit[314]: begin reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs; end - addr_hit[307]: begin + addr_hit[315]: begin reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs; end - addr_hit[308]: begin + addr_hit[316]: begin reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs; end - addr_hit[309]: begin + addr_hit[317]: begin reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs; end - addr_hit[310]: begin + addr_hit[318]: begin reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs; end - addr_hit[311]: begin + addr_hit[319]: begin reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs; end - addr_hit[312]: begin + addr_hit[320]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[313]: begin + addr_hit[321]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[314]: begin + addr_hit[322]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[315]: begin + addr_hit[323]: begin reg_rdata_next[0] = classc_ctrl_shadowed_en_qs; reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs; @@ -18863,59 +19263,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs; end - addr_hit[316]: begin + addr_hit[324]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[317]: begin + addr_hit[325]: begin reg_rdata_next[0] = classc_clr_shadowed_qs; end - addr_hit[318]: begin + addr_hit[326]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[319]: begin + addr_hit[327]: begin reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs; end - addr_hit[320]: begin + addr_hit[328]: begin reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs; end - addr_hit[321]: begin + addr_hit[329]: begin reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs; end - addr_hit[322]: begin + addr_hit[330]: begin reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs; end - addr_hit[323]: begin + addr_hit[331]: begin reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs; end - addr_hit[324]: begin + addr_hit[332]: begin reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs; end - addr_hit[325]: begin + addr_hit[333]: begin reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs; end - addr_hit[326]: begin + addr_hit[334]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[327]: begin + addr_hit[335]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[328]: begin + addr_hit[336]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[329]: begin + addr_hit[337]: begin reg_rdata_next[0] = classd_ctrl_shadowed_en_qs; reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs; @@ -18928,51 +19328,51 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs; end - addr_hit[330]: begin + addr_hit[338]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[331]: begin + addr_hit[339]: begin reg_rdata_next[0] = classd_clr_shadowed_qs; end - addr_hit[332]: begin + addr_hit[340]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[333]: begin + addr_hit[341]: begin reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs; end - addr_hit[334]: begin + addr_hit[342]: begin reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs; end - addr_hit[335]: begin + addr_hit[343]: begin reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs; end - addr_hit[336]: begin + addr_hit[344]: begin reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs; end - addr_hit[337]: begin + addr_hit[345]: begin reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs; end - addr_hit[338]: begin + addr_hit[346]: begin reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs; end - addr_hit[339]: begin + addr_hit[347]: begin reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs; end - addr_hit[340]: begin + addr_hit[348]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[341]: begin + addr_hit[349]: begin reg_rdata_next[2:0] = classd_state_qs; end @@ -19072,6 +19472,8 @@ module alert_handler_reg_top ( alert_en_shadowed_60_storage_err, alert_en_shadowed_61_storage_err, alert_en_shadowed_62_storage_err, + alert_en_shadowed_63_storage_err, + alert_en_shadowed_64_storage_err, alert_class_shadowed_0_storage_err, alert_class_shadowed_1_storage_err, alert_class_shadowed_2_storage_err, @@ -19135,6 +19537,8 @@ module alert_handler_reg_top ( alert_class_shadowed_60_storage_err, alert_class_shadowed_61_storage_err, alert_class_shadowed_62_storage_err, + alert_class_shadowed_63_storage_err, + alert_class_shadowed_64_storage_err, loc_alert_en_shadowed_0_storage_err, loc_alert_en_shadowed_1_storage_err, loc_alert_en_shadowed_2_storage_err, @@ -19288,6 +19692,8 @@ module alert_handler_reg_top ( alert_en_shadowed_60_update_err, alert_en_shadowed_61_update_err, alert_en_shadowed_62_update_err, + alert_en_shadowed_63_update_err, + alert_en_shadowed_64_update_err, alert_class_shadowed_0_update_err, alert_class_shadowed_1_update_err, alert_class_shadowed_2_update_err, @@ -19351,6 +19757,8 @@ module alert_handler_reg_top ( alert_class_shadowed_60_update_err, alert_class_shadowed_61_update_err, alert_class_shadowed_62_update_err, + alert_class_shadowed_63_update_err, + alert_class_shadowed_64_update_err, loc_alert_en_shadowed_0_update_err, loc_alert_en_shadowed_1_update_err, loc_alert_en_shadowed_2_update_err, diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson b/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson index 4670c106d457a..cebbfd70fbb30 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson @@ -46,7 +46,6 @@ ], bus_interfaces: [ { protocol: "tlul", direction: "host", name: "corei" } - { protocol: "tlul", direction: "host", name: "cored" } { protocol: "tlul", direction: "device", name: "cfg" } ], scan: "true", // Enable `scanmode_i` port @@ -81,6 +80,51 @@ package: "", }, + { struct: "mubi4", + type: "uni", + name: "cheriot_ena", + act: "req", + package: "prim_mubi_pkg", + default: "prim_mubi_pkg::MuBi4False", + desc: "CHERIoT mode enable." + }, + + { struct: "tl", + type: "req_rsp", + name: "cored_tl_h", + act: "req", + package: "tlul_pkg", + desc: "Core data host port to CHERIoT subsystem" + }, + + { struct: "logic", + type: "uni", + name: "cored_tag_h2d", + act: "req", + width: "1", + package: "", + default: "1'b0", + desc: "CHERIoT capability tag carried with the A-channel of cored_h." + }, + + { struct: "logic", + type: "uni", + name: "cored_tag_d2h", + act: "rcv", + width: "1", + package: "", + default: "1'b0", + desc: "Capability tag returned on the D-channel of cored_h." + }, + + { struct: "tl", + type: "req_rsp", + name: "corerevbm_tl", + act: "req", + package: "tlul_pkg", + desc: "Core revocation bitmap host port" + }, + { struct: "ram_1p_cfg", type: "uni", name: "ram_cfg_icache_tag", @@ -331,6 +375,34 @@ local: "false" expose: "true" }, + { name: "BaseIsa" + type: "ibex_pkg::base_isa_e" + default: "ibex_pkg::BaseIsaRV32I" + desc: "Base ISA" + local: "false" + expose: "true" + }, + { name: "CheriotRevBitmapAddrWidth" + type: "int unsigned" + default: "9" + desc: "Address width of the TRVK revocation bitmap" + local: "false" + expose: "true" + }, + { name: "CheriotRevBitmapBaseAddr" + type: "int unsigned" + default: "0" + desc: "Base address of the TRVK revocation bitmap" + local: "false" + expose: "true" + }, + { name: "CheriotTrvkHeapBaseAddr" + type: "int unsigned" + default: "0" + desc: "Base address of the heap" + local: "false" + expose: "true" + }, { name: "RV32E" type: "bit" default: "0" @@ -667,6 +739,11 @@ { name: "ICACHE.MEM.INTEGRITY" desc: "ICache memory integrity checking." } + { name: "CHERIOT_SWITCH.FSM.SPARSE" + desc: ''' + The write-once ePMP/CHERIoT execution mode switch FSM is sparsely encoded. + ''' + } ] regwidth: "32", @@ -1079,6 +1156,40 @@ ] }, + { name: "CHERIOT_ENA", + desc: ''' + Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). + ''', + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "3:0", + name: "VAL", + resval: "0x0" + desc: ''' + ''' + }, + ] + }, + + { name: "CHERIOT_LOCK", + desc: ''' + Locks the CHERIoT/ePMP mode. + If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. + ''', + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "3:0", + name: "VAL", + desc: ''' + ''' + }, + ] + }, + { name: "FPGA_INFO", desc: ''' FPGA build timestamp info. diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/top_earlgrey_rv_core_ibex.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/top_earlgrey_rv_core_ibex.ipconfig.hjson index 45d717172cecf..4bbab93f64622 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/top_earlgrey_rv_core_ibex.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/top_earlgrey_rv_core_ibex.ipconfig.hjson @@ -6,6 +6,7 @@ param_values: { num_regions: 2 + cheriot_available: true module_instance_name: rv_core_ibex topname: earlgrey uniquified_modules: {} diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md b/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md index 68752c6cc94e5..a27c61e5a9687 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/interfaces.md @@ -6,38 +6,42 @@ Referring to the [Comportable guideline for peripheral device functionality](htt - Primary Clock: **`clk_i`** - Other Clocks: **`clk_edn_i`**, **`clk_esc_i`**, **`clk_otp_i`** - Bus Device Interfaces (TL-UL): **`cfg_tl_d`** -- Bus Host Interfaces (TL-UL): **`corei_tl_h`**, **`cored_tl_h`** +- Bus Host Interfaces (TL-UL): **`corei_tl_h`** - Peripheral Pins for Chip IO: *none* - Interrupts: *none* ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:------------------------|:---------------------------------|:--------|:------|:------------|:--------------| -| rst_cpu_n | logic | uni | req | 1 | | -| ram_cfg_icache_tag | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | -| ram_cfg_rsp_icache_tag | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | | -| ram_cfg_icache_data | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | -| ram_cfg_rsp_icache_data | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | | -| hart_id | logic | uni | rcv | 32 | | -| boot_addr | logic | uni | rcv | 32 | | -| irq_software | logic | uni | rcv | 1 | | -| irq_timer | logic | uni | rcv | 1 | | -| irq_external | logic | uni | rcv | 1 | | -| esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | -| esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | -| debug_req | logic | uni | rcv | 1 | | -| crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | | -| lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | | -| nmi_wdog | logic | uni | rcv | 1 | | -| edn | edn_pkg::edn | req_rsp | req | 1 | | -| icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | -| fpga_info | logic | uni | rcv | 32 | | -| corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | -| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | -| cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------------------|:---------------------------------|:--------|:------|:------------|:--------------------------------------------------------------| +| rst_cpu_n | logic | uni | req | 1 | | +| cheriot_ena | prim_mubi_pkg::mubi4 | uni | req | 1 | CHERIoT mode enable. | +| cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | Core data host port to CHERIoT subsystem | +| cored_tag_h2d | logic | uni | req | 1 | CHERIoT capability tag carried with the A-channel of cored_h. | +| cored_tag_d2h | logic | uni | rcv | 1 | Capability tag returned on the D-channel of cored_h. | +| corerevbm_tl | tlul_pkg::tl | req_rsp | req | 1 | Core revocation bitmap host port | +| ram_cfg_icache_tag | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | +| ram_cfg_rsp_icache_tag | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | | +| ram_cfg_icache_data | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | +| ram_cfg_rsp_icache_data | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | ICacheNWays | | +| hart_id | logic | uni | rcv | 32 | | +| boot_addr | logic | uni | rcv | 32 | | +| irq_software | logic | uni | rcv | 1 | | +| irq_timer | logic | uni | rcv | 1 | | +| irq_external | logic | uni | rcv | 1 | | +| esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| debug_req | logic | uni | rcv | 1 | | +| crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | | +| lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| pwrmgr | rv_core_ibex_pkg::cpu_pwrmgr | uni | req | 1 | | +| nmi_wdog | logic | uni | rcv | 1 | | +| edn | edn_pkg::edn | req_rsp | req | 1 | | +| icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | | +| fpga_info | logic | uni | rcv | 32 | | +| corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | +| cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts @@ -65,6 +69,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.GLOBAL_ESC | A mechanism to detect and act on double faults. Global escalation sends a fatal alert when a double fault is seen. | | RV_CORE_IBEX.ICACHE.MEM.SCRAMBLE | ICache memory scrambling. | | RV_CORE_IBEX.ICACHE.MEM.INTEGRITY | ICache memory integrity checking. | +| RV_CORE_IBEX.CHERIOT_SWITCH.FSM.SPARSE | The write-once ePMP/CHERIoT execution mode switch FSM is sparsely encoded. | diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md b/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md index 88fe348c9837f..e27b1fcd764c6 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/doc/registers.md @@ -5,36 +5,38 @@ A number of memory-mapped registers are available to control Ibex-related functi ## Summary -| Name | Offset | Length | Description | -|:-------------------------------------------------------------------------|:---------|---------:|:------------------------------------------------------------------------------| -| rv_core_ibex.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | -| rv_core_ibex.[`SW_RECOV_ERR`](#sw_recov_err) | 0x4 | 4 | Software recoverable error | -| rv_core_ibex.[`SW_FATAL_ERR`](#sw_fatal_err) | 0x8 | 4 | Software fatal error | -| rv_core_ibex.[`IBUS_REGWEN_0`](#ibus_regwen) | 0xc | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_1`](#ibus_regwen) | 0x10 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_ADDR_EN_0`](#ibus_addr_en) | 0x14 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_1`](#ibus_addr_en) | 0x18 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching) | 0x1c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_1`](#ibus_addr_matching) | 0x20 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_0`](#ibus_remap_addr) | 0x24 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_1`](#ibus_remap_addr) | 0x28 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`DBUS_REGWEN_0`](#dbus_regwen) | 0x2c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_1`](#dbus_regwen) | 0x30 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_ADDR_EN_0`](#dbus_addr_en) | 0x34 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_1`](#dbus_addr_en) | 0x38 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_0`](#dbus_addr_matching) | 0x3c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_1`](#dbus_addr_matching) | 0x40 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_0`](#dbus_remap_addr) | 0x44 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_1`](#dbus_remap_addr) | 0x48 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`NMI_ENABLE`](#nmi_enable) | 0x4c | 4 | Enable mask for NMI. | -| rv_core_ibex.[`NMI_STATE`](#nmi_state) | 0x50 | 4 | Current NMI state | -| rv_core_ibex.[`ERR_STATUS`](#err_status) | 0x54 | 4 | error status | -| rv_core_ibex.[`RND_DATA`](#rnd_data) | 0x58 | 4 | Random data from EDN | -| rv_core_ibex.[`RND_STATUS`](#rnd_status) | 0x5c | 4 | Status of random data in [`RND_DATA`](#rnd_data) | -| rv_core_ibex.[`FPGA_INFO`](#fpga_info) | 0x60 | 4 | FPGA build timestamp info. | -| rv_core_ibex.[`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) | 0x64 | 4 | Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) | -| rv_core_ibex.[`MCOUNTEREN_WRITABLE`](#mcounteren_writable) | 0x68 | 4 | Controls whether Ibex mcounteren CSR is writable by software. | -| rv_core_ibex.[`DV_SIM_WINDOW`](#dv_sim_window) | 0x80 | 32 | Exposed tlul window for DV only purposes. | +| Name | Offset | Length | Description | +|:-------------------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| +| rv_core_ibex.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| rv_core_ibex.[`SW_RECOV_ERR`](#sw_recov_err) | 0x4 | 4 | Software recoverable error | +| rv_core_ibex.[`SW_FATAL_ERR`](#sw_fatal_err) | 0x8 | 4 | Software fatal error | +| rv_core_ibex.[`IBUS_REGWEN_0`](#ibus_regwen) | 0xc | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_1`](#ibus_regwen) | 0x10 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_ADDR_EN_0`](#ibus_addr_en) | 0x14 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_1`](#ibus_addr_en) | 0x18 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching) | 0x1c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_1`](#ibus_addr_matching) | 0x20 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_0`](#ibus_remap_addr) | 0x24 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_1`](#ibus_remap_addr) | 0x28 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`DBUS_REGWEN_0`](#dbus_regwen) | 0x2c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_1`](#dbus_regwen) | 0x30 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_ADDR_EN_0`](#dbus_addr_en) | 0x34 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_1`](#dbus_addr_en) | 0x38 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_0`](#dbus_addr_matching) | 0x3c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_1`](#dbus_addr_matching) | 0x40 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_0`](#dbus_remap_addr) | 0x44 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_1`](#dbus_remap_addr) | 0x48 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`NMI_ENABLE`](#nmi_enable) | 0x4c | 4 | Enable mask for NMI. | +| rv_core_ibex.[`NMI_STATE`](#nmi_state) | 0x50 | 4 | Current NMI state | +| rv_core_ibex.[`ERR_STATUS`](#err_status) | 0x54 | 4 | error status | +| rv_core_ibex.[`RND_DATA`](#rnd_data) | 0x58 | 4 | Random data from EDN | +| rv_core_ibex.[`RND_STATUS`](#rnd_status) | 0x5c | 4 | Status of random data in [`RND_DATA`](#rnd_data) | +| rv_core_ibex.[`CHERIOT_ENA`](#cheriot_ena) | 0x60 | 4 | Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). | +| rv_core_ibex.[`CHERIOT_LOCK`](#cheriot_lock) | 0x64 | 4 | Locks the CHERIoT/ePMP mode. | +| rv_core_ibex.[`FPGA_INFO`](#fpga_info) | 0x68 | 4 | FPGA build timestamp info. | +| rv_core_ibex.[`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) | 0x6c | 4 | Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) | +| rv_core_ibex.[`MCOUNTEREN_WRITABLE`](#mcounteren_writable) | 0x70 | 4 | Controls whether Ibex mcounteren CSR is writable by software. | +| rv_core_ibex.[`DV_SIM_WINDOW`](#dv_sim_window) | 0x80 | 32 | Exposed tlul window for DV only purposes. | ## ALERT_TEST Alert Test Register @@ -421,10 +423,45 @@ Status of random data in [`RND_DATA`](#rnd_data) | 1 | ro | 0x0 | RND_DATA_FIPS | When [`RND_STATUS.RND_DATA_VALID`](#rnd_status) is 1, this bit indicates whether [`RND_DATA`](#rnd_data) is fips quality. When [`RND_STATUS.RND_DATA_VALID`](#rnd_status) is 0, this bit has no meaning. | | 0 | ro | 0x0 | RND_DATA_VALID | When set, the data in [`RND_DATA`](#rnd_data) is valid. When clear an EDN request for new data for [`RND_DATA`](#rnd_data) is pending. | +## CHERIOT_ENA +Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). +- Offset: `0x60` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["wo"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:4 | | | | Reserved | +| 3:0 | wo | 0x0 | VAL | | + +## CHERIOT_LOCK +Locks the CHERIoT/ePMP mode. +If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. +- Offset: `0x64` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["wo"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:4 | | | | Reserved | +| 3:0 | wo | x | VAL | | + ## FPGA_INFO FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0. -- Offset: `0x60` +- Offset: `0x68` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -440,7 +477,7 @@ This register only contains valid data for fpga, for all other variants it is si ## MCOUNTEREN_WRITABLE_REGWEN Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) -- Offset: `0x64` +- Offset: `0x6c` - Reset default: `0x1` - Reset mask: `0x1` @@ -466,7 +503,7 @@ Write enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) Once set to 0, i ## MCOUNTEREN_WRITABLE Controls whether Ibex mcounteren CSR is writable by software. -- Offset: `0x68` +- Offset: `0x70` - Reset default: `0x6` - Reset mask: `0xf` - Register enable: [`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv index eddb743aeed2e..75580cee18977 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv @@ -3,6 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 `include "prim_assert.sv" +`include "prim_fifo_assert.svh" /** * Ibex RISC-V core @@ -14,6 +15,7 @@ module rv_core_ibex import rv_core_ibex_pkg::*; import rv_core_ibex_reg_pkg::*; #( + parameter ibex_pkg::base_isa_e BaseIsa = ibex_pkg::BaseIsaRV32IorCHERIoT, parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // Number of cycles a differential skew is tolerated on the alert and escalation signal parameter int unsigned AlertSkewCycles = 1, @@ -57,7 +59,10 @@ module rv_core_ibex parameter int unsigned WidthPingCounter = 16, parameter logic [tlul_pkg::RsvdWidth-1:0] TlulHostUserRsvdBits = 0, parameter logic [31:0] CsrMvendorId = 32'b0, - parameter logic [31:0] CsrMimpId = 32'b0 + parameter logic [31:0] CsrMimpId = 32'b0, + parameter int unsigned CheriotRevBitmapAddrWidth = 32'd9, + parameter int unsigned CheriotRevBitmapBaseAddr = 32'h0, + parameter int unsigned CheriotTrvkHeapBaseAddr = 32'h0 ) ( // Clock and Reset input logic clk_i, @@ -79,6 +84,8 @@ module rv_core_ibex input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, + output prim_mubi_pkg::mubi4_t cheriot_ena_o, + // Instruction memory interface output tlul_pkg::tl_h2d_t corei_tl_h_o, input tlul_pkg::tl_d2h_t corei_tl_h_i, @@ -87,6 +94,14 @@ module rv_core_ibex output tlul_pkg::tl_h2d_t cored_tl_h_o, input tlul_pkg::tl_d2h_t cored_tl_h_i, + // CHERIoT capability tags + output logic cored_tag_h2d_o, + input logic cored_tag_d2h_i, + + // CHERIoT TRVK revocation bitmap (revbm) memory interface + output tlul_pkg::tl_h2d_t corerevbm_tl_o, + input tlul_pkg::tl_d2h_t corerevbm_tl_i, + // Interrupt inputs input logic irq_software_i, input logic irq_timer_i, @@ -185,6 +200,15 @@ module rv_core_ibex logic [31:0] shadow_core_data_wdata; logic [6:0] shadow_core_data_wdata_intg; + // Main core CHERIoT TRVK revocation bitmap (revbm) interface (internal) + logic main_core_revbm_req; + logic main_core_revbm_gnt; + logic [31:0] main_core_revbm_addr; + logic main_core_revbm_rvalid; + logic [31:0] main_core_revbm_rdata; + logic [6:0] main_core_revbm_rdata_intg; + logic main_core_revbm_err; + // Lockstep interface logic [3:0] core_lockstep_cmp_en; @@ -193,6 +217,8 @@ module rv_core_ibex tl_d2h_t tl_i_fifo2ibex; tl_h2d_t tl_d_ibex2fifo_main_core; tl_d2h_t tl_d_fifo2ibex; + tl_h2d_t tl_revbm_ibex2fifo; + tl_d2h_t tl_revbm_fifo2ibex; // TLUL LC Gate interfaces tl_h2d_t tl_d_fifo2gate; @@ -236,6 +262,9 @@ module rv_core_ibex // core sleeping logic core_sleep; + // CHERIoT signals + logic cheriot_switch_error; + // The following intermediate signals are created to aid in simulations. // // If a parent port is connected directly to a port of sub-modules, the implicit wire connection @@ -253,6 +282,7 @@ module rv_core_ibex // errors and core alert events logic ibus_intg_err, dbus_intg_err; + logic revbmbus_intg_err; logic alert_minor, alert_major_internal, alert_major_bus; logic double_fault; logic fatal_intg_err, fatal_core_err, recov_core_err; @@ -264,7 +294,7 @@ module rv_core_ibex logic fatal_core_event; logic recov_core_event; // SEC_CM: BUS.INTEGRITY - assign fatal_intg_event = ibus_intg_err | dbus_intg_err | alert_major_bus; + assign fatal_intg_event = ibus_intg_err | dbus_intg_err | revbmbus_intg_err | alert_major_bus; assign fatal_core_event = alert_major_internal | double_fault | tlul_lc_gate_core_d_error | @@ -431,6 +461,7 @@ module rv_core_ibex ibex_pkg::crash_dump_t crash_dump; ibex_top #( + .BaseIsa ( BaseIsa ), .PMPEnable ( PMPEnable ), .PMPGranularity ( PMPGranularity ), .PMPNumRegions ( PMPNumRegions ), @@ -439,6 +470,8 @@ module rv_core_ibex .PMPRstCfg ( PMPRstCfg ), .PMPRstAddr ( PMPRstAddr ), .PMPRstMsecCfg ( PMPRstMsecCfg ), + .CheriotRevBitmapAddrWidth ( CheriotRevBitmapAddrWidth), + .CheriotRevBitmapBaseAddr ( CheriotRevBitmapBaseAddr ), .RV32E ( RV32E ), .RV32M ( RV32M ), .RV32B ( RV32B ), @@ -493,6 +526,8 @@ module rv_core_ibex .hart_id_i, .boot_addr_i, + .trvk_heap_base_addr_i(CheriotTrvkHeapBaseAddr), // SRAM base address + .instr_req_o (main_core_instr_req), .instr_gnt_i (main_core_instr_gnt_ibex), .instr_rvalid_i (main_core_instr_rvalid), @@ -509,10 +544,20 @@ module rv_core_ibex .data_addr_o (main_core_data_addr), .data_wdata_o (main_core_data_wdata), .data_wdata_intg_o (main_core_data_wdata_intg), + .data_tag_o (cored_tag_h2d_o), .data_rdata_i (main_core_data_rdata), .data_rdata_intg_i (main_core_data_rdata_intg), + .data_tag_i (cored_tag_d2h_i), .data_err_i (main_core_data_err), + .trvk_revbm_req_o (main_core_revbm_req), + .trvk_revbm_gnt_i (main_core_revbm_gnt), + .trvk_revbm_rvalid_i (main_core_revbm_rvalid), + .trvk_revbm_addr_o (main_core_revbm_addr), + .trvk_revbm_rdata_i (main_core_revbm_rdata), + .trvk_revbm_rdata_intg_i(main_core_revbm_rdata_intg), + .trvk_revbm_err_i (main_core_revbm_err), + .irq_software_i ( irq_software ), .irq_timer_i ( irq_timer ), .irq_external_i ( irq_external ), @@ -798,6 +843,75 @@ module rv_core_ibex .err_o (tlul_lc_gate_core_d_error) ); + if (BaseIsa == ibex_pkg::BaseIsaRV32IorCHERIoT) begin : gen_cheriot_revbm_tl_adapter + + logic [6:0] revbm_wdata_intg; + logic [top_pkg::TL_DW-1:0] unused_revbm_data; + // tl_adapter_host_revbm_ibex only reads revocation bm. a_data is always 0 + assign {revbm_wdata_intg, unused_revbm_data} = prim_secded_pkg::prim_secded_inv_39_32_enc('0); + // SEC_CM: BUS.INTEGRITY + tlul_adapter_host #( + .MAX_REQS(NumOutstandingReqs), + // if secure ibex is not set, data integrity is not generated + // from ibex, therefore generate it in the gasket instead. + .EnableDataIntgGen(~SecureIbex) + ) tl_adapter_host_revbm_ibex ( + .clk_i, + .rst_ni, + .req_i (main_core_revbm_req), + .instr_type_i (prim_mubi_pkg::MuBi4True), + .gnt_o (main_core_revbm_gnt), + .addr_i (main_core_revbm_addr), + .we_i (1'b0), + .wdata_i (32'b0), + .wdata_intg_i (revbm_wdata_intg), + .be_i (4'hF), + .user_rsvd_i (TlulHostUserRsvdBits), + .valid_o (main_core_revbm_rvalid), + .rdata_o (main_core_revbm_rdata), + .rdata_intg_o (main_core_revbm_rdata_intg), + .err_o (main_core_revbm_err), + .intg_err_o (revbmbus_intg_err), + .tl_o (tl_revbm_ibex2fifo), + .tl_i (tl_revbm_fifo2ibex) + ); + + tlul_fifo_sync #( + .ReqPass(FifoPass), + .RspPass(FifoPass), + .ReqDepth(FifoDepth), + .RspDepth(FifoDepth) + ) fifo_revbm ( + .clk_i, + .rst_ni, + .tl_h_i (tl_revbm_ibex2fifo), + .tl_h_o (tl_revbm_fifo2ibex), + .tl_d_o (corerevbm_tl_o), + .tl_d_i (corerevbm_tl_i), + .spare_req_i (1'b0), + .spare_req_o (), + .spare_rsp_i (1'b0), + .spare_rsp_o () + ); + + end else begin : gen_no_cheriot_revbm_tl_adapter + + // Tie-off unused signals + logic unused_cheriot_tl; + assign unused_cheriot_tl = ^{corerevbm_tl_i, + tl_revbm_ibex2fifo, + tl_revbm_fifo2ibex, + main_core_revbm_req, + main_core_revbm_addr + }; + assign corerevbm_tl_o = '0; + assign main_core_revbm_gnt = '0; + assign main_core_revbm_rvalid = '0; + assign main_core_revbm_rdata = '0; + assign main_core_revbm_rdata_intg = '0; + assign main_core_revbm_err = '0; + end + `ifdef RVFI ibex_tracer ibex_tracer_i ( .clk_i, @@ -922,7 +1036,7 @@ module rv_core_ibex assign alert_events[0] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_fatal_err.q)); assign alert_events[1] = mubi4_test_true_loose(mubi4_t'(reg2hw.sw_recov_err.q)); assign alert_events[2] = cfg_reg_intg_err | cfg_reg_intg_err_shadow | - fatal_intg_err | fatal_core_err; + fatal_intg_err | fatal_core_err | cheriot_switch_error; assign alert_events[3] = recov_core_err; logic unused_alert_acks; @@ -1012,6 +1126,31 @@ module rv_core_ibex assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q; assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q; + //////////////////// + // CHERIoT switch + //////////////////// + if (BaseIsa == ibex_pkg::BaseIsaRV32IorCHERIoT) begin : gen_cheriot_switch + // SEC_CM: CHERIOT_SWITCH.FSM.SPARSE + cheriot_switch u_cheriot_switch ( + .clk_i, + .rst_ni, + .ena_i (mubi4_t'(reg2hw.cheriot_ena.q)), + .lock_i (mubi4_t'(reg2hw.cheriot_lock.q)), + .lock_access_i(reg2hw.cheriot_lock.qe), + .ena_o (cheriot_ena_o), + .error_o (cheriot_switch_error) + ); + + end else begin : gen_no_cheriot_switch + logic unused_cheriot; + assign cheriot_switch_error = 1'b0; + assign cheriot_ena_o = prim_mubi_pkg::MuBi4False; + assign unused_cheriot = ^{cheriot_switch_error, + reg2hw.cheriot_ena, + reg2hw.cheriot_lock + }; + end + logic unused_reg2hw; assign unused_reg2hw = |reg2hw.rnd_data.q; @@ -1102,7 +1241,8 @@ module rv_core_ibex assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable, reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data, reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err, - reg2hw_shadow.mcounteren_writable}; + reg2hw_shadow.mcounteren_writable, + reg2hw_shadow.cheriot_ena, reg2hw_shadow.cheriot_lock}; ///////////////////////////////////////////////////////////////// // Shadow Core Data Address Translation Unit and TL-UL Adapter // @@ -1525,5 +1665,8 @@ module rv_core_ibex `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CoredTlLcGateFsm_A, u_tlul_lc_gate_cored.u_state_regs, alert_tx_o[2]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CheriotSwitchFsm_A, + gen_cheriot_switch.u_cheriot_switch.u_state_regs, alert_tx_o[2]) + `endif // ifdef INC_ASSERT endmodule diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv index bd489909982fa..2003143cc666d 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv @@ -57,9 +57,9 @@ module rv_core_ibex_cfg_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [26:0] reg_we_check; + logic [28:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(27) + .OneHotWidth(29) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -253,6 +253,10 @@ module rv_core_ibex_cfg_reg_top ( logic rnd_status_re; logic rnd_status_rnd_data_valid_qs; logic rnd_status_rnd_data_fips_qs; + logic cheriot_ena_we; + logic [3:0] cheriot_ena_wd; + logic cheriot_lock_we; + logic [3:0] cheriot_lock_wd; logic fpga_info_re; logic [31:0] fpga_info_qs; logic mcounteren_writable_regwen_we; @@ -1302,6 +1306,54 @@ module rv_core_ibex_cfg_reg_top ( ); + // R[cheriot_ena]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessWO), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cheriot_ena ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cheriot_ena_we), + .wd (cheriot_ena_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cheriot_ena.q), + .ds (), + + // to register interface (read) + .qs () + ); + + + // R[cheriot_lock]: V(True) + logic cheriot_lock_qe; + logic [0:0] cheriot_lock_flds_we; + assign cheriot_lock_qe = &cheriot_lock_flds_we; + prim_subreg_ext #( + .DW (4) + ) u_cheriot_lock ( + .re (1'b0), + .we (cheriot_lock_we), + .wd (cheriot_lock_wd), + .d ('0), + .qre (), + .qe (cheriot_lock_flds_we[0]), + .q (reg2hw.cheriot_lock.q), + .ds (), + .qs () + ); + assign reg2hw.cheriot_lock.qe = cheriot_lock_qe; + + // R[fpga_info]: V(True) prim_subreg_ext #( .DW (32) @@ -1378,7 +1430,7 @@ module rv_core_ibex_cfg_reg_top ( - logic [26:0] addr_hit; + logic [28:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RV_CORE_IBEX_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == RV_CORE_IBEX_SW_RECOV_ERR_OFFSET); @@ -1404,9 +1456,11 @@ module rv_core_ibex_cfg_reg_top ( addr_hit[21] = (reg_addr == RV_CORE_IBEX_ERR_STATUS_OFFSET); addr_hit[22] = (reg_addr == RV_CORE_IBEX_RND_DATA_OFFSET); addr_hit[23] = (reg_addr == RV_CORE_IBEX_RND_STATUS_OFFSET); - addr_hit[24] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET); - addr_hit[25] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET); - addr_hit[26] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET); + addr_hit[24] = (reg_addr == RV_CORE_IBEX_CHERIOT_ENA_OFFSET); + addr_hit[25] = (reg_addr == RV_CORE_IBEX_CHERIOT_LOCK_OFFSET); + addr_hit[26] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET); + addr_hit[27] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET); + addr_hit[28] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1440,7 +1494,9 @@ module rv_core_ibex_cfg_reg_top ( (addr_hit[23] & (|(RV_CORE_IBEX_CFG_PERMIT[23] & ~reg_be))) | (addr_hit[24] & (|(RV_CORE_IBEX_CFG_PERMIT[24] & ~reg_be))) | (addr_hit[25] & (|(RV_CORE_IBEX_CFG_PERMIT[25] & ~reg_be))) | - (addr_hit[26] & (|(RV_CORE_IBEX_CFG_PERMIT[26] & ~reg_be))))); + (addr_hit[26] & (|(RV_CORE_IBEX_CFG_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(RV_CORE_IBEX_CFG_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(RV_CORE_IBEX_CFG_PERMIT[28] & ~reg_be))))); end // Generate write-enables @@ -1528,11 +1584,17 @@ module rv_core_ibex_cfg_reg_top ( assign err_status_recov_core_err_wd = reg_wdata[10]; assign rnd_data_re = addr_hit[22] & reg_re & !reg_error; assign rnd_status_re = addr_hit[23] & reg_re & !reg_error; - assign fpga_info_re = addr_hit[24] & reg_re & !reg_error; - assign mcounteren_writable_regwen_we = addr_hit[25] & reg_we & !reg_error; + assign cheriot_ena_we = addr_hit[24] & reg_we & !reg_error; + + assign cheriot_ena_wd = reg_wdata[3:0]; + assign cheriot_lock_we = addr_hit[25] & reg_we & !reg_error; + + assign cheriot_lock_wd = reg_wdata[3:0]; + assign fpga_info_re = addr_hit[26] & reg_re & !reg_error; + assign mcounteren_writable_regwen_we = addr_hit[27] & reg_we & !reg_error; assign mcounteren_writable_regwen_wd = reg_wdata[0]; - assign mcounteren_writable_we = addr_hit[26] & reg_we & !reg_error; + assign mcounteren_writable_we = addr_hit[28] & reg_we & !reg_error; assign mcounteren_writable_wd = reg_wdata[3:0]; @@ -1562,9 +1624,11 @@ module rv_core_ibex_cfg_reg_top ( reg_we_check[21] = err_status_we; reg_we_check[22] = 1'b0; reg_we_check[23] = 1'b0; - reg_we_check[24] = 1'b0; - reg_we_check[25] = mcounteren_writable_regwen_we; - reg_we_check[26] = mcounteren_writable_gated_we; + reg_we_check[24] = cheriot_ena_we; + reg_we_check[25] = cheriot_lock_we; + reg_we_check[26] = 1'b0; + reg_we_check[27] = mcounteren_writable_regwen_we; + reg_we_check[28] = mcounteren_writable_gated_we; end // Read data return @@ -1677,14 +1741,22 @@ module rv_core_ibex_cfg_reg_top ( end addr_hit[24]: begin - reg_rdata_next[31:0] = fpga_info_qs; + reg_rdata_next[3:0] = '0; end addr_hit[25]: begin - reg_rdata_next[0] = mcounteren_writable_regwen_qs; + reg_rdata_next[3:0] = '0; end addr_hit[26]: begin + reg_rdata_next[31:0] = fpga_info_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = mcounteren_writable_regwen_qs; + end + + addr_hit[28]: begin reg_rdata_next[3:0] = mcounteren_writable_qs; end diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv index 2fe6515143947..328d7f99090ea 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv @@ -16,7 +16,7 @@ package rv_core_ibex_reg_pkg; parameter int CfgAw = 8; // Number of registers for every interface - parameter int NumRegsCfg = 27; + parameter int NumRegsCfg = 29; // Alert indices typedef enum int { @@ -110,6 +110,15 @@ package rv_core_ibex_reg_pkg; logic re; } rv_core_ibex_reg2hw_rnd_data_reg_t; + typedef struct packed { + logic [3:0] q; + } rv_core_ibex_reg2hw_cheriot_ena_reg_t; + + typedef struct packed { + logic [3:0] q; + logic qe; + } rv_core_ibex_reg2hw_cheriot_lock_reg_t; + typedef struct packed { logic [3:0] q; } rv_core_ibex_reg2hw_mcounteren_writable_reg_t; @@ -168,18 +177,20 @@ package rv_core_ibex_reg_pkg; // Register -> HW type for cfg interface typedef struct packed { - rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [328:321] - rv_core_ibex_reg2hw_sw_recov_err_reg_t sw_recov_err; // [320:317] - rv_core_ibex_reg2hw_sw_fatal_err_reg_t sw_fatal_err; // [316:313] - rv_core_ibex_reg2hw_ibus_addr_en_mreg_t [1:0] ibus_addr_en; // [312:309] - rv_core_ibex_reg2hw_ibus_addr_matching_mreg_t [1:0] ibus_addr_matching; // [308:243] - rv_core_ibex_reg2hw_ibus_remap_addr_mreg_t [1:0] ibus_remap_addr; // [242:177] - rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [1:0] dbus_addr_en; // [176:173] - rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [1:0] dbus_addr_matching; // [172:107] - rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [1:0] dbus_remap_addr; // [106:41] - rv_core_ibex_reg2hw_nmi_enable_reg_t nmi_enable; // [40:39] - rv_core_ibex_reg2hw_nmi_state_reg_t nmi_state; // [38:37] - rv_core_ibex_reg2hw_rnd_data_reg_t rnd_data; // [36:4] + rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [337:330] + rv_core_ibex_reg2hw_sw_recov_err_reg_t sw_recov_err; // [329:326] + rv_core_ibex_reg2hw_sw_fatal_err_reg_t sw_fatal_err; // [325:322] + rv_core_ibex_reg2hw_ibus_addr_en_mreg_t [1:0] ibus_addr_en; // [321:318] + rv_core_ibex_reg2hw_ibus_addr_matching_mreg_t [1:0] ibus_addr_matching; // [317:252] + rv_core_ibex_reg2hw_ibus_remap_addr_mreg_t [1:0] ibus_remap_addr; // [251:186] + rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [1:0] dbus_addr_en; // [185:182] + rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [1:0] dbus_addr_matching; // [181:116] + rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [1:0] dbus_remap_addr; // [115:50] + rv_core_ibex_reg2hw_nmi_enable_reg_t nmi_enable; // [49:48] + rv_core_ibex_reg2hw_nmi_state_reg_t nmi_state; // [47:46] + rv_core_ibex_reg2hw_rnd_data_reg_t rnd_data; // [45:13] + rv_core_ibex_reg2hw_cheriot_ena_reg_t cheriot_ena; // [12:9] + rv_core_ibex_reg2hw_cheriot_lock_reg_t cheriot_lock; // [8:4] rv_core_ibex_reg2hw_mcounteren_writable_reg_t mcounteren_writable; // [3:0] } rv_core_ibex_cfg_reg2hw_t; @@ -218,9 +229,11 @@ package rv_core_ibex_reg_pkg; parameter logic [CfgAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 8'h 54; parameter logic [CfgAw-1:0] RV_CORE_IBEX_RND_DATA_OFFSET = 8'h 58; parameter logic [CfgAw-1:0] RV_CORE_IBEX_RND_STATUS_OFFSET = 8'h 5c; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_FPGA_INFO_OFFSET = 8'h 60; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET = 8'h 64; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET = 8'h 68; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_CHERIOT_ENA_OFFSET = 8'h 60; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_CHERIOT_LOCK_OFFSET = 8'h 64; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_FPGA_INFO_OFFSET = 8'h 68; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET = 8'h 6c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET = 8'h 70; // Reset values for hwext registers and their fields for cfg interface parameter logic [3:0] RV_CORE_IBEX_ALERT_TEST_RESVAL = 4'h 0; @@ -233,6 +246,7 @@ package rv_core_ibex_reg_pkg; parameter logic [1:0] RV_CORE_IBEX_RND_STATUS_RESVAL = 2'h 0; parameter logic [0:0] RV_CORE_IBEX_RND_STATUS_RND_DATA_VALID_RESVAL = 1'h 0; parameter logic [0:0] RV_CORE_IBEX_RND_STATUS_RND_DATA_FIPS_RESVAL = 1'h 0; + parameter logic [3:0] RV_CORE_IBEX_CHERIOT_LOCK_RESVAL = 4'h 0; parameter logic [31:0] RV_CORE_IBEX_FPGA_INFO_RESVAL = 32'h 0; parameter logic [31:0] RV_CORE_IBEX_FPGA_INFO_VAL_RESVAL = 32'h 0; @@ -267,13 +281,15 @@ package rv_core_ibex_reg_pkg; RV_CORE_IBEX_ERR_STATUS, RV_CORE_IBEX_RND_DATA, RV_CORE_IBEX_RND_STATUS, + RV_CORE_IBEX_CHERIOT_ENA, + RV_CORE_IBEX_CHERIOT_LOCK, RV_CORE_IBEX_FPGA_INFO, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN, RV_CORE_IBEX_MCOUNTEREN_WRITABLE } rv_core_ibex_cfg_id_e; // Register width information to check illegal writes for cfg interface - parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [27] = '{ + parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [29] = '{ 4'b 0001, // index[ 0] RV_CORE_IBEX_ALERT_TEST 4'b 0001, // index[ 1] RV_CORE_IBEX_SW_RECOV_ERR 4'b 0001, // index[ 2] RV_CORE_IBEX_SW_FATAL_ERR @@ -298,9 +314,11 @@ package rv_core_ibex_reg_pkg; 4'b 0011, // index[21] RV_CORE_IBEX_ERR_STATUS 4'b 1111, // index[22] RV_CORE_IBEX_RND_DATA 4'b 0001, // index[23] RV_CORE_IBEX_RND_STATUS - 4'b 1111, // index[24] RV_CORE_IBEX_FPGA_INFO - 4'b 0001, // index[25] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN - 4'b 0001 // index[26] RV_CORE_IBEX_MCOUNTEREN_WRITABLE + 4'b 0001, // index[24] RV_CORE_IBEX_CHERIOT_ENA + 4'b 0001, // index[25] RV_CORE_IBEX_CHERIOT_LOCK + 4'b 1111, // index[26] RV_CORE_IBEX_FPGA_INFO + 4'b 0001, // index[27] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN + 4'b 0001 // index[28] RV_CORE_IBEX_MCOUNTEREN_WRITABLE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rv_core_ibex.core b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rv_core_ibex.core index 4010a7415c560..cf57dd884afb3 100644 --- a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rv_core_ibex.core +++ b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rv_core_ibex.core @@ -20,6 +20,7 @@ filesets: - lowrisc:prim:mubi - lowrisc:tlul:adapter_host - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:ip:cheriot_switch files: - rtl/rv_core_ibex_reg_pkg.sv diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index f822618b80711..43709142d3391 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -51,6 +51,12 @@ additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" rel_path: "hw/top_earlgrey/ip/ast/lint/{tool}" }, + { name: cheriot + fusesoc_core: lowrisc:ip:cheriot + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" + rel_path: "hw/ip/cheriot/lint/{tool}" + }, { name: entropy_src fusesoc_core: lowrisc:ip:entropy_src import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 2824b997eab06..a5b5dc04d8097 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -1336,6 +1336,7 @@ module chip_earlgrey_asic #( .obs_ctrl_i (obs_ctrl ), .ram_1p_cfg_i (ram_1p_cfg ), .sram_ctrl_main_cfg_i ('{ram_1p_cfg} ), + .sram_ctrl_meta_cfg_i ('{ram_1p_cfg} ), .spi_ram_2p_cfg_i (spi_ram_2p_cfg ), .usb_ram_1p_cfg_i (usb_ram_1p_cfg ), .rom_cfg_i (rom_cfg ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv index d0660893031d8..c656ccf2dbb91 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv @@ -1328,6 +1328,7 @@ module chip_earlgrey_cw340 #( .obs_ctrl_i (obs_ctrl ), .ram_1p_cfg_i (prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT), .sram_ctrl_main_cfg_i ('{prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT}), + .sram_ctrl_meta_cfg_i ('{prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT}), .spi_ram_2p_cfg_i (prim_ram_2p_pkg::RAM_2P_CFG_DEFAULT), .usb_ram_1p_cfg_i (prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT), .rom_cfg_i (prim_rom_pkg::ROM_CFG_DEFAULT), diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv index d5d60e2b352a6..a303e9d943466 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv @@ -19,17 +19,17 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter otp_ctrl_top_specific_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { - 40'h9C_AA47E5CE + 40'hCE_1CF9E202 }; // Compile-time random permutation for LFSR output parameter otp_ctrl_top_specific_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { - 240'h9200_8344A54D_5DF3076E_61840052_592CE892_21C79084_16255948_D33DD6A7 + 240'h2DB9_A0493142_7083D612_779888A7_4600C8C7_52135925_F9500D55_D168E064 }; // Compile-time random permutation for scrambling key/nonce register reset value parameter otp_ctrl_top_specific_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { - 256'h2A71D66B_5953DBC6_03379DA9_EFB2069B_D79815B2_F8D99A40_E7FDC4FB_13143D77 + 256'hA7F8B17F_A88FEE02_E3F08642_23A2E23A_8CC31E2D_E5E578D4_3D2DCE49_E360CFB5 }; // Compile-time scrambling key @@ -237,35 +237,35 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Diversification value used for all invalid life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { - 128'h53CE1CF9_E2029207_396945C9_5C9B54BA + 128'h94ACDDF1_70684F6E_AD2B7FEB_FE895523 }; // Diversification value used for the TEST_UNLOCKED* life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { - 128'hE6AEF30D_8577834C_CC6CAAA6_3A8E6604 + 128'hD7BC4846_A485956C_7F904B9E_DED09B89 }; // Diversification value used for the DEV life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { - 128'h338151B9_A23C08F9_EED04CA1_EBB0BDD3 + 128'hA7543356_6F4963D9_DC27F3EC_B11CE3B8 }; // Diversification value used for the PROD/PROD_END life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { - 128'h05FFB6C4_818054E0_E0EDB0AC_D0B040FC + 128'h7AAA7ABC_85920B18_81083AFF_7BDE18EA }; // Diversification value used for the RMA life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { - 128'h629EA7F8_B17FA88F_EE02E3F0_864223A2 + 128'hCFF85679_453DA77D_92A176B8_7118AF11 }; // Compile-time random bits used for invalid tokens in the token mux parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { - 256'hE23A8CC3_1E2DE5E5_78D43D2D_CE49E360_CFB594AC_DDF17068_4F6EAD2B_7FEBFE89, - 256'h5523D7BC_4846A485_956C7F90_4B9EDED0_9B89A754_33566F49_63D9DC27_F3ECB11C, - 256'hE3B87AAA_7ABC8592_0B188108_3AFF7BDE_18EACFF8_5679453D_A77D92A1_76B87118, - 256'hAF11CDBE_78D67060_615A20B9_C0740F07_969CCD2D_10A1A6E7_988FA528_AC032E0A + 256'hCDBE78D6_7060615A_20B9C074_0F07969C_CD2D10A1_A6E7988F_A528AC03_2E0A6138, + 256'hCB8316FF_95C65CD7_A1A768B0_6E0106D6_0EDA0F1B_C67ADF85_BD9A56EA_088D33FF, + 256'hAA6A1155_AFB0169A_B2DE3973_D027EE30_B8F901F6_44EC7CD3_E56C8ED1_EC38739F, + 256'h1D0DEB7C_774199CF_6DD057F4_4C13E25C_7A5877BC_5242E6EE_63ECDF45_8AE6596E }; //////////////////////////////////////////// @@ -273,12 +273,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter alert_handler_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { - 32'h6138CB83 + 32'h87F9F973 }; // Compile-time random permutation for LFSR output parameter alert_handler_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { - 160'h21BFE532_078BB254_F11778E6_1A83B66E_E9A5E242 + 160'h0973A43F_9D7248BB_1CD76E05_0F7D801C_552A567B }; //////////////////////////////////////////// @@ -286,23 +286,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = { - 128'h169AB2DE_3973D027_EE30B8F9_01F644EC + 128'h1FF0189B_04A4F7FB_A960FE09_8A4FB9D4 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = { - 128'h7CD3E56C_8ED1EC38_739F1D0D_EB7C7741 + 128'h69171B95_0E364B0D_AC546956_8E661498 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetAonLfsrSeed = { - 64'h99CF6DD0_57F44C13 + 64'hFD89197C_CAE8EA08 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetAonLfsrPerm = { - 128'h96C1F7F8_D3BF2419_CB13DDB9_AE94F53F, - 256'h3EC27CA3_30488D32_C6E0DAE8_582D6401_A3564A2A_99C85BF2_2458414B_DD59E5F8 + 128'h8084A61E_3F7ACE53_82676E0D_70CA7224, + 256'hA0275A45_7C4E111E_DCBD456B_4A14622A_C6B81B5F_743F916C_FE57AB1B_2FC3B43F }; //////////////////////////////////////////// @@ -310,28 +310,28 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for default address key parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlAddrKey = { - 128'h69568E66_1498FD89_197CCAE8_EA08FF43 + 128'h57C22C88_4ED49D87_A5B56BA7_353C5321 }; // Compile-time random bits for default data key parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlDataKey = { - 128'hEFC2BFB1_C6AB5CC6_3E6F4741_E80F777C + 128'h42F50667_E220C5B7_24C3FDB6_D060653B }; // Compile-time random bits for default seeds parameter flash_ctrl_top_specific_pkg::all_seeds_t RndCnstFlashCtrlAllSeeds = { - 256'hB7FC0504_1A1B8963_50C9636D_6814D23E_2F5FF127_5EF19959_AAA8B6A0_04D55749, - 256'h84DED1CC_79BD6787_D6663AA5_E622682A_6525E083_CCDDBD2A_1B008057_C22C884E + 256'h42A96F88_B574E4D3_814F5116_B3E6F3E3_31DA1182_DBC29C89_4F1800ED_ECF7B176, + 256'h82D2CE3D_B9B12E1A_F4339E1F_45164A41_8EBC5221_0D58DC65_508E869A_F565C1B8 }; // Compile-time random bits for initial LFSR seed parameter flash_ctrl_top_specific_pkg::lfsr_seed_t RndCnstFlashCtrlLfsrSeed = { - 32'hD49D87A5 + 32'h7D687EE8 }; // Compile-time random permutation for LFSR output parameter flash_ctrl_top_specific_pkg::lfsr_perm_t RndCnstFlashCtrlLfsrPerm = { - 160'h4B862905_F72F7D15_C39AC6E7_FAE58041_147351B6 + 160'h4412AADB_8CFB5E5E_E69B093C_706871C4_9D75CC46 }; //////////////////////////////////////////// @@ -339,34 +339,34 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for register clearing. parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { - 64'h4F1800ED_ECF7B176 + 64'h7D513AEA_01E9EE42 }; // Permutation applied to the LFSR of the PRNG used for clearing. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { - 128'hC6824AF1_D7B6E2B6_FDDE9895_B41FC2D4, - 256'h073AF989_72397E53_10D91A7E_A9A1C3B6_560C852F_8D048544_79CC18BB_2E3F3D20 + 128'hB62A538F_363D42FA_FB9F820B_D8512591, + 256'h1E667DD3_3F83067C_5DC6C254_1A0D86A3_9E1D2EB1_FAEB3424_AD771B20_1A3D4583 }; // Permutation applied to the clearing PRNG output for clearing the second share of registers. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { - 128'h128E70AD_3D98BB12_1D15B823_8AA46970, - 256'hCE17B752_E6FF4919_09506536_19FD7874_B3DECBC9_286CBB68_FF960D0F_00E8E51F + 128'h7FE7ABF6_D1D47559_61FFC8EC_34870E2B, + 256'h4A8C450B_C24B8EB2_C1B59769_91B3A4F1_27BA683B_26214B03_5C68DB94_C3918DC1 }; // Default seed of the PRNG used for masking. parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { - 32'hDF0A4F7D, - 256'hFF07DB05_DE63910E_4EE4D8A2_C7D4022F_16ED8A24_F80EEBCF_8299839C_103EAE3C + 32'h5C0CAE7E, + 256'hD7FE6C45_D1534FD3_90C7B068_CFE89687_94DE88E8_FF4ADC3D_02EBFA0A_1D5FAA5E }; // Permutation applied to the output of the PRNG used for masking. parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { - 256'h60190A71_809B6A5A_28649904_46967288_875D3712_311F9542_5638901B_8B767D3A, - 256'h099A8F41_2D93533C_62835149_4C78333B_654F2A7A_4E47107F_79027B23_395C7735, - 256'h2B307C14_6F070C9E_4D5B1750_7389450D_213E1C24_5F548408_328C1520_6E03110B, - 256'h741A527E_9D55970E_05861E98_4485434B_67345863_48822729_6822369C_8A8E062E, - 256'h0F706992_914A013D_2C133F6D_40755700_26618D81_1D16949F_256C595E_6B66182F + 256'h3A4B9583_6675195F_84465A2D_54244D26_9A8A727E_6D023C67_2F59118F_8D974851, + 256'h6A1D824C_63583D61_773E077A_6E50884E_7B711433_3F324498_761F1E25_5C800079, + 256'h3B2C4F37_94299B86_13089E36_70435E93_575B6962_15092238_1264019C_0A1C9D04, + 256'h90600353_999F0B6F_7892681B_7C6C5521_0F31205D_7445054A_47739652_6B2B5685, + 256'h7F28890E_18308C41_2E8E0D27_8B1A427D_39491635_1065812A_40870623_1791340C }; //////////////////////////////////////////// @@ -374,58 +374,58 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random data for PRNG default seed parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { - 32'h02C22995, - 256'h7B7D1597_40CA72CE_50C55920_BA14E126_DCD0A3F6_C9B71D03_E571BEE0_E47E5B49 + 32'h23F40E35, + 256'h8F1BF4FE_1D5A50B1_0232A8B3_C33A6017_B9703656_1AA26231_042404E5_EF74645B }; // Compile-time random permutation for PRNG output parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { - 64'h1DDF635E_4E89ADA5, - 256'h2CD5389F_165D0C8D_42FA9EA0_260CA4F6_D5596AF1_A1C00141_E334A3A6_5B682949, - 256'h9D0747EE_9076C258_FE56C2A3_16DD74B3_07B1BCA1_A1A30442_24401EB5_EA95A38E, - 256'h778D177B_54C5C493_B79D883C_F08B95B0_26603D14_66E1C15C_CF530CC0_BC2B4B4C, - 256'h44B7020A_F1BEC6D1_5131C67A_646BB17F_A51F2AE0_8B816677_E65B29DF_EA698584, - 256'h09FBBA5F_06CDD12F_0F425D98_8145AEDE_10B20E5A_E4187D0D_4D4C1378_FE7B8F1B, - 256'h627B9400_77354043_C6B549F4_41EC872A_B56F2FB8_AAD94EA1_3C443099_11FA21EC, - 256'h8F54401A_7D1B9AD3_EDB57831_D70C1C41_5CE48EED_576B7352_22342CB6_A40E912F, - 256'hF845025E_C9EB04B6_3EABAC50_EE569A36_FDE859E5_250DDF19_D6C1C45C_49DC2966, - 256'h3E6B8F21_F803C0E3_655E9F91_CD80A401_7EA02B35_838CDC9B_85BD1900_25F6E486, - 256'h9A896078_0528F451_78668049_99C817C9_A5A01797_47273F0B_3A11D189_7292196A, - 256'hCB0E480A_EA36DB25_93CAACB8_6115E53C_DB92C289_FEBDA009_08DC3E3A_9797DD8D, - 256'h8129178A_8491411A_6EAA266B_344A345B_D55A72BE_48A3937D_B45D6779_4C0B38CF, - 256'h8779F846_8AA73315_928ED7F5_C42DECE8_56F610D1_E4EC3ABD_21C5C0DC_BA126BF5, - 256'hD24D02DA_E5DA1698_66300C46_0BA7FEC3_8953FA4B_12750184_12934065_A1B4324D, - 256'hE709CEAD_C4EA188E_1251ED12_6E573318_2140C4BD_E6DC712A_598352B4_B0822637, - 256'h4E5C5B47_C0B8B964_9E4C3201_638A4541_943FCB10_8D87B58B_2B157C58_6F869E4F, - 256'h3F4E59C8_1690CA6A_0E75666B_0C69B347_2283DC56_C12F1604_26B42A30_FD2E6AA0, - 256'hC2466C11_D0A908F3_5DCAB68A_19B7D903_6908A26F_558B0DA0_8ECB11FC_B2671931, - 256'hDC3452C6_96D2210C_6200D62C_EE223083_BBE2D759_4DC06A42_52A8996E_33991134, - 256'hABF19A7E_A9452274_3C954311_55312362_185EB180_07D21441_5581D324_A057D933, - 256'h208AB530_818C5D1B_27C2B26B_0DCEB860_9C09E8A1_39F30547_69461621_AA9A9906, - 256'h7BDA41C0_7F9A1399_E81F181B_0BE44500_159C02C0_B9E034A5_69C19B16_3D030A98, - 256'hA44CA99E_5E602A38_2A11B124_CFB9B198_B249B085_B6E469AD_B091610B_5911962E, - 256'h6A560246_CA610647_96E8E18B_CE4505D7_2BD0E551_4A15C5E0_4822C0A1_B6EC614E, - 256'h2092FDEA_3F20B743_16520484_D8398AD2_F0F42B48_481570A2_BA846745_A0B1F180, - 256'hEC889517_E7960D16_434C7916_B821E296_85654730_DB0720A8_14CD284A_DF5AB095, - 256'h5D8C7B74_BD9B84A6_AD6E03EE_9239AF67_0C5C1433_1447A819_248EDA19_79C721CE, - 256'h04C21D24_9322EE97_C419D2F8_65C7CCB1_02F29355_12D6FA8A_4CE108BC_03698ABA, - 256'h87A7A14B_F9639D99_B3BD5358_31734E07_A3189988_4F72D3E7_16CA699A_C9BD2508, - 256'h5D56781A_5AA9D902_8B539E71_3598BAED_767E9664_41304188_1A8D9B95_80A88085, - 256'h08758F03_823EC625_EFC2D23A_150897C0_C2B3CE98_C8533E52_D89E78BC_DDD9A4F6 + 64'h98252C01_F83B9DF1, + 256'hDD1048EE_A73D9675_AA193246_801790B1_F2B4D5B9_F2E08A18_D909C99C_DBF3348F, + 256'h8B6F127D_556684BA_A9CE17D8_C5BDED88_45545C01_7D27DB65_07BF9832_86D622D2, + 256'h76B89D76_6A2BDA91_89EC229E_B614B083_0DE474D7_B0147B35_42544580_402577B9, + 256'hFA775FE8_716B0517_5A7D056D_D45408D2_6E18665E_C9ADF06A_52DC2621_276DF968, + 256'hC20435DC_9A920804_74B56B1B_FF079206_F35E10C2_F103F978_AA215AA5_821127B7, + 256'h801B9928_028EF0BD_F1945093_2166D374_64B8E745_B0C00A43_C19ADA3E_AA4C5007, + 256'h39D92532_EC1AEDFB_96753426_C548D47A_1DA37AB8_5FEB3519_5722430A_12365A0F, + 256'h22530201_9091B9CA_05ECEA57_13959407_841C43E8_6C46507F_D353D23E_5E9B6718, + 256'h0E6A17D8_E50C38A0_8650B630_5BC98EF3_9E1C11C9_C07B0CAA_D49A7DD3_C53E1819, + 256'hD431C45C_B8531A4A_5B7D91D4_7C7E3C40_38E9A959_EAD994D8_00ADB1A0_043C0091, + 256'h302F732F_83A20518_988999B3_87CB483C_AE8094D2_59159EA8_D2E14B5C_97136EB0, + 256'h0A2A0A98_E6242530_F8EA78D3_D9157396_9C2975B4_046BCB48_99C75129_26DE6116, + 256'h5AFAE248_A3D37DD2_9CAF5510_0B38CF82_308DBE4A_A7ACE99F_CED1F5E2_2DEF2A39, + 256'h49C6AEF1_0D1E4EF1_80EA4F8D_D85371BD_498137C5_5A4D02DB_75FB1695_D70F0C7A, + 256'h40C460BA_5C15E106_E79053FA_D2C7AFC1_8412A740_5D81B5DE_0C937A42_4EB40C2B, + 256'h0D748FE9_951EBA26_E559DE0C_BF450311_B5A4E229_73054A96_60D4AD2C_268A0F12, + 256'h8C64B5B4_7C0B8B96_B4D925E1_AA3D8E83_9509471B_69CFF2C4_2361EFA2_CAE95F16, + 256'h1C3DC485_CFD3963C_05A6129A_A584599B_5243A8D1_C910F76F_856B1031_60426BD3, + 256'h030FD2E6_AA25246B_211D0A97_CF35DE13_68A34881_90369087_2204B2D6_2645F03B, + 256'h2E8866ED_8926B8C1_FD750D14_B20AB448_43188035_8B3A09FC_8D6D8ABE_FCAAEBD0, + 256'h7AC5279C_D6962A33_2C12913A_1E31F88C_AB468F53_EEC620D5_6074C928_15F64CC8, + 256'h22AC09C0_631746CC_54ACC5C3_73AE3327_027AB04E_8B9F3A24_151DA718_588689AC, + 256'hCB21067B_DA41C07F_A2139A6C_1F181B0B_EC450015_91AAE4BB_A034A569_509B163D, + 256'h030A98A4_4CA9A6A4_77980A8E_0A846C49_928CFC29_2D8B267B_985B6E46_99667E0E, + 256'h05842D64_9611962E_8A560246_CABB0647_96E8E18B_CE4505D7_2BD0E551_4A15C5E0, + 256'h4822C261_B6EC614E_2092FDEA_3F20B9E5_D08C9481_21360E62_B4BC3D0A_D212055C, + 256'h28B0E119_D1A71A0C_70F90EC8_89517E79_60D16434_9A516C12_1E296856_54730D87, + 256'h520A814C_D284ADF5_B3C955D8_C7C04BD9_B84A6AD6_EAE40FC3_48E6BD9C_31408B34, + 256'h331447A8_19248EDA_1979C721_CE04C21D_249322EE_971519D2_F8653D8C_B1031693, + 256'h5512D71E_8A4CE108_BC03698A_BA87A7A1_4041639D_99B3BD53_5805334E_07A31899, + 256'h884F72D3_E716CA69_9AC9BD25_085D5678_1A5AA9D9_028B539E_713598BA_ED767E96 }; // Compile-time random data for PRNG buffer default seed parameter kmac_pkg::buffer_lfsr_seed_t RndCnstKmacBufferLfsrSeed = { - 32'hADCDFC5C, - 256'h5F76D4A8_E259D88D_FE9B670A_A0DD992B_FE5D2E12_489D2250_4AA7AC1C_67F59CBA, - 256'h5482C1E3_5E6E3335_C20CC778_FC309917_B9C870AB_E0895D76_F862EF81_F419E3C6, - 256'hCDC8662C_71EAC141_666E443C_6492D9BC_F7A82420_750E5DFC_5E3ED4F2_907532E1 + 32'h3335C20C, + 256'hC778FC30_9917B9C8_70ABE089_5D76F862_EF81F419_E3C6CDC8_662C71EA_C141666E, + 256'h443C6492_D9BCF7A8_2420750E_5DFC5E3E_D4F29075_32E179EB_EC7ED7D3_A5EF4982, + 256'hF73ED91C_4B1CD0C8_5EC5E548_B40184A6_9EB1E543_96460E36_C55C459E_FE9E4383 }; // Compile-time random permutation for LFSR Message output parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = { - 128'h6413B04D_41226A3A_C89962EF_089605B8, - 256'hA93CCDD5_6CD8631C_FDBDEAA3_13434654_27E6102D_F97CBDE0_73E04A9D_357FBE9E + 128'hB3B8145B_84219701_BD602251_D1A7280C, + 256'hF1F7C7F2_13D9D985_AB28C0A5_7B8B3739_27112D4A_06D562F0_EFABBDF3_19E5EE9B }; //////////////////////////////////////////// @@ -433,30 +433,30 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for URND. parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { - 32'hDD57022C, - 256'h77EDE860_9C409D90_5B3C7819_B26A6743_28819928_C5D79BF1_DB63D11E_1C31BBC9 + 32'hCA6BC0B9, + 256'h6812DE7C_775A54FF_19343CB3_2040B349_0768889D_27E0BA85_88D34C05_BCF127DA }; // Compile-time random permutation for URND permutation in BN MAC. parameter otbn_pkg::bn_mac_urnd_perm_t RndCnstOtbnBnMacUrndPerm = { - 256'hEB13709F_16DF8721_23F81090_2AD0740A_3972B4D8_76A0F957_BDC21CB2_7B310C09, - 256'h60A9BB79_8EAE36FD_2DC1AC32_E9419245_0B825B4E_1DA36675_24BE9AEC_2FDD9358, - 256'hED7F2B8F_33043EE4_F5A71135_EFC8A54B_AA1E01C6_8C17C5F3_CE3763F6_53F7CD46, - 256'hB8981815_6D02FF6C_D1F2FC42_2CD20FD9_DB00738D_26C306AF_D76496C9_F04DFA61, - 256'hEE699B28_52A41F8A_486FE8F1_4FA1255D_3ACFAB2E_945EDAA6_1B6259AD_67296A0E, - 256'h55D64486_9EB72243_0DDCB5B0_D5898197_FE3B7E7D_38565C6E_30917AE2_4A78D4E6, - 256'h509CB683_BF4784CB_035F951A_FBB1E571_E7998008_51A2658B_E1BC054C_D3E385BA, - 256'hE0279D88_F40749EA_4020B33C_3419545A_777CDE12_68B9C06B_CA143DCC_C43FC7A8 + 256'hCBA9D4DA_F76D68E2_C5126323_1D79F8BC_88D05773_C25A27F4_2D72AD61_75D10682, + 256'h13BD4510_2120461C_0993B0EC_FF4E140A_F253FE98_B9EF87B8_A6399632_6C174D3C, + 256'h642CEA74_3126C776_A5DF9AAE_B4BB36A1_8E9041D3_34DB16F3_9F7FAA3F_8DA7C93D, + 256'h7092D77B_196BF6C0_66D2ABE4_4233E68C_EEC13E18_00C41135_5B15EDE7_DD4BE91E, + 256'h022F240F_9B2B8F77_6037D92A_04B2B585_58A0014C_E00CD50B_DC5469A3_2852BA8A, + 256'h1FA4486F_407C4FBE_255D3AF5_C82E945E_05C3AC1B_6259AFCA_67296A0E_55A8FD44, + 256'h869ED822_430DF9FC_E3FB8981_97B7E8EB_3B7E7DCD_38CE565C_6E3091C6_7A9D4A78, + 256'hFAF149E1_509CB683_BF4784F0_DE035F95_1ACFCCB1_0771B399_800851A2_D6658BE5 }; // Compile-time random reset value for IMem/DMem scrambling key. parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { - 128'hBEF1F0B9_24C470AC_5A998099_85DC415B + 128'h02030621_A4D3D738_71FDAF5A_D0C1DD1E }; // Compile-time random reset value for IMem/DMem scrambling nonce. parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { - 64'hA1EACED3_82D54C9E + 64'h95F99D71_29CA6861 }; //////////////////////////////////////////// @@ -464,73 +464,73 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrLfsrSeed = { - 64'h378D030E_A5D37665 + 64'hA4425B9C_C42EDBA8 }; // Compile-time random permutation for LFSR output parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrLfsrPerm = { - 128'h6F2F2513_8426806B_A968F86A_C76091BD, - 256'hE2EB50C3_59174ED2_1D673F23_A9F705DC_E4C2C0E2_7D5B498F_E2BD639A_135C03B5 + 128'h6B879784_62C36608_C73D622A_B25D09CF, + 256'h507FDA8C_50540F7B_3BA73947_EACA7C2C_92353DE9_6C475832_FC249AE9_FC52D162 }; // Compile-time random permutation for entropy used in share overriding parameter keymgr_pkg::rand_perm_t RndCnstKeymgrRandPerm = { - 160'h5CE46D90_7D6FA366_5558800F_AFDE8812_4B9E3C2E + 160'h85E8B7F6_3BF28A31_0247D131_C9E59677_EA9305A8 }; // Compile-time random bits for revision seed parameter keymgr_pkg::seed_t RndCnstKeymgrRevisionSeed = { - 256'h6D07801B_027BD4E9_BF578B14_6F616B60_82465E44_680CE936_49A84575_B465479F + 256'h227A9781_79AA2E6A_DC5EA5FD_83777D38_7766BA9E_8C77A65B_1AAD174D_D41ACA70 }; // Compile-time random bits for creator identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrCreatorIdentitySeed = { - 256'h31A97523_4377E00D_28EC32FA_5850E8A7_F607A49B_2CADE12A_F0DD48B9_227A9781 + 256'hD3807BA5_4E793023_FA711994_CCF5D2F4_2DAFFA84_621AB157_014B7050_9DA8413D }; // Compile-time random bits for owner intermediate identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIntIdentitySeed = { - 256'h79AA2E6A_DC5EA5FD_83777D38_7766BA9E_8C77A65B_1AAD174D_D41ACA70_D3807BA5 + 256'hDA43FECD_D6C1A586_93232D1C_3E361D85_6AB2D1DC_6455D87F_13C9A467_1446BEA8 }; // Compile-time random bits for owner identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIdentitySeed = { - 256'h4E793023_FA711994_CCF5D2F4_2DAFFA84_621AB157_014B7050_9DA8413D_DA43FECD + 256'h56D5FBB5_4BB5B253_A70BC372_CFC9BB0A_B38A5EDA_BEE7D224_D1A66837_8437DD24 }; // Compile-time random bits for software generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrSoftOutputSeed = { - 256'hD6C1A586_93232D1C_3E361D85_6AB2D1DC_6455D87F_13C9A467_1446BEA8_56D5FBB5 + 256'h797B602B_068C0A1A_ECA298C9_6A8130AB_336462CE_E1BF8C65_3FDE5A40_A24DF78E }; // Compile-time random bits for hardware generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrHardOutputSeed = { - 256'h4BB5B253_A70BC372_CFC9BB0A_B38A5EDA_BEE7D224_D1A66837_8437DD24_797B602B + 256'h146916DC_55F8CE6D_BFAAD089_10FBE182_2C22A17A_376FA131_5C0CB3C2_9CF4D10A }; // Compile-time random bits for generation seed when aes destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrAesSeed = { - 256'h068C0A1A_ECA298C9_6A8130AB_336462CE_E1BF8C65_3FDE5A40_A24DF78E_146916DC + 256'hE5C8F0C7_B034BF23_C9068E30_7D8513B7_734AA78C_C36F947A_2737BBC0_ACD1447B }; // Compile-time random bits for generation seed when kmac destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrKmacSeed = { - 256'h55F8CE6D_BFAAD089_10FBE182_2C22A17A_376FA131_5C0CB3C2_9CF4D10A_E5C8F0C7 + 256'hAA83C3FC_818BB3B4_A840AD32_14CEB3F3_54CA2E08_9302C3EE_1D695AA6_16283205 }; // Compile-time random bits for generation seed when otbn destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrOtbnSeed = { - 256'hB034BF23_C9068E30_7D8513B7_734AA78C_C36F947A_2737BBC0_ACD1447B_AA83C3FC + 256'hDB05CD6C_18888AD0_1FE046EA_FD8BF298_DB7D5FE0_FD32A296_89A0C154_9C28C210 }; // Compile-time random bits for generation seed when no CDI is selected parameter keymgr_pkg::seed_t RndCnstKeymgrCdi = { - 256'h818BB3B4_A840AD32_14CEB3F3_54CA2E08_9302C3EE_1D695AA6_16283205_DB05CD6C + 256'hC01FF7E6_E6D20E04_04E7B51D_020AA369_5DF42597_CACAEA4E_16EF75A4_823EE1BF }; // Compile-time random bits for generation seed when no destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrNoneSeed = { - 256'h18888AD0_1FE046EA_FD8BF298_DB7D5FE0_FD32A296_89A0C154_9C28C210_C01FF7E6 + 256'h100B50C3_A2C1BA79_A60BD0D9_47C26D8D_3C3874C6_B8E34A85_925CE73B_8F155098 }; //////////////////////////////////////////// @@ -538,14 +538,14 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { - 128'hE6D20E04_04E7B51D_020AA369_5DF42597, - 256'hCACAEA4E_16EF75A4_823EE1BF_100B50C3_A2C1BA79_A60BD0D9_47C26D8D_3C3874C6 + 128'h5EB503E8_E4071315_2D132E9E_94DA720A, + 256'h712D7D6B_7326F310_2BA57AB1_2F0C11E4_64E61308_8D6DF2CC_4352AA62_DF6B0719 }; // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { - 128'hB8E34A85_925CE73B_8F155098_5EB503E8, - 256'hE4071315_2D132E9E_94DA720A_712D7D6B_7326F310_2BA57AB1_2F0C11E4_64E61308 + 128'h9EA6C678_2AD9BB2E_78FA04C6_8991DE3B, + 256'h57A9B612_06E6C0A2_AFA6A3C5_6D97128C_7811E36A_2829DB02_5EC69547_062345C4 }; //////////////////////////////////////////// @@ -553,23 +553,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { - 128'h8D6DF2CC_4352AA62_DF6B0719_9EA6C678 + 128'h00F5EF1B_06A11965_0A85C302_37536DC3 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { - 128'h2AD9BB2E_78FA04C6_8991DE3B_57A9B612 + 128'hE35040DE_9AC1A6F2_B35C99FB_71E1AAAB }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { - 64'h06E6C0A2_AFA6A3C5 + 64'h3C208383_ADF50311 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { - 128'hD85E43B8_C91DA6F4_AB25C7CF_9F2AA0E8, - 256'h7D153BB2_D69984E2_43CFD436_D84266CA_301B5CC8_051FB15C_0DCA6B8F_5E8C495B + 128'hC4564278_F7EF9E82_75134F5D_3BA60A4E, + 256'h5B79422B_94F0BF97_3164ABDB_88601F23_7BA40543_681B309B_76E3CEA2_0691173F }; //////////////////////////////////////////// @@ -577,12 +577,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Fixed nonce used for address / data scrambling parameter bit [63:0] RndCnstRomCtrlScrNonce = { - 64'hD35500E5_A51BBA34 + 64'hAE3157B7_279A2BD0 }; // Randomised constant used as a scrambling key for ROM data parameter bit [127:0] RndCnstRomCtrlScrKey = { - 128'hA71D81E9_EB876B6F_1996B2BE_4B58DFCF + 128'hF45178AD_D4099B46_3A9BFADE_B0A249E6 }; //////////////////////////////////////////// @@ -590,22 +590,46 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for random instructions. parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexLfsrSeed = { - 32'hB830B9E2 + 32'h7A25FEEA }; // Permutation applied to the LFSR of the PRNG used for random instructions. parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexLfsrPerm = { - 160'hD77E228D_8F0E2274_9897B391_954FC06C_255E536B + 160'h1BFB401D_1FF454C2_CCCBAE6F_A4C2CEC0_9BB20792 }; // Default icache scrambling key parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexIbexKeyDefault = { - 128'hB7279A2B_D0F45178_ADD4099B_463A9BFA + 128'h57A6A15F_AA577395_193CDE4A_6705BD11 }; // Default icache scrambling nonce parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexIbexNonceDefault = { - 64'hDEB0A249_E67A25FE + 64'h203330A9_27A8CE1A + }; + + //////////////////////////////////////////// + // sram_ctrl_meta + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMetaSramKey = { + 128'hC88224A4_41C4192A_BE1DC426_FEEE2C9B + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMetaSramNonce = { + 128'h1C8B34B1_A821AFE5_22E11C40_49D9B85F + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMetaLfsrSeed = { + 64'h9DC3C99A_37868579 + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMetaLfsrPerm = { + 128'h1E9E0FD2_7066EB55_51413322_58A78867, + 256'h7EF98FDB_2EFB6F33_2DF18E03_0FC49285_1BC98BCD_49D26572_BC43160A_970A16AD }; endpackage : top_earlgrey_rnd_cnst_pkg diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 077e0bb519256..0f1815698de7e 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -99,6 +99,7 @@ module top_earlgrey #( parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 2, + parameter int SramCtrlMainNumAddrScrRounds = 2, parameter bit SramCtrlMainEccCorrection = 0, // parameters for rom_ctrl parameter RomCtrlBootRomInitFile = "", @@ -112,6 +113,10 @@ module top_earlgrey #( parameter ibex_pkg::pmp_cfg_t RvCoreIbexPMPRstCfg[16] = ibex_pmp_reset_pkg::PmpCfgRst, parameter logic [33:0] RvCoreIbexPMPRstAddr[16] = ibex_pmp_reset_pkg::PmpAddrRst, parameter ibex_pkg::pmp_mseccfg_t RvCoreIbexPMPRstMsecCfg = ibex_pmp_reset_pkg::PmpMseccfgRst, + parameter ibex_pkg::base_isa_e RvCoreIbexBaseIsa = ibex_pkg::BaseIsaRV32IorCHERIoT, + parameter int unsigned RvCoreIbexCheriotRevBitmapAddrWidth = 9, + parameter int unsigned RvCoreIbexCheriotRevBitmapBaseAddr = 32'h1100_0000, + parameter int unsigned RvCoreIbexCheriotTrvkHeapBaseAddr = 32'h1000_0000, parameter bit RvCoreIbexRV32E = 0, parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle, parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey, @@ -136,7 +141,20 @@ module top_earlgrey #( parameter bit RvCoreIbexPipeLine = 0, parameter logic [tlul_pkg::RsvdWidth-1:0] RvCoreIbexTlulHostUserRsvdBits = '0, parameter logic [31:0] RvCoreIbexCsrMvendorId = '0, - parameter logic [31:0] RvCoreIbexCsrMimpId = '0 + parameter logic [31:0] RvCoreIbexCsrMimpId = '0, + // parameters for cheriot + parameter logic [top_pkg::TL_AW-1:0] CheriotMainSramBaseAddr = 32'h1000_0000, + parameter logic [top_pkg::TL_AW-1:0] CheriotMainSramTopAddr = 32'h1002_0000, + parameter logic [top_pkg::TL_AW-1:0] CheriotNvmBaseAddr = 32'h2000_0000, + parameter logic [top_pkg::TL_AW-1:0] CheriotNvmTopAddr = 32'h2020_0000, + parameter logic [top_pkg::TL_AW-1:0] CheriotMetaSramBaseAddr = 32'h1100_0000, + // parameters for sram_ctrl_meta + parameter int SramCtrlMetaInstSize = 36864, + parameter int SramCtrlMetaNumRamInst = 1, + parameter bit SramCtrlMetaInstrExec = 0, + parameter int SramCtrlMetaNumPrinceRoundsHalf = 2, + parameter int SramCtrlMetaNumAddrScrRounds = 0, + parameter bit SramCtrlMetaEccCorrection = 0 ) ( // Inter-module Signal External type output alert_handler_pkg::alert_crashdump_t alert_handler_crashdump_o, @@ -188,6 +206,7 @@ module top_earlgrey #( input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMetaNumRamInst-1:0] sram_ctrl_meta_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, input prim_ram_1p_pkg::ram_1p_cfg_t usb_ram_1p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, @@ -306,6 +325,8 @@ module top_earlgrey #( localparam bit RomCtrlFlopToKmac = 1'b0; // local parameters for rv_core_ibex localparam bit RvCoreIbexInstructionPipeline = 1'b0; + // local parameters for sram_ctrl_meta + localparam int SramCtrlMetaOutstanding = 2; // Signals logic [56:0] mio_p2d; @@ -414,6 +435,8 @@ module top_earlgrey #( // sram_ctrl_main // rom_ctrl // rv_core_ibex + // cheriot + // sram_ctrl_meta logic [183:0] intr_vector; @@ -666,12 +689,21 @@ module top_earlgrey #( logic rv_plic_msip; logic rv_plic_irq; logic rv_dm_debug_req; + tlul_pkg::tl_h2d_t rv_core_ibex_cored_tl_h_req; + tlul_pkg::tl_d2h_t rv_core_ibex_cored_tl_h_rsp; + tlul_pkg::tl_h2d_t rv_core_ibex_corerevbm_tl_req; + tlul_pkg::tl_d2h_t rv_core_ibex_corerevbm_tl_rsp; + logic rv_core_ibex_cored_tag_h2d; spi_device_pkg::passthrough_req_t spi_device_passthrough_req; spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; + tlul_pkg::tl_h2d_t cheriot_meta_sram_tl_req; + tlul_pkg::tl_d2h_t cheriot_meta_sram_tl_rsp; + logic cheriot_cored_tag_d2h; + prim_mubi_pkg::mubi4_t rv_core_ibex_cheriot_ena; tlul_pkg::tl_h2d_t main_tl_rv_core_ibex__corei_req; tlul_pkg::tl_d2h_t main_tl_rv_core_ibex__corei_rsp; - tlul_pkg::tl_h2d_t main_tl_rv_core_ibex__cored_req; - tlul_pkg::tl_d2h_t main_tl_rv_core_ibex__cored_rsp; + tlul_pkg::tl_h2d_t main_tl_cheriot__cored_req; + tlul_pkg::tl_d2h_t main_tl_cheriot__cored_rsp; tlul_pkg::tl_h2d_t main_tl_rv_dm__sba_req; tlul_pkg::tl_d2h_t main_tl_rv_dm__sba_rsp; tlul_pkg::tl_h2d_t rv_dm_regs_tl_d_req; @@ -722,6 +754,12 @@ module top_earlgrey #( tlul_pkg::tl_d2h_t sram_ctrl_main_regs_tl_rsp; tlul_pkg::tl_h2d_t sram_ctrl_main_ram_tl_req; tlul_pkg::tl_d2h_t sram_ctrl_main_ram_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_meta_regs_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_meta_regs_tl_rsp; + tlul_pkg::tl_h2d_t cheriot_regs_tl_d_req; + tlul_pkg::tl_d2h_t cheriot_regs_tl_d_rsp; + tlul_pkg::tl_h2d_t cheriot_revbm_tl_d_req; + tlul_pkg::tl_d2h_t cheriot_revbm_tl_d_rsp; tlul_pkg::tl_h2d_t uart0_tl_req; tlul_pkg::tl_d2h_t uart0_tl_rsp; tlul_pkg::tl_h2d_t uart1_tl_req; @@ -782,14 +820,6 @@ module top_earlgrey #( assign ast_usb_ram_1p_cfg = usb_ram_1p_cfg_i; assign ast_rom_cfg = rom_cfg_i; - // Dummy signal definitions for unused partial inter-module signals - otp_ctrl_pkg::sram_otp_key_rsp_t unused_otp_ctrl_sram_otp_key_rsp3; - - // Assign unused partial inter-module signals - assign unused_otp_ctrl_sram_otp_key_rsp3 = otp_ctrl_sram_otp_key_rsp[3]; - - // Assign undriven partial inter-module signals - assign otp_ctrl_sram_otp_key_req[3] = '0; // OTP HW_CFG* Broadcast signals. // TODO(#6713): The actual struct breakout and mapping currently needs to @@ -2385,6 +2415,7 @@ module top_earlgrey #( .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlMainNumAddrScrRounds), .Outstanding(SramCtrlMainOutstanding), .EccCorrection(SramCtrlMainEccCorrection) ) u_sram_ctrl_main ( @@ -2465,6 +2496,10 @@ module top_earlgrey #( .PMPRstCfg(RvCoreIbexPMPRstCfg), .PMPRstAddr(RvCoreIbexPMPRstAddr), .PMPRstMsecCfg(RvCoreIbexPMPRstMsecCfg), + .BaseIsa(RvCoreIbexBaseIsa), + .CheriotRevBitmapAddrWidth(RvCoreIbexCheriotRevBitmapAddrWidth), + .CheriotRevBitmapBaseAddr(RvCoreIbexCheriotRevBitmapBaseAddr), + .CheriotTrvkHeapBaseAddr(RvCoreIbexCheriotTrvkHeapBaseAddr), .RV32E(RvCoreIbexRV32E), .RV32M(RvCoreIbexRV32M), .RV32B(RvCoreIbexRV32B), @@ -2513,6 +2548,13 @@ module top_earlgrey #( // Inter-module signals .rst_cpu_n_o(), + .cheriot_ena_o(rv_core_ibex_cheriot_ena), + .cored_tl_h_o(rv_core_ibex_cored_tl_h_req), + .cored_tl_h_i(rv_core_ibex_cored_tl_h_rsp), + .cored_tag_h2d_o(rv_core_ibex_cored_tag_h2d), + .cored_tag_d2h_i(cheriot_cored_tag_d2h), + .corerevbm_tl_o(rv_core_ibex_corerevbm_tl_req), + .corerevbm_tl_i(rv_core_ibex_corerevbm_tl_rsp), .ram_cfg_icache_tag_i(ast_ram_1p_cfg), .ram_cfg_rsp_icache_tag_o(), .ram_cfg_icache_data_i(ast_ram_1p_cfg), @@ -2532,17 +2574,96 @@ module top_earlgrey #( .nmi_wdog_i(aon_timer_aon_nmi_wdog_timer_bark_i), .edn_o(edn0_edn_req[7]), .edn_i(edn0_edn_rsp[7]), - .icache_otp_key_o(otp_ctrl_sram_otp_key_req[2]), - .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]), + .icache_otp_key_o(otp_ctrl_sram_otp_key_req[3]), + .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[3]), .fpga_info_i(fpga_info_i), .corei_tl_h_o(main_tl_rv_core_ibex__corei_req), .corei_tl_h_i(main_tl_rv_core_ibex__corei_rsp), - .cored_tl_h_o(main_tl_rv_core_ibex__cored_req), - .cored_tl_h_i(main_tl_rv_core_ibex__cored_rsp), .cfg_tl_d_i(rv_core_ibex_cfg_tl_d_req), .cfg_tl_d_o(rv_core_ibex_cfg_tl_d_rsp) ); + cheriot #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .MainSramBaseAddr(CheriotMainSramBaseAddr), + .MainSramTopAddr(CheriotMainSramTopAddr), + .NvmBaseAddr(CheriotNvmBaseAddr), + .NvmTopAddr(CheriotNvmTopAddr), + .MetaSramBaseAddr(CheriotMetaSramBaseAddr) + ) u_cheriot ( + // Clock and reset connections + .clk_i(clkmgr_aon_clocks_i.clk_main_infra), + .rst_ni(rstmgr_aon_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), + + // alert_handler[63]: fatal_fault + .alert_tx_o(alert_tx[63]), + .alert_rx_i(alert_rx[63]), + + // Inter-module signals + .cheriot_ena_i(rv_core_ibex_cheriot_ena), + .cored_tl_d_i(rv_core_ibex_cored_tl_h_req), + .cored_tl_d_o(rv_core_ibex_cored_tl_h_rsp), + .cored_tag_h2d_i(rv_core_ibex_cored_tag_h2d), + .cored_tag_d2h_o(cheriot_cored_tag_d2h), + .corerevbm_tl_i(rv_core_ibex_corerevbm_tl_req), + .corerevbm_tl_o(rv_core_ibex_corerevbm_tl_rsp), + .meta_sram_tl_o(cheriot_meta_sram_tl_req), + .meta_sram_tl_i(cheriot_meta_sram_tl_rsp), + .cored_tl_h_o(main_tl_cheriot__cored_req), + .cored_tl_h_i(main_tl_cheriot__cored_rsp), + .regs_tl_d_i(cheriot_regs_tl_d_req), + .regs_tl_d_o(cheriot_regs_tl_d_rsp), + .revbm_tl_d_i(cheriot_revbm_tl_d_req), + .revbm_tl_d_o(cheriot_revbm_tl_d_rsp) + ); + + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstSramKey(RndCnstSramCtrlMetaSramKey), + .RndCnstSramNonce(RndCnstSramCtrlMetaSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlMetaLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlMetaLfsrPerm), + .MemSizeRam(36864), + .InstSize(SramCtrlMetaInstSize), + .NumRamInst(SramCtrlMetaNumRamInst), + .InstrExec(SramCtrlMetaInstrExec), + .NumPrinceRoundsHalf(SramCtrlMetaNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlMetaNumAddrScrRounds), + .Outstanding(SramCtrlMetaOutstanding), + .EccCorrection(SramCtrlMetaEccCorrection) + ) u_sram_ctrl_meta ( + // Clock and reset connections + .clk_i(clkmgr_aon_clocks_i.clk_main_infra), + .clk_otp_i(clkmgr_aon_clocks_i.clk_io_div4_infra), + .rst_ni(rstmgr_aon_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), + .rst_otp_ni(rstmgr_aon_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), + + // alert_handler[64]: fatal_error + .alert_tx_o(alert_tx[64]), + .alert_rx_i(alert_rx[64]), + + // RACL policies + .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[2]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]), + .cfg_i(sram_ctrl_meta_cfg_i), + .cfg_rsp_o(), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .sram_rerror_o(), + .regs_tl_i(sram_ctrl_meta_regs_tl_req), + .regs_tl_o(sram_ctrl_meta_regs_tl_rsp), + .ram_tl_i(cheriot_meta_sram_tl_req), + .ram_tl_o(cheriot_meta_sram_tl_rsp) + ); + // Interrupt assignments assign intr_vector = { @@ -2718,9 +2839,9 @@ module top_earlgrey #( .tl_rv_core_ibex__corei_i(main_tl_rv_core_ibex__corei_req), .tl_rv_core_ibex__corei_o(main_tl_rv_core_ibex__corei_rsp), - // port: tl_rv_core_ibex__cored - .tl_rv_core_ibex__cored_i(main_tl_rv_core_ibex__cored_req), - .tl_rv_core_ibex__cored_o(main_tl_rv_core_ibex__cored_rsp), + // port: tl_cheriot__cored + .tl_cheriot__cored_i(main_tl_cheriot__cored_req), + .tl_cheriot__cored_o(main_tl_cheriot__cored_rsp), // port: tl_rv_dm__sba .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req), @@ -2822,6 +2943,18 @@ module top_earlgrey #( .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req), .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp), + // port: tl_sram_ctrl_meta__regs + .tl_sram_ctrl_meta__regs_o(sram_ctrl_meta_regs_tl_req), + .tl_sram_ctrl_meta__regs_i(sram_ctrl_meta_regs_tl_rsp), + + // port: tl_cheriot__regs + .tl_cheriot__regs_o(cheriot_regs_tl_d_req), + .tl_cheriot__regs_i(cheriot_regs_tl_d_rsp), + + // port: tl_cheriot__revbm + .tl_cheriot__revbm_o(cheriot_revbm_tl_d_req), + .tl_cheriot__revbm_i(cheriot_revbm_tl_d_rsp), + .scanmode_i ); diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pd_aon.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pd_aon.sv index ef38d345829d5..0a309e18caa92 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pd_aon.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pd_aon.sv @@ -29,6 +29,7 @@ module top_earlgrey_pd_aon #( parameter int SramCtrlRetAonNumRamInst = 1, parameter bit SramCtrlRetAonInstrExec = 0, parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, + parameter int SramCtrlRetAonNumAddrScrRounds = 2, parameter bit SramCtrlRetAonEccCorrection = 0 ) ( // Inter-module Signal External type @@ -496,6 +497,7 @@ module top_earlgrey_pd_aon #( .NumRamInst(SramCtrlRetAonNumRamInst), .InstrExec(SramCtrlRetAonInstrExec), .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlRetAonNumAddrScrRounds), .Outstanding(SramCtrlRetAonOutstanding), .EccCorrection(SramCtrlRetAonEccCorrection) ) u_sram_ctrl_ret_aon ( diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 76d314b844d3f..cfb6b5fefb800 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -449,6 +449,26 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES = 32'h100; + /** + * Peripheral base address for regs device on cheriot in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR = 32'h411B0000; + + /** + * Peripheral size in bytes for regs device on cheriot in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_CHERIOT_REGS_SIZE_BYTES = 32'h4; + + /** + * Peripheral base address for regs device on sram_ctrl_meta in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR = 32'h411D0000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_meta in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES = 32'h40; + /** * Memory base address for ram memory on sram_ctrl_ret_aon in top earlgrey. */ @@ -489,6 +509,26 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES = 32'h8000; + /** + * Memory base address for revbm memory on cheriot in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_CHERIOT_REVBM_BASE_ADDR = 32'h11000000; + + /** + * Memory size for revbm memory on cheriot in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_CHERIOT_REVBM_SIZE_BYTES = 32'h800; + + /** + * Memory base address for ram memory on sram_ctrl_meta in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR = 32'h11000000; + + /** + * Memory size for ram memory on sram_ctrl_meta in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES = 32'h9000; + // Enumeration of alert modules typedef enum int unsigned { @@ -531,6 +571,8 @@ package top_earlgrey_pkg; TopEarlgreyAlertPeripheralSramCtrlMain = 36, TopEarlgreyAlertPeripheralRomCtrl = 37, TopEarlgreyAlertPeripheralRvCoreIbex = 38, + TopEarlgreyAlertPeripheralCheriot = 39, + TopEarlgreyAlertPeripheralSramCtrlMeta = 40, TopEarlgreyAlertPeripheralCount } alert_peripheral_e; @@ -599,6 +641,8 @@ package top_earlgrey_pkg; TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 60, TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 61, TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 62, + TopEarlgreyAlertIdCheriotFatalFault = 63, + TopEarlgreyAlertIdSramCtrlMetaFatalError = 64, TopEarlgreyAlertIdCount } alert_id_e; @@ -1048,6 +1092,7 @@ package top_earlgrey_pkg; PeripheralAlertHandler, PeripheralAonTimerAon, PeripheralAst, + PeripheralCheriot, PeripheralClkmgrAon, PeripheralCsrng, PeripheralEdn0, @@ -1078,6 +1123,7 @@ package top_earlgrey_pkg; PeripheralSpiHost0, PeripheralSpiHost1, PeripheralSramCtrlMain, + PeripheralSramCtrlMeta, PeripheralSramCtrlRetAon, PeripheralSysrstCtrlAon, PeripheralUart0, diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index 56099c4f3b064..49d9f86f5bf51 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -637,6 +637,34 @@ pub const RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x411F0000; /// `RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_CFG_SIZE_BYTES`. pub const RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x100; +/// Peripheral base address for regs device on cheriot in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const CHERIOT_REGS_BASE_ADDR: usize = 0x411B0000; + +/// Peripheral size for regs device on cheriot in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #CHERIOT_REGS_BASE_ADDR and +/// `CHERIOT_REGS_BASE_ADDR + CHERIOT_REGS_SIZE_BYTES`. +pub const CHERIOT_REGS_SIZE_BYTES: usize = 0x4; + +/// Peripheral base address for regs device on sram_ctrl_meta in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_META_REGS_BASE_ADDR: usize = 0x411D0000; + +/// Peripheral size for regs device on sram_ctrl_meta in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_META_REGS_BASE_ADDR and +/// `SRAM_CTRL_META_REGS_BASE_ADDR + SRAM_CTRL_META_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_META_REGS_SIZE_BYTES: usize = 0x40; + /// Memory base address for ram memory on sram_ctrl_ret_aon in top earlgrey. pub const SRAM_CTRL_RET_AON_RAM_BASE_ADDR: usize = 0x40600000; @@ -661,6 +689,18 @@ pub const ROM_CTRL_ROM_BASE_ADDR: usize = 0x8000; /// Memory size for rom memory on rom_ctrl in top earlgrey. pub const ROM_CTRL_ROM_SIZE_BYTES: usize = 0x8000; +/// Memory base address for revbm memory on cheriot in top earlgrey. +pub const CHERIOT_REVBM_BASE_ADDR: usize = 0x11000000; + +/// Memory size for revbm memory on cheriot in top earlgrey. +pub const CHERIOT_REVBM_SIZE_BYTES: usize = 0x800; + +/// Memory base address for ram memory on sram_ctrl_meta in top earlgrey. +pub const SRAM_CTRL_META_RAM_BASE_ADDR: usize = 0x11000000; + +/// Memory size for ram memory on sram_ctrl_meta in top earlgrey. +pub const SRAM_CTRL_META_RAM_SIZE_BYTES: usize = 0x9000; + /// PLIC Interrupt Source Peripheral. /// /// Enumeration used to determine which peripheral asserted the corresponding @@ -1812,6 +1852,10 @@ pub enum AlertPeripheral { RomCtrl = 38, /// rv_core_ibex RvCoreIbex = 39, + /// cheriot + Cheriot = 40, + /// sram_ctrl_meta + SramCtrlMeta = 41, } /// Alert Handler Alert Source. @@ -1947,6 +1991,10 @@ pub enum AlertId { RvCoreIbexFatalHwErr = 61, /// rv_core_ibex_recov_hw_err RvCoreIbexRecovHwErr = 62, + /// cheriot_fatal_fault + CheriotFatalFault = 63, + /// sram_ctrl_meta_fatal_error + SramCtrlMetaFatalError = 64, } impl TryFrom for AlertId { @@ -2016,6 +2064,8 @@ impl TryFrom for AlertId { 60 => Ok(Self::RvCoreIbexRecovSwErr), 61 => Ok(Self::RvCoreIbexFatalHwErr), 62 => Ok(Self::RvCoreIbexRecovHwErr), + 63 => Ok(Self::CheriotFatalFault), + 64 => Ok(Self::SramCtrlMetaFatalError), _ => Err(val), } } @@ -2025,7 +2075,7 @@ impl TryFrom for AlertId { /// /// This array is a mapping from `AlertId` to /// `AlertPeripheral`. -pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 63] = [ +pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [ // Uart0FatalFault -> AlertPeripheral::Uart0 AlertPeripheral::Uart0, // Uart1FatalFault -> AlertPeripheral::Uart1 @@ -2152,6 +2202,10 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 63] = [ AlertPeripheral::RvCoreIbex, // RvCoreIbexRecovHwErr -> AlertPeripheral::RvCoreIbex AlertPeripheral::RvCoreIbex, + // CheriotFatalFault -> AlertPeripheral::Cheriot + AlertPeripheral::Cheriot, + // SramCtrlMetaFatalError -> AlertPeripheral::SramCtrlMeta + AlertPeripheral::SramCtrlMeta, ]; // PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} diff --git a/hw/top_earlgrey/sw/autogen/tests/BUILD b/hw/top_earlgrey/sw/autogen/tests/BUILD index baabb0e59aa66..13bcfdc61405b 100644 --- a/hw/top_earlgrey/sw/autogen/tests/BUILD +++ b/hw/top_earlgrey/sw/autogen/tests/BUILD @@ -121,6 +121,7 @@ opentitan_test( "//sw/device/lib/dif/autogen:aes", "//sw/device/lib/dif/autogen:alert_handler", "//sw/device/lib/dif/autogen:aon_timer", + "//sw/device/lib/dif/autogen:cheriot", "//sw/device/lib/dif/autogen:clkmgr", "//sw/device/lib/dif/autogen:csrng", "//sw/device/lib/dif/autogen:edn", diff --git a/hw/top_earlgrey/sw/autogen/tests/alert_test.c b/hw/top_earlgrey/sw/autogen/tests/alert_test.c index db73bb2aa8143..4667a1f269cb9 100644 --- a/hw/top_earlgrey/sw/autogen/tests/alert_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/alert_test.c @@ -14,6 +14,7 @@ #include "sw/device/lib/dif/autogen/dif_aes_autogen.h" #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" #include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h" +#include "sw/device/lib/dif/autogen/dif_cheriot_autogen.h" #include "sw/device/lib/dif/autogen/dif_clkmgr_autogen.h" #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h" #include "sw/device/lib/dif/autogen/dif_edn_autogen.h" @@ -55,6 +56,7 @@ static dif_alert_handler_t alert_handler; static dif_adc_ctrl_t adc_ctrl_aon; static dif_aes_t aes; static dif_aon_timer_t aon_timer_aon; +static dif_cheriot_t cheriot; static dif_clkmgr_t clkmgr_aon; static dif_csrng_t csrng; static dif_edn_t edn0; @@ -83,6 +85,7 @@ static dif_spi_device_t spi_device; static dif_spi_host_t spi_host0; static dif_spi_host_t spi_host1; static dif_sram_ctrl_t sram_ctrl_main; +static dif_sram_ctrl_t sram_ctrl_meta; static dif_sram_ctrl_t sram_ctrl_ret_aon; static dif_sysrst_ctrl_t sysrst_ctrl_aon; static dif_uart_t uart0; @@ -108,6 +111,9 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR); CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_cheriot_init(base_addr, &cheriot)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR); CHECK_DIF_OK(dif_clkmgr_init(base_addr, &clkmgr_aon)); @@ -192,6 +198,9 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR); CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_main)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_meta)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR); CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_ret_aon)); @@ -316,6 +325,21 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } + // Write cheriot's alert_test reg and check alert_cause. + for (dif_cheriot_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_cheriot_alert_force(&cheriot, kDifCheriotAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = (int)kTopEarlgreyAlertIdCheriotFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + // Write clkmgr's alert_test reg and check alert_cause. for (dif_clkmgr_alert_t i = 0; i < 2; ++i) { CHECK_DIF_OK(dif_clkmgr_alert_force(&clkmgr_aon, kDifClkmgrAlertRecovFault + i)); @@ -739,6 +763,21 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } + // Write sram_ctrl's alert_test reg and check alert_cause. + for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_meta, kDifSramCtrlAlertFatalError + i)); + + // Verify that alert handler received it. + exp_alert = (int)kTopEarlgreyAlertIdSramCtrlMetaFatalError + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + // Write sram_ctrl's alert_test reg and check alert_cause. for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) { CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_ret_aon, kDifSramCtrlAlertFatalError + i)); diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index 379762e5ab176..565f334a70107 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c @@ -16,7 +16,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[63] = { + top_earlgrey_alert_for_peripheral[65] = { [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0, [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1, [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2, @@ -80,6 +80,8 @@ const top_earlgrey_alert_peripheral_t [kTopEarlgreyAlertIdRvCoreIbexRecovSwErr] = kTopEarlgreyAlertPeripheralRvCoreIbex, [kTopEarlgreyAlertIdRvCoreIbexFatalHwErr] = kTopEarlgreyAlertPeripheralRvCoreIbex, [kTopEarlgreyAlertIdRvCoreIbexRecovHwErr] = kTopEarlgreyAlertPeripheralRvCoreIbex, + [kTopEarlgreyAlertIdCheriotFatalFault] = kTopEarlgreyAlertPeripheralCheriot, + [kTopEarlgreyAlertIdSramCtrlMetaFatalError] = kTopEarlgreyAlertPeripheralSramCtrlMeta, }; /** diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 466b32e3bdf64..93e3546026611 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -822,6 +822,42 @@ extern "C" { */ #define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u +/** + * Peripheral base address for regs device on cheriot in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR 0x411B0000u + +/** + * Peripheral size for regs device on cheriot in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR and + * `TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR + TOP_EARLGREY_CHERIOT_REGS_SIZE_BYTES`. + */ +#define TOP_EARLGREY_CHERIOT_REGS_SIZE_BYTES 0x4u + +/** + * Peripheral base address for regs device on sram_ctrl_meta in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR 0x411D0000u + +/** + * Peripheral size for regs device on sram_ctrl_meta in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR and + * `TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES`. + */ +#define TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES 0x40u + /** * Memory base address for ram memory on sram_ctrl_ret_aon in top earlgrey. @@ -863,6 +899,26 @@ extern "C" { */ #define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000u +/** + * Memory base address for revbm memory on cheriot in top earlgrey. + */ +#define TOP_EARLGREY_CHERIOT_REVBM_BASE_ADDR 0x11000000u + +/** + * Memory size for revbm memory on cheriot in top earlgrey. + */ +#define TOP_EARLGREY_CHERIOT_REVBM_SIZE_BYTES 0x800u + +/** + * Memory base address for ram memory on sram_ctrl_meta in top earlgrey. + */ +#define TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR 0x11000000u + +/** + * Memory size for ram memory on sram_ctrl_meta in top earlgrey. + */ +#define TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES 0x9000u + /** * PLIC Interrupt Source Peripheral. @@ -1166,7 +1222,9 @@ typedef enum top_earlgrey_alert_peripheral { kTopEarlgreyAlertPeripheralSramCtrlMain = 37, /**< sram_ctrl_main */ kTopEarlgreyAlertPeripheralRomCtrl = 38, /**< rom_ctrl */ kTopEarlgreyAlertPeripheralRvCoreIbex = 39, /**< rv_core_ibex */ - kTopEarlgreyAlertPeripheralLast = 39, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralCheriot = 40, /**< cheriot */ + kTopEarlgreyAlertPeripheralSramCtrlMeta = 41, /**< sram_ctrl_meta */ + kTopEarlgreyAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -1239,7 +1297,9 @@ typedef enum top_earlgrey_alert_id { kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 60, /**< rv_core_ibex_recov_sw_err */ kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 61, /**< rv_core_ibex_fatal_hw_err */ kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 62, /**< rv_core_ibex_recov_hw_err */ - kTopEarlgreyAlertIdLast = 62, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdCheriotFatalFault = 63, /**< cheriot_fatal_fault */ + kTopEarlgreyAlertIdSramCtrlMetaFatalError = 64, /**< sram_ctrl_meta_fatal_error */ + kTopEarlgreyAlertIdLast = 64, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1249,7 +1309,7 @@ typedef enum top_earlgrey_alert_id { * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[63]; + top_earlgrey_alert_for_peripheral[65]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index 94c62ae493a3e..0e5caa3d66494 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -65,6 +65,26 @@ */ #define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000 +/** + * Memory base for revbm memory on cheriot in top earlgrey. + */ +#define TOP_EARLGREY_CHERIOT_REVBM_BASE_ADDR 0x11000000 + +/** + * Memory size for revbm memory on cheriot in top earlgrey. + */ +#define TOP_EARLGREY_CHERIOT_REVBM_SIZE_BYTES 0x800 + +/** + * Memory base for ram memory on sram_ctrl_meta in top earlgrey. + */ +#define TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR 0x11000000 + +/** + * Memory size for ram memory on sram_ctrl_meta in top earlgrey. + */ +#define TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES 0x9000 + /** * Peripheral base address for uart0 in top earlgrey. @@ -814,6 +834,40 @@ * `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`. */ #define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100 +/** + * Peripheral base address for regs device on cheriot in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR 0x411B0000 + +/** + * Peripheral size for regs device on cheriot in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR and + * `TOP_EARLGREY_CHERIOT_REGS_BASE_ADDR + TOP_EARLGREY_CHERIOT_REGS_SIZE_BYTES`. + */ +#define TOP_EARLGREY_CHERIOT_REGS_SIZE_BYTES 0x4 +/** + * Peripheral base address for regs device on sram_ctrl_meta in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR 0x411D0000 + +/** + * Peripheral size for regs device on sram_ctrl_meta in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR and + * `TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES`. + */ +#define TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES 0x40 /** * MMIO Region diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld index 19648541707bc..96121fba50336 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld @@ -18,6 +18,8 @@ MEMORY { eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000 + cheriot_revbm(rwx) : ORIGIN = 0x11000000, LENGTH = 0x800 + ram_cheriot_meta(rwx) : ORIGIN = 0x11000000, LENGTH = 0x9000 rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000 owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000 } diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 9983dcbd839fc..d33425c835ed4 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -17,6 +17,7 @@ filesets: - lowrisc:ip:rv_dm - lowrisc:ip:rv_timer - lowrisc:ip:tlul + - lowrisc:ip:cheriot - lowrisc:ip:spi_device - lowrisc:ip:spi_host - lowrisc:ip:i2c diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson index 85ce67e2d7b34..23019f3b50f0b 100644 --- a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson +++ b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson @@ -3842,6 +3842,15 @@ expose: "true" name_top: SramCtrlMainNumPrinceRoundsHalf } + { + name: NumAddrScrRounds + desc: Number of address scrambling rounds. 0 disables address scrambling + type: int + default: "2" + local: "false" + expose: "true" + name_top: SramCtrlMainNumAddrScrRounds + } { name: Outstanding desc: Number of outstanding TLUL transactions diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson index 4670c106d457a..fde4f3cbfe541 100644 --- a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson @@ -1079,6 +1079,40 @@ ] }, + { name: "CHERIOT_ENA", + desc: ''' + Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). + ''', + swaccess: "wo", + hwaccess: "hro", + fields: [ + { bits: "3:0", + name: "VAL", + resval: "0x0" + desc: ''' + ''' + }, + ] + }, + + { name: "CHERIOT_LOCK", + desc: ''' + Locks the CHERIoT/ePMP mode. + If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. + ''', + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "3:0", + name: "VAL", + desc: ''' + ''' + }, + ] + }, + { name: "FPGA_INFO", desc: ''' FPGA build timestamp info. diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/top_englishbreakfast_rv_core_ibex.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/top_englishbreakfast_rv_core_ibex.ipconfig.hjson index 7137a11fdd873..0269666a908ec 100644 --- a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/top_englishbreakfast_rv_core_ibex.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/top_englishbreakfast_rv_core_ibex.ipconfig.hjson @@ -10,6 +10,7 @@ topname: englishbreakfast uniquified_modules: {} racl_support: false + cheriot_available: false } dtgen: { diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/doc/registers.md b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/doc/registers.md index 16ad07f8053dc..3ccc585432819 100644 --- a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/doc/registers.md +++ b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/doc/registers.md @@ -5,36 +5,38 @@ A number of memory-mapped registers are available to control Ibex-related functi ## Summary -| Name | Offset | Length | Description | -|:-------------------------------------------------------------------------|:---------|---------:|:------------------------------------------------------------------------------| -| rv_core_ibex.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | -| rv_core_ibex.[`SW_RECOV_ERR`](#sw_recov_err) | 0x4 | 4 | Software recoverable error | -| rv_core_ibex.[`SW_FATAL_ERR`](#sw_fatal_err) | 0x8 | 4 | Software fatal error | -| rv_core_ibex.[`IBUS_REGWEN_0`](#ibus_regwen) | 0xc | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_REGWEN_1`](#ibus_regwen) | 0x10 | 4 | Ibus address control regwen. | -| rv_core_ibex.[`IBUS_ADDR_EN_0`](#ibus_addr_en) | 0x14 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_EN_1`](#ibus_addr_en) | 0x18 | 4 | Enable Ibus address matching | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching) | 0x1c | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_ADDR_MATCHING_1`](#ibus_addr_matching) | 0x20 | 4 | Matching region programming for ibus. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_0`](#ibus_remap_addr) | 0x24 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`IBUS_REMAP_ADDR_1`](#ibus_remap_addr) | 0x28 | 4 | The remap address after a match has been made. | -| rv_core_ibex.[`DBUS_REGWEN_0`](#dbus_regwen) | 0x2c | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_REGWEN_1`](#dbus_regwen) | 0x30 | 4 | Dbus address control regwen. | -| rv_core_ibex.[`DBUS_ADDR_EN_0`](#dbus_addr_en) | 0x34 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_EN_1`](#dbus_addr_en) | 0x38 | 4 | Enable dbus address matching | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_0`](#dbus_addr_matching) | 0x3c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_ADDR_MATCHING_1`](#dbus_addr_matching) | 0x40 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_0`](#dbus_remap_addr) | 0x44 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`DBUS_REMAP_ADDR_1`](#dbus_remap_addr) | 0x48 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | -| rv_core_ibex.[`NMI_ENABLE`](#nmi_enable) | 0x4c | 4 | Enable mask for NMI. | -| rv_core_ibex.[`NMI_STATE`](#nmi_state) | 0x50 | 4 | Current NMI state | -| rv_core_ibex.[`ERR_STATUS`](#err_status) | 0x54 | 4 | error status | -| rv_core_ibex.[`RND_DATA`](#rnd_data) | 0x58 | 4 | Random data from EDN | -| rv_core_ibex.[`RND_STATUS`](#rnd_status) | 0x5c | 4 | Status of random data in [`RND_DATA`](#rnd_data) | -| rv_core_ibex.[`FPGA_INFO`](#fpga_info) | 0x60 | 4 | FPGA build timestamp info. | -| rv_core_ibex.[`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) | 0x64 | 4 | Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) | -| rv_core_ibex.[`MCOUNTEREN_WRITABLE`](#mcounteren_writable) | 0x68 | 4 | Controls whether Ibex mcounteren CSR is writable by software. | -| rv_core_ibex.[`DV_SIM_WINDOW`](#dv_sim_window) | 0x80 | 32 | Exposed tlul window for DV only purposes. | +| Name | Offset | Length | Description | +|:-------------------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| +| rv_core_ibex.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| rv_core_ibex.[`SW_RECOV_ERR`](#sw_recov_err) | 0x4 | 4 | Software recoverable error | +| rv_core_ibex.[`SW_FATAL_ERR`](#sw_fatal_err) | 0x8 | 4 | Software fatal error | +| rv_core_ibex.[`IBUS_REGWEN_0`](#ibus_regwen) | 0xc | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_REGWEN_1`](#ibus_regwen) | 0x10 | 4 | Ibus address control regwen. | +| rv_core_ibex.[`IBUS_ADDR_EN_0`](#ibus_addr_en) | 0x14 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_EN_1`](#ibus_addr_en) | 0x18 | 4 | Enable Ibus address matching | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching) | 0x1c | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_ADDR_MATCHING_1`](#ibus_addr_matching) | 0x20 | 4 | Matching region programming for ibus. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_0`](#ibus_remap_addr) | 0x24 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`IBUS_REMAP_ADDR_1`](#ibus_remap_addr) | 0x28 | 4 | The remap address after a match has been made. | +| rv_core_ibex.[`DBUS_REGWEN_0`](#dbus_regwen) | 0x2c | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_REGWEN_1`](#dbus_regwen) | 0x30 | 4 | Dbus address control regwen. | +| rv_core_ibex.[`DBUS_ADDR_EN_0`](#dbus_addr_en) | 0x34 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_EN_1`](#dbus_addr_en) | 0x38 | 4 | Enable dbus address matching | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_0`](#dbus_addr_matching) | 0x3c | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_ADDR_MATCHING_1`](#dbus_addr_matching) | 0x40 | 4 | See [`IBUS_ADDR_MATCHING_0`](#ibus_addr_matching_0) for detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_0`](#dbus_remap_addr) | 0x44 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`DBUS_REMAP_ADDR_1`](#dbus_remap_addr) | 0x48 | 4 | See [`IBUS_REMAP_ADDR_0`](#ibus_remap_addr_0) for a detailed description. | +| rv_core_ibex.[`NMI_ENABLE`](#nmi_enable) | 0x4c | 4 | Enable mask for NMI. | +| rv_core_ibex.[`NMI_STATE`](#nmi_state) | 0x50 | 4 | Current NMI state | +| rv_core_ibex.[`ERR_STATUS`](#err_status) | 0x54 | 4 | error status | +| rv_core_ibex.[`RND_DATA`](#rnd_data) | 0x58 | 4 | Random data from EDN | +| rv_core_ibex.[`RND_STATUS`](#rnd_status) | 0x5c | 4 | Status of random data in [`RND_DATA`](#rnd_data) | +| rv_core_ibex.[`CHERIOT_ENA`](#cheriot_ena) | 0x60 | 4 | Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). | +| rv_core_ibex.[`CHERIOT_LOCK`](#cheriot_lock) | 0x64 | 4 | Locks the CHERIoT/ePMP mode. | +| rv_core_ibex.[`FPGA_INFO`](#fpga_info) | 0x68 | 4 | FPGA build timestamp info. | +| rv_core_ibex.[`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) | 0x6c | 4 | Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) | +| rv_core_ibex.[`MCOUNTEREN_WRITABLE`](#mcounteren_writable) | 0x70 | 4 | Controls whether Ibex mcounteren CSR is writable by software. | +| rv_core_ibex.[`DV_SIM_WINDOW`](#dv_sim_window) | 0x80 | 32 | Exposed tlul window for DV only purposes. | ## ALERT_TEST Alert Test Register @@ -421,10 +423,45 @@ Status of random data in [`RND_DATA`](#rnd_data) | 1 | ro | 0x0 | RND_DATA_FIPS | When [`RND_STATUS.RND_DATA_VALID`](#rnd_status) is 1, this bit indicates whether [`RND_DATA`](#rnd_data) is fips quality. When [`RND_STATUS.RND_DATA_VALID`](#rnd_status) is 0, this bit has no meaning. | | 0 | ro | 0x0 | RND_DATA_VALID | When set, the data in [`RND_DATA`](#rnd_data) is valid. When clear an EDN request for new data for [`RND_DATA`](#rnd_data) is pending. | +## CHERIOT_ENA +Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False). +- Offset: `0x60` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["wo"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:4 | | | | Reserved | +| 3:0 | wo | 0x0 | VAL | | + +## CHERIOT_LOCK +Locks the CHERIoT/ePMP mode. +If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register. +- Offset: `0x64` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["wo"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:4 | | | | Reserved | +| 3:0 | wo | x | VAL | | + ## FPGA_INFO FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0. -- Offset: `0x60` +- Offset: `0x68` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -440,7 +477,7 @@ This register only contains valid data for fpga, for all other variants it is si ## MCOUNTEREN_WRITABLE_REGWEN Register write-enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) -- Offset: `0x64` +- Offset: `0x6c` - Reset default: `0x1` - Reset mask: `0x1` @@ -466,7 +503,7 @@ Write enable for [`MCOUNTEREN_WRITABLE.`](#mcounteren_writable) Once set to 0, i ## MCOUNTEREN_WRITABLE Controls whether Ibex mcounteren CSR is writable by software. -- Offset: `0x68` +- Offset: `0x70` - Reset default: `0x6` - Reset mask: `0xf` - Register enable: [`MCOUNTEREN_WRITABLE_REGWEN`](#mcounteren_writable_regwen) diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv index eddb743aeed2e..9dddd35946990 100644 --- a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv @@ -3,6 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 `include "prim_assert.sv" +`include "prim_fifo_assert.svh" /** * Ibex RISC-V core @@ -431,6 +432,7 @@ module rv_core_ibex ibex_pkg::crash_dump_t crash_dump; ibex_top #( + .BaseIsa ( ibex_pkg::BaseIsaRV32I ), .PMPEnable ( PMPEnable ), .PMPGranularity ( PMPGranularity ), .PMPNumRegions ( PMPNumRegions ), @@ -493,6 +495,8 @@ module rv_core_ibex .hart_id_i, .boot_addr_i, + .trvk_heap_base_addr_i('0), // SRAM base address + .instr_req_o (main_core_instr_req), .instr_gnt_i (main_core_instr_gnt_ibex), .instr_rvalid_i (main_core_instr_rvalid), @@ -509,10 +513,20 @@ module rv_core_ibex .data_addr_o (main_core_data_addr), .data_wdata_o (main_core_data_wdata), .data_wdata_intg_o (main_core_data_wdata_intg), + .data_tag_o (), .data_rdata_i (main_core_data_rdata), .data_rdata_intg_i (main_core_data_rdata_intg), + .data_tag_i ('0), .data_err_i (main_core_data_err), + .trvk_revbm_req_o (), + .trvk_revbm_gnt_i ('0), + .trvk_revbm_rvalid_i ('0), + .trvk_revbm_addr_o (), + .trvk_revbm_rdata_i ('0), + .trvk_revbm_rdata_intg_i('0), + .trvk_revbm_err_i ('0), + .irq_software_i ( irq_software ), .irq_timer_i ( irq_timer ), .irq_external_i ( irq_external ), @@ -1012,6 +1026,9 @@ module rv_core_ibex assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q; assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q; + logic unused_cheriot; + assign unused_cheriot = ^{reg2hw.cheriot_ena, reg2hw.cheriot_lock}; + logic unused_reg2hw; assign unused_reg2hw = |reg2hw.rnd_data.q; @@ -1102,7 +1119,8 @@ module rv_core_ibex assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable, reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data, reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err, - reg2hw_shadow.mcounteren_writable}; + reg2hw_shadow.mcounteren_writable, + reg2hw_shadow.cheriot_ena, reg2hw_shadow.cheriot_lock}; ///////////////////////////////////////////////////////////////// // Shadow Core Data Address Translation Unit and TL-UL Adapter // diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv index bd489909982fa..2003143cc666d 100644 --- a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv +++ b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv @@ -57,9 +57,9 @@ module rv_core_ibex_cfg_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [26:0] reg_we_check; + logic [28:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(27) + .OneHotWidth(29) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -253,6 +253,10 @@ module rv_core_ibex_cfg_reg_top ( logic rnd_status_re; logic rnd_status_rnd_data_valid_qs; logic rnd_status_rnd_data_fips_qs; + logic cheriot_ena_we; + logic [3:0] cheriot_ena_wd; + logic cheriot_lock_we; + logic [3:0] cheriot_lock_wd; logic fpga_info_re; logic [31:0] fpga_info_qs; logic mcounteren_writable_regwen_we; @@ -1302,6 +1306,54 @@ module rv_core_ibex_cfg_reg_top ( ); + // R[cheriot_ena]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessWO), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cheriot_ena ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cheriot_ena_we), + .wd (cheriot_ena_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cheriot_ena.q), + .ds (), + + // to register interface (read) + .qs () + ); + + + // R[cheriot_lock]: V(True) + logic cheriot_lock_qe; + logic [0:0] cheriot_lock_flds_we; + assign cheriot_lock_qe = &cheriot_lock_flds_we; + prim_subreg_ext #( + .DW (4) + ) u_cheriot_lock ( + .re (1'b0), + .we (cheriot_lock_we), + .wd (cheriot_lock_wd), + .d ('0), + .qre (), + .qe (cheriot_lock_flds_we[0]), + .q (reg2hw.cheriot_lock.q), + .ds (), + .qs () + ); + assign reg2hw.cheriot_lock.qe = cheriot_lock_qe; + + // R[fpga_info]: V(True) prim_subreg_ext #( .DW (32) @@ -1378,7 +1430,7 @@ module rv_core_ibex_cfg_reg_top ( - logic [26:0] addr_hit; + logic [28:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RV_CORE_IBEX_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == RV_CORE_IBEX_SW_RECOV_ERR_OFFSET); @@ -1404,9 +1456,11 @@ module rv_core_ibex_cfg_reg_top ( addr_hit[21] = (reg_addr == RV_CORE_IBEX_ERR_STATUS_OFFSET); addr_hit[22] = (reg_addr == RV_CORE_IBEX_RND_DATA_OFFSET); addr_hit[23] = (reg_addr == RV_CORE_IBEX_RND_STATUS_OFFSET); - addr_hit[24] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET); - addr_hit[25] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET); - addr_hit[26] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET); + addr_hit[24] = (reg_addr == RV_CORE_IBEX_CHERIOT_ENA_OFFSET); + addr_hit[25] = (reg_addr == RV_CORE_IBEX_CHERIOT_LOCK_OFFSET); + addr_hit[26] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET); + addr_hit[27] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET); + addr_hit[28] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1440,7 +1494,9 @@ module rv_core_ibex_cfg_reg_top ( (addr_hit[23] & (|(RV_CORE_IBEX_CFG_PERMIT[23] & ~reg_be))) | (addr_hit[24] & (|(RV_CORE_IBEX_CFG_PERMIT[24] & ~reg_be))) | (addr_hit[25] & (|(RV_CORE_IBEX_CFG_PERMIT[25] & ~reg_be))) | - (addr_hit[26] & (|(RV_CORE_IBEX_CFG_PERMIT[26] & ~reg_be))))); + (addr_hit[26] & (|(RV_CORE_IBEX_CFG_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(RV_CORE_IBEX_CFG_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(RV_CORE_IBEX_CFG_PERMIT[28] & ~reg_be))))); end // Generate write-enables @@ -1528,11 +1584,17 @@ module rv_core_ibex_cfg_reg_top ( assign err_status_recov_core_err_wd = reg_wdata[10]; assign rnd_data_re = addr_hit[22] & reg_re & !reg_error; assign rnd_status_re = addr_hit[23] & reg_re & !reg_error; - assign fpga_info_re = addr_hit[24] & reg_re & !reg_error; - assign mcounteren_writable_regwen_we = addr_hit[25] & reg_we & !reg_error; + assign cheriot_ena_we = addr_hit[24] & reg_we & !reg_error; + + assign cheriot_ena_wd = reg_wdata[3:0]; + assign cheriot_lock_we = addr_hit[25] & reg_we & !reg_error; + + assign cheriot_lock_wd = reg_wdata[3:0]; + assign fpga_info_re = addr_hit[26] & reg_re & !reg_error; + assign mcounteren_writable_regwen_we = addr_hit[27] & reg_we & !reg_error; assign mcounteren_writable_regwen_wd = reg_wdata[0]; - assign mcounteren_writable_we = addr_hit[26] & reg_we & !reg_error; + assign mcounteren_writable_we = addr_hit[28] & reg_we & !reg_error; assign mcounteren_writable_wd = reg_wdata[3:0]; @@ -1562,9 +1624,11 @@ module rv_core_ibex_cfg_reg_top ( reg_we_check[21] = err_status_we; reg_we_check[22] = 1'b0; reg_we_check[23] = 1'b0; - reg_we_check[24] = 1'b0; - reg_we_check[25] = mcounteren_writable_regwen_we; - reg_we_check[26] = mcounteren_writable_gated_we; + reg_we_check[24] = cheriot_ena_we; + reg_we_check[25] = cheriot_lock_we; + reg_we_check[26] = 1'b0; + reg_we_check[27] = mcounteren_writable_regwen_we; + reg_we_check[28] = mcounteren_writable_gated_we; end // Read data return @@ -1677,14 +1741,22 @@ module rv_core_ibex_cfg_reg_top ( end addr_hit[24]: begin - reg_rdata_next[31:0] = fpga_info_qs; + reg_rdata_next[3:0] = '0; end addr_hit[25]: begin - reg_rdata_next[0] = mcounteren_writable_regwen_qs; + reg_rdata_next[3:0] = '0; end addr_hit[26]: begin + reg_rdata_next[31:0] = fpga_info_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = mcounteren_writable_regwen_qs; + end + + addr_hit[28]: begin reg_rdata_next[3:0] = mcounteren_writable_qs; end diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv index 2fe6515143947..328d7f99090ea 100644 --- a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_reg_pkg.sv @@ -16,7 +16,7 @@ package rv_core_ibex_reg_pkg; parameter int CfgAw = 8; // Number of registers for every interface - parameter int NumRegsCfg = 27; + parameter int NumRegsCfg = 29; // Alert indices typedef enum int { @@ -110,6 +110,15 @@ package rv_core_ibex_reg_pkg; logic re; } rv_core_ibex_reg2hw_rnd_data_reg_t; + typedef struct packed { + logic [3:0] q; + } rv_core_ibex_reg2hw_cheriot_ena_reg_t; + + typedef struct packed { + logic [3:0] q; + logic qe; + } rv_core_ibex_reg2hw_cheriot_lock_reg_t; + typedef struct packed { logic [3:0] q; } rv_core_ibex_reg2hw_mcounteren_writable_reg_t; @@ -168,18 +177,20 @@ package rv_core_ibex_reg_pkg; // Register -> HW type for cfg interface typedef struct packed { - rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [328:321] - rv_core_ibex_reg2hw_sw_recov_err_reg_t sw_recov_err; // [320:317] - rv_core_ibex_reg2hw_sw_fatal_err_reg_t sw_fatal_err; // [316:313] - rv_core_ibex_reg2hw_ibus_addr_en_mreg_t [1:0] ibus_addr_en; // [312:309] - rv_core_ibex_reg2hw_ibus_addr_matching_mreg_t [1:0] ibus_addr_matching; // [308:243] - rv_core_ibex_reg2hw_ibus_remap_addr_mreg_t [1:0] ibus_remap_addr; // [242:177] - rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [1:0] dbus_addr_en; // [176:173] - rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [1:0] dbus_addr_matching; // [172:107] - rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [1:0] dbus_remap_addr; // [106:41] - rv_core_ibex_reg2hw_nmi_enable_reg_t nmi_enable; // [40:39] - rv_core_ibex_reg2hw_nmi_state_reg_t nmi_state; // [38:37] - rv_core_ibex_reg2hw_rnd_data_reg_t rnd_data; // [36:4] + rv_core_ibex_reg2hw_alert_test_reg_t alert_test; // [337:330] + rv_core_ibex_reg2hw_sw_recov_err_reg_t sw_recov_err; // [329:326] + rv_core_ibex_reg2hw_sw_fatal_err_reg_t sw_fatal_err; // [325:322] + rv_core_ibex_reg2hw_ibus_addr_en_mreg_t [1:0] ibus_addr_en; // [321:318] + rv_core_ibex_reg2hw_ibus_addr_matching_mreg_t [1:0] ibus_addr_matching; // [317:252] + rv_core_ibex_reg2hw_ibus_remap_addr_mreg_t [1:0] ibus_remap_addr; // [251:186] + rv_core_ibex_reg2hw_dbus_addr_en_mreg_t [1:0] dbus_addr_en; // [185:182] + rv_core_ibex_reg2hw_dbus_addr_matching_mreg_t [1:0] dbus_addr_matching; // [181:116] + rv_core_ibex_reg2hw_dbus_remap_addr_mreg_t [1:0] dbus_remap_addr; // [115:50] + rv_core_ibex_reg2hw_nmi_enable_reg_t nmi_enable; // [49:48] + rv_core_ibex_reg2hw_nmi_state_reg_t nmi_state; // [47:46] + rv_core_ibex_reg2hw_rnd_data_reg_t rnd_data; // [45:13] + rv_core_ibex_reg2hw_cheriot_ena_reg_t cheriot_ena; // [12:9] + rv_core_ibex_reg2hw_cheriot_lock_reg_t cheriot_lock; // [8:4] rv_core_ibex_reg2hw_mcounteren_writable_reg_t mcounteren_writable; // [3:0] } rv_core_ibex_cfg_reg2hw_t; @@ -218,9 +229,11 @@ package rv_core_ibex_reg_pkg; parameter logic [CfgAw-1:0] RV_CORE_IBEX_ERR_STATUS_OFFSET = 8'h 54; parameter logic [CfgAw-1:0] RV_CORE_IBEX_RND_DATA_OFFSET = 8'h 58; parameter logic [CfgAw-1:0] RV_CORE_IBEX_RND_STATUS_OFFSET = 8'h 5c; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_FPGA_INFO_OFFSET = 8'h 60; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET = 8'h 64; - parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET = 8'h 68; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_CHERIOT_ENA_OFFSET = 8'h 60; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_CHERIOT_LOCK_OFFSET = 8'h 64; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_FPGA_INFO_OFFSET = 8'h 68; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET = 8'h 6c; + parameter logic [CfgAw-1:0] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET = 8'h 70; // Reset values for hwext registers and their fields for cfg interface parameter logic [3:0] RV_CORE_IBEX_ALERT_TEST_RESVAL = 4'h 0; @@ -233,6 +246,7 @@ package rv_core_ibex_reg_pkg; parameter logic [1:0] RV_CORE_IBEX_RND_STATUS_RESVAL = 2'h 0; parameter logic [0:0] RV_CORE_IBEX_RND_STATUS_RND_DATA_VALID_RESVAL = 1'h 0; parameter logic [0:0] RV_CORE_IBEX_RND_STATUS_RND_DATA_FIPS_RESVAL = 1'h 0; + parameter logic [3:0] RV_CORE_IBEX_CHERIOT_LOCK_RESVAL = 4'h 0; parameter logic [31:0] RV_CORE_IBEX_FPGA_INFO_RESVAL = 32'h 0; parameter logic [31:0] RV_CORE_IBEX_FPGA_INFO_VAL_RESVAL = 32'h 0; @@ -267,13 +281,15 @@ package rv_core_ibex_reg_pkg; RV_CORE_IBEX_ERR_STATUS, RV_CORE_IBEX_RND_DATA, RV_CORE_IBEX_RND_STATUS, + RV_CORE_IBEX_CHERIOT_ENA, + RV_CORE_IBEX_CHERIOT_LOCK, RV_CORE_IBEX_FPGA_INFO, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN, RV_CORE_IBEX_MCOUNTEREN_WRITABLE } rv_core_ibex_cfg_id_e; // Register width information to check illegal writes for cfg interface - parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [27] = '{ + parameter logic [3:0] RV_CORE_IBEX_CFG_PERMIT [29] = '{ 4'b 0001, // index[ 0] RV_CORE_IBEX_ALERT_TEST 4'b 0001, // index[ 1] RV_CORE_IBEX_SW_RECOV_ERR 4'b 0001, // index[ 2] RV_CORE_IBEX_SW_FATAL_ERR @@ -298,9 +314,11 @@ package rv_core_ibex_reg_pkg; 4'b 0011, // index[21] RV_CORE_IBEX_ERR_STATUS 4'b 1111, // index[22] RV_CORE_IBEX_RND_DATA 4'b 0001, // index[23] RV_CORE_IBEX_RND_STATUS - 4'b 1111, // index[24] RV_CORE_IBEX_FPGA_INFO - 4'b 0001, // index[25] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN - 4'b 0001 // index[26] RV_CORE_IBEX_MCOUNTEREN_WRITABLE + 4'b 0001, // index[24] RV_CORE_IBEX_CHERIOT_ENA + 4'b 0001, // index[25] RV_CORE_IBEX_CHERIOT_LOCK + 4'b 1111, // index[26] RV_CORE_IBEX_FPGA_INFO + 4'b 0001, // index[27] RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN + 4'b 0001 // index[28] RV_CORE_IBEX_MCOUNTEREN_WRITABLE }; endpackage diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv index bc2f5be0c7355..e467303c80a50 100644 --- a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv +++ b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv @@ -44,6 +44,7 @@ module top_englishbreakfast #( parameter int SramCtrlMainNumRamInst = 1, parameter bit SramCtrlMainInstrExec = 1, parameter int SramCtrlMainNumPrinceRoundsHalf = 3, + parameter int SramCtrlMainNumAddrScrRounds = 2, parameter bit SramCtrlMainEccCorrection = 0, // parameters for rom_ctrl parameter RomCtrlBootRomInitFile = "", @@ -921,6 +922,7 @@ module top_englishbreakfast #( .NumRamInst(SramCtrlMainNumRamInst), .InstrExec(SramCtrlMainInstrExec), .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf), + .NumAddrScrRounds(SramCtrlMainNumAddrScrRounds), .Outstanding(SramCtrlMainOutstanding), .EccCorrection(SramCtrlMainEccCorrection) ) u_sram_ctrl_main ( diff --git a/hw/vendor/lowrisc_ibex.lock.hjson b/hw/vendor/lowrisc_ibex.lock.hjson index 49aa7dcf98bc2..26b7c2df22297 100644 --- a/hw/vendor/lowrisc_ibex.lock.hjson +++ b/hw/vendor/lowrisc_ibex.lock.hjson @@ -8,7 +8,7 @@ { upstream: { - url: https://github.com/lowRISC/ibex.git - rev: aae4809aea170fc605bdaa64a70a13efd2408829 + url: https://github.com/thommythomaso/ibex-tbenz-pub.git + rev: 8348e15c8e6458e858c3f98601366d6880e8455f } } diff --git a/hw/vendor/lowrisc_ibex.vendor.hjson b/hw/vendor/lowrisc_ibex.vendor.hjson index c9a2aeb65255a..15a9bca214828 100644 --- a/hw/vendor/lowrisc_ibex.vendor.hjson +++ b/hw/vendor/lowrisc_ibex.vendor.hjson @@ -7,8 +7,8 @@ patch_dir: "patches/lowrisc_ibex", upstream: { - url: "https://github.com/lowRISC/ibex.git", - rev: "master", + url: "https://github.com/thommythomaso/ibex-tbenz-pub.git", + rev: "tbenz/cheriot-ibex-int", }, mapping: [ diff --git a/hw/vendor/lowrisc_ibex/dv/formal/check/top.sv b/hw/vendor/lowrisc_ibex/dv/formal/check/top.sv index 8f41c17f9e3ed..9ee34f94a8424 100644 --- a/hw/vendor/lowrisc_ibex/dv/formal/check/top.sv +++ b/hw/vendor/lowrisc_ibex/dv/formal/check/top.sv @@ -142,7 +142,33 @@ localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0; default clocking @(posedge clk_i); endclocking +// The TRVK (CHERIoT revocation) filter is only instantiated when BaseIsa is +// BaseIsaRV32IorCHERIoT. The core has no CHERIoT support yet and the formal spec +// is the plain RISC-V Sail model, so select BaseIsaRV32I to bypass the filter +// (a combinational pass-through of the data interface). The filter's ports still +// exist on ibex_top, so provide nets for the `.*` connection below: drive the +// inputs to their inactive values and leave the outputs as sinks. +logic [31:0] trvk_heap_base_addr_i; +logic data_tag_o; +logic data_tag_i; +logic trvk_revbm_req_o; +logic trvk_revbm_gnt_i; +logic trvk_revbm_rvalid_i; +logic [31:0] trvk_revbm_addr_o; +logic [31:0] trvk_revbm_rdata_i; +logic [ 6:0] trvk_revbm_rdata_intg_i; +logic trvk_revbm_err_i; + +assign trvk_heap_base_addr_i = 32'b0; +assign data_tag_i = 1'b0; +assign trvk_revbm_gnt_i = 1'b0; +assign trvk_revbm_rvalid_i = 1'b0; +assign trvk_revbm_rdata_i = 32'b0; +assign trvk_revbm_rdata_intg_i = 7'b0; +assign trvk_revbm_err_i = 1'b0; + ibex_top #( + .BaseIsa(ibex_pkg::BaseIsaRV32I), .DmHaltAddr(DmHaltAddr), .DmExceptionAddr(DmExceptionAddr), .SecureIbex(SecureIbex), diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv index 48ab742dc6d61..465418fa09543 100644 --- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv +++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv @@ -180,6 +180,8 @@ module ibex_riscv_compliance ( // First instruction executed is at 0x0 + 0x80 .boot_addr_i (32'h00000000 ), + .trvk_heap_base_addr_i (32'h00000000 ), + .instr_req_o (host_req[CoreI] ), .instr_gnt_i (host_gnt[CoreI] ), .instr_rvalid_i (host_rvalid[CoreI] ), @@ -196,10 +198,20 @@ module ibex_riscv_compliance ( .data_addr_o (host_addr[CoreD] ), .data_wdata_o (host_wdata[CoreD] ), .data_wdata_intg_o ( ), + .data_tag_o ( ), .data_rdata_i (host_rdata[CoreD] ), .data_rdata_intg_i (ibex_data_rdata_intg ), + .data_tag_i (1'b0 ), .data_err_i (host_err[CoreD] ), + .trvk_revbm_req_o ( ), + .trvk_revbm_gnt_i (1'b0 ), + .trvk_revbm_rvalid_i (1'b0 ), + .trvk_revbm_addr_o ( ), + .trvk_revbm_rdata_i ('0 ), + .trvk_revbm_rdata_intg_i ('0 ), + .trvk_revbm_err_i (1'b0 ), + .irq_software_i (1'b0 ), .irq_timer_i (1'b0 ), .irq_external_i (1'b0 ), diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f index 877870069d90f..44de3662af9d0 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f @@ -50,10 +50,18 @@ ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_39_32_dec.sv ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_72_64_enc.sv ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_72_64_dec.sv +${LOWRISC_IP_DIR}/ip/prim/rtl/prim_fifo_sync_cnt.sv +${LOWRISC_IP_DIR}/ip/prim/rtl/prim_fifo_sync.sv + +// Vendored PULP common cells (used by the TRVK filter) +${PRJ_DIR}/vendor/pulp_common_cells/rtl/stream_fork.sv +${PRJ_DIR}/vendor/pulp_common_cells/rtl/stream_fork_dynamic.sv +${PRJ_DIR}/vendor/pulp_common_cells/rtl/stream_join_dynamic.sv // ibex CORE RTL files +incdir+${PRJ_DIR}/rtl ${PRJ_DIR}/rtl/ibex_pkg.sv +${PRJ_DIR}/rtl/ibex_cheriot_pkg.sv ${PRJ_DIR}/rtl/ibex_tracer_pkg.sv ${PRJ_DIR}/rtl/ibex_tracer.sv ${PRJ_DIR}/rtl/ibex_alu.sv @@ -81,6 +89,7 @@ ${PRJ_DIR}/rtl/ibex_register_file_latch.sv ${PRJ_DIR}/rtl/ibex_pmp.sv ${PRJ_DIR}/rtl/ibex_core.sv +${PRJ_DIR}/rtl/ibex_trvk.sv ${PRJ_DIR}/rtl/ibex_top.sv ${PRJ_DIR}/rtl/ibex_top_tracing.sv diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv index 270ddac024fec..69472e3d44a6b 100644 --- a/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv +++ b/hw/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv @@ -132,6 +132,7 @@ module core_ibex_tb_top; .hart_id_i (32'b0 ), .boot_addr_i (BootAddr ), + .trvk_heap_base_addr_i (32'b0 ), .instr_req_o (instr_mem_vif.request ), .instr_gnt_i (instr_mem_vif.grant ), @@ -149,10 +150,20 @@ module core_ibex_tb_top; .data_be_o (data_mem_vif.be ), .data_rdata_i (data_mem_vif.rdata ), .data_rdata_intg_i (data_mem_vif.rintg ), + .data_tag_i (1'b0 ), .data_wdata_o (data_mem_vif.wdata ), .data_wdata_intg_o (data_mem_vif.wintg ), + .data_tag_o ( ), .data_err_i (data_mem_vif.error ), + .trvk_revbm_req_o ( ), + .trvk_revbm_gnt_i (1'b0 ), + .trvk_revbm_rvalid_i (1'b0 ), + .trvk_revbm_addr_o ( ), + .trvk_revbm_rdata_i ('b0 ), + .trvk_revbm_rdata_intg_i ('b0 ), + .trvk_revbm_err_i ( ), + .irq_software_i (irq_vif.irq_software ), .irq_timer_i (irq_vif.irq_timer ), .irq_external_i (irq_vif.irq_external ), diff --git a/hw/vendor/lowrisc_ibex/ibex_core.core b/hw/vendor/lowrisc_ibex/ibex_core.core index ab0ee64e83008..84dd40d49b1dc 100644 --- a/hw/vendor/lowrisc_ibex/ibex_core.core +++ b/hw/vendor/lowrisc_ibex/ibex_core.core @@ -12,6 +12,7 @@ filesets: - lowrisc:prim:clock_gating - lowrisc:prim:lfsr - lowrisc:prim:mubi + - lowrisc:prim:fifo - lowrisc:ibex:ibex_pkg - lowrisc:ibex:ibex_icache - lowrisc:dv:dv_fcov_macros diff --git a/hw/vendor/lowrisc_ibex/ibex_pkg.core b/hw/vendor/lowrisc_ibex/ibex_pkg.core index 17f47e08c4cce..68a512543a865 100644 --- a/hw/vendor/lowrisc_ibex/ibex_pkg.core +++ b/hw/vendor/lowrisc_ibex/ibex_pkg.core @@ -9,6 +9,7 @@ filesets: files_rtl: files: - rtl/ibex_pkg.sv + - rtl/ibex_cheriot_pkg.sv file_type: systemVerilogSource targets: diff --git a/hw/vendor/lowrisc_ibex/ibex_top.core b/hw/vendor/lowrisc_ibex/ibex_top.core index 82edbe133db3f..0bb94c2e3a1e4 100644 --- a/hw/vendor/lowrisc_ibex/ibex_top.core +++ b/hw/vendor/lowrisc_ibex/ibex_top.core @@ -19,10 +19,12 @@ filesets: - lowrisc:prim:onehot_check - lowrisc:prim:onehot - lowrisc:prim:util + - pulp-platform:common_cells:common_cells files: - rtl/ibex_register_file_ff.sv # generic FF-based - rtl/ibex_register_file_fpga.sv # FPGA - rtl/ibex_register_file_latch.sv # ASIC + - rtl/ibex_trvk.sv - rtl/ibex_lockstep.sv - rtl/ibex_top.sv file_type: systemVerilogSource diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_cheriot_pkg.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_cheriot_pkg.sv new file mode 100644 index 0000000000000..d944edf434e79 --- /dev/null +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_cheriot_pkg.sv @@ -0,0 +1,56 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ibex_cheriot_pkg; + + parameter int unsigned TOP_W = 9; + parameter int unsigned BOT_W = 9; + parameter int unsigned EXP_W = 5; + parameter int unsigned OTYPE_W = 3; + parameter int unsigned CPERMS_W = 6; + + + // Obtain 32-bit representation of top + function automatic logic[32:0] get_bound33(logic [TOP_W-1:0] top, logic [1:0] cor, + logic [EXP_W-1:0] exponent, logic [31:0] addr); + logic [32:0] t1, t2, mask, cor_val; + + if (cor[1]) + // negative sign extension + cor_val = {33{cor[1]}}; + else + cor_val = {32'h0, (~cor[1]) & cor[0]}; + + cor_val = (cor_val << exponent) << TOP_W; + mask = (33'h1_ffff_ffff << exponent) << TOP_W; + + // apply correction and truncate + t1 = ({1'b0, addr} & mask) + cor_val; + // extend to 32 bit + t2 = {24'h0, top}; + t1 = t1 | (t2 << exponent); + + return t1; + endfunction + + + // Update the top/base correction for a cap + function automatic logic [2:0] update_temp_fields(logic [TOP_W-1:0] top, logic [BOT_W-1:0] base, + logic [BOT_W-1:0] addrmi); + logic top_hi, addr_hi; + logic [2:0] res3; + + top_hi = (top < base); + addr_hi = (addrmi < base); + + // top_cor + res3[2:1] = (top_hi == addr_hi)? 2'b00 : ((top_hi && (!addr_hi))? 2'b01 : 2'b11); + + // base_cor + res3[0] = (addr_hi) ? 1'b1 : 1'b0; + + return res3; + endfunction + +endpackage diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv index 45b406444c812..b33311cc2c927 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv @@ -32,6 +32,11 @@ package ibex_pkg; // Parameter Enums // ///////////////////// + typedef enum integer { + BaseIsaRV32I = 0, // only RV32I + BaseIsaRV32IorCHERIoT = 1 // dual base ISA: RV32I/CHERIoT runtime switchable + } base_isa_e; + typedef enum integer { RegFileFF = 0, RegFileFPGA = 1, diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv index 0f6419a89d3a2..75092b79b4850 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_top.sv @@ -13,6 +13,7 @@ * Top level module of the ibex RISC-V core */ module ibex_top import ibex_pkg::*; #( + parameter ibex_pkg::base_isa_e BaseIsa = ibex_pkg::BaseIsaRV32IorCHERIoT, parameter bit PMPEnable = 1'b0, parameter int unsigned PMPGranularity = 0, parameter int unsigned PMPNumRegions = 4, @@ -21,6 +22,8 @@ module ibex_top import ibex_pkg::*; #( parameter ibex_pkg::pmp_cfg_t PMPRstCfg[PMP_MAX_REGIONS] = ibex_pkg::PmpCfgRst, parameter logic [PMP_ADDR_MSB:0] PMPRstAddr[PMP_MAX_REGIONS] = ibex_pkg::PmpAddrRst, parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg = ibex_pkg::PmpMseccfgRst, + parameter int unsigned CheriotRevBitmapAddrWidth = 32'd9, + parameter int unsigned CheriotRevBitmapBaseAddr = 32'h0, parameter bit RV32E = 1'b0, parameter rv32m_e RV32M = RV32MFast, parameter rv32b_e RV32B = RV32BNone, @@ -73,6 +76,8 @@ module ibex_top import ibex_pkg::*; #( input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, + input logic [31:0] trvk_heap_base_addr_i, + // Instruction memory interface output logic instr_req_o, input logic instr_gnt_i, @@ -91,10 +96,21 @@ module ibex_top import ibex_pkg::*; #( output logic [31:0] data_addr_o, output logic [31:0] data_wdata_o, output logic [6:0] data_wdata_intg_o, + output logic data_tag_o, input logic [31:0] data_rdata_i, input logic [6:0] data_rdata_intg_i, + input logic data_tag_i, input logic data_err_i, + // TRVK revocation bitmap read interface + output logic trvk_revbm_req_o, + input logic trvk_revbm_gnt_i, + input logic trvk_revbm_rvalid_i, + output logic [31:0] trvk_revbm_addr_o, + input logic [31:0] trvk_revbm_rdata_i, + input logic [6:0] trvk_revbm_rdata_intg_i, + input logic trvk_revbm_err_i, + // Interrupt inputs input logic irq_software_i, input logic irq_timer_i, @@ -222,6 +238,23 @@ module ibex_top import ibex_pkg::*; #( logic [MemDataWidth-1:0] data_rdata_core; logic [MemDataWidth-1:0] instr_rdata_core; + // Core <-> TRVK connection + logic trvk_req; + logic trvk_gnt; + logic trvk_rvalid; + logic trvk_we; + logic [3:0] trvk_be; + logic [31:0] trvk_addr; + logic [31:0] trvk_wdata; + logic [6:0] trvk_wdata_intg; + logic trvk_wtag; + logic [31:0] trvk_rdata; + logic [6:0] trvk_rdata_intg; + logic trvk_rtag; + logic trvk_err; + logic trvk_revbm_data_intg_error; + logic trvk_revbm_device_error; + // Core <-> RAMs signals logic [IC_NUM_WAYS-1:0] ic_tag_req; logic ic_tag_write; @@ -305,16 +338,16 @@ module ibex_top import ibex_pkg::*; #( // ibex_core takes integrity and data bits together. Combine the separate integrity and data // inputs here. - assign data_rdata_core[31:0] = data_rdata_i; + assign data_rdata_core[31:0] = trvk_rdata; assign instr_rdata_core[31:0] = instr_rdata_i; if (MemECC) begin : gen_mem_rdata_ecc - assign data_rdata_core[38:32] = data_rdata_intg_i; + assign data_rdata_core[38:32] = trvk_rdata_intg; assign instr_rdata_core[38:32] = instr_rdata_intg_i; end else begin : gen_non_mem_rdata_ecc logic unused_intg; - assign unused_intg = ^{instr_rdata_intg_i, data_rdata_intg_i}; + assign unused_intg = ^{instr_rdata_intg_i, trvk_rdata_intg}; end ibex_core #( @@ -370,15 +403,15 @@ module ibex_top import ibex_pkg::*; #( .instr_rdata_i(instr_rdata_core), .instr_err_i, - .data_req_o, - .data_gnt_i, - .data_rvalid_i, - .data_we_o, - .data_be_o, - .data_addr_o, - .data_wdata_o(data_wdata_core), - .data_rdata_i(data_rdata_core), - .data_err_i, + .data_req_o (trvk_req), + .data_gnt_i (trvk_gnt), + .data_rvalid_i(trvk_rvalid), + .data_we_o (trvk_we), + .data_be_o (trvk_be), + .data_addr_o (trvk_addr), + .data_wdata_o (data_wdata_core), + .data_rdata_i (data_rdata_core), + .data_err_i (trvk_err), .dummy_instr_id_o (dummy_instr_id), .dummy_instr_wb_o (dummy_instr_wb), @@ -777,15 +810,15 @@ module ibex_top import ibex_pkg::*; #( assign icache_data_alert = '{default:'b0}; end - assign data_wdata_o = data_wdata_core[31:0]; + assign trvk_wdata = data_wdata_core[31:0]; if (MemECC) begin : gen_mem_wdata_ecc prim_buf #(.Width(7)) u_prim_buf_data_wdata_intg ( .in_i (data_wdata_core[38:32]), - .out_o(data_wdata_intg_o) + .out_o(trvk_wdata_intg) ); end else begin : gen_no_mem_ecc - assign data_wdata_intg_o = '0; + assign trvk_wdata_intg = '0; end // Redundant lockstep core implementation @@ -806,15 +839,15 @@ module ibex_top import ibex_pkg::*; #( instr_addr_o, instr_rdata_core, instr_err_i, - data_req_o, - data_gnt_i, - data_rvalid_i, - data_we_o, - data_be_o, - data_addr_o, - data_wdata_o, + trvk_req, + trvk_gnt, + trvk_rvalid, + trvk_we, + trvk_be, + trvk_addr, + trvk_wdata, data_rdata_core, - data_err_i, + trvk_err, rf_rdata_a, rf_rdata_b, ic_tag_req, @@ -901,15 +934,15 @@ module ibex_top import ibex_pkg::*; #( instr_addr_o, instr_rdata_core, instr_err_i, - data_req_o, - data_gnt_i, - data_rvalid_i, - data_we_o, - data_be_o, - data_addr_o, - data_wdata_o, + trvk_req, + trvk_gnt, + trvk_rvalid, + trvk_we, + trvk_be, + trvk_addr, + trvk_wdata, data_rdata_core, - data_err_i, + trvk_err, rf_rdata_a, rf_rdata_b, ic_tag_req, @@ -1148,14 +1181,109 @@ module ibex_top import ibex_pkg::*; #( assign unused_scan = scan_rst_ni; end + + ////////// + // TRVK // + ////////// + + if (BaseIsa == BaseIsaRV32IorCHERIoT) begin : gen_cheriot_trvk + ibex_trvk #( + .NumOutstanding(32'd2), + .RevBitmapAddrWidth(CheriotRevBitmapAddrWidth), + .RevBitmapBaseAddr(CheriotRevBitmapBaseAddr) + ) i_ibex_trvk ( + .clk_i (clk), + .rst_ni (rst_ni), + .heap_base_addr_i (trvk_heap_base_addr_i), + .upstream_req_i (trvk_req), + .upstream_gnt_o (trvk_gnt), + .upstream_rvalid_o (trvk_rvalid), + .upstream_we_i (trvk_we), + .upstream_be_i (trvk_be), + .upstream_addr_i (trvk_addr), + .upstream_wdata_i (trvk_wdata), + .upstream_wdata_intg_i (trvk_wdata_intg), + .upstream_rdata_o (trvk_rdata), + .upstream_rdata_intg_o (trvk_rdata_intg), + .upstream_err_o (trvk_err), + .upstream_tag_i (trvk_wtag), + .upstream_tag_o (trvk_rtag), + .downstream_req_o (data_req_o), + .downstream_gnt_i (data_gnt_i), + .downstream_rvalid_i (data_rvalid_i), + .downstream_we_o (data_we_o), + .downstream_be_o (data_be_o), + .downstream_addr_o (data_addr_o), + .downstream_wdata_o (data_wdata_o), + .downstream_wdata_intg_o(data_wdata_intg_o), + .downstream_rdata_i (data_rdata_i), + .downstream_rdata_intg_i(data_rdata_intg_i), + .downstream_err_i (data_err_i), + .downstream_tag_o (data_tag_o), + .downstream_tag_i (data_tag_i), + .revbm_req_o (trvk_revbm_req_o), + .revbm_gnt_i (trvk_revbm_gnt_i), + .revbm_rvalid_i (trvk_revbm_rvalid_i), + .revbm_addr_o (trvk_revbm_addr_o), + .revbm_rdata_i (trvk_revbm_rdata_i), + .revbm_rdata_intg_i (trvk_revbm_rdata_intg_i), + .revbm_err_i (trvk_revbm_err_i), + .revbm_data_intg_error_o(trvk_revbm_data_intg_error), + .revbm_device_error_o (trvk_revbm_device_error) + ); + + // Tag connection towards the core is tied-off for now. This will change as soon as the core + // is updated to feature CHERIoT support. + logic unused_trvk; + assign trvk_wtag = 1'b0; + assign unused_trvk = trvk_rtag; + + end else begin : gen_no_cheriot_trvk + + logic unused_trvk; + + assign trvk_revbm_req_o = '0; + assign trvk_revbm_addr_o = '0; + assign trvk_wtag = 1'b0; + assign data_tag_o = 1'b0; + assign trvk_revbm_data_intg_error = 1'b0; + assign trvk_revbm_device_error = 1'b0; + assign unused_trvk = ^{ + trvk_heap_base_addr_i, + trvk_revbm_gnt_i, + trvk_revbm_rvalid_i, + trvk_revbm_rdata_i, + trvk_revbm_rdata_intg_i, + trvk_revbm_err_i, + trvk_rtag, + data_tag_i + }; + + // Through-connect TRVK + assign data_req_o = trvk_req; + assign trvk_gnt = data_gnt_i; + assign trvk_rvalid = data_rvalid_i; + assign data_we_o = trvk_we; + assign data_be_o = trvk_be; + assign data_addr_o = trvk_addr; + assign data_wdata_o = trvk_wdata; + assign data_wdata_intg_o = trvk_wdata_intg; + assign trvk_rdata = data_rdata_i; + assign trvk_rdata_intg = data_rdata_intg_i; + assign trvk_err = data_err_i; + end + + // Enable or disable iCache multi bit encoding checking error generation. // If enabled and a MuBi encoding error is detected, raise a major alert. logic icache_alert_major_internal; assign icache_alert_major_internal = (|icache_tag_alert) | (|icache_data_alert); - assign alert_major_internal_o = core_alert_major_internal | + assign alert_major_internal_o = core_alert_major_internal | lockstep_alert_major_internal | - icache_alert_major_internal; + icache_alert_major_internal | + trvk_revbm_data_intg_error | + trvk_revbm_device_error; assign alert_major_bus_o = core_alert_major_bus | lockstep_alert_major_bus; assign alert_minor_o = core_alert_minor | lockstep_alert_minor; diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv index 3823dd219e756..a742078142aee 100644 --- a/hw/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv @@ -7,6 +7,7 @@ */ module ibex_top_tracing import ibex_pkg::*; #( + parameter base_isa_e BaseIsa = BaseIsaRV32IorCHERIoT, parameter bit PMPEnable = 1'b0, parameter int unsigned PMPGranularity = 0, parameter int unsigned PMPNumRegions = 4, @@ -49,6 +50,7 @@ module ibex_top_tracing import ibex_pkg::*; #( input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_icache_data_i, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [ibex_pkg::IC_NUM_WAYS-1:0] ram_cfg_rsp_icache_data_o, + input logic [31:0] trvk_heap_base_addr_i, input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, @@ -71,10 +73,21 @@ module ibex_top_tracing import ibex_pkg::*; #( output logic [31:0] data_addr_o, output logic [31:0] data_wdata_o, output logic [6:0] data_wdata_intg_o, + output logic data_tag_o, input logic [31:0] data_rdata_i, input logic [6:0] data_rdata_intg_i, + input logic data_tag_i, input logic data_err_i, + // TRVK revocation bitmap read interface + output logic trvk_revbm_req_o, + input logic trvk_revbm_gnt_i, + input logic trvk_revbm_rvalid_i, + output logic [31:0] trvk_revbm_addr_o, + input logic [31:0] trvk_revbm_rdata_i, + input logic [6:0] trvk_revbm_rdata_intg_i, + input logic trvk_revbm_err_i, + // Interrupt inputs input logic irq_software_i, input logic irq_timer_i, @@ -196,6 +209,7 @@ module ibex_top_tracing import ibex_pkg::*; #( assign unused_rvfi_ext_expanded_insn_last = rvfi_ext_expanded_insn_last; ibex_top #( + .BaseIsa ( BaseIsa ), .PMPEnable ( PMPEnable ), .PMPGranularity ( PMPGranularity ), .PMPNumRegions ( PMPNumRegions ), @@ -259,6 +273,17 @@ module ibex_top_tracing import ibex_pkg::*; #( .data_rdata_intg_i, .data_err_i, + .trvk_heap_base_addr_i, + .data_tag_o, + .data_tag_i, + .trvk_revbm_req_o, + .trvk_revbm_gnt_i, + .trvk_revbm_rvalid_i, + .trvk_revbm_addr_o, + .trvk_revbm_rdata_i, + .trvk_revbm_rdata_intg_i, + .trvk_revbm_err_i, + .irq_software_i, .irq_timer_i, .irq_external_i, diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_trvk.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_trvk.sv new file mode 100644 index 0000000000000..b02835718862c --- /dev/null +++ b/hw/vendor/lowrisc_ibex/rtl/ibex_trvk.sv @@ -0,0 +1,383 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ibex_trvk #( + // The number of outstanding transaction the IP supports + parameter int unsigned NumOutstanding = 32'd4, + // The width of the meta memory address space used to store the revocation bits + parameter int unsigned RevBitmapAddrWidth = 32'd9, + // The base address of the meta SRAM holding the revocation bitmap + parameter int unsigned RevBitmapBaseAddr = 32'h0000_0000 +)( + input clk_i, + input rst_ni, + + // The base address of the (heap) memory where to be revocable capabilities point to + input logic [31:0] heap_base_addr_i, + + // Upstream port + input logic upstream_req_i, + output logic upstream_gnt_o, + output logic upstream_rvalid_o, + input logic upstream_we_i, + input logic [3:0] upstream_be_i, + input logic [31:0] upstream_addr_i, + input logic [31:0] upstream_wdata_i, + input logic [6:0] upstream_wdata_intg_i, + output logic [31:0] upstream_rdata_o, + output logic [6:0] upstream_rdata_intg_o, + output logic upstream_err_o, + input logic upstream_tag_i, + output logic upstream_tag_o, + + // Downstream port + output logic downstream_req_o, + input logic downstream_gnt_i, + input logic downstream_rvalid_i, + output logic downstream_we_o, + output logic [3:0] downstream_be_o, + output logic [31:0] downstream_addr_o, + output logic [31:0] downstream_wdata_o, + output logic [6:0] downstream_wdata_intg_o, + input logic [31:0] downstream_rdata_i, + input logic [6:0] downstream_rdata_intg_i, + input logic downstream_err_i, + output logic downstream_tag_o, + input logic downstream_tag_i, + + // Revocation bitmap memory port + output logic revbm_req_o, + input logic revbm_gnt_i, + input logic revbm_rvalid_i, + output logic [31:0] revbm_addr_o, + input logic [31:0] revbm_rdata_i, + input logic [6:0] revbm_rdata_intg_i, + input logic revbm_err_i, + + // Error signals + output logic revbm_data_intg_error_o, + output logic revbm_device_error_o +); + + + /////////// + // Types // + /////////// + + // Expanded exponent (5 bit). Exponent 'd15 stored in memory is mapped to 'd24. + typedef logic [ibex_cheriot_pkg::EXP_W-1:0] cheriot_exp_t; + typedef logic [ibex_cheriot_pkg::BOT_W-1:0] cheriot_bot_t; + typedef logic [ibex_cheriot_pkg::OTYPE_W-1:0] cheriot_otype_t; + typedef logic [ibex_cheriot_pkg::CPERMS_W-1:0] cheriot_cperms_t; + + // Revocation bitmap word address type + typedef logic [RevBitmapAddrWidth-1:0] revbm_addr_t; + + // Local capability metadata type to facilitate parsing of the fields. + typedef struct packed { + cheriot_exp_t exponent; + cheriot_bot_t base; + cheriot_otype_t otype; + cheriot_cperms_t cperms; + } cap_meta_t; + + // Local downstream response type + typedef struct packed { + logic [31:0] data; + logic [6:0] intg; + logic tag; + logic err; + } ds_rsp_t; + + + ///////////// + // Signals // + ///////////// + + // Signals connecting the request to the alignment store. + logic align_fork_valid; + logic align_fork_ready; + + // Alignment store output + logic align_out; + logic align_out_valid; + logic align_out_ready; + + // Pointer store signals + logic [31:0] ptr_store_q; + logic ptr_store_valid_q; + logic ptr_store_enable; + + // Downstream response store output + ds_rsp_t downstream_rsp_in; + ds_rsp_t downstream_rsp_out; + logic downstream_rsp_out_valid; + logic downstream_rsp_out_ready; + + // Base (address) calculation + cap_meta_t cap_meta; + logic unused_cap_meta; + logic is_sealing_cap; + logic [32:0] cap_base_33; + logic unused_cap_base_33; + logic [31:0] cap_base; + cheriot_bot_t addr_mid; + logic [ 2:0] cap_correction; + logic unused_cap_correction; + + // Revocation bitmap addressing + logic [31:0] revbm_cap_addr; + logic [31:0] revbm_bit_addr; + logic [ 4:0] revbm_bit_select; + revbm_addr_t revbm_addr; + logic revbm_out_of_range; + + // Revocation bitmap signals + logic revbm_req_required; + logic revbm_rsp_ready; + logic revbm_outstanding_q; + logic revbm_revoked; + + // Bitmap response ECC signals + logic [1:0] revbm_rsp_data_intg_error; + + + ////////////////////////////// + // Host to Device Intercept // + ////////////////////////////// + + // Both the device and the alignment store need to handshake for + // the stream to advance. + stream_fork #( + .N_OUP(32'd2) + ) u_stream_fork_h2d ( + .clk_i, + .rst_ni, + .valid_i(upstream_req_i), + .ready_o(upstream_gnt_o), + .valid_o({align_fork_valid, downstream_req_o}), + .ready_i({align_fork_ready, downstream_gnt_i}) + ); + + // The host and on lookup the revocation bitmap must handshake to advance the stream + // We use `revbm_req_required` as a section signal here. If there is a bitmap lookup required, + // this signal gets asserted beyond the request handshake completion until the response arrives. + stream_join_dynamic #( + .N_INP(32'd2) + ) u_stream_join_dynamic_d2h ( + .inp_valid_i({revbm_rvalid_i, downstream_rsp_out_valid}), + .inp_ready_o({revbm_rsp_ready, downstream_rsp_out_ready}), + .sel_i ({revbm_req_required, 1'b1 }), + .oup_valid_o(upstream_rvalid_o), + .oup_ready_i(1'b1) + ); + + // Forward OBI payload between host and device + assign downstream_we_o = upstream_we_i; + assign downstream_be_o = upstream_be_i; + assign downstream_addr_o = upstream_addr_i; + assign downstream_wdata_o = upstream_wdata_i; + assign downstream_wdata_intg_o = upstream_wdata_intg_i; + assign upstream_rdata_o = downstream_rsp_out.data; + assign upstream_rdata_intg_o = downstream_rsp_out.intg; + assign upstream_err_o = downstream_rsp_out.err; + + // Forward host to device CHERIoT tag w/o changes + assign downstream_tag_o = upstream_tag_i; + + // Tag handling; always return tag except if we do a revocation bitmap lookup + assign upstream_tag_o = revbm_rvalid_i ? !revbm_revoked : downstream_rsp_out.tag; + + // 64-bit alignment store + prim_fifo_sync #( + .Width(32'd1), + .Pass(1'b0), + .Depth(NumOutstanding), + .NeverClears(1'b1), + .Secure(1'b0) + ) u_prim_fifo_sync_align ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(align_fork_valid), + .wready_o(align_fork_ready), + .wdata_i (upstream_addr_i[2]), + .rvalid_o(align_out_valid), + .rready_i(align_out_ready), + .rdata_o (align_out), + .full_o (), + .depth_o (), + .err_o () + ); + + // Element is consumed, if host handshakes response + assign align_out_ready = upstream_rvalid_o; + + + /////////////////// + // Pointer Store // + /////////////////// + + // Pointer buffer is filled iff tag valid & 64-bit aligned + assign ptr_store_enable = downstream_rsp_out.tag && !align_out && align_out_valid && + align_out_ready; + + // Pointer store + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pointer_store + if(!rst_ni) begin + ptr_store_q <= '0; + end else begin + if (ptr_store_enable) begin + ptr_store_q <= downstream_rsp_out.data; + end + end + end + + // Pointer valid store + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pointer_vaild_store + if(!rst_ni) begin + ptr_store_valid_q <= 1'b0; + end else begin + if (align_out_ready) begin + ptr_store_valid_q <= ptr_store_enable; + end + end + end + + + ////////////////////////////////// + // Downstream Response Latching // + ////////////////////////////////// + + // downstream response store + prim_fifo_sync #( + .Width($bits(ds_rsp_t)), + .Pass(1'b1), + .Depth(NumOutstanding), + .NeverClears(1'b1), + .Secure(1'b0) + ) u_prim_fifo_ds_rsp_store ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .wvalid_i(downstream_rvalid_i), + .wready_o(), // Not connected as OBI is not configured to use rready + .wdata_i (downstream_rsp_in), + .rvalid_o(downstream_rsp_out_valid), + .rready_i(downstream_rsp_out_ready), + .rdata_o (downstream_rsp_out), + .full_o (), + .depth_o (), + .err_o () + ); + + assign downstream_rsp_in = '{ + data: downstream_rdata_i, + intg: downstream_rdata_intg_i, + tag: downstream_tag_i, + err: downstream_err_i + }; + + + //////////////////////////////// + // Bitmap Address Calculation // + //////////////////////////////// + + // Exponent is expanded (page 70, CHERIoT Architecture specification, Version 1.0) + assign cap_meta = '{ + base: downstream_rsp_out.data[8:0], + exponent: downstream_rsp_out.data[21:18] != 4'hf ? {1'b0, downstream_rsp_out.data[21:18]} : + 5'd24, + otype: downstream_rsp_out.data[24:22], + cperms: downstream_rsp_out.data[30:25] + }; + + // Not all fields are used + assign unused_cap_meta = ^{cap_meta.otype, cap_meta.cperms[5]}; + + // Check if cap is sealing cap + assign is_sealing_cap = (cap_meta.cperms[4:3] == 2'b00) && (|cap_meta.cperms[2:0]); + + // Extract the middle field from the pointer, bounds depend on exponent, width fixed + assign addr_mid = ptr_store_q[cap_meta.exponent +: ibex_cheriot_pkg::BOT_W]; + + // Fetch the correction values, we are only interested in the base correction value (1 bit) + // top-related inputs are set to zero, top-related outputs ignored + assign cap_correction = ibex_cheriot_pkg::update_temp_fields('0, cap_meta.base, addr_mid); + + // Calculate the base address of the capability as a 33-bit value + assign cap_base_33 = ibex_cheriot_pkg::get_bound33(cap_meta.base, {2{cap_correction[0]}}, + cap_meta.exponent, ptr_store_q); + + // We don't need the correction bits corresponding to the top address + assign unused_cap_correction = ^cap_correction[2:1]; + + // The MSB is unused in our case + assign {unused_cap_base_33, cap_base} = cap_base_33; + + // Address in the revocation bitmap + assign revbm_cap_addr = cap_base - heap_base_addr_i; + + // Bit address in the revocation bitmap (every bit corresponds to one 64-bit capability) + assign revbm_bit_addr = revbm_cap_addr >> 32'd3; + + // Word address of the revocation bitmap + assign revbm_addr = revbm_bit_addr[RevBitmapAddrWidth+5-1:5]; + + // Bit select + assign revbm_bit_select = revbm_bit_addr[4:0]; + + // Capability base is outside of the bitmap range + assign revbm_out_of_range = |(revbm_bit_addr[31:RevBitmapAddrWidth+5]); + + + ////////////////////// + // Bitmap Interface // + ////////////////////// + + // We have loaded valid capability pointer, now we see valid metadata, not a sealing cap, + // and are pointing into the revocation bitmap + assign revbm_req_required = !is_sealing_cap && // Not sealing cap + ptr_store_valid_q && // The base pointer stored is valid + downstream_rsp_out.tag && // We are looking at a capability + downstream_rsp_out_valid && // The stored response is valid + align_out && // We are on the second word of the cap + align_out_valid && // The alignment store is valid + !revbm_out_of_range; // We hit the heap range + + // Assemble read-only request + assign revbm_req_o = revbm_req_required && !revbm_outstanding_q; + assign revbm_addr_o = RevBitmapBaseAddr + {{32 - RevBitmapAddrWidth{1'b0}}, revbm_addr}; + + // Is the current capability marked as revoked? + assign revbm_revoked = revbm_rdata_i[revbm_bit_select] || revbm_err_i; + + // Did we receive a device error? + assign revbm_device_error_o = revbm_rvalid_i && revbm_err_i; + + // Check the bitmap response data integrity + prim_secded_inv_39_32_dec u_prim_secded_inv_39_32_dec_bm_rsp_data ( + .data_i ({revbm_rdata_intg_i, revbm_rdata_i}), + .data_o (), + .syndrome_o(), + .err_o (revbm_rsp_data_intg_error) + ); + + // Mask response integrity error if response is not being handshaked + assign revbm_data_intg_error_o = revbm_rvalid_i && (|revbm_rsp_data_intg_error); + + // One outstanding request + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_rev_req_store + if(!rst_ni) begin + revbm_outstanding_q <= 1'b0; + end else begin + if (revbm_rvalid_i && revbm_rsp_ready) begin + revbm_outstanding_q <= 1'b0; + end else if (revbm_req_o && revbm_gnt_i) begin + revbm_outstanding_q <= 1'b1; + end + end + end + +endmodule diff --git a/hw/vendor/lowrisc_ibex/syn/ibex_top_lr_synth_conf.tcl b/hw/vendor/lowrisc_ibex/syn/ibex_top_lr_synth_conf.tcl index f3f8622d6c856..8c3898147294c 100644 --- a/hw/vendor/lowrisc_ibex/syn/ibex_top_lr_synth_conf.tcl +++ b/hw/vendor/lowrisc_ibex/syn/ibex_top_lr_synth_conf.tcl @@ -7,13 +7,13 @@ # # {instr_req_o 70.0} # -# as an output means the instr_req_o output must be stable by 60% of total clock -# cycle +# as an output means the instr_req_o output must be stable by 70% of total clock +# cycle, # # {instr_gnt_i 30.0} # # as an input means the instr_gnt_i input will be stable by 30% of the total -# clock cycle +# clock cycle. # These IO constraints are an educated guess, they effectively assume there's a # bit of external logic on the inputs and outputs but not much before they reach @@ -46,11 +46,11 @@ set lr_synth_inputs [list {test_en_i 0.0 } \ {debug_req_i 10.0} \ {fetch_enable_i 0.0 }] -# clock and reset IO names (at top-level) +# Clock and reset IO names (at top-level). set lr_synth_clk_input clk_i set lr_synth_rst_input rst_ni -# clock period in ps, this gives a 250 MHz clock. using the nangate45 library +# Clock period in ps, this gives a 250 MHz clock. using the nangate45 library # Ibex can happily meet this on all paths with the lr_synth_abc_clk_uprate # setting below. With a lower uprate timing may not be met. set lr_synth_clk_period 4000.0 diff --git a/hw/vendor/patches/pulp_common_cells/stream_fork_dynamic_sv/0001-replace-assertions.patch b/hw/vendor/patches/pulp_common_cells/stream_fork_dynamic_sv/0001-replace-assertions.patch new file mode 100644 index 0000000000000..6d6b7533d5ca8 --- /dev/null +++ b/hw/vendor/patches/pulp_common_cells/stream_fork_dynamic_sv/0001-replace-assertions.patch @@ -0,0 +1,23 @@ +diff --git a/stream_fork_dynamic.sv b/stream_fork_dynamic.sv +index 8da5313d..1aa546b4 100644 +--- a/stream_fork_dynamic.sv ++++ b/stream_fork_dynamic.sv +@@ -11,7 +11,7 @@ + // Authors: + // - Andreas Kurth + +-`include "common_cells/assertions.svh" ++`include "prim_assert.sv" + + /// Dynamic stream fork: Connects the input stream (ready-valid) handshake to a combination of output + /// stream handshake. The combination is determined dynamically through another stream, which +@@ -87,7 +87,6 @@ module stream_fork_dynamic #( + .ready_i ( int_oup_ready ) + ); + +-`ifndef COMMON_CELLS_ASSERTS_OFF +- `ASSERT_INIT(n_oup_0, N_OUP >= 1, "N_OUP must be at least 1!") +-`endif ++ `ASSERT_INIT(NumOutputLargerZero_A, N_OUP >= 1) ++ + endmodule diff --git a/hw/vendor/patches/pulp_common_cells/stream_fork_sv/0001-replace-assertions.patch b/hw/vendor/patches/pulp_common_cells/stream_fork_sv/0001-replace-assertions.patch new file mode 100644 index 0000000000000..408c39eca7992 --- /dev/null +++ b/hw/vendor/patches/pulp_common_cells/stream_fork_sv/0001-replace-assertions.patch @@ -0,0 +1,23 @@ +diff --git a/stream_fork.sv b/stream_fork.sv +index ebe65f9b..7ae27c1a 100644 +--- a/stream_fork.sv ++++ b/stream_fork.sv +@@ -16,7 +16,7 @@ + // This module has no data ports because stream data does not need to be forked: the data of the + // input stream can just be applied at all output streams. + +-`include "common_cells/assertions.svh" ++`include "prim_assert.sv" + + module stream_fork #( + parameter int unsigned N_OUP = 0 // Synopsys DC requires a default value for parameters. +@@ -124,8 +124,6 @@ module stream_fork #( + assign all_ones = '1; // Synthesis fix for Vivado, which does not correctly compute the width + // of the '1 literal when assigned to a port of parametrized width. + +-`ifndef COMMON_CELLS_ASSERTS_OFF +- `ASSERT_INIT(n_oup_0, N_OUP >= 1, "Number of outputs must be at least 1!") +-`endif ++ `ASSERT_INIT(NumOutputLargerZero_A, N_OUP >= 1) + + endmodule diff --git a/hw/vendor/patches/pulp_common_cells/stream_fork_sv/0002-rename-wait-state.patch b/hw/vendor/patches/pulp_common_cells/stream_fork_sv/0002-rename-wait-state.patch new file mode 100644 index 0000000000000..b0e07fa66c688 --- /dev/null +++ b/hw/vendor/patches/pulp_common_cells/stream_fork_sv/0002-rename-wait-state.patch @@ -0,0 +1,46 @@ +diff --git a/stream_fork.sv b/stream_fork.sv +index 7ae27c1a06..e27b6e4549 100644 +--- a/stream_fork.sv ++++ b/stream_fork.sv +@@ -29,7 +29,7 @@ module stream_fork #( + input logic [N_OUP-1:0] ready_i + ); + +- typedef enum logic {READY, WAIT} state_t; ++ typedef enum logic {READY, WAITING} state_t; + + logic [N_OUP-1:0] oup_ready, + all_ones; +@@ -50,13 +50,13 @@ module stream_fork #( + end else begin + ready_o = 1'b0; + // Otherwise, wait for inputs that did not handshake yet. +- inp_state_d = WAIT; ++ inp_state_d = WAITING; + end + end else begin + ready_o = 1'b0; + end + end +- WAIT: begin ++ WAITING: begin + if (valid_i && oup_ready == all_ones) begin + ready_o = 1'b1; + inp_state_d = READY; +@@ -94,14 +94,14 @@ module stream_fork #( + valid_o[i] = 1'b1; + if (ready_i[i]) begin // Output handshake + if (!ready_o) begin // No input handshake yet +- oup_state_d = WAIT; ++ oup_state_d = WAITING; + end + end else begin // No output handshake + oup_ready[i] = 1'b0; + end + end + end +- WAIT: begin ++ WAITING: begin + if (valid_i && ready_o) begin // Input handshake + oup_state_d = READY; + end diff --git a/hw/vendor/patches/pulp_common_cells/stream_join_dynamic_sv/0001-replace-assertions.patch b/hw/vendor/patches/pulp_common_cells/stream_join_dynamic_sv/0001-replace-assertions.patch new file mode 100644 index 0000000000000..76cbb735cafd9 --- /dev/null +++ b/hw/vendor/patches/pulp_common_cells/stream_join_dynamic_sv/0001-replace-assertions.patch @@ -0,0 +1,23 @@ +diff --git a/stream_join_dynamic.sv b/stream_join_dynamic.sv +index 267990b9..0dec8875 100644 +--- a/stream_join_dynamic.sv ++++ b/stream_join_dynamic.sv +@@ -11,7 +11,7 @@ + // Authors: + // - Luca Colagrande + +-`include "common_cells/assertions.svh" ++`include "prim_assert.sv" + + // Stream join dynamic: Joins a parametrizable number of input streams (i.e. valid-ready + // handshaking with dependency rules as in AXI4) to a single output stream. The subset of streams +@@ -39,7 +39,6 @@ module stream_join_dynamic #( + assign inp_ready_o[i] = oup_valid_o & oup_ready_i & sel_i[i]; + end + +-`ifndef COMMON_CELLS_ASSERTS_OFF +- `ASSERT_INIT(n_inp_0, N_INP >= 1, "N_INP must be at least 1!") +-`endif ++ `ASSERT_INIT(NumInputLargerZero_A, N_INP >= 1) ++ + endmodule diff --git a/hw/vendor/pulp_common_cells.core b/hw/vendor/pulp_common_cells.core new file mode 100644 index 0000000000000..c877e01cb74b9 --- /dev/null +++ b/hw/vendor/pulp_common_cells.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "pulp-platform:common_cells:common_cells:0.1" +description: "PULP Common Cells" + +filesets: + files_src: + depend: + - lowrisc:prim:assert + files: + - pulp_common_cells/rtl/stream_fork.sv + - pulp_common_cells/rtl/stream_fork_dynamic.sv + - pulp_common_cells/rtl/stream_join_dynamic.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_src diff --git a/hw/vendor/pulp_common_cells.lock.hjson b/hw/vendor/pulp_common_cells.lock.hjson new file mode 100644 index 0000000000000..df71f11911037 --- /dev/null +++ b/hw/vendor/pulp_common_cells.lock.hjson @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is generated by the util/vendor script. Please do not modify it +// manually. + +{ + upstream: + { + url: https://github.com/pulp-platform/common_cells.git + rev: 63e1b679a70eca3a1d60d686bc1fa170ec08e1ab + } +} diff --git a/hw/vendor/pulp_common_cells.vendor.hjson b/hw/vendor/pulp_common_cells.vendor.hjson new file mode 100644 index 0000000000000..62b16ea1d6d0f --- /dev/null +++ b/hw/vendor/pulp_common_cells.vendor.hjson @@ -0,0 +1,28 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pulp_common_cells", + target_dir: "pulp_common_cells", + patch_dir: "patches/pulp_common_cells", + + upstream: { + url: "https://github.com/pulp-platform/common_cells.git" + rev: "master" + }, + + mapping: [ + { + from: "src/stream_fork.sv", + to: "rtl/stream_fork.sv", + patch_dir: "stream_fork_sv"}, + { + from: "src/stream_fork_dynamic.sv", + to: "rtl/stream_fork_dynamic.sv", + patch_dir: "stream_fork_dynamic_sv"}, + { + from: "src/stream_join_dynamic.sv", + to: "rtl/stream_join_dynamic.sv", + patch_dir: "stream_join_dynamic_sv"}, + ] +} diff --git a/hw/vendor/pulp_common_cells/rtl/stream_fork.sv b/hw/vendor/pulp_common_cells/rtl/stream_fork.sv new file mode 100644 index 0000000000000..e27b6e45498b8 --- /dev/null +++ b/hw/vendor/pulp_common_cells/rtl/stream_fork.sv @@ -0,0 +1,129 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream fork: Connects the input stream (ready-valid) handshake to *all* of `N_OUP` output stream +// handshakes. For each input stream handshake, every output stream handshakes exactly once. The +// input stream only handshakes when all output streams have handshaked, but the output streams do +// not have to handshake simultaneously. +// +// This module has no data ports because stream data does not need to be forked: the data of the +// input stream can just be applied at all output streams. + +`include "prim_assert.sv" + +module stream_fork #( + parameter int unsigned N_OUP = 0 // Synopsys DC requires a default value for parameters. +) ( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + output logic ready_o, + output logic [N_OUP-1:0] valid_o, + input logic [N_OUP-1:0] ready_i +); + + typedef enum logic {READY, WAITING} state_t; + + logic [N_OUP-1:0] oup_ready, + all_ones; + + state_t inp_state_d, inp_state_q; + + // Input control FSM + always_comb begin + // ready_o = 1'b0; + inp_state_d = inp_state_q; + + unique case (inp_state_q) + READY: begin + if (valid_i) begin + if (valid_o == all_ones && ready_i == all_ones) begin + // If handshake on all outputs, handshake on input. + ready_o = 1'b1; + end else begin + ready_o = 1'b0; + // Otherwise, wait for inputs that did not handshake yet. + inp_state_d = WAITING; + end + end else begin + ready_o = 1'b0; + end + end + WAITING: begin + if (valid_i && oup_ready == all_ones) begin + ready_o = 1'b1; + inp_state_d = READY; + end else begin + ready_o = 1'b0; + end + end + default: begin + inp_state_d = READY; + ready_o = 1'b0; + end + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + inp_state_q <= READY; + end else begin + inp_state_q <= inp_state_d; + end + end + + // Output control FSM + for (genvar i = 0; i < N_OUP; i++) begin: gen_oup_state + state_t oup_state_d, oup_state_q; + + always_comb begin + oup_ready[i] = 1'b1; + valid_o[i] = 1'b0; + oup_state_d = oup_state_q; + + unique case (oup_state_q) + READY: begin + if (valid_i) begin + valid_o[i] = 1'b1; + if (ready_i[i]) begin // Output handshake + if (!ready_o) begin // No input handshake yet + oup_state_d = WAITING; + end + end else begin // No output handshake + oup_ready[i] = 1'b0; + end + end + end + WAITING: begin + if (valid_i && ready_o) begin // Input handshake + oup_state_d = READY; + end + end + default: begin + oup_state_d = READY; + end + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + oup_state_q <= READY; + end else begin + oup_state_q <= oup_state_d; + end + end + end + + assign all_ones = '1; // Synthesis fix for Vivado, which does not correctly compute the width + // of the '1 literal when assigned to a port of parametrized width. + + `ASSERT_INIT(NumOutputLargerZero_A, N_OUP >= 1) + +endmodule diff --git a/hw/vendor/pulp_common_cells/rtl/stream_fork_dynamic.sv b/hw/vendor/pulp_common_cells/rtl/stream_fork_dynamic.sv new file mode 100644 index 0000000000000..1aa546b44a536 --- /dev/null +++ b/hw/vendor/pulp_common_cells/rtl/stream_fork_dynamic.sv @@ -0,0 +1,92 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Authors: +// - Andreas Kurth + +`include "prim_assert.sv" + +/// Dynamic stream fork: Connects the input stream (ready-valid) handshake to a combination of output +/// stream handshake. The combination is determined dynamically through another stream, which +/// provides a bitmask for the fork. For each input stream handshake, every output stream handshakes +/// exactly once. The input stream only handshakes when all output streams have handshaked, but the +/// output streams do not have to handshake simultaneously. +/// +/// This module has no data ports because stream data does not need to be forked: the data of the +/// input stream can just be applied at all output streams. +module stream_fork_dynamic #( + /// Number of output streams + parameter int unsigned N_OUP = 32'd0 // Synopsys DC requires a default value for parameters. +) ( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Input stream valid handshake, + input logic valid_i, + /// Input stream ready handshake + output logic ready_o, + /// Selection mask for the output handshake + input logic [N_OUP-1:0] sel_i, + /// Selection mask valid + input logic sel_valid_i, + /// Selection mask ready + output logic sel_ready_o, + /// Output streams valid handshakes + output logic [N_OUP-1:0] valid_o, + /// Output streams ready handshakes + input logic [N_OUP-1:0] ready_i +); + + logic int_inp_valid, int_inp_ready; + logic [N_OUP-1:0] int_oup_valid, int_oup_ready; + + // Output handshaking + for (genvar i = 0; i < N_OUP; i++) begin : gen_oups + always_comb begin + valid_o[i] = 1'b0; + int_oup_ready[i] = 1'b0; + if (sel_valid_i) begin + if (sel_i[i]) begin + valid_o[i] = int_oup_valid[i]; + int_oup_ready[i] = ready_i[i]; + end else begin + int_oup_ready[i] = 1'b1; + end + end + end + end + + // Input handshaking + always_comb begin + int_inp_valid = 1'b0; + ready_o = 1'b0; + sel_ready_o = 1'b0; + if (sel_valid_i) begin + int_inp_valid = valid_i; + ready_o = int_inp_ready; + sel_ready_o = int_inp_ready; + end + end + + stream_fork #( + .N_OUP ( N_OUP ) + ) i_fork ( + .clk_i, + .rst_ni, + .valid_i ( int_inp_valid ), + .ready_o ( int_inp_ready ), + .valid_o ( int_oup_valid ), + .ready_i ( int_oup_ready ) + ); + + `ASSERT_INIT(NumOutputLargerZero_A, N_OUP >= 1) + +endmodule diff --git a/hw/vendor/pulp_common_cells/rtl/stream_join_dynamic.sv b/hw/vendor/pulp_common_cells/rtl/stream_join_dynamic.sv new file mode 100644 index 0000000000000..0dec8875e9a99 --- /dev/null +++ b/hw/vendor/pulp_common_cells/rtl/stream_join_dynamic.sv @@ -0,0 +1,44 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Authors: +// - Luca Colagrande + +`include "prim_assert.sv" + +// Stream join dynamic: Joins a parametrizable number of input streams (i.e. valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. The subset of streams +// to join can be configured dynamically via `sel_i`. The output handshake happens only after +// there has been a handshake. The data channel flows outside of this module. +module stream_join_dynamic #( + /// Number of input streams + parameter int unsigned N_INP = 32'd0 // Synopsys DC requires a default value for parameters. +) ( + /// Input streams valid handshakes + input logic [N_INP-1:0] inp_valid_i, + /// Input streams ready handshakes + output logic [N_INP-1:0] inp_ready_o, + /// Selection mask for the output handshake + input logic [N_INP-1:0] sel_i, + /// Output stream valid handshake + output logic oup_valid_o, + /// Output stream ready handshake + input logic oup_ready_i +); + + // Corner case when `sel_i` is all 0s should not generate valid + assign oup_valid_o = &(inp_valid_i | ~sel_i) && |sel_i; + for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready + assign inp_ready_o[i] = oup_valid_o & oup_ready_i & sel_i[i]; + end + + `ASSERT_INIT(NumInputLargerZero_A, N_INP >= 1) + +endmodule diff --git a/sw/device/lib/dif/dif_alert_handler_unittest.cc b/sw/device/lib/dif/dif_alert_handler_unittest.cc index 8ecf087c1ca60..629a1f41ec0f2 100644 --- a/sw/device/lib/dif/dif_alert_handler_unittest.cc +++ b/sw/device/lib/dif/dif_alert_handler_unittest.cc @@ -30,7 +30,7 @@ using ::testing::Return; // so if the number of alerts change, the digest will be changed // as well. This process is not yet automated, so the user // must be aware on how to update the value. -static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 63, +static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 64, "The number of alerts have changed."); constexpr int kAlerts = ALERT_HANDLER_PARAM_N_ALERTS; diff --git a/sw/device/tests/penetrationtests/json/pentest_lib_commands.h b/sw/device/tests/penetrationtests/json/pentest_lib_commands.h index 164322771feb2..b42f61ba03da1 100644 --- a/sw/device/tests/penetrationtests/json/pentest_lib_commands.h +++ b/sw/device/tests/penetrationtests/json/pentest_lib_commands.h @@ -14,7 +14,7 @@ extern "C" { #define MODULE_ID MAKE_MODULE_ID('j', 'p', 'c') -#define ALERT_HANDLER_PARAM_N_ALERTS 63 +#define ALERT_HANDLER_PARAM_N_ALERTS 64 #define ALERT_HANDLER_PARAM_N_CLASSES 4 #define SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS 11 #define ALERT_HANDLER_PARAM_N_PHASES 4 diff --git a/util/mdbook_dashboard.py b/util/mdbook_dashboard.py index 79a3df2e14110..8d282d53c03b3 100755 --- a/util/mdbook_dashboard.py +++ b/util/mdbook_dashboard.py @@ -23,6 +23,7 @@ 'comportable': [ REPO_TOP / "hw/ip/aes/data/aes.hjson", REPO_TOP / "hw/ip/aon_timer/data/aon_timer.hjson", + REPO_TOP / "hw/ip/cheriot/data/cheriot.hjson", REPO_TOP / "hw/ip/entropy_src/data/entropy_src.hjson", REPO_TOP / "hw/ip/csrng/data/csrng.hjson", REPO_TOP / "hw/ip/adc_ctrl/data/adc_ctrl.hjson", diff --git a/util/reggen/ip_block.py b/util/reggen/ip_block.py index e7c212324f1c7..afa4f3d36817f 100644 --- a/util/reggen/ip_block.py +++ b/util/reggen/ip_block.py @@ -70,7 +70,8 @@ 43: 'racl_ctrl', 44: 'otp_macro', 45: 'rram_ctrl', - 46: 'rram_macro' + 46: 'rram_macro', + 47: 'cheriot', } REQUIRED_ALIAS_FIELDS = {