From aa0e54678e38dd6c1907c31b1ccd1e1d0b519a27 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 25 Feb 2026 18:25:51 +0100 Subject: [PATCH 01/41] [earlgrey_top,rtl] add rram_ctrl+rram_macro This commit adds rram_ctrl + rram_macro and connects them to the bus system. The RRAM can already be used for read/write operations through the controller and host port. Software binaries are still mapped to the flash macro, and otp_ctrl is not yet connected to rram_ctrl. No functional change so far as RRAM is not yet used in any testcase (except for chip level csr_rw test). Signed-off-by: Michael Gautschi --- hw/ip/BUILD | 2 + hw/top_earlgrey/data/top_earlgrey.hjson | 75 ++++++++++++++++--- hw/top_earlgrey/data/xbar_main.hjson | 29 ++++++- hw/top_earlgrey/doc/memory_map.md | 3 + hw/top_earlgrey/dv/env/chip_env.core | 1 + hw/top_earlgrey/dv/env/chip_env_pkg.sv | 2 + hw/top_earlgrey/dv/env/chip_if.sv | 2 + .../chip_sw_all_escalation_resets_vseq.sv | 2 + .../seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv | 10 +-- hw/top_earlgrey/dv/tb/chip_hier_macros.svh | 3 + hw/top_earlgrey/dv/tb/tb.sv | 26 +++++++ .../templates/earlgrey_pd_main.sv.tpl | 8 ++ hw/top_earlgrey/top_earlgrey.core | 2 + .../lib/dif/dif_alert_handler_unittest.cc | 2 +- sw/device/lib/dif/dif_rv_plic_unittest.cc | 6 +- .../json/pentest_lib_commands.h | 2 +- util/topgen.py | 1 + 17 files changed, 155 insertions(+), 21 deletions(-) diff --git a/hw/ip/BUILD b/hw/ip/BUILD index ef325e2a42929..25b9066acb9f8 100644 --- a/hw/ip/BUILD +++ b/hw/ip/BUILD @@ -39,6 +39,8 @@ filegroup( "//hw/ip/prim_xilinx:rtl_files", "//hw/ip/prim_xilinx_ultrascale:rtl_files", "//hw/ip/rom_ctrl:rtl_files", + "//hw/ip/rram_ctrl:rtl_files", + "//hw/ip/rram_macro:rtl_files", "//hw/ip/rv_dm:rtl_files", "//hw/ip/rv_timer:rtl_files", "//hw/ip/soc_dbg_ctrl:rtl_files", diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 2277e38301864..a22a40b65ecd1 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -230,6 +230,8 @@ "sram_ctrl_ret", "flash_ctrl.core", "flash_ctrl.prim", + "rram_ctrl.core" + "rram_macro.prim" "rv_plic", "aes", "hmac", @@ -796,6 +798,46 @@ }, attr: "ipgen", }, + { name: "rram_ctrl", + type: "rram_ctrl", + clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, + base_addrs: { + core: {hart: "0x41010000"}, + host: {hart: "0x30000000"} + } + param_decl: { + WrFifoDepth: "4", + RdFifoDepth: "16", + }, + memory: { + host: { + label: "rram", + swaccess: "ro", + data_intg_passthru: "true", + exec: "True", + byte_write: "False", + size: "0x200000" + } + }, + }, + { name: "rram_macro", + type: "rram_macro", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + prim: {hart: "0x41018000"}, + }, + param_decl: { + TotalPages: "rram_ctrl_pkg::TotalPages", + DataWidth: "rram_ctrl_pkg::DataWidth", + WordsPerPage: "rram_ctrl_pkg::WordsPerPage", + TotalInfoPages: "rram_ctrl_pkg::TotalInfoPages", + MaxWrWords: "rram_ctrl_pkg::MaxWrWords", + }, + }, { name: "rv_dm", type: "rv_dm", clock_srcs: {clk_i: "main", clk_lc_i: "main"}, @@ -1117,7 +1159,8 @@ inter_module: { 'connect': { 'ast.obs_ctrl' : ['flash_ctrl.obs_ctrl', - 'otp_macro.obs_ctrl'], + 'otp_macro.obs_ctrl', + 'rram_macro.obs_ctrl'], 'alert_handler.crashdump' : ['rstmgr.alert_dump'], 'alert_handler.esc_rx' : ['rv_core_ibex.esc_rx', 'lc_ctrl.esc_scrap_state0_rx', @@ -1132,7 +1175,7 @@ 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'], 'flash_ctrl.keymgr' : ['keymgr.flash'], 'flash_ctrl.otp' : ['otp_ctrl.nvm_otp_key'], - 'lc_ctrl.lc_nvm_rma_seed' : ['flash_ctrl.rma_seed'], + 'lc_ctrl.lc_nvm_rma_seed' : ['flash_ctrl.rma_seed', 'rram_ctrl.rma_seed'], 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', 'sram_ctrl_sec.sram_otp_key', 'sram_ctrl_ret.sram_otp_key', @@ -1153,7 +1196,7 @@ // LC RMA req/ack interface: LC --> Flash -> LC // |-> OTBN -> LC - 'lc_ctrl.lc_nvm_rma_req' : ['flash_ctrl.rma_req', 'otbn.lc_rma_req'], + 'lc_ctrl.lc_nvm_rma_req' : ['flash_ctrl.rma_req', 'otbn.lc_rma_req', 'rram_ctrl.rma_req'], 'lc_ctrl.lc_nvm_rma_ack' : ['flash_ctrl.rma_ack', 'otbn.lc_rma_ack'], // usbdev connection to pinmux @@ -1219,7 +1262,8 @@ 'pwrmgr.lc_dft_en', 'rv_dm.lc_dft_en' ], - 'lc_ctrl.lc_nvm_debug_en' : ['flash_ctrl.lc_nvm_debug_en'], + 'lc_ctrl.lc_nvm_debug_en' : ['flash_ctrl.lc_nvm_debug_en', + 'rram_macro.lc_nvm_debug_en'], 'lc_ctrl.lc_hw_debug_clr' : ['pinmux.lc_hw_debug_clr', 'rv_dm.lc_hw_debug_clr'], 'lc_ctrl.lc_init_done' : ['rv_dm.lc_init_done'], @@ -1241,6 +1285,7 @@ 'sram_ctrl_ret.lc_escalate_en', 'aon_timer.lc_escalate_en', 'flash_ctrl.lc_escalate_en', + 'rram_ctrl.lc_escalate_en', 'pinmux.lc_escalate_en'], 'lc_ctrl.lc_check_byp_en' : ['otp_ctrl.lc_check_byp_en', @@ -1250,12 +1295,17 @@ // LC access control signal broadcast 'lc_ctrl.lc_creator_seed_sw_rw_en' : ['otp_ctrl.lc_creator_seed_sw_rw_en', - 'flash_ctrl.lc_creator_seed_sw_rw_en'], - 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['flash_ctrl.lc_owner_seed_sw_rw_en'], - 'lc_ctrl.lc_iso_part_sw_rd_en' : ['flash_ctrl.lc_iso_part_sw_rd_en'], - 'lc_ctrl.lc_iso_part_sw_wr_en' : ['flash_ctrl.lc_iso_part_sw_wr_en'], + 'flash_ctrl.lc_creator_seed_sw_rw_en', + 'rram_ctrl.lc_creator_seed_sw_rw_en'], + 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['flash_ctrl.lc_owner_seed_sw_rw_en', + 'rram_ctrl.lc_owner_seed_sw_rw_en'], + 'lc_ctrl.lc_iso_part_sw_rd_en' : ['flash_ctrl.lc_iso_part_sw_rd_en', + 'rram_ctrl.lc_iso_part_sw_rd_en'], + 'lc_ctrl.lc_iso_part_sw_wr_en' : ['flash_ctrl.lc_iso_part_sw_wr_en', + 'rram_ctrl.lc_iso_part_sw_wr_en'], 'lc_ctrl.lc_seed_hw_rd_en' : ['otp_ctrl.lc_seed_hw_rd_en', - 'flash_ctrl.lc_seed_hw_rd_en'], + 'flash_ctrl.lc_seed_hw_rd_en', + 'rram_ctrl.lc_seed_hw_rd_en'], 'lc_ctrl.lc_rma_state' : ['otp_ctrl.lc_rma_state'], // OTP OTP_MACRO connections @@ -1283,6 +1333,9 @@ // Reset manager software reset request to pwrmgr 'rstmgr.sw_rst_req' : ['pwrmgr.sw_rst_req'], + + // connection between rram_macro and rram_ctrl + 'rram_ctrl.rram_macro' : ['rram_macro.rram_macro'], }, // top is to connect to top net/struct. @@ -1309,6 +1362,9 @@ // Xbars + // Temporary RRAM helpers + 'rram_ctrl.otp_key', + // Pinmux JTAG signals for the tool-inserted DFT TAP 'pinmux.dft_jtag', @@ -1603,6 +1659,7 @@ { instance: "spi_device", port: 'tpm_csb', connection: 'muxed' , pad: '' , desc: ''}, { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "rram_macro", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "sensor_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, { instance: "otp_macro", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''}, // Sysrst ctrl has both muxed and dedicated IOs diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index 8324b68fff31d..8b3133b3ec65c 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson @@ -20,7 +20,7 @@ // For device interfaces, especially configuration registers, latency is // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline // true. - // For device accesses to memories (ram / rom / flash), performance is a concern, + // For device accesses to memories (ram / rom / flash / rram), performance is a concern, // so use pipeline false where permissible by timing. If not, find a combination // that works. nodes: [ @@ -125,6 +125,27 @@ req_fifo_pass: false, rsp_fifo_pass: false, }, + { name: "rram_ctrl.core", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rram_macro.prim", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rram_ctrl.host", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, { name: "hmac", type: "device", clock: "clk_main_i", @@ -231,11 +252,14 @@ }, ], connections: { - rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.mem", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", "flash_ctrl.mem"], + rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.mem", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", + "flash_ctrl.mem", "rram_ctrl.host" + ], rv_core_ibex.cored: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", "peri", "spi_host0", "spi_host1", "usbdev", "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", + "rram_ctrl.core", "rram_ctrl.host", "rram_macro.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", "sram_ctrl_sec.regs", "rv_core_ibex.cfg" @@ -244,6 +268,7 @@ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "sram_ctrl_sec.ram", "peri", "spi_host0", "spi_host1", "usbdev", "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", + "rram_ctrl.core", "rram_ctrl.host", "rram_macro.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", "sram_ctrl_sec.regs", "rv_core_ibex.cfg", diff --git a/hw/top_earlgrey/doc/memory_map.md b/hw/top_earlgrey/doc/memory_map.md index abac0f509f2ae..803d1c9769c6e 100644 --- a/hw/top_earlgrey/doc/memory_map.md +++ b/hw/top_earlgrey/doc/memory_map.md @@ -43,6 +43,8 @@ The main address space, shared between the CPU and DM | sram_ctrl_ret | regs | `0x40500000` | `0x40` | `0x10` | regs device on sram_ctrl_ret | | flash_ctrl | core | `0x41000000` | `0x200` | `0x80` | core device on flash_ctrl | | flash_ctrl | prim | `0x41008000` | `0x80` | `0x20` | prim device on flash_ctrl | +| rram_ctrl | core | `0x41010000` | `0x200` | `0x80` | core device on rram_ctrl | +| rram_macro | prim | `0x41018000` | `0x10` | `0x4` | prim device on rram_macro | | rv_dm | regs | `0x41200000` | `0x10` | `0x4` | regs device on rv_dm | | rv_dm | mem | `0x10000` | `0x1000` | `0x400` | mem device on rv_dm | | rv_plic | default | `0x48000000` | `0x8000000` | `0x2000000` | rv_plic | @@ -66,6 +68,7 @@ The main address space, shared between the CPU and DM |----------------|-------------|----------------|----------------|----------------| | sram_ctrl_ret | ram | `0x40600000` | `0x1000` | `0x400` | | flash_ctrl | mem | `0x20000000` | `0x100000` | `0x40000` | +| rram_ctrl | host | `0x30000000` | `0x200000` | `0x80000` | | sram_ctrl_main | ram | `0x10000000` | `0x20000` | `0x8000` | | sram_ctrl_sec | ram | `0x10020000` | `0x10000` | `0x4000` | | rom_ctrl | rom | `0x40000` | `0xC000` | `0x3000` | diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index 7c38393c33f61..7fd1c03c0745e 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -22,6 +22,7 @@ filesets: - lowrisc:dv:jtag_dmi_agent - lowrisc:dv:lc_ctrl_dv_utils - lowrisc:earlgrey_dv:flash_ctrl_bkdr_util + - lowrisc:dv:rram_ctrl_bkdr_util - lowrisc:earlgrey_dv:otp_ctrl_mem_bkdr_util - lowrisc:dv:spi_agent - lowrisc:dv:spi_host_sva diff --git a/hw/top_earlgrey/dv/env/chip_env_pkg.sv b/hw/top_earlgrey/dv/env/chip_env_pkg.sv index 2b7f0616b1b41..06569e14361d6 100644 --- a/hw/top_earlgrey/dv/env/chip_env_pkg.sv +++ b/hw/top_earlgrey/dv/env/chip_env_pkg.sv @@ -84,6 +84,8 @@ package chip_env_pkg; FlashBank1Data, FlashBank0Info, FlashBank1Info, + RramData, + RramInfo, ICacheWay0Tag, ICacheWay1Tag, ICacheWay0Data, diff --git a/hw/top_earlgrey/dv/env/chip_if.sv b/hw/top_earlgrey/dv/env/chip_if.sv index 8ef791c061af4..8cac1276af44e 100644 --- a/hw/top_earlgrey/dv/env/chip_if.sv +++ b/hw/top_earlgrey/dv/env/chip_if.sv @@ -54,6 +54,8 @@ interface chip_if; `define ENTROPY_SRC_HIER `PD_MAIN_HIER.u_entropy_src `define EDN_HIER(i) `PD_MAIN_HIER.u_edn``i `define FLASH_CTRL_HIER `PD_MAIN_HIER.u_flash_ctrl +`define RRAM_CTRL_HIER `PD_MAIN_HIER.u_rram_ctrl +`define RRAM_MACRO_HIER `PD_MAIN_HIER.u_rram_macro `define GPIO_HIER `PD_MAIN_HIER.u_gpio `define HMAC_HIER `PD_MAIN_HIER.u_hmac `define I2C_HIER(i) `PD_MAIN_HIER.u_i2c``i diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv index ab9404e895926..5efa4c999f403 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv @@ -23,9 +23,11 @@ class chip_sw_all_escalation_resets_vseq extends chip_sw_base_vseq; '{"*edn1*prim_reg_we_check*", TopEarlgreyAlertIdEdn1FatalAlert}, '{"*entropy_src*prim_reg_we_check*", TopEarlgreyAlertIdEntropySrcFatalAlert}, '{"*flash_ctrl*prim_reg_we_check*", TopEarlgreyAlertIdFlashCtrlFatalStdErr}, + '{"*rram_ctrl*prim_reg_we_check*", TopEarlgreyAlertIdRramCtrlFatalStdErr}, // test u_eflash.u_flash alert TopEarlgreyAlertIdFlashCtrlFatalErr is implemented in the // `chip_sw_flash_host_gnt_err_inj_vseq` sequence. '{"*flash_ctrl*.u_flash.*prim_reg_we_check*", TopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert}, + '{"*rram_macro*prim_reg_we_check*", TopEarlgreyAlertIdRramCtrlFatalMacroErr}, '{"*gpio*prim_reg_we_check*", TopEarlgreyAlertIdGpioFatalFault}, '{"*hmac*prim_reg_we_check*", TopEarlgreyAlertIdHmacFatalFault}, '{"*i2c0*prim_reg_we_check*", TopEarlgreyAlertIdI2c0FatalFault}, diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv index cd051d2fea646..dd64b86dbbfd9 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv @@ -13,7 +13,7 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq; localparam bit [2:0] EPMP_ACCESS_RWX = 3'b111; // Read-write-execute access. localparam bit [31:0] RAM_STACK_GUARD_ADDRESS = 32'h1001C000; - localparam bit [31:0] FLASH_TEXT_START_ADDRESS = 32'h20000400; + localparam bit [31:0] NVM_TEXT_START_ADDRESS = 32'h20000400; localparam bit [31:0] MMIO_START_ADDRESS = 32'h40000000; localparam bit [31:0] MMIO_END_ADDRESS = 32'h50000000; @@ -115,7 +115,7 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq; `DV_CHECK_EQ(cfg.chip_vif.pmp_cfg[14][2:0], EPMP_ACCESS_NONE) `DV_CHECK_EQ(cfg.chip_vif.pmp_cfg[15][2:0], EPMP_ACCESS_RW) - // ePMP regions for Flash + // ePMP regions for NVM `DV_CHECK_EQ(cfg.chip_vif.pmp_cfg[4].mode, ibex_pkg::PMP_MODE_OFF) `DV_CHECK_EQ(cfg.chip_vif.pmp_cfg[5].mode, ibex_pkg::PMP_MODE_NAPOT) `DV_CHECK(cfg.chip_vif.pmp_cfg[5].lock) @@ -167,13 +167,13 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq; end `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest, - "Timeout waiting to boot flash stage.", 200_000_000) + "Timeout waiting to boot nvm stage.", 200_000_000) - // ePMP is unlocked for flash once the signature verification succeeds. + // ePMP is unlocked for nvm once the signature verification succeeds. `DV_CHECK_EQ(cfg.chip_vif.pmp_cfg[4].mode, ibex_pkg::PMP_MODE_TOR) `DV_CHECK(cfg.chip_vif.pmp_cfg[4].lock) `DV_CHECK_EQ(cfg.chip_vif.pmp_cfg[4][2:0], EPMP_ACCESS_RX) - `DV_CHECK_EQ(cfg.chip_vif.pmp_addr[3], epmp_addr_tor(FLASH_TEXT_START_ADDRESS)) + `DV_CHECK_EQ(cfg.chip_vif.pmp_addr[3], epmp_addr_tor(NVM_TEXT_START_ADDRESS)) endtask endclass : chip_sw_rom_e2e_asm_init_vseq diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index e7957960f6e7d..78f04cf7bf20c 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -14,6 +14,7 @@ `define CPU_CORE_HIER `CPU_HIER.u_core `define CPU_TL_ADAPT_D_HIER `CPU_HIER.tl_adapter_host_d_ibex `define EFLASH_HIER `PD_MAIN_HIER.u_flash_ctrl.u_eflash.u_flash +`define RRAM_MACRO_HIER `PD_MAIN_HIER.u_rram_macro `define GPIO_HIER `PD_MAIN_HIER.u_gpio `define KEYMGR_HIER `PD_MAIN_HIER.u_keymgr `define LC_CTRL_HIER `PD_MAIN_HIER.u_lc_ctrl @@ -49,6 +50,8 @@ `define FLASH0_INFO_MEM_HIER `FLASH_BANK0_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB `define FLASH1_DATA_MEM_HIER `FLASH_BANK1_HIER.u_mem.`MEM_ARRAY_SUB `define FLASH1_INFO_MEM_HIER `FLASH_BANK1_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB +`define RRAM_DATA_MEM_HIER `RRAM_MACRO_HIER.u_data_array.`MEM_ARRAY_SUB +`define RRAM_INFO_MEM_HIER `RRAM_MACRO_HIER.u_info_array.`MEM_ARRAY_SUB `define ICACHE_WAY0_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[0].gen_scramble_rams `define ICACHE_WAY1_HIER `CPU_CORE_HIER.gen_rams.gen_rams_inner[1].gen_scramble_rams `define ICACHE0_TAG_MEM_HIER `ICACHE_WAY0_HIER.tag_bank.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv index b9e2e02d0a66d..db6b5303f7453 100644 --- a/hw/top_earlgrey/dv/tb/tb.sv +++ b/hw/top_earlgrey/dv/tb/tb.sv @@ -14,6 +14,7 @@ module tb; import chip_test_pkg::*; import xbar_test_pkg::*; import flash_ctrl_bkdr_util_pkg::*; + import rram_ctrl_bkdr_util_pkg::*; import mem_bkdr_util_pkg::*; import rom_ctrl_bkdr_util_pkg::*; import sram_ctrl_bkdr_util_pkg::*; @@ -461,12 +462,35 @@ module tb; initial begin // Unfortunately xcelium does not understand typed constructors so we must assign to local // variables first. + rram_ctrl_bkdr_util data, info; flash_ctrl_bkdr_util data0, info0, data1, info1; sram_ctrl_bkdr_util ram_main0, ram_ret0; rom_ctrl_bkdr_util rom; chip_mem_e mem; mem_bkdr_util m_mem_bkdr_util[chip_mem_e]; + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for RRAM data", UVM_MEDIUM) + data = new( + .name ("mem_bkdr_util[RramData]"), + .path (`DV_STRINGIFY(`RRAM_DATA_MEM_HIER)), + .depth ($size(`RRAM_DATA_MEM_HIER)), + .n_bits($bits(`RRAM_DATA_MEM_HIER)), + .err_detection_scheme(mem_bkdr_util_pkg::ErrDetectionNone), + .system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR)); + m_mem_bkdr_util[RramData] = data; + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RramData], `RRAM_DATA_MEM_HIER) + + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for RRAM info", UVM_MEDIUM) + info = new( + .name ("mem_bkdr_util[RramInfo]"), + .path (`DV_STRINGIFY(`RRAM_INFO_MEM_HIER)), + .depth ($size(`RRAM_INFO_MEM_HIER)), + .n_bits($bits(`RRAM_INFO_MEM_HIER)), + .err_detection_scheme(mem_bkdr_util_pkg::ErrDetectionNone), + .system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR)); + m_mem_bkdr_util[RramInfo] = info; + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RramInfo], `RRAM_INFO_MEM_HIER) + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for flash 0 data", UVM_MEDIUM) data0 = new( .name ("mem_bkdr_util[FlashBank0Data]"), @@ -672,6 +696,7 @@ module tb; forever @dut.chip_if.chip_padctrl_attributes_test_sva_disable begin if (dut.chip_if.chip_padctrl_attributes_test_sva_disable) begin $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl); + $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_rram_ctrl); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_gpio); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_i2c0); $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_i2c1); @@ -688,6 +713,7 @@ module tb; $assertoff(0, dut.top_earlgrey.earlgrey_pd_main.u_usbdev); end else begin $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_flash_ctrl); + $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_rram_ctrl); $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_gpio); $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_i2c0); $asserton(0, dut.top_earlgrey.earlgrey_pd_main.u_i2c1); diff --git a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl index 90b803f66cd91..765e32180ced9 100644 --- a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl +++ b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl @@ -71,6 +71,14 @@ module ${top["name"]}_pd_${domain.lower()} #( }; % endif + % if m.get("name") == "rram_ctrl": + // TODO: remove once RRAM is connected to OTP + assign rram_ctrl_otp_key_rsp.data_ack = rram_ctrl_otp_key_req.data_req; + assign rram_ctrl_otp_key_rsp.addr_ack = rram_ctrl_otp_key_req.addr_req; + assign rram_ctrl_otp_key_rsp.key = '0; + assign rram_ctrl_otp_key_rsp.rand_key = '0; + assign rram_ctrl_otp_key_rsp.seed_valid = 1'b0; + % endif % endfor // Ibex-specific assignments diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index fdbf8c6ca6091..f73281e23503c 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -29,6 +29,8 @@ filesets: - lowrisc:ip:otbn - lowrisc:prim:ram_1p_scr - lowrisc:prim:flash + - lowrisc:ip:rram_ctrl + - lowrisc:ip:rram_macro - lowrisc:ip:sram_ctrl - lowrisc:ip:keymgr - lowrisc:earlgrey_constants:top_pkg diff --git a/sw/device/lib/dif/dif_alert_handler_unittest.cc b/sw/device/lib/dif/dif_alert_handler_unittest.cc index 629a1f41ec0f2..6e7893623fd7f 100644 --- a/sw/device/lib/dif/dif_alert_handler_unittest.cc +++ b/sw/device/lib/dif/dif_alert_handler_unittest.cc @@ -30,7 +30,7 @@ using ::testing::Return; // so if the number of alerts change, the digest will be changed // as well. This process is not yet automated, so the user // must be aware on how to update the value. -static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 64, +static_assert(ALERT_HANDLER_PARAM_N_ALERTS == 69, "The number of alerts have changed."); constexpr int kAlerts = ALERT_HANDLER_PARAM_N_ALERTS; diff --git a/sw/device/lib/dif/dif_rv_plic_unittest.cc b/sw/device/lib/dif/dif_rv_plic_unittest.cc index a9fcd2c83651d..59924a8b8271b 100644 --- a/sw/device/lib/dif/dif_rv_plic_unittest.cc +++ b/sw/device/lib/dif/dif_rv_plic_unittest.cc @@ -21,7 +21,7 @@ using testing::Test; // If either of these static assertions fail, then the unit-tests for related // API should be revisited. -static_assert(RV_PLIC_PARAM_NUM_SRC == 184, +static_assert(RV_PLIC_PARAM_NUM_SRC == 190, "PLIC instantiation parameters have changed."); static_assert(RV_PLIC_PARAM_NUM_TARGET == 1, "PLIC instantiation parameters have changed."); @@ -100,7 +100,7 @@ class IrqTest : public PlicTest { {RV_PLIC_IE0_2_REG_OFFSET, RV_PLIC_IE0_2_E_95_BIT}, {RV_PLIC_IE0_3_REG_OFFSET, RV_PLIC_IE0_3_E_127_BIT}, {RV_PLIC_IE0_4_REG_OFFSET, RV_PLIC_IE0_4_E_159_BIT}, - {RV_PLIC_IE0_5_REG_OFFSET, RV_PLIC_IE0_5_E_183_BIT}, + {RV_PLIC_IE0_5_REG_OFFSET, RV_PLIC_IE0_5_E_189_BIT}, }}; static constexpr std::array kPendingRegisters{{ @@ -109,7 +109,7 @@ class IrqTest : public PlicTest { {RV_PLIC_IP_2_REG_OFFSET, RV_PLIC_IP_2_P_95_BIT}, {RV_PLIC_IP_3_REG_OFFSET, RV_PLIC_IP_3_P_127_BIT}, {RV_PLIC_IP_4_REG_OFFSET, RV_PLIC_IP_4_P_159_BIT}, - {RV_PLIC_IP_5_REG_OFFSET, RV_PLIC_IP_5_P_183_BIT}, + {RV_PLIC_IP_5_REG_OFFSET, RV_PLIC_IP_5_P_189_BIT}, }}; // Set enable/disable multireg expectations, one bit per call. diff --git a/sw/device/tests/penetrationtests/json/pentest_lib_commands.h b/sw/device/tests/penetrationtests/json/pentest_lib_commands.h index b42f61ba03da1..7bbae67c10338 100644 --- a/sw/device/tests/penetrationtests/json/pentest_lib_commands.h +++ b/sw/device/tests/penetrationtests/json/pentest_lib_commands.h @@ -14,7 +14,7 @@ extern "C" { #define MODULE_ID MAKE_MODULE_ID('j', 'p', 'c') -#define ALERT_HANDLER_PARAM_N_ALERTS 64 +#define ALERT_HANDLER_PARAM_N_ALERTS 69 #define ALERT_HANDLER_PARAM_N_CLASSES 4 #define SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS 11 #define ALERT_HANDLER_PARAM_N_PHASES 4 diff --git a/util/topgen.py b/util/topgen.py index 81870f60f9f28..42306f3634746 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -1883,6 +1883,7 @@ def render_template(template_path: str, rendered_path: Path, "otbn": ["lowrisc:ip:otbn_pkg"], "keymgr": ["lowrisc:ip:keymgr_pkg"], "csrng": ["lowrisc:ip:csrng_pkg"], + "rram_ctrl": ["lowrisc:ip:rram_ctrl_pkg"], } for m in completecfg["module"]: From d46f3f7f667ad68d3fc2142d43a5d7933af01124 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 18 Jun 2026 09:47:35 +0200 Subject: [PATCH 02/41] [rram_ctrl,top] Autogen changes for RRAM integration This commit is to be squashed into the previous one before merge. It contains all autogen changes that were generated with `make -C hw` Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/autogen/defs.bzl | 9 + .../data/autogen/top_earlgrey.gen.hjson | 1410 ++++- .../top_earlgrey.secrets.testing.gen.hjson | 206 +- .../data/otp/otp_ctrl_img_owner_sw_cfg.hjson | 13 +- .../dv/autogen/tb__alert_handler_connect.sv | 57 +- .../dv/autogen/tb__xbar_connect.sv | 6 + .../dv/autogen/xbar_env_pkg__params.sv | 18 +- hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg | 10 + .../dv/env/autogen/chip_env_pkg__params.sv | 7 +- .../data/autogen/xbar_main.gen.hjson | 112 + .../ip/xbar_main/data/autogen/xbar_main.hjson | 18 + .../xbar_main/dv/autogen/tb__xbar_connect.sv | 3 + .../ip/xbar_main/dv/autogen/xbar_cover.cfg | 10 + .../dv/autogen/xbar_env_pkg__params.sv | 18 +- .../ip/xbar_main/dv/autogen/xbar_main_bind.sv | 18 + .../ip/xbar_main/rtl/autogen/tl_main_pkg.sv | 41 +- .../ip/xbar_main/rtl/autogen/xbar_main.sv | 1291 ++--- .../alert_handler/data/alert_handler.hjson | 12 +- .../top_earlgrey_alert_handler.ipconfig.hjson | 12 +- .../alert_handler/doc/theory_of_operation.md | 2 +- .../rtl/alert_handler_reg_pkg.sv | 1202 ++--- .../rtl/alert_handler_reg_top.sv | 3588 ++++++++----- .../ip_autogen/pinmux/data/pinmux.hjson | 4 +- .../data/top_earlgrey_pinmux.ipconfig.hjson | 4 +- .../ip_autogen/pinmux/doc/pinout_asic.md | 4 + .../ip_autogen/pinmux/doc/pinout_cw340.md | 4 + .../ip_autogen/pinmux/doc/pinout_verilator.md | 4 + .../ip_autogen/pinmux/doc/registers.md | 2052 ++++---- .../ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv | 2070 ++++---- .../ip_autogen/pinmux/rtl/pinmux_reg_top.sv | 4523 +++++++++-------- .../ip_autogen/rv_plic/data/rv_plic.hjson | 2 +- .../data/top_earlgrey_rv_plic.ipconfig.hjson | 2 +- .../ip_autogen/rv_plic/rtl/rv_plic.sv | 10 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv | 62 +- .../ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv | 742 ++- .../rtl/autogen/earlgrey_pd_main.sv | 346 +- .../testing/top_earlgrey_rnd_cnst_pkg.sv | 280 +- .../top_earlgrey_testing_rnd_cnst_pkg.core | 1 + hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 7 + .../rtl/autogen/top_earlgrey_pkg.sv | 220 +- .../sw/autogen/chip/top_earlgrey.rs | 448 +- hw/top_earlgrey/sw/autogen/tests/BUILD | 2 + hw/top_earlgrey/sw/autogen/tests/alert_test.c | 20 + .../sw/autogen/tests/plic_all_irqs_test.c | 238 +- hw/top_earlgrey/sw/autogen/top_earlgrey.c | 15 +- hw/top_earlgrey/sw/autogen/top_earlgrey.h | 263 +- .../sw/autogen/top_earlgrey_memory.h | 44 + .../sw/autogen/top_earlgrey_memory.ld | 1 + sw/host/opentitanlib/src/otp/alert_handler.rs | 12 +- .../src/otp/alert_handler_regs.rs | 634 ++- sw/host/ot_hal/src/top/autogen/earlgrey.rs | 54 +- 51 files changed, 12261 insertions(+), 7870 deletions(-) diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index e5de27f456816..77a0f3e3c487e 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -29,6 +29,8 @@ load("//hw/ip/otp_macro:defs.bzl", "OTP_MACRO") load("//hw/top_earlgrey/ip_autogen/pinmux:defs.bzl", "PINMUX") load("//hw/top_earlgrey/ip_autogen/pwrmgr:defs.bzl", "PWRMGR") load("//hw/ip/rom_ctrl:defs.bzl", "ROM_CTRL") +load("//hw/ip/rram_ctrl:defs.bzl", "RRAM_CTRL") +load("//hw/ip/rram_macro:defs.bzl", "RRAM_MACRO") load("//hw/top_earlgrey/ip_autogen/rstmgr:defs.bzl", "RSTMGR") load("//hw/top_earlgrey/ip_autogen/rv_core_ibex:defs.bzl", "RV_CORE_IBEX") load("//hw/ip/rv_dm:defs.bzl", "RV_DM") @@ -65,6 +67,8 @@ EARLGREY_IPS = [ PINMUX, PWRMGR, ROM_CTRL, + RRAM_CTRL, + RRAM_MACRO, RSTMGR, RV_CORE_IBEX, RV_DM, @@ -118,6 +122,11 @@ EARLGREY_ALERTS = [ "flash_ctrl_fatal_err", "flash_ctrl_fatal_prim_flash_alert", "flash_ctrl_recov_prim_flash_alert", + "rram_ctrl_recov_err", + "rram_ctrl_fatal_std_err", + "rram_ctrl_fatal_err", + "rram_ctrl_fatal_macro_err", + "rram_ctrl_recov_macro_err", "rv_dm_fatal_fault", "rv_plic_fatal_fault", "aes_recov_ctrl_update_err", diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 0bb292edc3596..b642c9a054bf9 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -593,6 +593,8 @@ sram_ctrl_ret flash_ctrl.core flash_ctrl.prim + rram_ctrl.core + rram_macro.prim rv_plic aes hmac @@ -6418,6 +6420,451 @@ generate_dif: true domain: Main } + { + name: rram_ctrl + type: rram_ctrl + clock_srcs: + { + clk_i: main + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: Main + } + rst_otp_ni: + { + name: lc_io_div4 + domain: Main + } + } + base_addrs: + { + core: + { + hart: 0x41010000 + } + host: + { + hart: 0x30000000 + } + } + param_decl: + { + WrFifoDepth: "4" + RdFifoDepth: "16" + } + memory: + { + host: + { + label: rram + swaccess: ro + data_intg_passthru: "true" + exec: True + byte_write: False + size: 0x200000 + } + } + clock_connections: + { + clk_i: clkmgr_clocks_i.clk_main_infra + clk_otp_i: clkmgr_clocks_i.clk_io_div4_infra + } + param_list: + [ + { + name: SecScrambleEn + desc: Compile-time option to enable RRAM scrambling + type: bit + default: "1" + local: "false" + expose: "true" + name_top: SecRramCtrlScrambleEn + } + { + name: WrFifoDepth + desc: Depth of write fifo + type: int + default: "4" + local: "false" + expose: "true" + name_top: RramCtrlWrFifoDepth + } + { + name: RdFifoDepth + desc: Depth of read fifo + type: int + default: "16" + local: "false" + expose: "true" + name_top: RramCtrlRdFifoDepth + } + ] + inter_signal_list: + [ + { + name: rram_macro + struct: rram_macro + package: rram_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: rram_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_ctrl_rram_macro + index: -1 + } + { + name: otp_key + struct: nvm_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: rram_ctrl + default: "" + top_signame: rram_ctrl_otp_key + index: -1 + } + { + name: otp_macro + desc: Data interface for the OTP macro. + struct: otp_ctrl_macro + package: otp_ctrl_macro_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: rram_ctrl + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_iso_part_sw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_iso_part_sw_rd_en + index: -1 + } + { + name: lc_iso_part_sw_wr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_iso_part_sw_wr_en + index: -1 + } + { + name: lc_seed_hw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_nvm_rma_req + index: -1 + } + { + name: rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rram_ctrl + index: -1 + } + { + name: rma_seed + struct: lc_nvm_rma_seed + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_nvm_rma_seed + index: -1 + } + { + name: pwrmgr + struct: pwr_nvm + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: rram_ctrl + index: -1 + } + { + name: keymgr + struct: keymgr_rram + package: rram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rram_ctrl + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_ctrl_core_tl + index: -1 + } + { + name: host_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_ctrl_host_tl + index: -1 + } + ] + generate_dif: true + domain: Main + } + { + name: rram_macro + type: rram_macro + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: Main + } + } + base_addrs: + { + prim: + { + hart: 0x41018000 + } + } + param_decl: + { + TotalPages: rram_ctrl_pkg::TotalPages + DataWidth: rram_ctrl_pkg::DataWidth + WordsPerPage: rram_ctrl_pkg::WordsPerPage + TotalInfoPages: rram_ctrl_pkg::TotalInfoPages + MaxWrWords: rram_ctrl_pkg::MaxWrWords + } + clock_connections: + { + clk_i: clkmgr_clocks_i.clk_main_infra + } + memory: {} + param_list: + [ + { + name: TotalPages + desc: Total number of data pages + type: int + default: rram_ctrl_pkg::TotalPages + local: "true" + expose: "true" + name_top: RramMacroTotalPages + } + { + name: DataWidth + desc: RRAM word data width + type: int + default: rram_ctrl_pkg::DataWidth + local: "true" + expose: "true" + name_top: RramMacroDataWidth + } + { + name: WordsPerPage + desc: Number of words per page + type: int + default: rram_ctrl_pkg::WordsPerPage + local: "true" + expose: "true" + name_top: RramMacroWordsPerPage + } + { + name: TotalInfoPages + desc: Total number of info pages + type: int + default: rram_ctrl_pkg::TotalInfoPages + local: "true" + expose: "true" + name_top: RramMacroTotalInfoPages + } + { + name: MaxWrWords + desc: Maximum number of words per write + type: int + default: rram_ctrl_pkg::MaxWrWords + local: "true" + expose: "true" + name_top: RramMacroMaxWrWords + } + ] + inter_signal_list: + [ + { + name: rram_macro + struct: rram_macro + package: rram_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_macro + default: "" + domain: Main + top_signame: rram_ctrl_rram_macro + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_macro + default: "" + domain: Main + top_signame: lc_ctrl_lc_nvm_debug_en + index: -1 + } + { + name: obs_ctrl + desc: AST observability control signals. + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_macro + default: "" + domain: Main + top_signame: ast_obs_ctrl + index: -1 + } + { + name: rram_obs + desc: AST observability bus. + struct: logic + type: uni + act: req + width: 8 + inst_name: rram_macro + index: -1 + } + { + name: prim_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_macro + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_macro_prim_tl + index: -1 + } + ] + generate_dif: true + domain: Main + } { name: rv_dm type: rv_dm @@ -10158,6 +10605,7 @@ [ flash_ctrl.obs_ctrl otp_macro.obs_ctrl + rram_macro.obs_ctrl ] alert_handler.crashdump: [ @@ -10201,6 +10649,7 @@ lc_ctrl.lc_nvm_rma_seed: [ flash_ctrl.rma_seed + rram_ctrl.rma_seed ] otp_ctrl.sram_otp_key: [ @@ -10254,6 +10703,7 @@ [ flash_ctrl.rma_req otbn.lc_rma_req + rram_ctrl.rma_req ] lc_ctrl.lc_nvm_rma_ack: [ @@ -10384,6 +10834,7 @@ lc_ctrl.lc_nvm_debug_en: [ flash_ctrl.lc_nvm_debug_en + rram_macro.lc_nvm_debug_en ] lc_ctrl.lc_hw_debug_clr: [ @@ -10423,6 +10874,7 @@ sram_ctrl_ret.lc_escalate_en aon_timer.lc_escalate_en flash_ctrl.lc_escalate_en + rram_ctrl.lc_escalate_en pinmux.lc_escalate_en ] lc_ctrl.lc_check_byp_en: @@ -10442,23 +10894,28 @@ [ otp_ctrl.lc_creator_seed_sw_rw_en flash_ctrl.lc_creator_seed_sw_rw_en + rram_ctrl.lc_creator_seed_sw_rw_en ] lc_ctrl.lc_owner_seed_sw_rw_en: [ flash_ctrl.lc_owner_seed_sw_rw_en + rram_ctrl.lc_owner_seed_sw_rw_en ] lc_ctrl.lc_iso_part_sw_rd_en: [ flash_ctrl.lc_iso_part_sw_rd_en + rram_ctrl.lc_iso_part_sw_rd_en ] lc_ctrl.lc_iso_part_sw_wr_en: [ flash_ctrl.lc_iso_part_sw_wr_en + rram_ctrl.lc_iso_part_sw_wr_en ] lc_ctrl.lc_seed_hw_rd_en: [ otp_ctrl.lc_seed_hw_rd_en flash_ctrl.lc_seed_hw_rd_en + rram_ctrl.lc_seed_hw_rd_en ] lc_ctrl.lc_rma_state: [ @@ -10500,6 +10957,10 @@ [ pwrmgr.sw_rst_req ] + rram_ctrl.rram_macro: + [ + rram_macro.rram_macro + ] pwrmgr.wakeups: [ sysrst_ctrl.wkup_req @@ -10570,6 +11031,18 @@ [ main.tl_flash_ctrl__mem ] + rram_ctrl.core_tl: + [ + main.tl_rram_ctrl__core + ] + rram_macro.prim_tl: + [ + main.tl_rram_macro__prim + ] + rram_ctrl.host_tl: + [ + main.tl_rram_ctrl__host + ] hmac.tl: [ main.tl_hmac @@ -10736,6 +11209,7 @@ rv_core_ibex.irq_timer rv_core_ibex.hart_id rv_core_ibex.boot_addr + rram_ctrl.otp_key pinmux.dft_jtag otp_ctrl.otp_broadcast csrng.otp_en_csrng_sw_app_read @@ -10879,6 +11353,7 @@ sram_ctrl_main.ram sram_ctrl_sec.ram flash_ctrl.mem + rram_ctrl.host ] rv_core_ibex.cored: [ @@ -10895,6 +11370,9 @@ flash_ctrl.core flash_ctrl.prim flash_ctrl.mem + rram_ctrl.core + rram_ctrl.host + rram_macro.prim aes entropy_src csrng @@ -10924,6 +11402,9 @@ flash_ctrl.core flash_ctrl.prim flash_ctrl.mem + rram_ctrl.core + rram_ctrl.host + rram_macro.prim aes entropy_src csrng @@ -11229,6 +11710,72 @@ stub: false pipeline: true } + { + name: rram_ctrl.core + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x41010000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rram_macro.prim + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rram_macro + addr_range: + [ + { + base_addrs: + { + hart: 0x41018000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rram_ctrl.host + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x200000 + } + ] + xbar: false + stub: false + pipeline: true + } { name: hmac type: device @@ -11752,6 +12299,45 @@ top_signame: flash_ctrl_mem_tl index: -1 } + { + name: tl_rram_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_ctrl_core_tl + index: -1 + } + { + name: tl_rram_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_macro_prim_tl + index: -1 + } + { + name: tl_rram_ctrl__host + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_ctrl_host_tl + index: -1 + } { name: tl_hmac struct: tl @@ -13757,6 +14343,14 @@ desc: "" attr: "" } + { + instance: rram_macro + port: "" + connection: muxed + pad: "" + desc: "" + attr: "" + } { instance: sensor_ctrl port: "" @@ -14668,6 +15262,42 @@ domain: Main glob_idx: 49 } + { + name: rram_macro_tck + width: 1 + type: input + idx: -1 + pad: "" + attr: "" + connection: muxed + desc: "" + domain: Main + glob_idx: 50 + } + { + name: rram_macro_tms + width: 1 + type: input + idx: -1 + pad: "" + attr: "" + connection: muxed + desc: "" + domain: Main + glob_idx: 51 + } + { + name: rram_macro_tdi + width: 1 + type: input + idx: -1 + pad: "" + attr: "" + connection: muxed + desc: "" + domain: Main + glob_idx: 52 + } { name: sysrst_ctrl_ac_present width: 1 @@ -14678,7 +15308,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 50 + glob_idx: 53 } { name: sysrst_ctrl_key0_in @@ -14690,7 +15320,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 51 + glob_idx: 54 } { name: sysrst_ctrl_key1_in @@ -14702,7 +15332,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 52 + glob_idx: 55 } { name: sysrst_ctrl_key2_in @@ -14714,7 +15344,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 53 + glob_idx: 56 } { name: sysrst_ctrl_pwrb_in @@ -14726,7 +15356,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 54 + glob_idx: 57 } { name: sysrst_ctrl_lid_open @@ -14738,7 +15368,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 55 + glob_idx: 58 } { name: usbdev_sense @@ -14750,7 +15380,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 56 + glob_idx: 59 } { name: spi_host0_sck @@ -14860,6 +15490,18 @@ domain: Main glob_idx: 48 } + { + name: rram_macro_tdo + width: 1 + type: output + idx: -1 + pad: "" + attr: "" + connection: muxed + desc: "" + domain: Main + glob_idx: 49 + } { name: sensor_ctrl_ast_debug_out width: 9 @@ -14870,7 +15512,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 49 + glob_idx: 50 } { name: sensor_ctrl_ast_debug_out @@ -14882,7 +15524,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 50 + glob_idx: 51 } { name: sensor_ctrl_ast_debug_out @@ -14894,7 +15536,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 51 + glob_idx: 52 } { name: sensor_ctrl_ast_debug_out @@ -14906,7 +15548,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 52 + glob_idx: 53 } { name: sensor_ctrl_ast_debug_out @@ -14918,7 +15560,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 53 + glob_idx: 54 } { name: sensor_ctrl_ast_debug_out @@ -14930,7 +15572,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 54 + glob_idx: 55 } { name: sensor_ctrl_ast_debug_out @@ -14942,7 +15584,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 55 + glob_idx: 56 } { name: sensor_ctrl_ast_debug_out @@ -14954,7 +15596,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 56 + glob_idx: 57 } { name: sensor_ctrl_ast_debug_out @@ -14966,7 +15608,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 57 + glob_idx: 58 } { name: otp_macro_test @@ -14978,7 +15620,7 @@ connection: muxed desc: "" domain: Main - glob_idx: 58 + glob_idx: 59 } { name: sysrst_ctrl_bat_disable @@ -14990,7 +15632,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 59 + glob_idx: 60 } { name: sysrst_ctrl_key0_out @@ -15002,7 +15644,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 60 + glob_idx: 61 } { name: sysrst_ctrl_key1_out @@ -15014,7 +15656,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 61 + glob_idx: 62 } { name: sysrst_ctrl_key2_out @@ -15026,7 +15668,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 62 + glob_idx: 63 } { name: sysrst_ctrl_pwrb_out @@ -15038,7 +15680,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 63 + glob_idx: 64 } { name: sysrst_ctrl_z3_wakeup @@ -15050,7 +15692,7 @@ connection: muxed desc: "" domain: Aon - glob_idx: 64 + glob_idx: 65 } ] io_counts: @@ -15065,8 +15707,8 @@ muxed: { inouts: 42 - inputs: 15 - outputs: 23 + inputs: 18 + outputs: 24 pads: 47 } } @@ -16129,6 +16771,61 @@ lpg_name: infra_lc_Main lpg_idx: 17 } + { + name: rram_ctrl_recov_err + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: rram_ctrl + desc: rram_ctrl recov_err alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } + { + name: rram_ctrl_fatal_std_err + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: rram_ctrl + desc: rram_ctrl fatal_std_err alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } + { + name: rram_ctrl_fatal_err + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: rram_ctrl + desc: rram_ctrl fatal_err alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } + { + name: rram_ctrl_fatal_macro_err + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: rram_ctrl + desc: rram_ctrl fatal_macro_err alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } + { + name: rram_ctrl_recov_macro_err + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: rram_ctrl + desc: rram_ctrl recov_macro_err alert + lpg_name: infra_lc_Main + lpg_idx: 17 + } { name: rv_dm_fatal_fault width: 1 @@ -18135,6 +18832,84 @@ plic: rv_plic outgoing: false } + { + name: rram_ctrl_wr_empty + width: 1 + type: interrupt + module_name: rram_ctrl + desc: rram_ctrl wr_empty interrupt + intr_type: IntrType.Status + default_val: true + incoming: false + domain: Main + plic: rv_plic + outgoing: false + } + { + name: rram_ctrl_wr_lvl + width: 1 + type: interrupt + module_name: rram_ctrl + desc: rram_ctrl wr_lvl interrupt + intr_type: IntrType.Status + default_val: true + incoming: false + domain: Main + plic: rv_plic + outgoing: false + } + { + name: rram_ctrl_rd_full + width: 1 + type: interrupt + module_name: rram_ctrl + desc: rram_ctrl rd_full interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + domain: Main + plic: rv_plic + outgoing: false + } + { + name: rram_ctrl_rd_lvl + width: 1 + type: interrupt + module_name: rram_ctrl + desc: rram_ctrl rd_lvl interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + domain: Main + plic: rv_plic + outgoing: false + } + { + name: rram_ctrl_op_done + width: 1 + type: interrupt + module_name: rram_ctrl + desc: rram_ctrl op_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + domain: Main + plic: rv_plic + outgoing: false + } + { + name: rram_ctrl_corr_err + width: 1 + type: interrupt + module_name: rram_ctrl + desc: rram_ctrl corr_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + domain: Main + plic: rv_plic + outgoing: false + } { name: hmac_hmac_done width: 1 @@ -18402,11 +19177,11 @@ rv_plic: { domain: Main - count_tot: 184 + count_tot: 190 count_pd: { Aon: 7 - Main: 176 + Main: 182 } } } @@ -19310,6 +20085,7 @@ sensor_ctrl sram_ctrl_ret flash_ctrl + rram_ctrl rv_dm rv_plic aes @@ -19591,165 +20367,179 @@ alert_handler[37]: recov_prim_flash_alert ] } + module_rram_ctrl: + { + tx_expr: alert_tx[42:38] + rx_expr: alert_rx[42:38] + async_expr: alert_handler_reg_pkg::AsyncOn[42:38] + comments: + [ + alert_handler[38]: recov_err + alert_handler[39]: fatal_std_err + alert_handler[40]: fatal_err + alert_handler[41]: fatal_macro_err + alert_handler[42]: recov_macro_err + ] + } module_rv_dm: { - tx_expr: alert_tx[38] - rx_expr: alert_rx[38] - async_expr: alert_handler_reg_pkg::AsyncOn[38] + tx_expr: alert_tx[43] + rx_expr: alert_rx[43] + async_expr: alert_handler_reg_pkg::AsyncOn[43] comments: [ - alert_handler[38]: fatal_fault + alert_handler[43]: fatal_fault ] } module_rv_plic: { - tx_expr: alert_tx[39] - rx_expr: alert_rx[39] - async_expr: alert_handler_reg_pkg::AsyncOn[39] + tx_expr: alert_tx[44] + rx_expr: alert_rx[44] + async_expr: alert_handler_reg_pkg::AsyncOn[44] comments: [ - alert_handler[39]: fatal_fault + alert_handler[44]: fatal_fault ] } module_aes: { - tx_expr: alert_tx[41:40] - rx_expr: alert_rx[41:40] - async_expr: alert_handler_reg_pkg::AsyncOn[41:40] + tx_expr: alert_tx[46:45] + rx_expr: alert_rx[46:45] + async_expr: alert_handler_reg_pkg::AsyncOn[46:45] comments: [ - alert_handler[40]: recov_ctrl_update_err - alert_handler[41]: fatal_fault + alert_handler[45]: recov_ctrl_update_err + alert_handler[46]: fatal_fault ] } module_hmac: { - tx_expr: alert_tx[42] - rx_expr: alert_rx[42] - async_expr: alert_handler_reg_pkg::AsyncOn[42] + tx_expr: alert_tx[47] + rx_expr: alert_rx[47] + async_expr: alert_handler_reg_pkg::AsyncOn[47] comments: [ - alert_handler[42]: fatal_fault + alert_handler[47]: fatal_fault ] } module_kmac: { - tx_expr: alert_tx[44:43] - rx_expr: alert_rx[44:43] - async_expr: alert_handler_reg_pkg::AsyncOn[44:43] + tx_expr: alert_tx[49:48] + rx_expr: alert_rx[49:48] + async_expr: alert_handler_reg_pkg::AsyncOn[49:48] comments: [ - alert_handler[43]: recov_operation_err - alert_handler[44]: fatal_fault_err + alert_handler[48]: recov_operation_err + alert_handler[49]: fatal_fault_err ] } module_otbn: { - tx_expr: alert_tx[46:45] - rx_expr: alert_rx[46:45] - async_expr: alert_handler_reg_pkg::AsyncOn[46:45] + tx_expr: alert_tx[51:50] + rx_expr: alert_rx[51:50] + async_expr: alert_handler_reg_pkg::AsyncOn[51:50] comments: [ - alert_handler[45]: fatal - alert_handler[46]: recov + alert_handler[50]: fatal + alert_handler[51]: recov ] } module_keymgr: { - tx_expr: alert_tx[48:47] - rx_expr: alert_rx[48:47] - async_expr: alert_handler_reg_pkg::AsyncOn[48:47] + tx_expr: alert_tx[53:52] + rx_expr: alert_rx[53:52] + async_expr: alert_handler_reg_pkg::AsyncOn[53:52] comments: [ - alert_handler[47]: recov_operation_err - alert_handler[48]: fatal_fault_err + alert_handler[52]: recov_operation_err + alert_handler[53]: fatal_fault_err ] } module_csrng: { - tx_expr: alert_tx[50:49] - rx_expr: alert_rx[50:49] - async_expr: alert_handler_reg_pkg::AsyncOn[50:49] + tx_expr: alert_tx[55:54] + rx_expr: alert_rx[55:54] + async_expr: alert_handler_reg_pkg::AsyncOn[55:54] comments: [ - alert_handler[49]: recov_alert - alert_handler[50]: fatal_alert + alert_handler[54]: recov_alert + alert_handler[55]: fatal_alert ] } module_entropy_src: { - tx_expr: alert_tx[52:51] - rx_expr: alert_rx[52:51] - async_expr: alert_handler_reg_pkg::AsyncOn[52:51] + tx_expr: alert_tx[57:56] + rx_expr: alert_rx[57:56] + async_expr: alert_handler_reg_pkg::AsyncOn[57:56] comments: [ - alert_handler[51]: recov_alert - alert_handler[52]: fatal_alert + alert_handler[56]: recov_alert + alert_handler[57]: fatal_alert ] } module_edn0: { - tx_expr: alert_tx[54:53] - rx_expr: alert_rx[54:53] - async_expr: alert_handler_reg_pkg::AsyncOn[54:53] + tx_expr: alert_tx[59:58] + rx_expr: alert_rx[59:58] + async_expr: alert_handler_reg_pkg::AsyncOn[59:58] comments: [ - alert_handler[53]: recov_alert - alert_handler[54]: fatal_alert + alert_handler[58]: recov_alert + alert_handler[59]: fatal_alert ] } module_edn1: { - tx_expr: alert_tx[56:55] - rx_expr: alert_rx[56:55] - async_expr: alert_handler_reg_pkg::AsyncOn[56:55] + tx_expr: alert_tx[61:60] + rx_expr: alert_rx[61:60] + async_expr: alert_handler_reg_pkg::AsyncOn[61:60] comments: [ - alert_handler[55]: recov_alert - alert_handler[56]: fatal_alert + alert_handler[60]: recov_alert + alert_handler[61]: fatal_alert ] } module_sram_ctrl_main: { - tx_expr: alert_tx[57] - rx_expr: alert_rx[57] - async_expr: alert_handler_reg_pkg::AsyncOn[57] + tx_expr: alert_tx[62] + rx_expr: alert_rx[62] + async_expr: alert_handler_reg_pkg::AsyncOn[62] comments: [ - alert_handler[57]: fatal_error + alert_handler[62]: fatal_error ] } module_sram_ctrl_sec: { - tx_expr: alert_tx[58] - rx_expr: alert_rx[58] - async_expr: alert_handler_reg_pkg::AsyncOn[58] + tx_expr: alert_tx[63] + rx_expr: alert_rx[63] + async_expr: alert_handler_reg_pkg::AsyncOn[63] comments: [ - alert_handler[58]: fatal_error + alert_handler[63]: fatal_error ] } module_rom_ctrl: { - tx_expr: alert_tx[59] - rx_expr: alert_rx[59] - async_expr: alert_handler_reg_pkg::AsyncOn[59] + tx_expr: alert_tx[64] + rx_expr: alert_rx[64] + async_expr: alert_handler_reg_pkg::AsyncOn[64] comments: [ - alert_handler[59]: fatal + alert_handler[64]: fatal ] } module_rv_core_ibex: { - tx_expr: alert_tx[63:60] - rx_expr: alert_rx[63:60] - async_expr: alert_handler_reg_pkg::AsyncOn[63:60] + tx_expr: alert_tx[68:65] + rx_expr: alert_rx[68:65] + async_expr: alert_handler_reg_pkg::AsyncOn[68:65] comments: [ - alert_handler[60]: fatal_sw_err - alert_handler[61]: recov_sw_err - alert_handler[62]: fatal_hw_err - alert_handler[63]: recov_hw_err + alert_handler[65]: fatal_sw_err + alert_handler[66]: recov_sw_err + alert_handler[67]: fatal_hw_err + alert_handler[68]: recov_hw_err ] } } @@ -19758,11 +20548,11 @@ alert_handler: { domain: Main - count_tot: 64 + count_tot: 69 count_pd: { Aon: 11 - Main: 53 + Main: 58 } connect_pd: { @@ -19847,6 +20637,7 @@ aon_timer sensor_ctrl flash_ctrl + rram_ctrl hmac kmac otbn @@ -24435,6 +25226,270 @@ top_signame: flash_ctrl_mem_tl index: -1 } + { + name: rram_macro + struct: rram_macro + package: rram_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: rram_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_ctrl_rram_macro + index: -1 + } + { + name: otp_key + struct: nvm_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: rram_ctrl + default: "" + top_signame: rram_ctrl_otp_key + index: -1 + } + { + name: otp_macro + desc: Data interface for the OTP macro. + struct: otp_ctrl_macro + package: otp_ctrl_macro_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: rram_ctrl + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_iso_part_sw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_iso_part_sw_rd_en + index: -1 + } + { + name: lc_iso_part_sw_wr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_iso_part_sw_wr_en + index: -1 + } + { + name: lc_seed_hw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_nvm_rma_req + index: -1 + } + { + name: rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rram_ctrl + index: -1 + } + { + name: rma_seed + struct: lc_nvm_rma_seed + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_ctrl + default: "" + domain: Main + top_signame: lc_ctrl_lc_nvm_rma_seed + index: -1 + } + { + name: pwrmgr + struct: pwr_nvm + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: rram_ctrl + index: -1 + } + { + name: keymgr + struct: keymgr_rram + package: rram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rram_ctrl + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_ctrl_core_tl + index: -1 + } + { + name: host_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_ctrl + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_ctrl_host_tl + index: -1 + } + { + name: rram_macro + struct: rram_macro + package: rram_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_macro + default: "" + domain: Main + top_signame: rram_ctrl_rram_macro + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_macro + default: "" + domain: Main + top_signame: lc_ctrl_lc_nvm_debug_en + index: -1 + } + { + name: obs_ctrl + desc: AST observability control signals. + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: rram_macro + default: "" + domain: Main + top_signame: ast_obs_ctrl + index: -1 + } + { + name: rram_obs + desc: AST observability bus. + struct: logic + type: uni + act: req + width: 8 + inst_name: rram_macro + index: -1 + } + { + name: prim_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rram_macro + default: "" + end_idx: -1 + top_type: one-to-one + top_signame: rram_macro_prim_tl + index: -1 + } { name: next_dm_addr desc: @@ -26643,6 +27698,45 @@ top_signame: flash_ctrl_mem_tl index: -1 } + { + name: tl_rram_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_ctrl_core_tl + index: -1 + } + { + name: tl_rram_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_macro_prim_tl + index: -1 + } + { + name: tl_rram_ctrl__host + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_ctrl_host_tl + index: -1 + } { name: tl_hmac struct: tl @@ -32782,6 +33876,30 @@ suffix: "" default: prim_mubi_pkg::MUBI4_DEFAULT } + { + package: rram_ctrl_pkg + struct: rram_macro_req + domain: Main + signame: rram_ctrl_rram_macro_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: rram_ctrl_pkg + struct: rram_macro_rsp + domain: Main + signame: rram_ctrl_rram_macro_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: rram_ctrl_pkg::RRAM_MACRO_RSP_DEFAULT + } { package: "" struct: logic @@ -33142,6 +34260,78 @@ suffix: rsp default: "" } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: rram_ctrl_core_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: rram_ctrl_core_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: rram_macro_prim_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: rram_macro_prim_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + domain: Main + signame: rram_ctrl_host_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + domain: Main + signame: rram_ctrl_host_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } { package: tlul_pkg struct: tl_h2d @@ -33932,6 +35122,26 @@ end_idx: -1 default: "" } + { + package: otp_ctrl_pkg + struct: nvm_otp_key_req + domain: Main + signame: rram_ctrl_otp_key_req + width: 1 + type: req_rsp + end_idx: -1 + default: "" + } + { + package: otp_ctrl_pkg + struct: nvm_otp_key_rsp + domain: Main + signame: rram_ctrl_otp_key_rsp + width: 1 + type: req_rsp + end_idx: -1 + default: "" + } { package: jtag_pkg struct: jtag_req diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson index 7d17b90d264ea..b136226acf1a8 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson @@ -47,7 +47,7 @@ randcount: 40 randtype: data name_top: RndCnstOtpCtrlLfsrSeed - default: 0x8f9eed04c + default: 0xe6596e87f9 randwidth: 40 } { @@ -57,7 +57,7 @@ randcount: 40 randtype: perm name_top: RndCnstOtpCtrlLfsrPerm - default: 0x9577622d23674e16822a46c638c25664f14344750422379c01f610566801 + default: 0x6e589d6858603d61c92c462744a5d47c838c04d0c27904d26401a356499c randwidth: 240 } { @@ -67,7 +67,7 @@ randcount: 256 randtype: data name_top: RndCnstOtpCtrlScrmblKeyInit - default: 0x956c7f904b9eded09b89a75433566f4963d9dc27f3ecb11ce3b87aaa7abc8592 + default: 0x4fb9d469171b950e364b0dac5469568e661498fd89197ccae8ea08ff43efc2bf randwidth: 256 } { @@ -2935,7 +2935,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivInvalid - default: 0xb1881083aff7bde18eacff85679453d + default: 0xb1c6ab5cc63e6f4741e80f777cb7fc05 randwidth: 128 } { @@ -2945,7 +2945,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked - default: 0xa77d92a176b87118af11cdbe78d67060 + default: 0x41a1b896350c9636d6814d23e2f5ff1 randwidth: 128 } { @@ -2955,7 +2955,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivDev - default: 0x615a20b9c0740f07969ccd2d10a1a6e7 + default: 0x275ef19959aaa8b6a004d5574984ded1 randwidth: 128 } { @@ -2965,7 +2965,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivProduction - default: 0x988fa528ac032e0a6138cb8316ff95c6 + default: 0xcc79bd6787d6663aa5e622682a6525e0 randwidth: 128 } { @@ -2975,7 +2975,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivRma - default: 0x5cd7a1a768b06e0106d60eda0f1bc67a + default: 0x83ccddbd2a1b008057c22c884ed49d87 randwidth: 128 } { @@ -2985,7 +2985,7 @@ randcount: 1024 randtype: data name_top: RndCnstLcCtrlInvalidTokens - default: 0xdf85bd9a56ea088d33ffaa6a1155afb0169ab2de3973d027ee30b8f901f644ec7cd3e56c8ed1ec38739f1d0deb7c774199cf6dd057f44c13e25c7a5877bc5242e6ee63ecdf458ae6596e87f9f973db98aaa293568fd1f31a0165939d819d1518690e6473cdb2479391635057ca1045b9e1917e1ff0189b04a4f7fba960fe098a + default: 0xa5b56ba7353c532142f50667e220c5b724c3fdb6d060653b42a96f88b574e4d3814f5116b3e6f3e331da1182dbc29c894f1800edecf7b17682d2ce3db9b12e1af4339e1f45164a418ebc52210d58dc65508e869af565c1b87d687ee837fc119f5bbe7395cac38919c27006c23e1425910840042a75ecc25d4e2267e3bff26e00 randwidth: 1024 } ] @@ -3010,7 +3010,7 @@ randcount: 32 randtype: data name_top: RndCnstAlertHandlerLfsrSeed - default: 0x4fb9d469 + default: 0x3aacbf7d randwidth: 32 } { @@ -3020,7 +3020,7 @@ randcount: 32 randtype: perm name_top: RndCnstAlertHandlerLfsrPerm - default: 0x769f9b6fa88170b20267f53ec8ddaaaf1260c862 + default: 0x13cc975993de297d46b0cc8851f1befac28074ea randwidth: 160 } ] @@ -3061,7 +3061,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetSramKey - default: 0xfc05041a1b896350c9636d6814d23e2f + default: 0xcd6cd2ce715e7cceb1bc1c61b3d27bb8 randwidth: 128 } { @@ -3071,7 +3071,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetSramNonce - default: 0x5ff1275ef19959aaa8b6a004d5574984 + default: 0xe8398e880ecd252956ba81616362b27e randwidth: 128 } { @@ -3081,7 +3081,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlRetLfsrSeed - default: 0xded1cc79bd6787d6 + default: 0xafb903ec79bddf0a randwidth: 64 } { @@ -3091,7 +3091,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlRetLfsrPerm - default: 0x765997732c42d6c6d20eeb45de3f91af4c07a8ca1e7c4598938050ed43cdebd8674e22d5d801bcbf3809fca688e69399 + default: 0x7aaaecc251dd554e63ef872f34838acfe31142e09287cd296d65da646cb53c49ed9a0e898852c0c68fc3918dfdd817d3 randwidth: 384 } ] @@ -3145,7 +3145,7 @@ randcount: 128 randtype: data name_top: RndCnstFlashCtrlAddrKey - default: 0xb12e1af4339e1f45164a418ebc52210d + default: 0x5c0cae7ed7fe6c45d1534fd390c7b068 randwidth: 128 } { @@ -3155,7 +3155,7 @@ randcount: 128 randtype: data name_top: RndCnstFlashCtrlDataKey - default: 0x58dc65508e869af565c1b87d687ee837 + default: 0xcfe8968794de88e8ff4adc3d02ebfa0a randwidth: 128 } { @@ -3165,7 +3165,7 @@ randcount: 512 randtype: data name_top: RndCnstFlashCtrlAllSeeds - default: 0xfc119f5bbe7395cac38919c27006c23e1425910840042a75ecc25d4e2267e3bff26e003aacbf7d513aea01e9ee420d5b523f6b00c81bded7282425b1bb59b801 + default: 0x1d5faa5ee00ca534911723e1ea0687402a816510c535a8164939d97df7421ad4d2c18b270d422ec39c41f727d130ed9b18b90e42e4287f60ad57d6a551e78f94 randwidth: 512 } { @@ -3175,7 +3175,7 @@ randcount: 64 randtype: data name_top: RndCnstFlashCtrlLfsrSeed - default: 0x481ed5793accfb3a + default: 0xb8ae9f2bb40621f randwidth: 64 } { @@ -3185,12 +3185,92 @@ randcount: 64 randtype: perm name_top: RndCnstFlashCtrlLfsrPerm - default: 0xb869f01442d0211e544e5f2a66948c7746a6eb8f40c643d6ee8b60dca2438a339ebd81ec7d77356f3095cb607f36b87e + default: 0x56869361988cc8f1eb9b97e5537227b6e5de0fe4bab1b75687dc4a111bc9cc0e3b3a409cc01a60185fe32f4375daaf10 randwidth: 384 } ] template_type: flash_ctrl } + { + name: rram_ctrl + type: rram_ctrl + base_addrs: + { + core: + { + hart: 0x41010000 + } + host: + { + hart: 0x30000000 + } + } + memory: + { + host: + { + label: rram + swaccess: ro + data_intg_passthru: "true" + exec: True + byte_write: False + size: 0x200000 + } + } + param_list: + [ + { + name: RndCnstAddrKey + desc: Compile-time random bits for default address key + type: rram_ctrl_pkg::rram_key_t + randcount: 128 + randtype: data + name_top: RndCnstRramCtrlAddrKey + default: 0x40ca72ce50c55920ba14e126dcd0a3f6 + randwidth: 128 + } + { + name: RndCnstDataKey + desc: Compile-time random bits for default data key + type: rram_ctrl_pkg::rram_key_t + randcount: 128 + randtype: data + name_top: RndCnstRramCtrlDataKey + default: 0xc9b71d03e571bee0e47e5b49e80e3da3 + randwidth: 128 + } + { + name: RndCnstAllSeeds + desc: Compile-time random bits for default seeds + type: rram_ctrl_pkg::all_seeds_t + randcount: 512 + randtype: data + name_top: RndCnstRramCtrlAllSeeds + default: 0x9a52777dbcfd9e38d4d189ec4b433e5314f88c893a6cb3fd30a87c38225a15108e992d14bf1225d4b19b23f40e358f1bf4fe1d5a50b10232a8b3c33a6017b970 + randwidth: 512 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: rram_ctrl_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstRramCtrlLfsrSeed + default: 0x36561aa262310424 + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: rram_ctrl_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstRramCtrlLfsrPerm + default: 0x8f2be5ef95bac5548a3348742170e9c647700d6133099acabcc72e9a2e4520d1e8e27c4ff5c2edbdb690f859977be41 + randwidth: 384 + } + ] + } { name: aes type: aes @@ -3211,7 +3291,7 @@ randcount: 64 randtype: data name_top: RndCnstAesClearingLfsrSeed - default: 0x3eae3c2f18b4666b + default: 0xd66b581354cbcb9a randwidth: 64 } { @@ -3221,7 +3301,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingLfsrPerm - default: 0x7dc306fb5d82893b03a5445e87fc8a20ddeef6604eaabcd96b8c52be8e843f9f1091d540ed8c23807165b672c96f4597 + default: 0x7be94f37f4088f9c141f87434554e6cda61b4ad93428915ff5cf2bb84b0b5c08b71b282aa3aa4286fd8c056ee7d59c4e randwidth: 384 } { @@ -3231,7 +3311,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingSharePerm - default: 0x967bfc5c0d074f65b5742cee8dbadef98ef045c51add590ff66a6c332a0bb432621b97ce4bfa8dc44660290841eb8205 + default: 0x7fa5f85b1aff09154166eb3ed4aa3d60f404a6fabcd06d9e372e5d0d41478a03128db6a497b9f320b3addc04dc866270 randwidth: 384 } { @@ -3241,7 +3321,7 @@ randcount: 288 randtype: data name_top: RndCnstAesMaskingLfsrSeed - default: 0xef142e028325714513bfdc2a062c2eb4ecdc716a92861ff7c06c6910e727cbed4ee2b19e + default: 0xd85825526737c611fa0e7d754ae64a354cc7c16fa06ae28e208c1d5afc5f0d9de8d61cc3 randwidth: 288 } { @@ -3251,7 +3331,7 @@ randcount: 160 randtype: perm name_top: RndCnstAesMaskingLfsrPerm - default: 0x640581943f4345358388890f786266924b904e132a5d10600c57399b2e063b5c37002f4a4817915182538b276c2c635a348f2455748c8d3c6f1e2380224175049c42338656323a8561976d317f2b1b380b30701901287a840d651a07694d9a12095f67164c9f08982d117c3e54188e368a79460a961f9d259944686a1c4f875e93779e3d0e495b7e71031d26142059507240157d7b9529027376586b6e215247 + default: 0x5b671e8f6a9a72185a85382f120b49921c0698117b91909f4e524c3643762c9447587732196b1d352a0a5481159950531b4439828a7a782d935913348b7d513137230c304b273b9e898c61001f41634f757f48466c9b0109034a26043c627197253d079c05695c7e248e732e107c2b576f42885d5614705e744d55080f96283a2186953f683e0e3322178d805f647960836d16020d846e451a8740299d666520 randwidth: 1280 } ] @@ -3276,7 +3356,7 @@ randcount: 288 randtype: data name_top: RndCnstKmacLfsrSeed - default: 0x9d9f58f70432d8bf8509a79ca1d3ab83a61af330c5cfd188035e2f18108133b38a7167f8 + default: 0xb4592ff19842d51606fe22b8ed0e3f50759650ef701a4e6e4916eee56ef868e4092f9516 randwidth: 288 } { @@ -3286,7 +3366,7 @@ randcount: 800 randtype: perm name_top: RndCnstKmacLfsrPerm - default: 0x1730472dbe79e7235e533d135b58559045f55c9d1d0219553c5b270885c0b3cd35c62d1ecf7260d87aeb26a5da341f11c5f694a4300d6b76edb13e3d252f9632a8a34d50c01c4b84b502e7ac70151a6ac6c3130c771be1a9ddb84b1ce9fe053195b74c84b4a6c284890967854a5653d9645c676f2be71805b7a71b3b05761e28a50c84ed042a5b47168728bc66e25531116f5795e1f7414e7596f0c02aea387e7ed104f4caa1cd449e35436f23360e73e2a42588a268fc55a836a28bdf113c583a0f0a65e648ea115bdadc42c14761f9d1075160aa88f30b2a37867e0fcfe8c1cc6bb073585224ed51ca688565d22f0354efb8109f0057d2d9c3480ee34992111dd996eac201b5eae66ab1893ab3ae234b0e88a98854531311c648800e704170a43c198061bac87a4deac2a93bd1f268fa29d737206bb02846fd0f55624a5960306bb83e61082acc75823c9e4408dd52e198729f7e9f25fca3b9131c0a2733ac5749fc388149b407b500285c68010f0026750bdf9b28e8a6aed821b7a41ee910b4534ae97e7a25a14a90562e1727598636e930a201a64e68027b808ea78ef477d9f099fda1ae304612512fc265c9c19125d70d6cd9090943c6712489dc37c0da76c46500b38cf82308d8e69e2aa493a6513b47d914b710aba526f87544347ad74ed4e0e985c25b4372467e12604d80a555a4d1b60b70c2005a5a95daadde5880c462185c15e10717b75c24fee1bd4d106104b4d012446d5dd9a0c937af1849daff30af15d20c69a5051ee8a9c9b7827d68aa56663195ebf140c47c181ba64b6252a88c352b4b07f9ffc3aaf678b39cefd5b47c0b8b97a2da751c425edf8fd9163a33541ec661a73fcb108d87b80b2c697c585258da3c3f4e5c7816a2e07b45f4242cc0f84c30263930a61884d0697b998d948c8fc3e828f8ec455b58426ba51d97b4ba59da304108635009816699e62b72a0b62eb07af3279cd889a593cccbbca44e878b0a482ad1a3d4fba60835581d324a057d933208abba8018c5d1b2c92b2b70dceb96a8a27027b663713a2e7ceb505476a6e1621a26beaf6419ef690701fe5cad139b1c1f181b058c45001591ab14c7e034a569509b163d030a98a44ca9b1a477980a8e0a8b8a7c46c49928cf7152d8b291c585b6e469966aa0e05842d649611962eb6560246caad064796eaa1386928bce4505d72bd0e5514a15c5e048224fa1b6ec614e2092fdea3f20b9e5d08c948121360e62b4bc3d0ad212055c28a6f119d1a71a0c70f90ec88952bd5f9e5834590d26945a8c878a5a1595b2c730d87520a814cd284adf5bf8955d8c714cbd9b84a6ad6eae40f6b2e5239af670c5022cd0cc511ea064923b6865e71c873813087492c2d322ee971519d2f8653daec32c409024d544b5 + default: 0x30a2887d19a2cb9a171b18cb3951ea60edcb28d031a948b1626e2a586c97c193ea12f357c4ec5e9a69186a0cd66f8e7655e4a881d5d1d11c9e13a6d39f22311d6e5983e5349c0615770813191e5408da5443b01e9189cf650af28a4421e5d7996ea6eef129c50b7abac3817185af260c520dfa4cc903fe880665c306d9b60ca76dd2002ff41a2a9eed41b6815c2141cf1e641eb80d368922d9481e2aa1523173af5b5a09de86604c551087925ab8328ca7021149bba3a0c6866a8e81aca3018b5b6c8f6b4020bd8b7398430e5799a451dec2180378982a66e1046dd555915aa1ff52dedb6961006dd47ed04e99c6b2d51e8541a60d77d6b7b08a07d43ad46fb22c04f67890db2b5c5db383a41302582a76685e2c4053f213c3d0d06dd8afcaf83cd57ca6f9c60059169a74553b8a891f0421a9b1b8229fc438f00d3dee1020d97650e6058c4b535608f5ac5584a4a1421e27f00f8c2554aeb23449220589a7dc60963faa716a30517d8f02d8ef012672fd75ad1995e00b2b5cd3f5c79922b21c8b6b988ba0bd85c93a5c65a7a682ecea8d98a89545928cc2e96f548662f2ad4e4cf255ef2445c5fac6339cf42a779e60951a1a431b663e21c30992997a7703d67dc143c0ebd0527d4cbb34e11f6f81d5dd72a052907091848bfb1f95a1c4ca746c476371725a211b14214b0689048e3e82e70da0c61b7804204aa2eaee924bb01781189fae5bdaccb2da6bbd3cb1c3564d0511a49522693824e071c5392b783a98ae42c652ed96c162e11dc225a7317c8cf13b907893d23c64c85da5f0cc2834d97b8e8a56dc87026b6eae07e22f85a4d8d5161a8344c1cbc2e73554453d295bf44a486803aef59d52f3cf10450f2b5b05930d8a907438d98295d06965031d276594e4e2317dc582804b5505b15d1e76aa37eda26fc36af0ac0fe39189f436ea67c537882993989f45e63132eb614880c0e279e59c70dfb9d53c502dbeaaa4c500468bec285a25041a3cc07e687798d72c8c9098ab59e4082a8e7a55075853259a75959dab1115dd248629094c2b13dab88907566071c5e86f5137f8dd3c60b8197faf9a182237c1c148e2b8c68677ce9600dc98f83996163482f9b04fe9b28dc341168c5f3ef037501a644238313f0e0d2a70cd288b097b118497d26dbc5e50b1349e4ecec9e9b4504893e56d9a87bb458d214293b55e5eedf602c352a7287449a25409831da859e3111c63afcac0591f2622364b78c6ca8171c02e261c0c4a009b9922b483caaecf4989a37a34568d457202a4eb674ca96c1446cc24abef07c09d921ee04903911349f63b2b80a974e5056fb2d26eacdb9405c404044945fd1014c8f48053d929b512ba509b26f7bb3095a9479da613e0b709c7e1fda815b12576c49096c6a482 randwidth: 8000 } { @@ -3296,7 +3376,7 @@ randcount: 800 randtype: data name_top: RndCnstKmacBufferLfsrSeed - default: 0x3238dcdf7de88b56b405e02bbfd73849c511f7f0b79f91dcd1d589b4cac4372c385f89d902019dabb6dd57022c77ede8609c409d905b3c7819b26a674328819928c5d79bf1db63d11e1c31bbc9a8c73fc4cc3d14ca6bc0b96812de7c775a54ff19343cb3 + default: 0x740a7ce7c92a49f71747d5a7e3b7e444732a39a69f03f5a88525a587cedea90913bbce814e6794df2bdd99e66d07801b027bd4e9bf578b146f616b6082465e44680ce93649a84575b465479f31a975234377e00d28ec32fa5850e8a7f607a49b2cade12a randwidth: 800 } { @@ -3306,7 +3386,7 @@ randcount: 64 randtype: perm name_top: RndCnstKmacMsgPerm - default: 0xfe376b54463de2a7873833052cdc7c7ede8f6f6c0acd6fa4475a405e51b2726802528674defed3e61b899e26814ac408 + default: 0x375a21bc7d010bbcd4ca2458d8900a6cc4159acf43fc490fe7ec5cad31465ad8e767039f778a5768baba825788b92dfc randwidth: 384 } ] @@ -3331,7 +3411,7 @@ randcount: 288 randtype: data name_top: RndCnstOtbnUrndPrngSeed - default: 0xe856f1d908e3f70de343d2226e9e864465a8ee55ec0e6a296789ded5c0af59ee62f1fd1b + default: 0xb2d1dc6455d87f13c9a4671446bea856d5fbb54bb5b253a70bc372cfc9bb0ab38a5edabe randwidth: 288 } { @@ -3341,7 +3421,7 @@ randcount: 256 randtype: perm name_top: RndCnstOtbnBnMacUrndPerm - default: 0xb9330db845b48936b039a170f15f724ee2a65a141eef3f7dae11c54dfb2113d4b218d85c83ee4a16970e296c9baa79bfd553c3643eb34943759881cdea730923479ef28b27fa4b86da3b07a3461b7f41f99c2042c7f7cf88ba3812340a625067dc1517bb55a8ddb556d663edf5f61c195becc4d0e3fdc17b8c0078de769da2262da5f891dfce1d6d80ad61826e68102ce8e93c747e3590d703c032bd57f4846608e631cc87fc6bb606d3af968f3d02a49f2f8e240fdb2ba0a7c6778d6037302ac804f35993928558a9e0959901cbca4c510c44c90bfe9a7ac25469e428526a8a1fe5f0486f407ce1d2bc4fabd965255dd13a711aebb72ee7945eb10522acffbe + default: 0xf265907e8b6c14f5711c345e3baa8cc74fa5e71218dad7eaef100208f0de56bbed4d95b3b4387f5cbc52d7896e229f4fb90ed952aa4c2e41b66a9f6481963b8bc4e3d1572b756353e50386739b5177f9b580903012f4c6ecd47f8da494225c4761c1e9136febdb2533c80f25161a097c6bb70b141523a770baf757cde4b12fc5d9dc09f9e86040e92d39aa3cf995fb9b4461f8a88186cea05a528d5dcd61d0293082e54d732db8bff83d0f344acc827e994c7dfa74a7313857de6d8f02334b0ee9cb30c5c31ca6ff77aa1222c821089aae06de1551669148e4deb405a3f65efbfce626433ab30816ac998a2ec1a0a8c062b607b79fdddf9843768a6d124d2e7 randwidth: 2048 } { @@ -3351,7 +3431,7 @@ randcount: 128 randtype: data name_top: RndCnstOtbnOtbnKey - default: 0xd5a7e3b7e444732a39a69f03f5a88525 + default: 0xa6f2b35c99fb71e1aaab3c208383adf5 randwidth: 128 } { @@ -3361,7 +3441,7 @@ randcount: 64 randtype: data name_top: RndCnstOtbnOtbnNonce - default: 0xa587cedea90913bb + default: 0x311ff71fd469219 randwidth: 64 } ] @@ -3386,7 +3466,7 @@ randcount: 64 randtype: data name_top: RndCnstKeymgrLfsrSeed - default: 0xce814e6794df2bdd + default: 0x23a8cd8c6ff98f9b randwidth: 64 } { @@ -3396,7 +3476,7 @@ randcount: 64 randtype: perm name_top: RndCnstKeymgrLfsrPerm - default: 0x938856d294289ea0b63df8c7109df24ecf9428beb3f1c3ae22533f65dad2343c2d5d1ef1698f45895bf57801a005be66 + default: 0x20a733fe35c48be4587532c5acf642e67b5ec7227caa639f414efdbe4a0c5929786fa8601f536e1a9015d036b606cc37 randwidth: 384 } { @@ -3406,7 +3486,7 @@ randcount: 32 randtype: perm name_top: RndCnstKeymgrRandPerm - default: 0xd13cc6a8a03237d09ff8959f0e6522a8d7474677 + default: 0x1f75401d1bcc54c2cccbaded8fc1c26f83223f89 randwidth: 160 } { @@ -3416,7 +3496,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrRevisionSeed - default: 0x9da8413dda43fecdd6c1a58693232d1c3e361d856ab2d1dc6455d87f13c9a467 + default: 0x57a6a15faa577395193cde4a6705bd11203330a927a8ce1ac88224a441c4192a randwidth: 256 } { @@ -3426,7 +3506,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrCreatorIdentitySeed - default: 0x1446bea856d5fbb54bb5b253a70bc372cfc9bb0ab38a5edabee7d224d1a66837 + default: 0xbe1dc426feee2c9b1c8b34b1a821afe522e11c4049d9b85f9dc3c99a37868579 randwidth: 256 } { @@ -3436,7 +3516,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOwnerIntIdentitySeed - default: 0x8437dd24797b602b068c0a1aeca298c96a8130ab336462cee1bf8c653fde5a40 + default: 0xb46a84095ea981140ff7f0c4ad73d59726774a37e33560266d52a2d9c4901261 randwidth: 256 } { @@ -3446,7 +3526,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOwnerIdentitySeed - default: 0xa24df78e146916dc55f8ce6dbfaad08910fbe1822c22a17a376fa1315c0cb3c2 + default: 0xc19f480238c0197cfa2c9010eefdd66d4b91725b5e1a95a1411451c3da5967f2 randwidth: 256 } { @@ -3456,7 +3536,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrSoftOutputSeed - default: 0x9cf4d10ae5c8f0c7b034bf23c9068e307d8513b7734aa78cc36f947a2737bbc0 + default: 0xcc89f1b0eca3388f277ffae4319b4144b76b7c902a9c89f6f8f8856d8b76b9b8 randwidth: 256 } { @@ -3466,7 +3546,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrHardOutputSeed - default: 0xacd1447baa83c3fc818bb3b4a840ad3214ceb3f354ca2e089302c3ee1d695aa6 + default: 0xec2f4f0eae6d9d26c47e279080dd58bcf5aa54a3f54824b5c6538f8aae68ec24 randwidth: 256 } { @@ -3476,7 +3556,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrAesSeed - default: 0x16283205db05cd6c18888ad01fe046eafd8bf298db7d5fe0fd32a29689a0c154 + default: 0xdf2d9b070658cb5b072bb74e79dea47a41863adaed04a043653afa5748aefe46 randwidth: 256 } { @@ -3486,7 +3566,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrKmacSeed - default: 0x9c28c210c01ff7e6e6d20e0404e7b51d020aa3695df42597cacaea4e16ef75a4 + default: 0xb7a5195322d57d74af0790f5050e1343b18dda6827d474657b77f7eda1a07047 randwidth: 256 } { @@ -3496,7 +3576,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOtbnSeed - default: 0x823ee1bf100b50c3a2c1ba79a60bd0d947c26d8d3c3874c6b8e34a85925ce73b + default: 0xf937051a057461414b8b3587c6de71b922084ec4ea31a97e0acb1acb48cba01d randwidth: 256 } { @@ -3506,7 +3586,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrCdi - default: 0x8f1550985eb503e8e40713152d132e9e94da720a712d7d6b7326f3102ba57ab1 + default: 0xea88816dc0357c3d419213eebd8fed49c167447d0a22fbfd5230d29fb8e5b65e randwidth: 256 } { @@ -3516,7 +3596,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrNoneSeed - default: 0x2f0c11e464e613088d6df2cc4352aa62df6b07199ea6c6782ad9bb2e78fa04c6 + default: 0x7c4102c37bc6a83863a98a9a7f84ea7c2377f98cf20ccaaa3bd0e4e02590e09c randwidth: 256 } ] @@ -3541,7 +3621,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivNonProduction - default: 0x8991de3b57a9b61206e6c0a2afa6a3c56d97128c7811e36a2829db025ec69547062345c400f5ef1b06a119650a85c302 + default: 0x975c71ca965f7b316d6c12ea819870d451dc29ee296da1850be6bed073f6ee870f58b89fabfe08c827837c7867eec58f randwidth: 384 } { @@ -3551,7 +3631,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivProduction - default: 0x37536dc3e35040de9ac1a6f2b35c99fb71e1aaab3c208383adf50311ff71fd46921923a8cd8c6ff98f9bdfc2b205d869 + default: 0xf573db5aaf6e95644dfad4262a7adb7f05d963e4282ae9ddb8fbe7a138d956ac336341a536f70c3ee90caeae11cb84b6 randwidth: 384 } ] @@ -3591,7 +3671,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramKey - default: 0xdd35500e5a51bba34a71d81e9eb876b + default: 0x5fdc5c702578f9f893c20a2865ef55e0 randwidth: 128 } { @@ -3601,7 +3681,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramNonce - default: 0x6f1996b2be4b58dfcfb830b9e25bdaa3 + default: 0xa6e7a0ba0b1c296731c59d861e3633e7 randwidth: 128 } { @@ -3611,7 +3691,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlMainLfsrSeed - default: 0xe1affa91806d01a8 + default: 0x5586c29b02cb9de8 randwidth: 64 } { @@ -3621,7 +3701,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlMainLfsrPerm - default: 0xe4d3302f22ce229ea15318ba7b5d9a3a5be8cdc8182e3dcc4e4767bd2bf25532b7da107635e656d20bcb5d430854de6 + default: 0xef96905642c5e12b25c9f6fd9d65e82a912252a84347380ffc70b7c2e63ed0e7094d9f2dd71eb6763bcc9801ab20178d randwidth: 384 } ] @@ -3661,7 +3741,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlSecSramKey - default: 0x57a6a15faa577395193cde4a6705bd11 + default: 0xc752a9c4607cec7dca3eb5f3d09295a3 randwidth: 128 } { @@ -3671,7 +3751,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlSecSramNonce - default: 0x203330a927a8ce1ac88224a441c4192a + default: 0x2c9cbafe5eff3cf35156b7815f112bb8 randwidth: 128 } { @@ -3681,7 +3761,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlSecLfsrSeed - default: 0xbe1dc426feee2c9b + default: 0xbdc22909ad6a99cf randwidth: 64 } { @@ -3691,7 +3771,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlSecLfsrPerm - default: 0xdb154be68e0e3db7fc0595919770234fea7b6142b210c1a4bf5749703160cc2b5a7b487d9b09d7b9243feab22ab0d887 + default: 0x7126ae213c3c463a2fdac6c434518bd4ccf1ca29960277c15255691d8fb47612b7ffdb79ed0aba399e0f5eb7a00c2264 randwidth: 384 } ] @@ -3731,7 +3811,7 @@ randcount: 64 randtype: data name_top: RndCnstRomCtrlScrNonce - default: 0x51c3da5967f2cc89 + default: 0x9e648fb10ee6f51a randwidth: 64 } { @@ -3741,7 +3821,7 @@ randcount: 128 randtype: data name_top: RndCnstRomCtrlScrKey - default: 0xf1b0eca3388f277ffae4319b4144b76b + default: 0xc4fcdb4b8f96f97753b0a8247424b489 randwidth: 128 } ] @@ -3766,7 +3846,7 @@ randcount: 32 randtype: data name_top: RndCnstRvCoreIbexLfsrSeed - default: 0x7c902a9c + default: 0x90156c71 randwidth: 32 } { @@ -3776,7 +3856,7 @@ randcount: 32 randtype: perm name_top: RndCnstRvCoreIbexLfsrPerm - default: 0x38066d0b75eb14bc511693c93e0525cdddf6c3d1 + default: 0x3d59fd396ddf262f01e81961d50629bd2d8c9246 randwidth: 160 } { @@ -3786,7 +3866,7 @@ randcount: 128 randtype: data name_top: RndCnstRvCoreIbexIbexKeyDefault - default: 0xec24df2d9b070658cb5b072bb74e79de + default: 0x8cd14c0f2e129d943abf68da18dbf422 randwidth: 128 } { @@ -3796,7 +3876,7 @@ randcount: 64 randtype: data name_top: RndCnstRvCoreIbexIbexNonceDefault - default: 0xa47a41863adaed04 + default: 0xa9ebb7ebaf19be85 randwidth: 64 } ] diff --git a/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson b/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson index 4f5a11908a6e7..6801195138b66 100644 --- a/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson +++ b/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson @@ -113,6 +113,11 @@ "0x94949494", "0x94949494", "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", ], }, { @@ -163,19 +168,19 @@ }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", - value: "0x18cbd487", + value: "0x363b8f75", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", - value: "0x7663f368", + value: "0x5893a89a", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", - value: "0x822817ed", + value: "0xacd84c1f", }, { name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", - value: "0xdc1d5bcc", + value: "0xf2ed003e", }, { name: "OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG", diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index 147c9a9d5a99e..95f6471ac9460 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv @@ -42,29 +42,34 @@ assign alert_if[34].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[1]; assign alert_if[35].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[2]; assign alert_if[36].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[3]; assign alert_if[37].alert_tx = `PD_MAIN_HIER.u_flash_ctrl.alert_tx_o[4]; -assign alert_if[38].alert_tx = `PD_MAIN_HIER.u_rv_dm.alert_tx_o[0]; -assign alert_if[39].alert_tx = `PD_MAIN_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[40].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[0]; -assign alert_if[41].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[1]; -assign alert_if[42].alert_tx = `PD_MAIN_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[43].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[44].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[1]; -assign alert_if[45].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[46].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[1]; -assign alert_if[47].alert_tx = `PD_MAIN_HIER.u_keymgr.alert_tx_o[0]; -assign alert_if[48].alert_tx = `PD_MAIN_HIER.u_keymgr.alert_tx_o[1]; -assign alert_if[49].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[0]; -assign alert_if[50].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[1]; -assign alert_if[51].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[52].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[1]; -assign alert_if[53].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[0]; -assign alert_if[54].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[1]; -assign alert_if[55].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[0]; -assign alert_if[56].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[1]; -assign alert_if[57].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[58].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_sec.alert_tx_o[0]; -assign alert_if[59].alert_tx = `PD_MAIN_HIER.u_rom_ctrl.alert_tx_o[0]; -assign alert_if[60].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[0]; -assign alert_if[61].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[1]; -assign alert_if[62].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[2]; -assign alert_if[63].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[3]; +assign alert_if[38].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[0]; +assign alert_if[39].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[1]; +assign alert_if[40].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[2]; +assign alert_if[41].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[3]; +assign alert_if[42].alert_tx = `PD_MAIN_HIER.u_rram_ctrl.alert_tx_o[4]; +assign alert_if[43].alert_tx = `PD_MAIN_HIER.u_rv_dm.alert_tx_o[0]; +assign alert_if[44].alert_tx = `PD_MAIN_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[45].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[0]; +assign alert_if[46].alert_tx = `PD_MAIN_HIER.u_aes.alert_tx_o[1]; +assign alert_if[47].alert_tx = `PD_MAIN_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[48].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[49].alert_tx = `PD_MAIN_HIER.u_kmac.alert_tx_o[1]; +assign alert_if[50].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[51].alert_tx = `PD_MAIN_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[52].alert_tx = `PD_MAIN_HIER.u_keymgr.alert_tx_o[0]; +assign alert_if[53].alert_tx = `PD_MAIN_HIER.u_keymgr.alert_tx_o[1]; +assign alert_if[54].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[55].alert_tx = `PD_MAIN_HIER.u_csrng.alert_tx_o[1]; +assign alert_if[56].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[57].alert_tx = `PD_MAIN_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[58].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[59].alert_tx = `PD_MAIN_HIER.u_edn0.alert_tx_o[1]; +assign alert_if[60].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[61].alert_tx = `PD_MAIN_HIER.u_edn1.alert_tx_o[1]; +assign alert_if[62].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[63].alert_tx = `PD_MAIN_HIER.u_sram_ctrl_sec.alert_tx_o[0]; +assign alert_if[64].alert_tx = `PD_MAIN_HIER.u_rom_ctrl.alert_tx_o[0]; +assign alert_if[65].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[0]; +assign alert_if[66].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[1]; +assign alert_if[67].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[2]; +assign alert_if[68].alert_tx = `PD_MAIN_HIER.u_rv_core_ibex.alert_tx_o[3]; diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index e677aa2d242a7..3e6b39b2e1a73 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv @@ -51,6 +51,9 @@ tl_if usbdev_tl_if(clk_usb, rst_n); tl_if flash_ctrl__core_tl_if(clk_main, rst_n); tl_if flash_ctrl__prim_tl_if(clk_main, rst_n); tl_if flash_ctrl__mem_tl_if(clk_main, rst_n); +tl_if rram_ctrl__core_tl_if(clk_main, rst_n); +tl_if rram_macro__prim_tl_if(clk_main, rst_n); +tl_if rram_ctrl__host_tl_if(clk_main, rst_n); tl_if hmac_tl_if(clk_main, rst_n); tl_if kmac_tl_if(clk_main, rst_n); tl_if aes_tl_if(clk_main, rst_n); @@ -133,6 +136,9 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl, main) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__prim, flash_ctrl, prim_tl, main) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__mem, flash_ctrl, mem_tl, main) + `DRIVE_CHIP_TL_DEVICE_IF(rram_ctrl__core, rram_ctrl, core_tl, main) + `DRIVE_CHIP_TL_DEVICE_IF(rram_macro__prim, rram_macro, prim_tl, main) + `DRIVE_CHIP_TL_DEVICE_IF(rram_ctrl__host, rram_ctrl, host_tl, main) `DRIVE_CHIP_TL_DEVICE_IF(hmac, hmac, tl, main) `DRIVE_CHIP_TL_DEVICE_IF(kmac, kmac, tl, main) `DRIVE_CHIP_TL_DEVICE_IF(aes, aes, tl, main) diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index 74d187b268fc2..80c728a3a60d9 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -37,6 +37,15 @@ tl_device_t xbar_devices[$] = '{ '{"flash_ctrl__mem", '{ '{32'h20000000, 32'h200fffff} }}, + '{"rram_ctrl__core", '{ + '{32'h41010000, 32'h410101ff} + }}, + '{"rram_macro__prim", '{ + '{32'h41018000, 32'h4101800f} + }}, + '{"rram_ctrl__host", '{ + '{32'h30000000, 32'h301fffff} + }}, '{"hmac", '{ '{32'h41110000, 32'h41111fff} }}, @@ -165,7 +174,8 @@ tl_host_t xbar_hosts[$] = '{ "rv_dm__mem", "sram_ctrl_main__ram", "sram_ctrl_sec__ram", - "flash_ctrl__mem"}} + "flash_ctrl__mem", + "rram_ctrl__host"}} , '{"rv_core_ibex__cored", 1, '{ "rom_ctrl__rom", @@ -205,6 +215,9 @@ tl_host_t xbar_hosts[$] = '{ "flash_ctrl__core", "flash_ctrl__prim", "flash_ctrl__mem", + "rram_ctrl__core", + "rram_ctrl__host", + "rram_macro__prim", "aes", "entropy_src", "csrng", @@ -257,6 +270,9 @@ tl_host_t xbar_hosts[$] = '{ "flash_ctrl__core", "flash_ctrl__prim", "flash_ctrl__mem", + "rram_ctrl__core", + "rram_ctrl__host", + "rram_macro__prim", "aes", "entropy_src", "csrng", diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 217defd51984f..badca9ecd0991 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -55,6 +55,16 @@ -node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[31:31] -node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[28:20] -node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[31:30] +-node tb.dut*.u_rram_ctrl core_tl_*i.a_address[15:9] +-node tb.dut*.u_rram_ctrl core_tl_*i.a_address[23:17] +-node tb.dut*.u_rram_ctrl core_tl_*i.a_address[29:25] +-node tb.dut*.u_rram_ctrl core_tl_*i.a_address[31:31] +-node tb.dut*.u_rram_macro prim_tl_*i.a_address[14:4] +-node tb.dut*.u_rram_macro prim_tl_*i.a_address[23:17] +-node tb.dut*.u_rram_macro prim_tl_*i.a_address[29:25] +-node tb.dut*.u_rram_macro prim_tl_*i.a_address[31:31] +-node tb.dut*.u_rram_ctrl host_tl_*i.a_address[27:21] +-node tb.dut*.u_rram_ctrl host_tl_*i.a_address[31:30] -node tb.dut*.u_hmac tl_*i.a_address[15:13] -node tb.dut*.u_hmac tl_*i.a_address[19:17] -node tb.dut*.u_hmac tl_*i.a_address[23:21] diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 794438be00ac6..9bc9ecc5de5e7 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv @@ -4,7 +4,7 @@ // Generated by topgen.py -parameter uint NUM_ALERTS = 64; +parameter uint NUM_ALERTS = 69; parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "uart0_fatal_fault", "uart1_fatal_fault", @@ -44,6 +44,11 @@ parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "flash_ctrl_fatal_err", "flash_ctrl_fatal_prim_flash_alert", "flash_ctrl_recov_prim_flash_alert", + "rram_ctrl_recov_err", + "rram_ctrl_fatal_std_err", + "rram_ctrl_fatal_err", + "rram_ctrl_fatal_macro_err", + "rram_ctrl_recov_macro_err", "rv_dm_fatal_fault", "rv_plic_fatal_fault", "aes_recov_ctrl_update_err", diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 98901f8d91410..60006133f4e1d 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -64,6 +64,7 @@ sram_ctrl_main.ram sram_ctrl_sec.ram flash_ctrl.mem + rram_ctrl.host ] rv_core_ibex.cored: [ @@ -80,6 +81,9 @@ flash_ctrl.core flash_ctrl.prim flash_ctrl.mem + rram_ctrl.core + rram_ctrl.host + rram_macro.prim aes entropy_src csrng @@ -109,6 +113,9 @@ flash_ctrl.core flash_ctrl.prim flash_ctrl.mem + rram_ctrl.core + rram_ctrl.host + rram_macro.prim aes entropy_src csrng @@ -414,6 +421,72 @@ stub: false pipeline: true } + { + name: rram_ctrl.core + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x41010000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rram_macro.prim + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rram_macro + addr_range: + [ + { + base_addrs: + { + hart: 0x41018000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rram_ctrl.host + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x200000 + } + ] + xbar: false + stub: false + pipeline: true + } { name: hmac type: device @@ -937,6 +1010,45 @@ top_signame: flash_ctrl_mem_tl index: -1 } + { + name: tl_rram_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_ctrl_core_tl + index: -1 + } + { + name: tl_rram_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_macro_prim_tl + index: -1 + } + { + name: tl_rram_ctrl__host + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + domain: Main + top_signame: rram_ctrl_host_tl + index: -1 + } { name: tl_hmac struct: tl diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 1876de9fe4917..b94aa132d8764 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson @@ -97,6 +97,24 @@ act: "req" package: "tlul_pkg" } + { struct: "tl" + type: "req_rsp" + name: "tl_rram_ctrl__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rram_macro__prim" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rram_ctrl__host" + act: "req" + package: "tlul_pkg" + } { struct: "tl" type: "req_rsp" name: "tl_hmac" diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 810c5d39511ea..1a50644fdc104 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -42,6 +42,9 @@ initial force dut.rst_spi_host1_ni = rst_n; `CONNECT_TL_DEVICE_IF(flash_ctrl__core, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(flash_ctrl__prim, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(flash_ctrl__mem, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rram_ctrl__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rram_macro__prim, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rram_ctrl__host, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(hmac, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(kmac, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(aes, dut, clk_main_i, rst_n) diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index 13ec6a771100d..7d10d5d4f8097 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -53,6 +53,16 @@ -node tb.dut tl_flash_ctrl__prim_o.a_address[31:31] -node tb.dut tl_flash_ctrl__mem_o.a_address[28:20] -node tb.dut tl_flash_ctrl__mem_o.a_address[31:30] +-node tb.dut tl_rram_ctrl__core_o.a_address[15:9] +-node tb.dut tl_rram_ctrl__core_o.a_address[23:17] +-node tb.dut tl_rram_ctrl__core_o.a_address[29:25] +-node tb.dut tl_rram_ctrl__core_o.a_address[31:31] +-node tb.dut tl_rram_macro__prim_o.a_address[14:4] +-node tb.dut tl_rram_macro__prim_o.a_address[23:17] +-node tb.dut tl_rram_macro__prim_o.a_address[29:25] +-node tb.dut tl_rram_macro__prim_o.a_address[31:31] +-node tb.dut tl_rram_ctrl__host_o.a_address[27:21] +-node tb.dut tl_rram_ctrl__host_o.a_address[31:30] -node tb.dut tl_hmac_o.a_address[15:13] -node tb.dut tl_hmac_o.a_address[19:17] -node tb.dut tl_hmac_o.a_address[23:21] diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index 8dabe927102b6..71c957f504753 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -41,6 +41,15 @@ tl_device_t xbar_devices[$] = '{ '{"flash_ctrl__mem", '{ '{32'h20000000, 32'h200fffff} }}, + '{"rram_ctrl__core", '{ + '{32'h41010000, 32'h410101ff} + }}, + '{"rram_macro__prim", '{ + '{32'h41018000, 32'h4101800f} + }}, + '{"rram_ctrl__host", '{ + '{32'h30000000, 32'h301fffff} + }}, '{"hmac", '{ '{32'h41110000, 32'h41111fff} }}, @@ -94,7 +103,8 @@ tl_host_t xbar_hosts[$] = '{ "rv_dm__mem", "sram_ctrl_main__ram", "sram_ctrl_sec__ram", - "flash_ctrl__mem"}} + "flash_ctrl__mem", + "rram_ctrl__host"}} , '{"rv_core_ibex__cored", 1, '{ "rom_ctrl__rom", @@ -110,6 +120,9 @@ tl_host_t xbar_hosts[$] = '{ "flash_ctrl__core", "flash_ctrl__prim", "flash_ctrl__mem", + "rram_ctrl__core", + "rram_ctrl__host", + "rram_macro__prim", "aes", "entropy_src", "csrng", @@ -138,6 +151,9 @@ tl_host_t xbar_hosts[$] = '{ "flash_ctrl__core", "flash_ctrl__prim", "flash_ctrl__mem", + "rram_ctrl__core", + "rram_ctrl__host", + "rram_macro__prim", "aes", "entropy_src", "csrng", diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index 48243299f36f4..35ef3362e8da1 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -92,6 +92,24 @@ module xbar_main_bind; .h2d (tl_flash_ctrl__mem_o), .d2h (tl_flash_ctrl__mem_i) ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rram_ctrl__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rram_ctrl__core_o), + .d2h (tl_rram_ctrl__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rram_macro__prim ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rram_macro__prim_o), + .d2h (tl_rram_macro__prim_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rram_ctrl__host ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rram_ctrl__host_o), + .d2h (tl_rram_ctrl__host_i) + ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_hmac ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index e417e0a8c3b78..28295597197bb 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -20,6 +20,9 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__CORE = 32'h 41000000; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__PRIM = 32'h 41008000; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__MEM = 32'h 20000000; + localparam logic [31:0] ADDR_SPACE_RRAM_CTRL__CORE = 32'h 41010000; + localparam logic [31:0] ADDR_SPACE_RRAM_MACRO__PRIM = 32'h 41018000; + localparam logic [31:0] ADDR_SPACE_RRAM_CTRL__HOST = 32'h 30000000; localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 41110000; localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 41120000; localparam logic [31:0] ADDR_SPACE_AES = 32'h 41100000; @@ -50,6 +53,9 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__CORE = 32'h 000001ff; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__PRIM = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__MEM = 32'h 000fffff; + localparam logic [31:0] ADDR_MASK_RRAM_CTRL__CORE = 32'h 000001ff; + localparam logic [31:0] ADDR_MASK_RRAM_MACRO__PRIM = 32'h 0000000f; + localparam logic [31:0] ADDR_MASK_RRAM_CTRL__HOST = 32'h 001fffff; localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00001fff; localparam logic [31:0] ADDR_MASK_KMAC = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_AES = 32'h 000000ff; @@ -67,7 +73,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_SEC__RAM = 32'h 0000ffff; localparam int N_HOST = 3; - localparam int N_DEVICE = 26; + localparam int N_DEVICE = 29; typedef enum int { TlRvDmRegs = 0, @@ -81,21 +87,24 @@ package tl_main_pkg; TlFlashCtrlCore = 8, TlFlashCtrlPrim = 9, TlFlashCtrlMem = 10, - TlHmac = 11, - TlKmac = 12, - TlAes = 13, - TlEntropySrc = 14, - TlCsrng = 15, - TlEdn0 = 16, - TlEdn1 = 17, - TlRvPlic = 18, - TlOtbn = 19, - TlKeymgr = 20, - TlRvCoreIbexCfg = 21, - TlSramCtrlMainRegs = 22, - TlSramCtrlMainRam = 23, - TlSramCtrlSecRegs = 24, - TlSramCtrlSecRam = 25 + TlRramCtrlCore = 11, + TlRramMacroPrim = 12, + TlRramCtrlHost = 13, + TlHmac = 14, + TlKmac = 15, + TlAes = 16, + TlEntropySrc = 17, + TlCsrng = 18, + TlEdn0 = 19, + TlEdn1 = 20, + TlRvPlic = 21, + TlOtbn = 22, + TlKeymgr = 23, + TlRvCoreIbexCfg = 24, + TlSramCtrlMainRegs = 25, + TlSramCtrlMainRam = 26, + TlSramCtrlSecRegs = 27, + TlSramCtrlSecRam = 28 } tl_device_e; typedef enum int { diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index 58d63e5ccd943..337df4e0c0659 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -7,132 +7,146 @@ // // Interconnect // rv_core_ibex.corei -// -> s1n_29 -// -> sm1_30 +// -> s1n_32 +// -> sm1_33 // -> rom_ctrl.rom -// -> sm1_31 +// -> sm1_34 // -> rv_dm.mem -// -> sm1_32 +// -> sm1_35 // -> sram_ctrl_main.ram -// -> sm1_33 +// -> sm1_36 // -> sram_ctrl_sec.ram -// -> sm1_34 +// -> sm1_37 // -> flash_ctrl.mem +// -> sm1_38 +// -> rram_ctrl.host // rv_core_ibex.cored -// -> s1n_35 -// -> sm1_30 +// -> s1n_39 +// -> sm1_33 // -> rom_ctrl.rom -// -> sm1_36 +// -> sm1_40 // -> rom_ctrl.regs -// -> sm1_31 +// -> sm1_34 // -> rv_dm.mem -// -> sm1_37 +// -> sm1_41 // -> rv_dm.regs -// -> sm1_32 +// -> sm1_35 // -> sram_ctrl_main.ram -// -> sm1_33 +// -> sm1_36 // -> sram_ctrl_sec.ram -// -> sm1_39 -// -> asf_38 -// -> peri -// -> sm1_41 -// -> asf_40 -// -> spi_host0 // -> sm1_43 // -> asf_42 -// -> spi_host1 +// -> peri // -> sm1_45 // -> asf_44 +// -> spi_host0 +// -> sm1_47 +// -> asf_46 +// -> spi_host1 +// -> sm1_49 +// -> asf_48 // -> usbdev -// -> sm1_46 +// -> sm1_50 // -> flash_ctrl.core -// -> sm1_47 +// -> sm1_51 // -> flash_ctrl.prim -// -> sm1_34 +// -> sm1_37 // -> flash_ctrl.mem -// -> sm1_48 +// -> sm1_52 +// -> rram_ctrl.core +// -> sm1_38 +// -> rram_ctrl.host +// -> sm1_53 +// -> rram_macro.prim +// -> sm1_54 // -> aes -// -> sm1_49 +// -> sm1_55 // -> entropy_src -// -> sm1_50 +// -> sm1_56 // -> csrng -// -> sm1_51 +// -> sm1_57 // -> edn0 -// -> sm1_52 +// -> sm1_58 // -> edn1 -// -> sm1_53 +// -> sm1_59 // -> hmac -// -> sm1_54 +// -> sm1_60 // -> rv_plic -// -> sm1_55 +// -> sm1_61 // -> otbn -// -> sm1_56 +// -> sm1_62 // -> keymgr -// -> sm1_57 +// -> sm1_63 // -> kmac -// -> sm1_58 +// -> sm1_64 // -> sram_ctrl_main.regs -// -> sm1_59 +// -> sm1_65 // -> sram_ctrl_sec.regs -// -> sm1_60 +// -> sm1_66 // -> rv_core_ibex.cfg // rv_dm.sba -// -> s1n_61 -// -> sm1_30 +// -> s1n_67 +// -> sm1_33 // -> rom_ctrl.rom -// -> sm1_36 +// -> sm1_40 // -> rom_ctrl.regs -// -> sm1_31 +// -> sm1_34 // -> rv_dm.mem -// -> sm1_37 +// -> sm1_41 // -> rv_dm.regs -// -> sm1_32 +// -> sm1_35 // -> sram_ctrl_main.ram -// -> sm1_33 +// -> sm1_36 // -> sram_ctrl_sec.ram -// -> sm1_39 -// -> asf_38 -// -> peri -// -> sm1_41 -// -> asf_40 -// -> spi_host0 // -> sm1_43 // -> asf_42 -// -> spi_host1 +// -> peri // -> sm1_45 // -> asf_44 +// -> spi_host0 +// -> sm1_47 +// -> asf_46 +// -> spi_host1 +// -> sm1_49 +// -> asf_48 // -> usbdev -// -> sm1_46 +// -> sm1_50 // -> flash_ctrl.core -// -> sm1_47 +// -> sm1_51 // -> flash_ctrl.prim -// -> sm1_34 +// -> sm1_37 // -> flash_ctrl.mem -// -> sm1_48 +// -> sm1_52 +// -> rram_ctrl.core +// -> sm1_38 +// -> rram_ctrl.host +// -> sm1_53 +// -> rram_macro.prim +// -> sm1_54 // -> aes -// -> sm1_49 +// -> sm1_55 // -> entropy_src -// -> sm1_50 +// -> sm1_56 // -> csrng -// -> sm1_51 +// -> sm1_57 // -> edn0 -// -> sm1_52 +// -> sm1_58 // -> edn1 -// -> sm1_53 +// -> sm1_59 // -> hmac -// -> sm1_54 +// -> sm1_60 // -> rv_plic -// -> sm1_55 +// -> sm1_61 // -> otbn -// -> sm1_56 +// -> sm1_62 // -> keymgr -// -> sm1_57 +// -> sm1_63 // -> kmac -// -> sm1_58 +// -> sm1_64 // -> sram_ctrl_main.regs -// -> sm1_59 +// -> sm1_65 // -> sram_ctrl_sec.regs -// -> sm1_60 +// -> sm1_66 // -> rv_core_ibex.cfg module xbar_main ( @@ -178,6 +192,12 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_flash_ctrl__prim_i, output tlul_pkg::tl_h2d_t tl_flash_ctrl__mem_o, input tlul_pkg::tl_d2h_t tl_flash_ctrl__mem_i, + output tlul_pkg::tl_h2d_t tl_rram_ctrl__core_o, + input tlul_pkg::tl_d2h_t tl_rram_ctrl__core_i, + output tlul_pkg::tl_h2d_t tl_rram_macro__prim_o, + input tlul_pkg::tl_d2h_t tl_rram_macro__prim_i, + output tlul_pkg::tl_h2d_t tl_rram_ctrl__host_o, + input tlul_pkg::tl_d2h_t tl_rram_ctrl__host_i, output tlul_pkg::tl_h2d_t tl_hmac_o, input tlul_pkg::tl_d2h_t tl_hmac_i, output tlul_pkg::tl_h2d_t tl_kmac_o, @@ -220,36 +240,15 @@ module xbar_main ( logic unused_scanmode; assign unused_scanmode = ^scanmode_i; - tl_h2d_t tl_s1n_29_us_h2d ; - tl_d2h_t tl_s1n_29_us_d2h ; + tl_h2d_t tl_s1n_32_us_h2d ; + tl_d2h_t tl_s1n_32_us_d2h ; - tl_h2d_t tl_s1n_29_ds_h2d [5]; - tl_d2h_t tl_s1n_29_ds_d2h [5]; + tl_h2d_t tl_s1n_32_ds_h2d [6]; + tl_d2h_t tl_s1n_32_ds_d2h [6]; // Create steering signal - logic [2:0] dev_sel_s1n_29; - - - tl_h2d_t tl_sm1_30_us_h2d [3]; - tl_d2h_t tl_sm1_30_us_d2h [3]; - - tl_h2d_t tl_sm1_30_ds_h2d ; - tl_d2h_t tl_sm1_30_ds_d2h ; - - - tl_h2d_t tl_sm1_31_us_h2d [3]; - tl_d2h_t tl_sm1_31_us_d2h [3]; - - tl_h2d_t tl_sm1_31_ds_h2d ; - tl_d2h_t tl_sm1_31_ds_d2h ; - - - tl_h2d_t tl_sm1_32_us_h2d [3]; - tl_d2h_t tl_sm1_32_us_d2h [3]; - - tl_h2d_t tl_sm1_32_ds_h2d ; - tl_d2h_t tl_sm1_32_ds_d2h ; + logic [2:0] dev_sel_s1n_32; tl_h2d_t tl_sm1_33_us_h2d [3]; @@ -265,46 +264,50 @@ module xbar_main ( tl_h2d_t tl_sm1_34_ds_h2d ; tl_d2h_t tl_sm1_34_ds_d2h ; - tl_h2d_t tl_s1n_35_us_h2d ; - tl_d2h_t tl_s1n_35_us_d2h ; + tl_h2d_t tl_sm1_35_us_h2d [3]; + tl_d2h_t tl_sm1_35_us_d2h [3]; - tl_h2d_t tl_s1n_35_ds_h2d [26]; - tl_d2h_t tl_s1n_35_ds_d2h [26]; - - // Create steering signal - logic [4:0] dev_sel_s1n_35; + tl_h2d_t tl_sm1_35_ds_h2d ; + tl_d2h_t tl_sm1_35_ds_d2h ; - tl_h2d_t tl_sm1_36_us_h2d [2]; - tl_d2h_t tl_sm1_36_us_d2h [2]; + tl_h2d_t tl_sm1_36_us_h2d [3]; + tl_d2h_t tl_sm1_36_us_d2h [3]; tl_h2d_t tl_sm1_36_ds_h2d ; tl_d2h_t tl_sm1_36_ds_d2h ; - tl_h2d_t tl_sm1_37_us_h2d [2]; - tl_d2h_t tl_sm1_37_us_d2h [2]; + tl_h2d_t tl_sm1_37_us_h2d [3]; + tl_d2h_t tl_sm1_37_us_d2h [3]; tl_h2d_t tl_sm1_37_ds_h2d ; tl_d2h_t tl_sm1_37_ds_d2h ; - tl_h2d_t tl_asf_38_us_h2d ; - tl_d2h_t tl_asf_38_us_d2h ; - tl_h2d_t tl_asf_38_ds_h2d ; - tl_d2h_t tl_asf_38_ds_d2h ; + tl_h2d_t tl_sm1_38_us_h2d [3]; + tl_d2h_t tl_sm1_38_us_d2h [3]; + + tl_h2d_t tl_sm1_38_ds_h2d ; + tl_d2h_t tl_sm1_38_ds_d2h ; - tl_h2d_t tl_sm1_39_us_h2d [2]; - tl_d2h_t tl_sm1_39_us_d2h [2]; + tl_h2d_t tl_s1n_39_us_h2d ; + tl_d2h_t tl_s1n_39_us_d2h ; - tl_h2d_t tl_sm1_39_ds_h2d ; - tl_d2h_t tl_sm1_39_ds_d2h ; - tl_h2d_t tl_asf_40_us_h2d ; - tl_d2h_t tl_asf_40_us_d2h ; - tl_h2d_t tl_asf_40_ds_h2d ; - tl_d2h_t tl_asf_40_ds_d2h ; + tl_h2d_t tl_s1n_39_ds_h2d [29]; + tl_d2h_t tl_s1n_39_ds_d2h [29]; + + // Create steering signal + logic [4:0] dev_sel_s1n_39; + + + tl_h2d_t tl_sm1_40_us_h2d [2]; + tl_d2h_t tl_sm1_40_us_d2h [2]; + + tl_h2d_t tl_sm1_40_ds_h2d ; + tl_d2h_t tl_sm1_40_ds_d2h ; tl_h2d_t tl_sm1_41_us_h2d [2]; @@ -337,12 +340,10 @@ module xbar_main ( tl_h2d_t tl_sm1_45_ds_h2d ; tl_d2h_t tl_sm1_45_ds_d2h ; - - tl_h2d_t tl_sm1_46_us_h2d [2]; - tl_d2h_t tl_sm1_46_us_d2h [2]; - - tl_h2d_t tl_sm1_46_ds_h2d ; - tl_d2h_t tl_sm1_46_ds_d2h ; + tl_h2d_t tl_asf_46_us_h2d ; + tl_d2h_t tl_asf_46_us_d2h ; + tl_h2d_t tl_asf_46_ds_h2d ; + tl_d2h_t tl_asf_46_ds_d2h ; tl_h2d_t tl_sm1_47_us_h2d [2]; @@ -351,12 +352,10 @@ module xbar_main ( tl_h2d_t tl_sm1_47_ds_h2d ; tl_d2h_t tl_sm1_47_ds_d2h ; - - tl_h2d_t tl_sm1_48_us_h2d [2]; - tl_d2h_t tl_sm1_48_us_d2h [2]; - - tl_h2d_t tl_sm1_48_ds_h2d ; - tl_d2h_t tl_sm1_48_ds_d2h ; + tl_h2d_t tl_asf_48_us_h2d ; + tl_d2h_t tl_asf_48_us_d2h ; + tl_h2d_t tl_asf_48_ds_h2d ; + tl_d2h_t tl_asf_48_ds_d2h ; tl_h2d_t tl_sm1_49_us_h2d [2]; @@ -442,532 +441,632 @@ module xbar_main ( tl_h2d_t tl_sm1_60_ds_h2d ; tl_d2h_t tl_sm1_60_ds_d2h ; - tl_h2d_t tl_s1n_61_us_h2d ; - tl_d2h_t tl_s1n_61_us_d2h ; + tl_h2d_t tl_sm1_61_us_h2d [2]; + tl_d2h_t tl_sm1_61_us_d2h [2]; + + tl_h2d_t tl_sm1_61_ds_h2d ; + tl_d2h_t tl_sm1_61_ds_d2h ; + + + tl_h2d_t tl_sm1_62_us_h2d [2]; + tl_d2h_t tl_sm1_62_us_d2h [2]; + + tl_h2d_t tl_sm1_62_ds_h2d ; + tl_d2h_t tl_sm1_62_ds_d2h ; + + + tl_h2d_t tl_sm1_63_us_h2d [2]; + tl_d2h_t tl_sm1_63_us_d2h [2]; + + tl_h2d_t tl_sm1_63_ds_h2d ; + tl_d2h_t tl_sm1_63_ds_d2h ; + + + tl_h2d_t tl_sm1_64_us_h2d [2]; + tl_d2h_t tl_sm1_64_us_d2h [2]; + + tl_h2d_t tl_sm1_64_ds_h2d ; + tl_d2h_t tl_sm1_64_ds_d2h ; + + + tl_h2d_t tl_sm1_65_us_h2d [2]; + tl_d2h_t tl_sm1_65_us_d2h [2]; + + tl_h2d_t tl_sm1_65_ds_h2d ; + tl_d2h_t tl_sm1_65_ds_d2h ; - tl_h2d_t tl_s1n_61_ds_h2d [26]; - tl_d2h_t tl_s1n_61_ds_d2h [26]; + + tl_h2d_t tl_sm1_66_us_h2d [2]; + tl_d2h_t tl_sm1_66_us_d2h [2]; + + tl_h2d_t tl_sm1_66_ds_h2d ; + tl_d2h_t tl_sm1_66_ds_d2h ; + + tl_h2d_t tl_s1n_67_us_h2d ; + tl_d2h_t tl_s1n_67_us_d2h ; + + + tl_h2d_t tl_s1n_67_ds_h2d [29]; + tl_d2h_t tl_s1n_67_ds_d2h [29]; // Create steering signal - logic [4:0] dev_sel_s1n_61; + logic [4:0] dev_sel_s1n_67; + + assign tl_sm1_33_us_h2d[0] = tl_s1n_32_ds_h2d[0]; + assign tl_s1n_32_ds_d2h[0] = tl_sm1_33_us_d2h[0]; - assign tl_sm1_30_us_h2d[0] = tl_s1n_29_ds_h2d[0]; - assign tl_s1n_29_ds_d2h[0] = tl_sm1_30_us_d2h[0]; + assign tl_sm1_34_us_h2d[0] = tl_s1n_32_ds_h2d[1]; + assign tl_s1n_32_ds_d2h[1] = tl_sm1_34_us_d2h[0]; - assign tl_sm1_31_us_h2d[0] = tl_s1n_29_ds_h2d[1]; - assign tl_s1n_29_ds_d2h[1] = tl_sm1_31_us_d2h[0]; + assign tl_sm1_35_us_h2d[0] = tl_s1n_32_ds_h2d[2]; + assign tl_s1n_32_ds_d2h[2] = tl_sm1_35_us_d2h[0]; - assign tl_sm1_32_us_h2d[0] = tl_s1n_29_ds_h2d[2]; - assign tl_s1n_29_ds_d2h[2] = tl_sm1_32_us_d2h[0]; + assign tl_sm1_36_us_h2d[0] = tl_s1n_32_ds_h2d[3]; + assign tl_s1n_32_ds_d2h[3] = tl_sm1_36_us_d2h[0]; - assign tl_sm1_33_us_h2d[0] = tl_s1n_29_ds_h2d[3]; - assign tl_s1n_29_ds_d2h[3] = tl_sm1_33_us_d2h[0]; + assign tl_sm1_37_us_h2d[0] = tl_s1n_32_ds_h2d[4]; + assign tl_s1n_32_ds_d2h[4] = tl_sm1_37_us_d2h[0]; - assign tl_sm1_34_us_h2d[0] = tl_s1n_29_ds_h2d[4]; - assign tl_s1n_29_ds_d2h[4] = tl_sm1_34_us_d2h[0]; + assign tl_sm1_38_us_h2d[0] = tl_s1n_32_ds_h2d[5]; + assign tl_s1n_32_ds_d2h[5] = tl_sm1_38_us_d2h[0]; - assign tl_sm1_30_us_h2d[1] = tl_s1n_35_ds_h2d[0]; - assign tl_s1n_35_ds_d2h[0] = tl_sm1_30_us_d2h[1]; + assign tl_sm1_33_us_h2d[1] = tl_s1n_39_ds_h2d[0]; + assign tl_s1n_39_ds_d2h[0] = tl_sm1_33_us_d2h[1]; - assign tl_sm1_36_us_h2d[0] = tl_s1n_35_ds_h2d[1]; - assign tl_s1n_35_ds_d2h[1] = tl_sm1_36_us_d2h[0]; + assign tl_sm1_40_us_h2d[0] = tl_s1n_39_ds_h2d[1]; + assign tl_s1n_39_ds_d2h[1] = tl_sm1_40_us_d2h[0]; - assign tl_sm1_31_us_h2d[1] = tl_s1n_35_ds_h2d[2]; - assign tl_s1n_35_ds_d2h[2] = tl_sm1_31_us_d2h[1]; + assign tl_sm1_34_us_h2d[1] = tl_s1n_39_ds_h2d[2]; + assign tl_s1n_39_ds_d2h[2] = tl_sm1_34_us_d2h[1]; - assign tl_sm1_37_us_h2d[0] = tl_s1n_35_ds_h2d[3]; - assign tl_s1n_35_ds_d2h[3] = tl_sm1_37_us_d2h[0]; + assign tl_sm1_41_us_h2d[0] = tl_s1n_39_ds_h2d[3]; + assign tl_s1n_39_ds_d2h[3] = tl_sm1_41_us_d2h[0]; - assign tl_sm1_32_us_h2d[1] = tl_s1n_35_ds_h2d[4]; - assign tl_s1n_35_ds_d2h[4] = tl_sm1_32_us_d2h[1]; + assign tl_sm1_35_us_h2d[1] = tl_s1n_39_ds_h2d[4]; + assign tl_s1n_39_ds_d2h[4] = tl_sm1_35_us_d2h[1]; - assign tl_sm1_33_us_h2d[1] = tl_s1n_35_ds_h2d[5]; - assign tl_s1n_35_ds_d2h[5] = tl_sm1_33_us_d2h[1]; + assign tl_sm1_36_us_h2d[1] = tl_s1n_39_ds_h2d[5]; + assign tl_s1n_39_ds_d2h[5] = tl_sm1_36_us_d2h[1]; - assign tl_sm1_39_us_h2d[0] = tl_s1n_35_ds_h2d[6]; - assign tl_s1n_35_ds_d2h[6] = tl_sm1_39_us_d2h[0]; + assign tl_sm1_43_us_h2d[0] = tl_s1n_39_ds_h2d[6]; + assign tl_s1n_39_ds_d2h[6] = tl_sm1_43_us_d2h[0]; - assign tl_sm1_41_us_h2d[0] = tl_s1n_35_ds_h2d[7]; - assign tl_s1n_35_ds_d2h[7] = tl_sm1_41_us_d2h[0]; + assign tl_sm1_45_us_h2d[0] = tl_s1n_39_ds_h2d[7]; + assign tl_s1n_39_ds_d2h[7] = tl_sm1_45_us_d2h[0]; - assign tl_sm1_43_us_h2d[0] = tl_s1n_35_ds_h2d[8]; - assign tl_s1n_35_ds_d2h[8] = tl_sm1_43_us_d2h[0]; + assign tl_sm1_47_us_h2d[0] = tl_s1n_39_ds_h2d[8]; + assign tl_s1n_39_ds_d2h[8] = tl_sm1_47_us_d2h[0]; - assign tl_sm1_45_us_h2d[0] = tl_s1n_35_ds_h2d[9]; - assign tl_s1n_35_ds_d2h[9] = tl_sm1_45_us_d2h[0]; + assign tl_sm1_49_us_h2d[0] = tl_s1n_39_ds_h2d[9]; + assign tl_s1n_39_ds_d2h[9] = tl_sm1_49_us_d2h[0]; - assign tl_sm1_46_us_h2d[0] = tl_s1n_35_ds_h2d[10]; - assign tl_s1n_35_ds_d2h[10] = tl_sm1_46_us_d2h[0]; + assign tl_sm1_50_us_h2d[0] = tl_s1n_39_ds_h2d[10]; + assign tl_s1n_39_ds_d2h[10] = tl_sm1_50_us_d2h[0]; - assign tl_sm1_47_us_h2d[0] = tl_s1n_35_ds_h2d[11]; - assign tl_s1n_35_ds_d2h[11] = tl_sm1_47_us_d2h[0]; + assign tl_sm1_51_us_h2d[0] = tl_s1n_39_ds_h2d[11]; + assign tl_s1n_39_ds_d2h[11] = tl_sm1_51_us_d2h[0]; - assign tl_sm1_34_us_h2d[1] = tl_s1n_35_ds_h2d[12]; - assign tl_s1n_35_ds_d2h[12] = tl_sm1_34_us_d2h[1]; + assign tl_sm1_37_us_h2d[1] = tl_s1n_39_ds_h2d[12]; + assign tl_s1n_39_ds_d2h[12] = tl_sm1_37_us_d2h[1]; - assign tl_sm1_48_us_h2d[0] = tl_s1n_35_ds_h2d[13]; - assign tl_s1n_35_ds_d2h[13] = tl_sm1_48_us_d2h[0]; + assign tl_sm1_52_us_h2d[0] = tl_s1n_39_ds_h2d[13]; + assign tl_s1n_39_ds_d2h[13] = tl_sm1_52_us_d2h[0]; - assign tl_sm1_49_us_h2d[0] = tl_s1n_35_ds_h2d[14]; - assign tl_s1n_35_ds_d2h[14] = tl_sm1_49_us_d2h[0]; + assign tl_sm1_38_us_h2d[1] = tl_s1n_39_ds_h2d[14]; + assign tl_s1n_39_ds_d2h[14] = tl_sm1_38_us_d2h[1]; - assign tl_sm1_50_us_h2d[0] = tl_s1n_35_ds_h2d[15]; - assign tl_s1n_35_ds_d2h[15] = tl_sm1_50_us_d2h[0]; + assign tl_sm1_53_us_h2d[0] = tl_s1n_39_ds_h2d[15]; + assign tl_s1n_39_ds_d2h[15] = tl_sm1_53_us_d2h[0]; - assign tl_sm1_51_us_h2d[0] = tl_s1n_35_ds_h2d[16]; - assign tl_s1n_35_ds_d2h[16] = tl_sm1_51_us_d2h[0]; + assign tl_sm1_54_us_h2d[0] = tl_s1n_39_ds_h2d[16]; + assign tl_s1n_39_ds_d2h[16] = tl_sm1_54_us_d2h[0]; - assign tl_sm1_52_us_h2d[0] = tl_s1n_35_ds_h2d[17]; - assign tl_s1n_35_ds_d2h[17] = tl_sm1_52_us_d2h[0]; + assign tl_sm1_55_us_h2d[0] = tl_s1n_39_ds_h2d[17]; + assign tl_s1n_39_ds_d2h[17] = tl_sm1_55_us_d2h[0]; - assign tl_sm1_53_us_h2d[0] = tl_s1n_35_ds_h2d[18]; - assign tl_s1n_35_ds_d2h[18] = tl_sm1_53_us_d2h[0]; + assign tl_sm1_56_us_h2d[0] = tl_s1n_39_ds_h2d[18]; + assign tl_s1n_39_ds_d2h[18] = tl_sm1_56_us_d2h[0]; - assign tl_sm1_54_us_h2d[0] = tl_s1n_35_ds_h2d[19]; - assign tl_s1n_35_ds_d2h[19] = tl_sm1_54_us_d2h[0]; + assign tl_sm1_57_us_h2d[0] = tl_s1n_39_ds_h2d[19]; + assign tl_s1n_39_ds_d2h[19] = tl_sm1_57_us_d2h[0]; - assign tl_sm1_55_us_h2d[0] = tl_s1n_35_ds_h2d[20]; - assign tl_s1n_35_ds_d2h[20] = tl_sm1_55_us_d2h[0]; + assign tl_sm1_58_us_h2d[0] = tl_s1n_39_ds_h2d[20]; + assign tl_s1n_39_ds_d2h[20] = tl_sm1_58_us_d2h[0]; - assign tl_sm1_56_us_h2d[0] = tl_s1n_35_ds_h2d[21]; - assign tl_s1n_35_ds_d2h[21] = tl_sm1_56_us_d2h[0]; + assign tl_sm1_59_us_h2d[0] = tl_s1n_39_ds_h2d[21]; + assign tl_s1n_39_ds_d2h[21] = tl_sm1_59_us_d2h[0]; - assign tl_sm1_57_us_h2d[0] = tl_s1n_35_ds_h2d[22]; - assign tl_s1n_35_ds_d2h[22] = tl_sm1_57_us_d2h[0]; + assign tl_sm1_60_us_h2d[0] = tl_s1n_39_ds_h2d[22]; + assign tl_s1n_39_ds_d2h[22] = tl_sm1_60_us_d2h[0]; - assign tl_sm1_58_us_h2d[0] = tl_s1n_35_ds_h2d[23]; - assign tl_s1n_35_ds_d2h[23] = tl_sm1_58_us_d2h[0]; + assign tl_sm1_61_us_h2d[0] = tl_s1n_39_ds_h2d[23]; + assign tl_s1n_39_ds_d2h[23] = tl_sm1_61_us_d2h[0]; - assign tl_sm1_59_us_h2d[0] = tl_s1n_35_ds_h2d[24]; - assign tl_s1n_35_ds_d2h[24] = tl_sm1_59_us_d2h[0]; + assign tl_sm1_62_us_h2d[0] = tl_s1n_39_ds_h2d[24]; + assign tl_s1n_39_ds_d2h[24] = tl_sm1_62_us_d2h[0]; - assign tl_sm1_60_us_h2d[0] = tl_s1n_35_ds_h2d[25]; - assign tl_s1n_35_ds_d2h[25] = tl_sm1_60_us_d2h[0]; + assign tl_sm1_63_us_h2d[0] = tl_s1n_39_ds_h2d[25]; + assign tl_s1n_39_ds_d2h[25] = tl_sm1_63_us_d2h[0]; - assign tl_sm1_30_us_h2d[2] = tl_s1n_61_ds_h2d[0]; - assign tl_s1n_61_ds_d2h[0] = tl_sm1_30_us_d2h[2]; + assign tl_sm1_64_us_h2d[0] = tl_s1n_39_ds_h2d[26]; + assign tl_s1n_39_ds_d2h[26] = tl_sm1_64_us_d2h[0]; - assign tl_sm1_36_us_h2d[1] = tl_s1n_61_ds_h2d[1]; - assign tl_s1n_61_ds_d2h[1] = tl_sm1_36_us_d2h[1]; + assign tl_sm1_65_us_h2d[0] = tl_s1n_39_ds_h2d[27]; + assign tl_s1n_39_ds_d2h[27] = tl_sm1_65_us_d2h[0]; - assign tl_sm1_31_us_h2d[2] = tl_s1n_61_ds_h2d[2]; - assign tl_s1n_61_ds_d2h[2] = tl_sm1_31_us_d2h[2]; + assign tl_sm1_66_us_h2d[0] = tl_s1n_39_ds_h2d[28]; + assign tl_s1n_39_ds_d2h[28] = tl_sm1_66_us_d2h[0]; - assign tl_sm1_37_us_h2d[1] = tl_s1n_61_ds_h2d[3]; - assign tl_s1n_61_ds_d2h[3] = tl_sm1_37_us_d2h[1]; + assign tl_sm1_33_us_h2d[2] = tl_s1n_67_ds_h2d[0]; + assign tl_s1n_67_ds_d2h[0] = tl_sm1_33_us_d2h[2]; - assign tl_sm1_32_us_h2d[2] = tl_s1n_61_ds_h2d[4]; - assign tl_s1n_61_ds_d2h[4] = tl_sm1_32_us_d2h[2]; + assign tl_sm1_40_us_h2d[1] = tl_s1n_67_ds_h2d[1]; + assign tl_s1n_67_ds_d2h[1] = tl_sm1_40_us_d2h[1]; - assign tl_sm1_33_us_h2d[2] = tl_s1n_61_ds_h2d[5]; - assign tl_s1n_61_ds_d2h[5] = tl_sm1_33_us_d2h[2]; + assign tl_sm1_34_us_h2d[2] = tl_s1n_67_ds_h2d[2]; + assign tl_s1n_67_ds_d2h[2] = tl_sm1_34_us_d2h[2]; - assign tl_sm1_39_us_h2d[1] = tl_s1n_61_ds_h2d[6]; - assign tl_s1n_61_ds_d2h[6] = tl_sm1_39_us_d2h[1]; + assign tl_sm1_41_us_h2d[1] = tl_s1n_67_ds_h2d[3]; + assign tl_s1n_67_ds_d2h[3] = tl_sm1_41_us_d2h[1]; - assign tl_sm1_41_us_h2d[1] = tl_s1n_61_ds_h2d[7]; - assign tl_s1n_61_ds_d2h[7] = tl_sm1_41_us_d2h[1]; + assign tl_sm1_35_us_h2d[2] = tl_s1n_67_ds_h2d[4]; + assign tl_s1n_67_ds_d2h[4] = tl_sm1_35_us_d2h[2]; - assign tl_sm1_43_us_h2d[1] = tl_s1n_61_ds_h2d[8]; - assign tl_s1n_61_ds_d2h[8] = tl_sm1_43_us_d2h[1]; + assign tl_sm1_36_us_h2d[2] = tl_s1n_67_ds_h2d[5]; + assign tl_s1n_67_ds_d2h[5] = tl_sm1_36_us_d2h[2]; - assign tl_sm1_45_us_h2d[1] = tl_s1n_61_ds_h2d[9]; - assign tl_s1n_61_ds_d2h[9] = tl_sm1_45_us_d2h[1]; + assign tl_sm1_43_us_h2d[1] = tl_s1n_67_ds_h2d[6]; + assign tl_s1n_67_ds_d2h[6] = tl_sm1_43_us_d2h[1]; - assign tl_sm1_46_us_h2d[1] = tl_s1n_61_ds_h2d[10]; - assign tl_s1n_61_ds_d2h[10] = tl_sm1_46_us_d2h[1]; + assign tl_sm1_45_us_h2d[1] = tl_s1n_67_ds_h2d[7]; + assign tl_s1n_67_ds_d2h[7] = tl_sm1_45_us_d2h[1]; - assign tl_sm1_47_us_h2d[1] = tl_s1n_61_ds_h2d[11]; - assign tl_s1n_61_ds_d2h[11] = tl_sm1_47_us_d2h[1]; + assign tl_sm1_47_us_h2d[1] = tl_s1n_67_ds_h2d[8]; + assign tl_s1n_67_ds_d2h[8] = tl_sm1_47_us_d2h[1]; - assign tl_sm1_34_us_h2d[2] = tl_s1n_61_ds_h2d[12]; - assign tl_s1n_61_ds_d2h[12] = tl_sm1_34_us_d2h[2]; + assign tl_sm1_49_us_h2d[1] = tl_s1n_67_ds_h2d[9]; + assign tl_s1n_67_ds_d2h[9] = tl_sm1_49_us_d2h[1]; - assign tl_sm1_48_us_h2d[1] = tl_s1n_61_ds_h2d[13]; - assign tl_s1n_61_ds_d2h[13] = tl_sm1_48_us_d2h[1]; + assign tl_sm1_50_us_h2d[1] = tl_s1n_67_ds_h2d[10]; + assign tl_s1n_67_ds_d2h[10] = tl_sm1_50_us_d2h[1]; - assign tl_sm1_49_us_h2d[1] = tl_s1n_61_ds_h2d[14]; - assign tl_s1n_61_ds_d2h[14] = tl_sm1_49_us_d2h[1]; + assign tl_sm1_51_us_h2d[1] = tl_s1n_67_ds_h2d[11]; + assign tl_s1n_67_ds_d2h[11] = tl_sm1_51_us_d2h[1]; - assign tl_sm1_50_us_h2d[1] = tl_s1n_61_ds_h2d[15]; - assign tl_s1n_61_ds_d2h[15] = tl_sm1_50_us_d2h[1]; + assign tl_sm1_37_us_h2d[2] = tl_s1n_67_ds_h2d[12]; + assign tl_s1n_67_ds_d2h[12] = tl_sm1_37_us_d2h[2]; - assign tl_sm1_51_us_h2d[1] = tl_s1n_61_ds_h2d[16]; - assign tl_s1n_61_ds_d2h[16] = tl_sm1_51_us_d2h[1]; + assign tl_sm1_52_us_h2d[1] = tl_s1n_67_ds_h2d[13]; + assign tl_s1n_67_ds_d2h[13] = tl_sm1_52_us_d2h[1]; - assign tl_sm1_52_us_h2d[1] = tl_s1n_61_ds_h2d[17]; - assign tl_s1n_61_ds_d2h[17] = tl_sm1_52_us_d2h[1]; + assign tl_sm1_38_us_h2d[2] = tl_s1n_67_ds_h2d[14]; + assign tl_s1n_67_ds_d2h[14] = tl_sm1_38_us_d2h[2]; - assign tl_sm1_53_us_h2d[1] = tl_s1n_61_ds_h2d[18]; - assign tl_s1n_61_ds_d2h[18] = tl_sm1_53_us_d2h[1]; + assign tl_sm1_53_us_h2d[1] = tl_s1n_67_ds_h2d[15]; + assign tl_s1n_67_ds_d2h[15] = tl_sm1_53_us_d2h[1]; - assign tl_sm1_54_us_h2d[1] = tl_s1n_61_ds_h2d[19]; - assign tl_s1n_61_ds_d2h[19] = tl_sm1_54_us_d2h[1]; + assign tl_sm1_54_us_h2d[1] = tl_s1n_67_ds_h2d[16]; + assign tl_s1n_67_ds_d2h[16] = tl_sm1_54_us_d2h[1]; - assign tl_sm1_55_us_h2d[1] = tl_s1n_61_ds_h2d[20]; - assign tl_s1n_61_ds_d2h[20] = tl_sm1_55_us_d2h[1]; + assign tl_sm1_55_us_h2d[1] = tl_s1n_67_ds_h2d[17]; + assign tl_s1n_67_ds_d2h[17] = tl_sm1_55_us_d2h[1]; - assign tl_sm1_56_us_h2d[1] = tl_s1n_61_ds_h2d[21]; - assign tl_s1n_61_ds_d2h[21] = tl_sm1_56_us_d2h[1]; + assign tl_sm1_56_us_h2d[1] = tl_s1n_67_ds_h2d[18]; + assign tl_s1n_67_ds_d2h[18] = tl_sm1_56_us_d2h[1]; - assign tl_sm1_57_us_h2d[1] = tl_s1n_61_ds_h2d[22]; - assign tl_s1n_61_ds_d2h[22] = tl_sm1_57_us_d2h[1]; + assign tl_sm1_57_us_h2d[1] = tl_s1n_67_ds_h2d[19]; + assign tl_s1n_67_ds_d2h[19] = tl_sm1_57_us_d2h[1]; - assign tl_sm1_58_us_h2d[1] = tl_s1n_61_ds_h2d[23]; - assign tl_s1n_61_ds_d2h[23] = tl_sm1_58_us_d2h[1]; + assign tl_sm1_58_us_h2d[1] = tl_s1n_67_ds_h2d[20]; + assign tl_s1n_67_ds_d2h[20] = tl_sm1_58_us_d2h[1]; - assign tl_sm1_59_us_h2d[1] = tl_s1n_61_ds_h2d[24]; - assign tl_s1n_61_ds_d2h[24] = tl_sm1_59_us_d2h[1]; + assign tl_sm1_59_us_h2d[1] = tl_s1n_67_ds_h2d[21]; + assign tl_s1n_67_ds_d2h[21] = tl_sm1_59_us_d2h[1]; - assign tl_sm1_60_us_h2d[1] = tl_s1n_61_ds_h2d[25]; - assign tl_s1n_61_ds_d2h[25] = tl_sm1_60_us_d2h[1]; + assign tl_sm1_60_us_h2d[1] = tl_s1n_67_ds_h2d[22]; + assign tl_s1n_67_ds_d2h[22] = tl_sm1_60_us_d2h[1]; - assign tl_s1n_29_us_h2d = tl_rv_core_ibex__corei_i; - assign tl_rv_core_ibex__corei_o = tl_s1n_29_us_d2h; + assign tl_sm1_61_us_h2d[1] = tl_s1n_67_ds_h2d[23]; + assign tl_s1n_67_ds_d2h[23] = tl_sm1_61_us_d2h[1]; - assign tl_rom_ctrl__rom_o = tl_sm1_30_ds_h2d; - assign tl_sm1_30_ds_d2h = tl_rom_ctrl__rom_i; + assign tl_sm1_62_us_h2d[1] = tl_s1n_67_ds_h2d[24]; + assign tl_s1n_67_ds_d2h[24] = tl_sm1_62_us_d2h[1]; - assign tl_rv_dm__mem_o = tl_sm1_31_ds_h2d; - assign tl_sm1_31_ds_d2h = tl_rv_dm__mem_i; + assign tl_sm1_63_us_h2d[1] = tl_s1n_67_ds_h2d[25]; + assign tl_s1n_67_ds_d2h[25] = tl_sm1_63_us_d2h[1]; - assign tl_sram_ctrl_main__ram_o = tl_sm1_32_ds_h2d; - assign tl_sm1_32_ds_d2h = tl_sram_ctrl_main__ram_i; + assign tl_sm1_64_us_h2d[1] = tl_s1n_67_ds_h2d[26]; + assign tl_s1n_67_ds_d2h[26] = tl_sm1_64_us_d2h[1]; - assign tl_sram_ctrl_sec__ram_o = tl_sm1_33_ds_h2d; - assign tl_sm1_33_ds_d2h = tl_sram_ctrl_sec__ram_i; + assign tl_sm1_65_us_h2d[1] = tl_s1n_67_ds_h2d[27]; + assign tl_s1n_67_ds_d2h[27] = tl_sm1_65_us_d2h[1]; - assign tl_flash_ctrl__mem_o = tl_sm1_34_ds_h2d; - assign tl_sm1_34_ds_d2h = tl_flash_ctrl__mem_i; + assign tl_sm1_66_us_h2d[1] = tl_s1n_67_ds_h2d[28]; + assign tl_s1n_67_ds_d2h[28] = tl_sm1_66_us_d2h[1]; - assign tl_s1n_35_us_h2d = tl_rv_core_ibex__cored_i; - assign tl_rv_core_ibex__cored_o = tl_s1n_35_us_d2h; + assign tl_s1n_32_us_h2d = tl_rv_core_ibex__corei_i; + assign tl_rv_core_ibex__corei_o = tl_s1n_32_us_d2h; - assign tl_rom_ctrl__regs_o = tl_sm1_36_ds_h2d; - assign tl_sm1_36_ds_d2h = tl_rom_ctrl__regs_i; + assign tl_rom_ctrl__rom_o = tl_sm1_33_ds_h2d; + assign tl_sm1_33_ds_d2h = tl_rom_ctrl__rom_i; - assign tl_rv_dm__regs_o = tl_sm1_37_ds_h2d; - assign tl_sm1_37_ds_d2h = tl_rv_dm__regs_i; + assign tl_rv_dm__mem_o = tl_sm1_34_ds_h2d; + assign tl_sm1_34_ds_d2h = tl_rv_dm__mem_i; - assign tl_peri_o = tl_asf_38_ds_h2d; - assign tl_asf_38_ds_d2h = tl_peri_i; + assign tl_sram_ctrl_main__ram_o = tl_sm1_35_ds_h2d; + assign tl_sm1_35_ds_d2h = tl_sram_ctrl_main__ram_i; - assign tl_asf_38_us_h2d = tl_sm1_39_ds_h2d; - assign tl_sm1_39_ds_d2h = tl_asf_38_us_d2h; + assign tl_sram_ctrl_sec__ram_o = tl_sm1_36_ds_h2d; + assign tl_sm1_36_ds_d2h = tl_sram_ctrl_sec__ram_i; - assign tl_spi_host0_o = tl_asf_40_ds_h2d; - assign tl_asf_40_ds_d2h = tl_spi_host0_i; + assign tl_flash_ctrl__mem_o = tl_sm1_37_ds_h2d; + assign tl_sm1_37_ds_d2h = tl_flash_ctrl__mem_i; - assign tl_asf_40_us_h2d = tl_sm1_41_ds_h2d; - assign tl_sm1_41_ds_d2h = tl_asf_40_us_d2h; + assign tl_rram_ctrl__host_o = tl_sm1_38_ds_h2d; + assign tl_sm1_38_ds_d2h = tl_rram_ctrl__host_i; - assign tl_spi_host1_o = tl_asf_42_ds_h2d; - assign tl_asf_42_ds_d2h = tl_spi_host1_i; + assign tl_s1n_39_us_h2d = tl_rv_core_ibex__cored_i; + assign tl_rv_core_ibex__cored_o = tl_s1n_39_us_d2h; + + assign tl_rom_ctrl__regs_o = tl_sm1_40_ds_h2d; + assign tl_sm1_40_ds_d2h = tl_rom_ctrl__regs_i; + + assign tl_rv_dm__regs_o = tl_sm1_41_ds_h2d; + assign tl_sm1_41_ds_d2h = tl_rv_dm__regs_i; + + assign tl_peri_o = tl_asf_42_ds_h2d; + assign tl_asf_42_ds_d2h = tl_peri_i; assign tl_asf_42_us_h2d = tl_sm1_43_ds_h2d; assign tl_sm1_43_ds_d2h = tl_asf_42_us_d2h; - assign tl_usbdev_o = tl_asf_44_ds_h2d; - assign tl_asf_44_ds_d2h = tl_usbdev_i; + assign tl_spi_host0_o = tl_asf_44_ds_h2d; + assign tl_asf_44_ds_d2h = tl_spi_host0_i; assign tl_asf_44_us_h2d = tl_sm1_45_ds_h2d; assign tl_sm1_45_ds_d2h = tl_asf_44_us_d2h; - assign tl_flash_ctrl__core_o = tl_sm1_46_ds_h2d; - assign tl_sm1_46_ds_d2h = tl_flash_ctrl__core_i; + assign tl_spi_host1_o = tl_asf_46_ds_h2d; + assign tl_asf_46_ds_d2h = tl_spi_host1_i; + + assign tl_asf_46_us_h2d = tl_sm1_47_ds_h2d; + assign tl_sm1_47_ds_d2h = tl_asf_46_us_d2h; + + assign tl_usbdev_o = tl_asf_48_ds_h2d; + assign tl_asf_48_ds_d2h = tl_usbdev_i; - assign tl_flash_ctrl__prim_o = tl_sm1_47_ds_h2d; - assign tl_sm1_47_ds_d2h = tl_flash_ctrl__prim_i; + assign tl_asf_48_us_h2d = tl_sm1_49_ds_h2d; + assign tl_sm1_49_ds_d2h = tl_asf_48_us_d2h; - assign tl_aes_o = tl_sm1_48_ds_h2d; - assign tl_sm1_48_ds_d2h = tl_aes_i; + assign tl_flash_ctrl__core_o = tl_sm1_50_ds_h2d; + assign tl_sm1_50_ds_d2h = tl_flash_ctrl__core_i; - assign tl_entropy_src_o = tl_sm1_49_ds_h2d; - assign tl_sm1_49_ds_d2h = tl_entropy_src_i; + assign tl_flash_ctrl__prim_o = tl_sm1_51_ds_h2d; + assign tl_sm1_51_ds_d2h = tl_flash_ctrl__prim_i; - assign tl_csrng_o = tl_sm1_50_ds_h2d; - assign tl_sm1_50_ds_d2h = tl_csrng_i; + assign tl_rram_ctrl__core_o = tl_sm1_52_ds_h2d; + assign tl_sm1_52_ds_d2h = tl_rram_ctrl__core_i; - assign tl_edn0_o = tl_sm1_51_ds_h2d; - assign tl_sm1_51_ds_d2h = tl_edn0_i; + assign tl_rram_macro__prim_o = tl_sm1_53_ds_h2d; + assign tl_sm1_53_ds_d2h = tl_rram_macro__prim_i; - assign tl_edn1_o = tl_sm1_52_ds_h2d; - assign tl_sm1_52_ds_d2h = tl_edn1_i; + assign tl_aes_o = tl_sm1_54_ds_h2d; + assign tl_sm1_54_ds_d2h = tl_aes_i; - assign tl_hmac_o = tl_sm1_53_ds_h2d; - assign tl_sm1_53_ds_d2h = tl_hmac_i; + assign tl_entropy_src_o = tl_sm1_55_ds_h2d; + assign tl_sm1_55_ds_d2h = tl_entropy_src_i; - assign tl_rv_plic_o = tl_sm1_54_ds_h2d; - assign tl_sm1_54_ds_d2h = tl_rv_plic_i; + assign tl_csrng_o = tl_sm1_56_ds_h2d; + assign tl_sm1_56_ds_d2h = tl_csrng_i; - assign tl_otbn_o = tl_sm1_55_ds_h2d; - assign tl_sm1_55_ds_d2h = tl_otbn_i; + assign tl_edn0_o = tl_sm1_57_ds_h2d; + assign tl_sm1_57_ds_d2h = tl_edn0_i; - assign tl_keymgr_o = tl_sm1_56_ds_h2d; - assign tl_sm1_56_ds_d2h = tl_keymgr_i; + assign tl_edn1_o = tl_sm1_58_ds_h2d; + assign tl_sm1_58_ds_d2h = tl_edn1_i; - assign tl_kmac_o = tl_sm1_57_ds_h2d; - assign tl_sm1_57_ds_d2h = tl_kmac_i; + assign tl_hmac_o = tl_sm1_59_ds_h2d; + assign tl_sm1_59_ds_d2h = tl_hmac_i; - assign tl_sram_ctrl_main__regs_o = tl_sm1_58_ds_h2d; - assign tl_sm1_58_ds_d2h = tl_sram_ctrl_main__regs_i; + assign tl_rv_plic_o = tl_sm1_60_ds_h2d; + assign tl_sm1_60_ds_d2h = tl_rv_plic_i; - assign tl_sram_ctrl_sec__regs_o = tl_sm1_59_ds_h2d; - assign tl_sm1_59_ds_d2h = tl_sram_ctrl_sec__regs_i; + assign tl_otbn_o = tl_sm1_61_ds_h2d; + assign tl_sm1_61_ds_d2h = tl_otbn_i; - assign tl_rv_core_ibex__cfg_o = tl_sm1_60_ds_h2d; - assign tl_sm1_60_ds_d2h = tl_rv_core_ibex__cfg_i; + assign tl_keymgr_o = tl_sm1_62_ds_h2d; + assign tl_sm1_62_ds_d2h = tl_keymgr_i; - assign tl_s1n_61_us_h2d = tl_rv_dm__sba_i; - assign tl_rv_dm__sba_o = tl_s1n_61_us_d2h; + assign tl_kmac_o = tl_sm1_63_ds_h2d; + assign tl_sm1_63_ds_d2h = tl_kmac_i; + + assign tl_sram_ctrl_main__regs_o = tl_sm1_64_ds_h2d; + assign tl_sm1_64_ds_d2h = tl_sram_ctrl_main__regs_i; + + assign tl_sram_ctrl_sec__regs_o = tl_sm1_65_ds_h2d; + assign tl_sm1_65_ds_d2h = tl_sram_ctrl_sec__regs_i; + + assign tl_rv_core_ibex__cfg_o = tl_sm1_66_ds_h2d; + assign tl_sm1_66_ds_d2h = tl_rv_core_ibex__cfg_i; + + assign tl_s1n_67_us_h2d = tl_rv_dm__sba_i; + assign tl_rv_dm__sba_o = tl_s1n_67_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_29 = 3'd5; - if (((tl_s1n_29_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && - (tl_s1n_29_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin - dev_sel_s1n_29 = 3'd0; + dev_sel_s1n_32 = 3'd6; + if (((tl_s1n_32_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && + (tl_s1n_32_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin + dev_sel_s1n_32 = 3'd0; - end else if ((tl_s1n_29_us_h2d.a_address & + end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_29 = 3'd1; + dev_sel_s1n_32 = 3'd1; - end else if ((tl_s1n_29_us_h2d.a_address & + end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_29 = 3'd2; + dev_sel_s1n_32 = 3'd2; - end else if ((tl_s1n_29_us_h2d.a_address & + end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__RAM)) == ADDR_SPACE_SRAM_CTRL_SEC__RAM) begin - dev_sel_s1n_29 = 3'd3; + dev_sel_s1n_32 = 3'd3; - end else if ((tl_s1n_29_us_h2d.a_address & + end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_29 = 3'd4; + dev_sel_s1n_32 = 3'd4; + + end else if ((tl_s1n_32_us_h2d.a_address & + ~(ADDR_MASK_RRAM_CTRL__HOST)) == ADDR_SPACE_RRAM_CTRL__HOST) begin + dev_sel_s1n_32 = 3'd5; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_35 = 5'd26; - if (((tl_s1n_35_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && - (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin - dev_sel_s1n_35 = 5'd0; + dev_sel_s1n_39 = 5'd29; + if (((tl_s1n_39_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && + (tl_s1n_39_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin + dev_sel_s1n_39 = 5'd0; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_35 = 5'd1; + dev_sel_s1n_39 = 5'd1; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_35 = 5'd2; + dev_sel_s1n_39 = 5'd2; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin - dev_sel_s1n_35 = 5'd3; + dev_sel_s1n_39 = 5'd3; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_35 = 5'd4; + dev_sel_s1n_39 = 5'd4; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__RAM)) == ADDR_SPACE_SRAM_CTRL_SEC__RAM) begin - dev_sel_s1n_35 = 5'd5; + dev_sel_s1n_39 = 5'd5; end else if ( - ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || - ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) + ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || + ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) ) begin - dev_sel_s1n_35 = 5'd6; + dev_sel_s1n_39 = 5'd6; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin - dev_sel_s1n_35 = 5'd7; + dev_sel_s1n_39 = 5'd7; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin - dev_sel_s1n_35 = 5'd8; + dev_sel_s1n_39 = 5'd8; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_35 = 5'd9; + dev_sel_s1n_39 = 5'd9; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_35 = 5'd10; + dev_sel_s1n_39 = 5'd10; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_35 = 5'd11; + dev_sel_s1n_39 = 5'd11; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_35 = 5'd12; + dev_sel_s1n_39 = 5'd12; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & + ~(ADDR_MASK_RRAM_CTRL__CORE)) == ADDR_SPACE_RRAM_CTRL__CORE) begin + dev_sel_s1n_39 = 5'd13; + + end else if ((tl_s1n_39_us_h2d.a_address & + ~(ADDR_MASK_RRAM_CTRL__HOST)) == ADDR_SPACE_RRAM_CTRL__HOST) begin + dev_sel_s1n_39 = 5'd14; + + end else if ((tl_s1n_39_us_h2d.a_address & + ~(ADDR_MASK_RRAM_MACRO__PRIM)) == ADDR_SPACE_RRAM_MACRO__PRIM) begin + dev_sel_s1n_39 = 5'd15; + + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_35 = 5'd13; + dev_sel_s1n_39 = 5'd16; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_35 = 5'd14; + dev_sel_s1n_39 = 5'd17; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_35 = 5'd15; + dev_sel_s1n_39 = 5'd18; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_35 = 5'd16; + dev_sel_s1n_39 = 5'd19; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_35 = 5'd17; + dev_sel_s1n_39 = 5'd20; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_35 = 5'd18; + dev_sel_s1n_39 = 5'd21; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_35 = 5'd19; + dev_sel_s1n_39 = 5'd22; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_35 = 5'd20; + dev_sel_s1n_39 = 5'd23; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin - dev_sel_s1n_35 = 5'd21; + dev_sel_s1n_39 = 5'd24; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_35 = 5'd22; + dev_sel_s1n_39 = 5'd25; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin - dev_sel_s1n_35 = 5'd23; + dev_sel_s1n_39 = 5'd26; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__REGS)) == ADDR_SPACE_SRAM_CTRL_SEC__REGS) begin - dev_sel_s1n_35 = 5'd24; + dev_sel_s1n_39 = 5'd27; - end else if ((tl_s1n_35_us_h2d.a_address & + end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin - dev_sel_s1n_35 = 5'd25; + dev_sel_s1n_39 = 5'd28; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_61 = 5'd26; - if (((tl_s1n_61_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && - (tl_s1n_61_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin - dev_sel_s1n_61 = 5'd0; + dev_sel_s1n_67 = 5'd29; + if (((tl_s1n_67_us_h2d.a_address < (ADDR_SPACE_ROM_CTRL__ROM + ADDR_SIZE_ROM_CTRL__ROM)) && + (tl_s1n_67_us_h2d.a_address >= ADDR_SPACE_ROM_CTRL__ROM))) begin + dev_sel_s1n_67 = 5'd0; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_61 = 5'd1; + dev_sel_s1n_67 = 5'd1; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin - dev_sel_s1n_61 = 5'd2; + dev_sel_s1n_67 = 5'd2; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin - dev_sel_s1n_61 = 5'd3; + dev_sel_s1n_67 = 5'd3; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin - dev_sel_s1n_61 = 5'd4; + dev_sel_s1n_67 = 5'd4; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__RAM)) == ADDR_SPACE_SRAM_CTRL_SEC__RAM) begin - dev_sel_s1n_61 = 5'd5; + dev_sel_s1n_67 = 5'd5; end else if ( - ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || - ((tl_s1n_61_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) + ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) || + ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1]) ) begin - dev_sel_s1n_61 = 5'd6; + dev_sel_s1n_67 = 5'd6; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin - dev_sel_s1n_61 = 5'd7; + dev_sel_s1n_67 = 5'd7; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin - dev_sel_s1n_61 = 5'd8; + dev_sel_s1n_67 = 5'd8; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin - dev_sel_s1n_61 = 5'd9; + dev_sel_s1n_67 = 5'd9; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_61 = 5'd10; + dev_sel_s1n_67 = 5'd10; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_61 = 5'd11; + dev_sel_s1n_67 = 5'd11; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin - dev_sel_s1n_61 = 5'd12; + dev_sel_s1n_67 = 5'd12; + + end else if ((tl_s1n_67_us_h2d.a_address & + ~(ADDR_MASK_RRAM_CTRL__CORE)) == ADDR_SPACE_RRAM_CTRL__CORE) begin + dev_sel_s1n_67 = 5'd13; + + end else if ((tl_s1n_67_us_h2d.a_address & + ~(ADDR_MASK_RRAM_CTRL__HOST)) == ADDR_SPACE_RRAM_CTRL__HOST) begin + dev_sel_s1n_67 = 5'd14; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & + ~(ADDR_MASK_RRAM_MACRO__PRIM)) == ADDR_SPACE_RRAM_MACRO__PRIM) begin + dev_sel_s1n_67 = 5'd15; + + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_61 = 5'd13; + dev_sel_s1n_67 = 5'd16; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_61 = 5'd14; + dev_sel_s1n_67 = 5'd17; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_61 = 5'd15; + dev_sel_s1n_67 = 5'd18; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_61 = 5'd16; + dev_sel_s1n_67 = 5'd19; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_61 = 5'd17; + dev_sel_s1n_67 = 5'd20; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_61 = 5'd18; + dev_sel_s1n_67 = 5'd21; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_61 = 5'd19; + dev_sel_s1n_67 = 5'd22; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_61 = 5'd20; + dev_sel_s1n_67 = 5'd23; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin - dev_sel_s1n_61 = 5'd21; + dev_sel_s1n_67 = 5'd24; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_61 = 5'd22; + dev_sel_s1n_67 = 5'd25; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin - dev_sel_s1n_61 = 5'd23; + dev_sel_s1n_67 = 5'd26; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_SEC__REGS)) == ADDR_SPACE_SRAM_CTRL_SEC__REGS) begin - dev_sel_s1n_61 = 5'd24; + dev_sel_s1n_67 = 5'd27; - end else if ((tl_s1n_61_us_h2d.a_address & + end else if ((tl_s1n_67_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin - dev_sel_s1n_61 = 5'd25; + dev_sel_s1n_67 = 5'd28; end end @@ -976,30 +1075,30 @@ end tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (20'h0), - .DRspDepth (20'h0), - .N (5) - ) u_s1n_29 ( + .DReqDepth (24'h0), + .DRspDepth (24'h0), + .N (6) + ) u_s1n_32 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_29_us_h2d), - .tl_h_o (tl_s1n_29_us_d2h), - .tl_d_o (tl_s1n_29_ds_h2d), - .tl_d_i (tl_s1n_29_ds_d2h), - .dev_select_i (dev_sel_s1n_29) + .tl_h_i (tl_s1n_32_us_h2d), + .tl_h_o (tl_s1n_32_us_d2h), + .tl_d_o (tl_s1n_32_ds_h2d), + .tl_d_i (tl_s1n_32_ds_d2h), + .dev_select_i (dev_sel_s1n_32) ); tlul_socket_m1 #( .HReqDepth (12'h0), .HRspDepth (12'h0), .DRspPass (1'b0), .M (3) - ) u_sm1_30 ( + ) u_sm1_33 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_30_us_h2d), - .tl_h_o (tl_sm1_30_us_d2h), - .tl_d_o (tl_sm1_30_ds_h2d), - .tl_d_i (tl_sm1_30_ds_d2h) + .tl_h_i (tl_sm1_33_us_h2d), + .tl_h_o (tl_sm1_33_us_d2h), + .tl_d_o (tl_sm1_33_ds_h2d), + .tl_d_i (tl_sm1_33_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1007,13 +1106,13 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (3) - ) u_sm1_31 ( + ) u_sm1_34 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_31_us_h2d), - .tl_h_o (tl_sm1_31_us_d2h), - .tl_d_o (tl_sm1_31_ds_h2d), - .tl_d_i (tl_sm1_31_ds_d2h) + .tl_h_i (tl_sm1_34_us_h2d), + .tl_h_o (tl_sm1_34_us_d2h), + .tl_d_o (tl_sm1_34_ds_h2d), + .tl_d_i (tl_sm1_34_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1021,13 +1120,13 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_32 ( + ) u_sm1_35 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_32_us_h2d), - .tl_h_o (tl_sm1_32_us_d2h), - .tl_d_o (tl_sm1_32_ds_h2d), - .tl_d_i (tl_sm1_32_ds_d2h) + .tl_h_i (tl_sm1_35_us_h2d), + .tl_h_o (tl_sm1_35_us_d2h), + .tl_d_o (tl_sm1_35_ds_h2d), + .tl_d_i (tl_sm1_35_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1035,13 +1134,13 @@ end .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_33 ( + ) u_sm1_36 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_33_us_h2d), - .tl_h_o (tl_sm1_33_us_d2h), - .tl_d_o (tl_sm1_33_ds_h2d), - .tl_d_i (tl_sm1_33_ds_d2h) + .tl_h_i (tl_sm1_36_us_h2d), + .tl_h_o (tl_sm1_36_us_d2h), + .tl_d_o (tl_sm1_36_ds_h2d), + .tl_d_i (tl_sm1_36_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -1049,28 +1148,42 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (3) - ) u_sm1_34 ( + ) u_sm1_37 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_34_us_h2d), - .tl_h_o (tl_sm1_34_us_d2h), - .tl_d_o (tl_sm1_34_ds_h2d), - .tl_d_i (tl_sm1_34_ds_d2h) + .tl_h_i (tl_sm1_37_us_h2d), + .tl_h_o (tl_sm1_37_us_d2h), + .tl_d_o (tl_sm1_37_ds_h2d), + .tl_d_i (tl_sm1_37_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_38 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_38_us_h2d), + .tl_h_o (tl_sm1_38_us_d2h), + .tl_d_o (tl_sm1_38_ds_h2d), + .tl_d_i (tl_sm1_38_ds_d2h) ); tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (104'h0), - .DRspDepth (104'h0), - .N (26) - ) u_s1n_35 ( + .DReqDepth (116'h0), + .DRspDepth (116'h0), + .N (29) + ) u_s1n_39 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_35_us_h2d), - .tl_h_o (tl_s1n_35_us_d2h), - .tl_d_o (tl_s1n_35_ds_h2d), - .tl_d_i (tl_s1n_35_ds_d2h), - .dev_select_i (dev_sel_s1n_35) + .tl_h_i (tl_s1n_39_us_h2d), + .tl_h_o (tl_s1n_39_us_d2h), + .tl_d_o (tl_s1n_39_ds_h2d), + .tl_d_i (tl_s1n_39_ds_d2h), + .dev_select_i (dev_sel_s1n_39) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1078,13 +1191,13 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (2) - ) u_sm1_36 ( + ) u_sm1_40 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_36_us_h2d), - .tl_h_o (tl_sm1_36_us_d2h), - .tl_d_o (tl_sm1_36_ds_h2d), - .tl_d_i (tl_sm1_36_ds_d2h) + .tl_h_i (tl_sm1_40_us_h2d), + .tl_h_o (tl_sm1_40_us_d2h), + .tl_d_o (tl_sm1_40_ds_h2d), + .tl_d_i (tl_sm1_40_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -1092,60 +1205,6 @@ end .DReqPass (1'b0), .DRspPass (1'b0), .M (2) - ) u_sm1_37 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_37_us_h2d), - .tl_h_o (tl_sm1_37_us_d2h), - .tl_d_o (tl_sm1_37_ds_h2d), - .tl_d_i (tl_sm1_37_ds_d2h) - ); - tlul_fifo_async #( - .ReqDepth (1), - .RspDepth (1) - ) u_asf_38 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_38_us_h2d), - .tl_h_o (tl_asf_38_us_d2h), - .tl_d_o (tl_asf_38_ds_h2d), - .tl_d_i (tl_asf_38_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (2) - ) u_sm1_39 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_39_us_h2d), - .tl_h_o (tl_sm1_39_us_d2h), - .tl_d_o (tl_sm1_39_ds_h2d), - .tl_d_i (tl_sm1_39_ds_d2h) - ); - tlul_fifo_async #( - .ReqDepth (1), - .RspDepth (1) - ) u_asf_40 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_spi_host0_i), - .rst_d_ni (rst_spi_host0_ni), - .tl_h_i (tl_asf_40_us_h2d), - .tl_h_o (tl_asf_40_us_d2h), - .tl_d_o (tl_asf_40_ds_h2d), - .tl_d_i (tl_asf_40_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (2) ) u_sm1_41 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -1160,8 +1219,8 @@ end ) u_asf_42 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), - .clk_d_i (clk_spi_host1_i), - .rst_d_ni (rst_spi_host1_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), .tl_h_i (tl_asf_42_us_h2d), .tl_h_o (tl_asf_42_us_d2h), .tl_d_o (tl_asf_42_ds_h2d), @@ -1187,8 +1246,8 @@ end ) u_asf_44 ( .clk_h_i (clk_main_i), .rst_h_ni (rst_main_ni), - .clk_d_i (clk_usb_i), - .rst_d_ni (rst_usb_ni), + .clk_d_i (clk_spi_host0_i), + .rst_d_ni (rst_spi_host0_ni), .tl_h_i (tl_asf_44_us_h2d), .tl_h_o (tl_asf_44_us_d2h), .tl_d_o (tl_asf_44_ds_h2d), @@ -1208,25 +1267,24 @@ end .tl_d_o (tl_sm1_45_ds_h2d), .tl_d_i (tl_sm1_45_ds_d2h) ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_46 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_46_us_h2d), - .tl_h_o (tl_sm1_46_us_d2h), - .tl_d_o (tl_sm1_46_ds_h2d), - .tl_d_i (tl_sm1_46_ds_d2h) + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_46 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_spi_host1_i), + .rst_d_ni (rst_spi_host1_ni), + .tl_h_i (tl_asf_46_us_h2d), + .tl_h_o (tl_asf_46_us_d2h), + .tl_d_o (tl_asf_46_ds_h2d), + .tl_d_i (tl_asf_46_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), .M (2) ) u_sm1_47 ( .clk_i (clk_main_i), @@ -1236,25 +1294,24 @@ end .tl_d_o (tl_sm1_47_ds_h2d), .tl_d_i (tl_sm1_47_ds_d2h) ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_48 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_48_us_h2d), - .tl_h_o (tl_sm1_48_us_d2h), - .tl_d_o (tl_sm1_48_ds_h2d), - .tl_d_i (tl_sm1_48_ds_d2h) + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_48 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_usb_i), + .rst_d_ni (rst_usb_ni), + .tl_h_i (tl_asf_48_us_h2d), + .tl_h_o (tl_asf_48_us_d2h), + .tl_d_o (tl_asf_48_ds_h2d), + .tl_d_i (tl_asf_48_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), .M (2) ) u_sm1_49 ( .clk_i (clk_main_i), @@ -1418,20 +1475,104 @@ end .tl_d_o (tl_sm1_60_ds_h2d), .tl_d_i (tl_sm1_60_ds_d2h) ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_61 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_61_us_h2d), + .tl_h_o (tl_sm1_61_us_d2h), + .tl_d_o (tl_sm1_61_ds_h2d), + .tl_d_i (tl_sm1_61_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_62 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_62_us_h2d), + .tl_h_o (tl_sm1_62_us_d2h), + .tl_d_o (tl_sm1_62_ds_h2d), + .tl_d_i (tl_sm1_62_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_63 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_63_us_h2d), + .tl_h_o (tl_sm1_63_us_d2h), + .tl_d_o (tl_sm1_63_ds_h2d), + .tl_d_i (tl_sm1_63_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_64 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_64_us_h2d), + .tl_h_o (tl_sm1_64_us_d2h), + .tl_d_o (tl_sm1_64_ds_h2d), + .tl_d_i (tl_sm1_64_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_65 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_65_us_h2d), + .tl_h_o (tl_sm1_65_us_d2h), + .tl_d_o (tl_sm1_65_ds_h2d), + .tl_d_i (tl_sm1_65_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_66 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_66_us_h2d), + .tl_h_o (tl_sm1_66_us_d2h), + .tl_d_o (tl_sm1_66_ds_h2d), + .tl_d_i (tl_sm1_66_ds_d2h) + ); tlul_socket_1n #( .HReqPass (1'b0), .HRspPass (1'b0), - .DReqDepth (104'h0), - .DRspDepth (104'h0), - .N (26) - ) u_s1n_61 ( + .DReqDepth (116'h0), + .DRspDepth (116'h0), + .N (29) + ) u_s1n_67 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_61_us_h2d), - .tl_h_o (tl_s1n_61_us_d2h), - .tl_d_o (tl_s1n_61_ds_h2d), - .tl_d_i (tl_s1n_61_ds_d2h), - .dev_select_i (dev_sel_s1n_61) + .tl_h_i (tl_s1n_67_us_h2d), + .tl_h_o (tl_s1n_67_us_d2h), + .tl_d_o (tl_s1n_67_ds_h2d), + .tl_d_i (tl_s1n_67_ds_d2h), + .dev_select_i (dev_sel_s1n_67) ); endmodule diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson index 91e13451558c2..933592cfdc7c3 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson @@ -49,7 +49,7 @@ { name: "NAlerts", desc: "Number of alert channels.", type: "int", - default: "64", + default: "69", local: "true" }, { name: "NLpg", @@ -102,6 +102,11 @@ 5'd17, 5'd17, 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, 5'd16, 5'd12, 5'd12, @@ -222,6 +227,11 @@ 1'b1, 1'b1, 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, 1'b1 } ''' diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index e8794e3a35322..94f9480afb3dd 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -6,7 +6,7 @@ param_values: { module_instance_name: alert_handler - n_alerts: 64 + n_alerts: 69 esc_cnt_dw: 32 accu_cnt_dw: 16 async_on: @@ -75,6 +75,11 @@ 1'b1 1'b1 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 ] n_classes: 4 n_esc_sev: 4 @@ -120,6 +125,11 @@ 5'd17 5'd17 5'd17 + 5'd17 + 5'd17 + 5'd17 + 5'd17 + 5'd17 5'd18 5'd19 5'd20 diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md index cba96ec13df43..d00ba1166d01f 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md +++ b/hw/top_earlgrey/ip_autogen/alert_handler/doc/theory_of_operation.md @@ -24,7 +24,7 @@ The parameterization rules are explained in more detail in the architectural des Localparam | Default (Max) | This Core | Description ---------------|-----------------------|----------------|--------------- -`NAlerts` | 8 (248) | 64 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. +`NAlerts` | 8 (248) | 69 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. `NLpg` | 1 | 24 | Number of unique low-power groups as determined by topgen. `LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen. `EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit. diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv index 8f751fde35a80..18d5276b5d15a 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -7,7 +7,7 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 64; + parameter int NAlerts = 69; parameter int NLpg = 24; parameter int NLpgWidth = 5; parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { @@ -42,6 +42,11 @@ package alert_handler_reg_pkg; 5'd17, 5'd17, 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, + 5'd17, 5'd16, 5'd12, 5'd12, @@ -142,6 +147,11 @@ package alert_handler_reg_pkg; 1'b1, 1'b1, 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, 1'b1 }; parameter int N_CLASSES = 4; @@ -164,7 +174,7 @@ package alert_handler_reg_pkg; parameter int BlockAw = 11; // Number of registers for every interface - parameter int NumRegs = 346; + parameter int NumRegs = 366; //////////////////////////// // Typedefs for registers // @@ -618,15 +628,15 @@ package alert_handler_reg_pkg; // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [1156:1153] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1152:1149] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [1148:1141] - alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1140:1125] - alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1124:1124] - alert_handler_reg2hw_alert_regwen_mreg_t [63:0] alert_regwen; // [1123:1060] - alert_handler_reg2hw_alert_en_shadowed_mreg_t [63:0] alert_en_shadowed; // [1059:996] - alert_handler_reg2hw_alert_class_shadowed_mreg_t [63:0] alert_class_shadowed; // [995:868] - alert_handler_reg2hw_alert_cause_mreg_t [63:0] alert_cause; // [867:804] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1181:1178] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1177:1174] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1173:1166] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1165:1150] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1149:1149] + alert_handler_reg2hw_alert_regwen_mreg_t [68:0] alert_regwen; // [1148:1080] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [68:0] alert_en_shadowed; // [1079:1011] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [68:0] alert_class_shadowed; // [1010:873] + alert_handler_reg2hw_alert_cause_mreg_t [68:0] alert_cause; // [872:804] alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] loc_alert_class_shadowed; // [796:783] @@ -679,8 +689,8 @@ package alert_handler_reg_pkg; // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [361:354] - alert_handler_hw2reg_alert_cause_mreg_t [63:0] alert_cause; // [353:226] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [371:364] + alert_handler_hw2reg_alert_cause_mreg_t [68:0] alert_cause; // [363:226] alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -771,282 +781,302 @@ package alert_handler_reg_pkg; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 118; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 11c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 460; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 464; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 468; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 46c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 470; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 474; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 478; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 47c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 480; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 484; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 488; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 48c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 490; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 494; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 498; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 49c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 4c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 4cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 500; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 504; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 508; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 50c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 510; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 514; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 518; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 51c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 520; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 524; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 528; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 52c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 530; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 534; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 538; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 53c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 540; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 544; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 548; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 54c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 550; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 554; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 558; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 55c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 560; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_67_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_68_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_67_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_68_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 5b4; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -1139,6 +1169,11 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_REGWEN_61, ALERT_HANDLER_ALERT_REGWEN_62, ALERT_HANDLER_ALERT_REGWEN_63, + ALERT_HANDLER_ALERT_REGWEN_64, + ALERT_HANDLER_ALERT_REGWEN_65, + ALERT_HANDLER_ALERT_REGWEN_66, + ALERT_HANDLER_ALERT_REGWEN_67, + ALERT_HANDLER_ALERT_REGWEN_68, ALERT_HANDLER_ALERT_EN_SHADOWED_0, ALERT_HANDLER_ALERT_EN_SHADOWED_1, ALERT_HANDLER_ALERT_EN_SHADOWED_2, @@ -1203,6 +1238,11 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_EN_SHADOWED_61, ALERT_HANDLER_ALERT_EN_SHADOWED_62, ALERT_HANDLER_ALERT_EN_SHADOWED_63, + ALERT_HANDLER_ALERT_EN_SHADOWED_64, + ALERT_HANDLER_ALERT_EN_SHADOWED_65, + ALERT_HANDLER_ALERT_EN_SHADOWED_66, + ALERT_HANDLER_ALERT_EN_SHADOWED_67, + ALERT_HANDLER_ALERT_EN_SHADOWED_68, ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, @@ -1267,6 +1307,11 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CLASS_SHADOWED_61, ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_65, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_66, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_67, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_68, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -1331,6 +1376,11 @@ package alert_handler_reg_pkg; ALERT_HANDLER_ALERT_CAUSE_61, ALERT_HANDLER_ALERT_CAUSE_62, ALERT_HANDLER_ALERT_CAUSE_63, + ALERT_HANDLER_ALERT_CAUSE_64, + ALERT_HANDLER_ALERT_CAUSE_65, + ALERT_HANDLER_ALERT_CAUSE_66, + ALERT_HANDLER_ALERT_CAUSE_67, + ALERT_HANDLER_ALERT_CAUSE_68, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -1418,7 +1468,7 @@ package alert_handler_reg_pkg; } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [346] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [366] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1489,282 +1539,302 @@ package alert_handler_reg_pkg; 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 - 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_7 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_8 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_9 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_10 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_11 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_12 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_13 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_14 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_15 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_16 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_17 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_18 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_19 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_20 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_21 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_22 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_23 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_24 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_25 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_26 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_27 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_28 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_29 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_30 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_31 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_32 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_33 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_34 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_35 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_36 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_37 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_38 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_39 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_40 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_41 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_42 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_43 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_44 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_45 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_46 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_47 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_48 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_49 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_50 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_51 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_52 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_53 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_54 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_55 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_56 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_57 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_58 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_59 - 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_60 - 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_61 - 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_62 - 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_63 - 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 - 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 - 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 - 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 - 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 - 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 - 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 - 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 - 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 - 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 - 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 - 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 - 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 - 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 - 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 - 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 - 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 - 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 - 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 - 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 - 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 - 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 - 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 - 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 - 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 - 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 - 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 - 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 - 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 - 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 - 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 - 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 - 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 - 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 - 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 - 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 - 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 - 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 - 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 - 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 - 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 - 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 - 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 - 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 - 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 - 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 - 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 - 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 - 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 - 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 - 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 - 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 - 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 - 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 - 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 - 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 - 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 - 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_31 - 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_32 - 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_33 - 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_34 - 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_35 - 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_36 - 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_37 - 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_38 - 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_39 - 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_40 - 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_41 - 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_42 - 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_43 - 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_44 - 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_45 - 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_46 - 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_47 - 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_48 - 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_49 - 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_50 - 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_51 - 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_52 - 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_53 - 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_54 - 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_55 - 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_56 - 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_57 - 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_58 - 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_59 - 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_60 - 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_61 - 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_62 - 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_63 - 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_REGWEN_5 - 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_REGWEN_6 - 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 - 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 - 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 - 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 - 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 - 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 - 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 - 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 - 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 - 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 - 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 - 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 - 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 - 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 - 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CAUSE_4 - 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CAUSE_5 - 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_6 - 4'b 0001, // index[290] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[291] ALERT_HANDLER_CLASSA_CTRL_SHADOWED - 4'b 0001, // index[292] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[293] ALERT_HANDLER_CLASSA_CLR_SHADOWED - 4'b 0011, // index[294] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[296] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[298] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED - 4'b 1111, // index[299] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED - 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED - 4'b 1111, // index[301] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED - 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[303] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[304] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[305] ALERT_HANDLER_CLASSB_CTRL_SHADOWED - 4'b 0001, // index[306] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[307] ALERT_HANDLER_CLASSB_CLR_SHADOWED - 4'b 0011, // index[308] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[309] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[310] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[311] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[312] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED - 4'b 1111, // index[313] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED - 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED - 4'b 1111, // index[315] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED - 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[317] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[318] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[319] ALERT_HANDLER_CLASSC_CTRL_SHADOWED - 4'b 0001, // index[320] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[321] ALERT_HANDLER_CLASSC_CLR_SHADOWED - 4'b 0011, // index[322] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[323] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[324] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[325] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[326] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED - 4'b 1111, // index[327] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED - 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED - 4'b 1111, // index[329] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED - 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[331] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[332] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[333] ALERT_HANDLER_CLASSD_CTRL_SHADOWED - 4'b 0001, // index[334] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[335] ALERT_HANDLER_CLASSD_CLR_SHADOWED - 4'b 0011, // index[336] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED - 4'b 1111, // index[338] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED - 4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED - 4'b 1111, // index[340] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED - 4'b 1111, // index[341] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED - 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED - 4'b 1111, // index[343] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED - 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[345] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_REGWEN_67 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_REGWEN_68 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_SHADOWED_64 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_EN_SHADOWED_65 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_EN_SHADOWED_66 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_EN_SHADOWED_67 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_EN_SHADOWED_68 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[274] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[275] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[276] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[277] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[278] ALERT_HANDLER_ALERT_CAUSE_65 + 4'b 0001, // index[279] ALERT_HANDLER_ALERT_CAUSE_66 + 4'b 0001, // index[280] ALERT_HANDLER_ALERT_CAUSE_67 + 4'b 0001, // index[281] ALERT_HANDLER_ALERT_CAUSE_68 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[294] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[295] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[296] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[297] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[298] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[299] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[300] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[301] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[302] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[303] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[304] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[305] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[306] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[307] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[308] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[309] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[310] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[311] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[312] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[313] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[314] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[315] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[316] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[317] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[318] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[319] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[320] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[321] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[322] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[323] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[324] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[325] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[326] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[327] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[328] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[329] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[330] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[331] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[332] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[333] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[334] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[335] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[336] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[337] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[338] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[339] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[340] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[341] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[342] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[343] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[344] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[345] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[346] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[347] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[348] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[349] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[350] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[351] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[352] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[353] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[354] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[355] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[356] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[357] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[358] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[359] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[360] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[361] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[362] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[363] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[364] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[365] ALERT_HANDLER_CLASSD_STATE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv index c40fe370f5de3..f2f17212870b7 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv @@ -56,9 +56,9 @@ module alert_handler_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [345:0] reg_we_check; + logic [365:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(346) + .OneHotWidth(366) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -355,6 +355,21 @@ module alert_handler_reg_top ( logic alert_regwen_63_we; logic alert_regwen_63_qs; logic alert_regwen_63_wd; + logic alert_regwen_64_we; + logic alert_regwen_64_qs; + logic alert_regwen_64_wd; + logic alert_regwen_65_we; + logic alert_regwen_65_qs; + logic alert_regwen_65_wd; + logic alert_regwen_66_we; + logic alert_regwen_66_qs; + logic alert_regwen_66_wd; + logic alert_regwen_67_we; + logic alert_regwen_67_qs; + logic alert_regwen_67_wd; + logic alert_regwen_68_we; + logic alert_regwen_68_qs; + logic alert_regwen_68_wd; logic alert_en_shadowed_0_re; logic alert_en_shadowed_0_we; logic alert_en_shadowed_0_qs; @@ -739,6 +754,36 @@ module alert_handler_reg_top ( logic alert_en_shadowed_63_wd; logic alert_en_shadowed_63_storage_err; logic alert_en_shadowed_63_update_err; + logic alert_en_shadowed_64_re; + logic alert_en_shadowed_64_we; + logic alert_en_shadowed_64_qs; + logic alert_en_shadowed_64_wd; + logic alert_en_shadowed_64_storage_err; + logic alert_en_shadowed_64_update_err; + logic alert_en_shadowed_65_re; + logic alert_en_shadowed_65_we; + logic alert_en_shadowed_65_qs; + logic alert_en_shadowed_65_wd; + logic alert_en_shadowed_65_storage_err; + logic alert_en_shadowed_65_update_err; + logic alert_en_shadowed_66_re; + logic alert_en_shadowed_66_we; + logic alert_en_shadowed_66_qs; + logic alert_en_shadowed_66_wd; + logic alert_en_shadowed_66_storage_err; + logic alert_en_shadowed_66_update_err; + logic alert_en_shadowed_67_re; + logic alert_en_shadowed_67_we; + logic alert_en_shadowed_67_qs; + logic alert_en_shadowed_67_wd; + logic alert_en_shadowed_67_storage_err; + logic alert_en_shadowed_67_update_err; + logic alert_en_shadowed_68_re; + logic alert_en_shadowed_68_we; + logic alert_en_shadowed_68_qs; + logic alert_en_shadowed_68_wd; + logic alert_en_shadowed_68_storage_err; + logic alert_en_shadowed_68_update_err; logic alert_class_shadowed_0_re; logic alert_class_shadowed_0_we; logic [1:0] alert_class_shadowed_0_qs; @@ -1123,6 +1168,36 @@ module alert_handler_reg_top ( logic [1:0] alert_class_shadowed_63_wd; logic alert_class_shadowed_63_storage_err; logic alert_class_shadowed_63_update_err; + logic alert_class_shadowed_64_re; + logic alert_class_shadowed_64_we; + logic [1:0] alert_class_shadowed_64_qs; + logic [1:0] alert_class_shadowed_64_wd; + logic alert_class_shadowed_64_storage_err; + logic alert_class_shadowed_64_update_err; + logic alert_class_shadowed_65_re; + logic alert_class_shadowed_65_we; + logic [1:0] alert_class_shadowed_65_qs; + logic [1:0] alert_class_shadowed_65_wd; + logic alert_class_shadowed_65_storage_err; + logic alert_class_shadowed_65_update_err; + logic alert_class_shadowed_66_re; + logic alert_class_shadowed_66_we; + logic [1:0] alert_class_shadowed_66_qs; + logic [1:0] alert_class_shadowed_66_wd; + logic alert_class_shadowed_66_storage_err; + logic alert_class_shadowed_66_update_err; + logic alert_class_shadowed_67_re; + logic alert_class_shadowed_67_we; + logic [1:0] alert_class_shadowed_67_qs; + logic [1:0] alert_class_shadowed_67_wd; + logic alert_class_shadowed_67_storage_err; + logic alert_class_shadowed_67_update_err; + logic alert_class_shadowed_68_re; + logic alert_class_shadowed_68_we; + logic [1:0] alert_class_shadowed_68_qs; + logic [1:0] alert_class_shadowed_68_wd; + logic alert_class_shadowed_68_storage_err; + logic alert_class_shadowed_68_update_err; logic alert_cause_0_we; logic alert_cause_0_qs; logic alert_cause_0_wd; @@ -1315,6 +1390,21 @@ module alert_handler_reg_top ( logic alert_cause_63_we; logic alert_cause_63_qs; logic alert_cause_63_wd; + logic alert_cause_64_we; + logic alert_cause_64_qs; + logic alert_cause_64_wd; + logic alert_cause_65_we; + logic alert_cause_65_qs; + logic alert_cause_65_wd; + logic alert_cause_66_we; + logic alert_cause_66_qs; + logic alert_cause_66_wd; + logic alert_cause_67_we; + logic alert_cause_67_qs; + logic alert_cause_67_wd; + logic alert_cause_68_we; + logic alert_cause_68_qs; + logic alert_cause_68_wd; logic loc_alert_regwen_0_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; @@ -4104,6 +4194,151 @@ module alert_handler_reg_top ( ); + // Subregister 64 of Multireg alert_regwen + // R[alert_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_64_we), + .wd (alert_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[64].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_64_qs) + ); + + + // Subregister 65 of Multireg alert_regwen + // R[alert_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_65_we), + .wd (alert_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[65].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_65_qs) + ); + + + // Subregister 66 of Multireg alert_regwen + // R[alert_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_66_we), + .wd (alert_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[66].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_66_qs) + ); + + + // Subregister 67 of Multireg alert_regwen + // R[alert_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_67_we), + .wd (alert_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[67].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_67_qs) + ); + + + // Subregister 68 of Multireg alert_regwen + // R[alert_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_68_we), + .wd (alert_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[68].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_68_qs) + ); + + // Subregister 0 of Multireg alert_en_shadowed // R[alert_en_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -6728,6 +6963,211 @@ module alert_handler_reg_top ( ); + // Subregister 64 of Multireg alert_en_shadowed + // R[alert_en_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_64_gated_we; + assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_64_re), + .we (alert_en_shadowed_64_gated_we), + .wd (alert_en_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_64_update_err), + .err_storage (alert_en_shadowed_64_storage_err) + ); + + + // Subregister 65 of Multireg alert_en_shadowed + // R[alert_en_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_65_gated_we; + assign alert_en_shadowed_65_gated_we = alert_en_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_65_re), + .we (alert_en_shadowed_65_gated_we), + .wd (alert_en_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_65_update_err), + .err_storage (alert_en_shadowed_65_storage_err) + ); + + + // Subregister 66 of Multireg alert_en_shadowed + // R[alert_en_shadowed_66]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_66_gated_we; + assign alert_en_shadowed_66_gated_we = alert_en_shadowed_66_we & alert_regwen_66_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_66_re), + .we (alert_en_shadowed_66_gated_we), + .wd (alert_en_shadowed_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[66].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_66_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_66_update_err), + .err_storage (alert_en_shadowed_66_storage_err) + ); + + + // Subregister 67 of Multireg alert_en_shadowed + // R[alert_en_shadowed_67]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_67_gated_we; + assign alert_en_shadowed_67_gated_we = alert_en_shadowed_67_we & alert_regwen_67_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_67_re), + .we (alert_en_shadowed_67_gated_we), + .wd (alert_en_shadowed_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[67].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_67_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_67_update_err), + .err_storage (alert_en_shadowed_67_storage_err) + ); + + + // Subregister 68 of Multireg alert_en_shadowed + // R[alert_en_shadowed_68]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_68_gated_we; + assign alert_en_shadowed_68_gated_we = alert_en_shadowed_68_we & alert_regwen_68_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_68_re), + .we (alert_en_shadowed_68_gated_we), + .wd (alert_en_shadowed_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[68].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_68_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_68_update_err), + .err_storage (alert_en_shadowed_68_storage_err) + ); + + // Subregister 0 of Multireg alert_class_shadowed // R[alert_class_shadowed_0]: V(False) // Create REGWEN-gated WE signal @@ -9352,7 +9792,212 @@ module alert_handler_reg_top ( ); - // Subregister 0 of Multireg alert_cause + // Subregister 64 of Multireg alert_class_shadowed + // R[alert_class_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_64_gated_we; + assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_64_re), + .we (alert_class_shadowed_64_gated_we), + .wd (alert_class_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_64_update_err), + .err_storage (alert_class_shadowed_64_storage_err) + ); + + + // Subregister 65 of Multireg alert_class_shadowed + // R[alert_class_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_65_gated_we; + assign alert_class_shadowed_65_gated_we = alert_class_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_65_re), + .we (alert_class_shadowed_65_gated_we), + .wd (alert_class_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_65_update_err), + .err_storage (alert_class_shadowed_65_storage_err) + ); + + + // Subregister 66 of Multireg alert_class_shadowed + // R[alert_class_shadowed_66]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_66_gated_we; + assign alert_class_shadowed_66_gated_we = alert_class_shadowed_66_we & alert_regwen_66_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_66_re), + .we (alert_class_shadowed_66_gated_we), + .wd (alert_class_shadowed_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[66].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_66_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_66_update_err), + .err_storage (alert_class_shadowed_66_storage_err) + ); + + + // Subregister 67 of Multireg alert_class_shadowed + // R[alert_class_shadowed_67]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_67_gated_we; + assign alert_class_shadowed_67_gated_we = alert_class_shadowed_67_we & alert_regwen_67_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_67_re), + .we (alert_class_shadowed_67_gated_we), + .wd (alert_class_shadowed_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[67].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_67_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_67_update_err), + .err_storage (alert_class_shadowed_67_storage_err) + ); + + + // Subregister 68 of Multireg alert_class_shadowed + // R[alert_class_shadowed_68]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_68_gated_we; + assign alert_class_shadowed_68_gated_we = alert_class_shadowed_68_we & alert_regwen_68_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_68_re), + .we (alert_class_shadowed_68_gated_we), + .wd (alert_class_shadowed_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[68].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_68_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_68_update_err), + .err_storage (alert_class_shadowed_68_storage_err) + ); + + + // Subregister 0 of Multireg alert_cause // R[alert_cause_0]: V(False) prim_subreg #( .DW (1), @@ -11208,6 +11853,151 @@ module alert_handler_reg_top ( ); + // Subregister 64 of Multireg alert_cause + // R[alert_cause_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_64_we), + .wd (alert_cause_64_wd), + + // from internal hardware + .de (hw2reg.alert_cause[64].de), + .d (hw2reg.alert_cause[64].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[64].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_64_qs) + ); + + + // Subregister 65 of Multireg alert_cause + // R[alert_cause_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_65_we), + .wd (alert_cause_65_wd), + + // from internal hardware + .de (hw2reg.alert_cause[65].de), + .d (hw2reg.alert_cause[65].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[65].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_65_qs) + ); + + + // Subregister 66 of Multireg alert_cause + // R[alert_cause_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_66_we), + .wd (alert_cause_66_wd), + + // from internal hardware + .de (hw2reg.alert_cause[66].de), + .d (hw2reg.alert_cause[66].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[66].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_66_qs) + ); + + + // Subregister 67 of Multireg alert_cause + // R[alert_cause_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_67_we), + .wd (alert_cause_67_wd), + + // from internal hardware + .de (hw2reg.alert_cause[67].de), + .d (hw2reg.alert_cause[67].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[67].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_67_qs) + ); + + + // Subregister 68 of Multireg alert_cause + // R[alert_cause_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_68_we), + .wd (alert_cause_68_wd), + + // from internal hardware + .de (hw2reg.alert_cause[68].de), + .d (hw2reg.alert_cause[68].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[68].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_68_qs) + ); + + // Subregister 0 of Multireg loc_alert_regwen // R[loc_alert_regwen_0]: V(False) prim_subreg #( @@ -15404,7 +16194,7 @@ module alert_handler_reg_top ( - logic [345:0] addr_hit; + logic [365:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET); @@ -15476,282 +16266,302 @@ module alert_handler_reg_top ( addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET); addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET); addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); - addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); - addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); - addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); - addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); - addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); - addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); - addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); - addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); - addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); - addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); - addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); - addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); - addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); - addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); - addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); - addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); - addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); - addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); - addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); - addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); - addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); - addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); - addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); - addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); - addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); - addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); - addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); - addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); - addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); - addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); - addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); - addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); - addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); - addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); - addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); - addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); - addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); - addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); - addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); - addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); - addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); - addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); - addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); - addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); - addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); - addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); - addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); - addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); - addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); - addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); - addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); - addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); - addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); - addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); - addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); - addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); - addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); - addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); - addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); - addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); - addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); - addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); - addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); - addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); - addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); - addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); - addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); - addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_67_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_68_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_67_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_68_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[350] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[351] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[352] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[353] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); + addr_hit[354] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[355] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); + addr_hit[356] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[357] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[358] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[359] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[360] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[361] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[362] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[363] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[364] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[365] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -16104,7 +16914,27 @@ module alert_handler_reg_top ( (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) | (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) | (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) | - (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))))); + (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) | + (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) | + (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) | + (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) | + (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))) | + (addr_hit[350] & (|(ALERT_HANDLER_PERMIT[350] & ~reg_be))) | + (addr_hit[351] & (|(ALERT_HANDLER_PERMIT[351] & ~reg_be))) | + (addr_hit[352] & (|(ALERT_HANDLER_PERMIT[352] & ~reg_be))) | + (addr_hit[353] & (|(ALERT_HANDLER_PERMIT[353] & ~reg_be))) | + (addr_hit[354] & (|(ALERT_HANDLER_PERMIT[354] & ~reg_be))) | + (addr_hit[355] & (|(ALERT_HANDLER_PERMIT[355] & ~reg_be))) | + (addr_hit[356] & (|(ALERT_HANDLER_PERMIT[356] & ~reg_be))) | + (addr_hit[357] & (|(ALERT_HANDLER_PERMIT[357] & ~reg_be))) | + (addr_hit[358] & (|(ALERT_HANDLER_PERMIT[358] & ~reg_be))) | + (addr_hit[359] & (|(ALERT_HANDLER_PERMIT[359] & ~reg_be))) | + (addr_hit[360] & (|(ALERT_HANDLER_PERMIT[360] & ~reg_be))) | + (addr_hit[361] & (|(ALERT_HANDLER_PERMIT[361] & ~reg_be))) | + (addr_hit[362] & (|(ALERT_HANDLER_PERMIT[362] & ~reg_be))) | + (addr_hit[363] & (|(ALERT_HANDLER_PERMIT[363] & ~reg_be))) | + (addr_hit[364] & (|(ALERT_HANDLER_PERMIT[364] & ~reg_be))) | + (addr_hit[365] & (|(ALERT_HANDLER_PERMIT[365] & ~reg_be))))); end // Generate write-enables @@ -16338,813 +17168,883 @@ module alert_handler_reg_top ( assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error; assign alert_regwen_63_wd = reg_wdata[0]; - assign alert_en_shadowed_0_re = addr_hit[70] & reg_re & !reg_error; - assign alert_en_shadowed_0_we = addr_hit[70] & reg_we & !reg_error; + assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error; + + assign alert_regwen_64_wd = reg_wdata[0]; + assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error; + + assign alert_regwen_65_wd = reg_wdata[0]; + assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error; + + assign alert_regwen_66_wd = reg_wdata[0]; + assign alert_regwen_67_we = addr_hit[73] & reg_we & !reg_error; + + assign alert_regwen_67_wd = reg_wdata[0]; + assign alert_regwen_68_we = addr_hit[74] & reg_we & !reg_error; + + assign alert_regwen_68_wd = reg_wdata[0]; + assign alert_en_shadowed_0_re = addr_hit[75] & reg_re & !reg_error; + assign alert_en_shadowed_0_we = addr_hit[75] & reg_we & !reg_error; assign alert_en_shadowed_0_wd = reg_wdata[0]; - assign alert_en_shadowed_1_re = addr_hit[71] & reg_re & !reg_error; - assign alert_en_shadowed_1_we = addr_hit[71] & reg_we & !reg_error; + assign alert_en_shadowed_1_re = addr_hit[76] & reg_re & !reg_error; + assign alert_en_shadowed_1_we = addr_hit[76] & reg_we & !reg_error; assign alert_en_shadowed_1_wd = reg_wdata[0]; - assign alert_en_shadowed_2_re = addr_hit[72] & reg_re & !reg_error; - assign alert_en_shadowed_2_we = addr_hit[72] & reg_we & !reg_error; + assign alert_en_shadowed_2_re = addr_hit[77] & reg_re & !reg_error; + assign alert_en_shadowed_2_we = addr_hit[77] & reg_we & !reg_error; assign alert_en_shadowed_2_wd = reg_wdata[0]; - assign alert_en_shadowed_3_re = addr_hit[73] & reg_re & !reg_error; - assign alert_en_shadowed_3_we = addr_hit[73] & reg_we & !reg_error; + assign alert_en_shadowed_3_re = addr_hit[78] & reg_re & !reg_error; + assign alert_en_shadowed_3_we = addr_hit[78] & reg_we & !reg_error; assign alert_en_shadowed_3_wd = reg_wdata[0]; - assign alert_en_shadowed_4_re = addr_hit[74] & reg_re & !reg_error; - assign alert_en_shadowed_4_we = addr_hit[74] & reg_we & !reg_error; + assign alert_en_shadowed_4_re = addr_hit[79] & reg_re & !reg_error; + assign alert_en_shadowed_4_we = addr_hit[79] & reg_we & !reg_error; assign alert_en_shadowed_4_wd = reg_wdata[0]; - assign alert_en_shadowed_5_re = addr_hit[75] & reg_re & !reg_error; - assign alert_en_shadowed_5_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_shadowed_5_re = addr_hit[80] & reg_re & !reg_error; + assign alert_en_shadowed_5_we = addr_hit[80] & reg_we & !reg_error; assign alert_en_shadowed_5_wd = reg_wdata[0]; - assign alert_en_shadowed_6_re = addr_hit[76] & reg_re & !reg_error; - assign alert_en_shadowed_6_we = addr_hit[76] & reg_we & !reg_error; + assign alert_en_shadowed_6_re = addr_hit[81] & reg_re & !reg_error; + assign alert_en_shadowed_6_we = addr_hit[81] & reg_we & !reg_error; assign alert_en_shadowed_6_wd = reg_wdata[0]; - assign alert_en_shadowed_7_re = addr_hit[77] & reg_re & !reg_error; - assign alert_en_shadowed_7_we = addr_hit[77] & reg_we & !reg_error; + assign alert_en_shadowed_7_re = addr_hit[82] & reg_re & !reg_error; + assign alert_en_shadowed_7_we = addr_hit[82] & reg_we & !reg_error; assign alert_en_shadowed_7_wd = reg_wdata[0]; - assign alert_en_shadowed_8_re = addr_hit[78] & reg_re & !reg_error; - assign alert_en_shadowed_8_we = addr_hit[78] & reg_we & !reg_error; + assign alert_en_shadowed_8_re = addr_hit[83] & reg_re & !reg_error; + assign alert_en_shadowed_8_we = addr_hit[83] & reg_we & !reg_error; assign alert_en_shadowed_8_wd = reg_wdata[0]; - assign alert_en_shadowed_9_re = addr_hit[79] & reg_re & !reg_error; - assign alert_en_shadowed_9_we = addr_hit[79] & reg_we & !reg_error; + assign alert_en_shadowed_9_re = addr_hit[84] & reg_re & !reg_error; + assign alert_en_shadowed_9_we = addr_hit[84] & reg_we & !reg_error; assign alert_en_shadowed_9_wd = reg_wdata[0]; - assign alert_en_shadowed_10_re = addr_hit[80] & reg_re & !reg_error; - assign alert_en_shadowed_10_we = addr_hit[80] & reg_we & !reg_error; + assign alert_en_shadowed_10_re = addr_hit[85] & reg_re & !reg_error; + assign alert_en_shadowed_10_we = addr_hit[85] & reg_we & !reg_error; assign alert_en_shadowed_10_wd = reg_wdata[0]; - assign alert_en_shadowed_11_re = addr_hit[81] & reg_re & !reg_error; - assign alert_en_shadowed_11_we = addr_hit[81] & reg_we & !reg_error; + assign alert_en_shadowed_11_re = addr_hit[86] & reg_re & !reg_error; + assign alert_en_shadowed_11_we = addr_hit[86] & reg_we & !reg_error; assign alert_en_shadowed_11_wd = reg_wdata[0]; - assign alert_en_shadowed_12_re = addr_hit[82] & reg_re & !reg_error; - assign alert_en_shadowed_12_we = addr_hit[82] & reg_we & !reg_error; + assign alert_en_shadowed_12_re = addr_hit[87] & reg_re & !reg_error; + assign alert_en_shadowed_12_we = addr_hit[87] & reg_we & !reg_error; assign alert_en_shadowed_12_wd = reg_wdata[0]; - assign alert_en_shadowed_13_re = addr_hit[83] & reg_re & !reg_error; - assign alert_en_shadowed_13_we = addr_hit[83] & reg_we & !reg_error; + assign alert_en_shadowed_13_re = addr_hit[88] & reg_re & !reg_error; + assign alert_en_shadowed_13_we = addr_hit[88] & reg_we & !reg_error; assign alert_en_shadowed_13_wd = reg_wdata[0]; - assign alert_en_shadowed_14_re = addr_hit[84] & reg_re & !reg_error; - assign alert_en_shadowed_14_we = addr_hit[84] & reg_we & !reg_error; + assign alert_en_shadowed_14_re = addr_hit[89] & reg_re & !reg_error; + assign alert_en_shadowed_14_we = addr_hit[89] & reg_we & !reg_error; assign alert_en_shadowed_14_wd = reg_wdata[0]; - assign alert_en_shadowed_15_re = addr_hit[85] & reg_re & !reg_error; - assign alert_en_shadowed_15_we = addr_hit[85] & reg_we & !reg_error; + assign alert_en_shadowed_15_re = addr_hit[90] & reg_re & !reg_error; + assign alert_en_shadowed_15_we = addr_hit[90] & reg_we & !reg_error; assign alert_en_shadowed_15_wd = reg_wdata[0]; - assign alert_en_shadowed_16_re = addr_hit[86] & reg_re & !reg_error; - assign alert_en_shadowed_16_we = addr_hit[86] & reg_we & !reg_error; + assign alert_en_shadowed_16_re = addr_hit[91] & reg_re & !reg_error; + assign alert_en_shadowed_16_we = addr_hit[91] & reg_we & !reg_error; assign alert_en_shadowed_16_wd = reg_wdata[0]; - assign alert_en_shadowed_17_re = addr_hit[87] & reg_re & !reg_error; - assign alert_en_shadowed_17_we = addr_hit[87] & reg_we & !reg_error; + assign alert_en_shadowed_17_re = addr_hit[92] & reg_re & !reg_error; + assign alert_en_shadowed_17_we = addr_hit[92] & reg_we & !reg_error; assign alert_en_shadowed_17_wd = reg_wdata[0]; - assign alert_en_shadowed_18_re = addr_hit[88] & reg_re & !reg_error; - assign alert_en_shadowed_18_we = addr_hit[88] & reg_we & !reg_error; + assign alert_en_shadowed_18_re = addr_hit[93] & reg_re & !reg_error; + assign alert_en_shadowed_18_we = addr_hit[93] & reg_we & !reg_error; assign alert_en_shadowed_18_wd = reg_wdata[0]; - assign alert_en_shadowed_19_re = addr_hit[89] & reg_re & !reg_error; - assign alert_en_shadowed_19_we = addr_hit[89] & reg_we & !reg_error; + assign alert_en_shadowed_19_re = addr_hit[94] & reg_re & !reg_error; + assign alert_en_shadowed_19_we = addr_hit[94] & reg_we & !reg_error; assign alert_en_shadowed_19_wd = reg_wdata[0]; - assign alert_en_shadowed_20_re = addr_hit[90] & reg_re & !reg_error; - assign alert_en_shadowed_20_we = addr_hit[90] & reg_we & !reg_error; + assign alert_en_shadowed_20_re = addr_hit[95] & reg_re & !reg_error; + assign alert_en_shadowed_20_we = addr_hit[95] & reg_we & !reg_error; assign alert_en_shadowed_20_wd = reg_wdata[0]; - assign alert_en_shadowed_21_re = addr_hit[91] & reg_re & !reg_error; - assign alert_en_shadowed_21_we = addr_hit[91] & reg_we & !reg_error; + assign alert_en_shadowed_21_re = addr_hit[96] & reg_re & !reg_error; + assign alert_en_shadowed_21_we = addr_hit[96] & reg_we & !reg_error; assign alert_en_shadowed_21_wd = reg_wdata[0]; - assign alert_en_shadowed_22_re = addr_hit[92] & reg_re & !reg_error; - assign alert_en_shadowed_22_we = addr_hit[92] & reg_we & !reg_error; + assign alert_en_shadowed_22_re = addr_hit[97] & reg_re & !reg_error; + assign alert_en_shadowed_22_we = addr_hit[97] & reg_we & !reg_error; assign alert_en_shadowed_22_wd = reg_wdata[0]; - assign alert_en_shadowed_23_re = addr_hit[93] & reg_re & !reg_error; - assign alert_en_shadowed_23_we = addr_hit[93] & reg_we & !reg_error; + assign alert_en_shadowed_23_re = addr_hit[98] & reg_re & !reg_error; + assign alert_en_shadowed_23_we = addr_hit[98] & reg_we & !reg_error; assign alert_en_shadowed_23_wd = reg_wdata[0]; - assign alert_en_shadowed_24_re = addr_hit[94] & reg_re & !reg_error; - assign alert_en_shadowed_24_we = addr_hit[94] & reg_we & !reg_error; + assign alert_en_shadowed_24_re = addr_hit[99] & reg_re & !reg_error; + assign alert_en_shadowed_24_we = addr_hit[99] & reg_we & !reg_error; assign alert_en_shadowed_24_wd = reg_wdata[0]; - assign alert_en_shadowed_25_re = addr_hit[95] & reg_re & !reg_error; - assign alert_en_shadowed_25_we = addr_hit[95] & reg_we & !reg_error; + assign alert_en_shadowed_25_re = addr_hit[100] & reg_re & !reg_error; + assign alert_en_shadowed_25_we = addr_hit[100] & reg_we & !reg_error; assign alert_en_shadowed_25_wd = reg_wdata[0]; - assign alert_en_shadowed_26_re = addr_hit[96] & reg_re & !reg_error; - assign alert_en_shadowed_26_we = addr_hit[96] & reg_we & !reg_error; + assign alert_en_shadowed_26_re = addr_hit[101] & reg_re & !reg_error; + assign alert_en_shadowed_26_we = addr_hit[101] & reg_we & !reg_error; assign alert_en_shadowed_26_wd = reg_wdata[0]; - assign alert_en_shadowed_27_re = addr_hit[97] & reg_re & !reg_error; - assign alert_en_shadowed_27_we = addr_hit[97] & reg_we & !reg_error; + assign alert_en_shadowed_27_re = addr_hit[102] & reg_re & !reg_error; + assign alert_en_shadowed_27_we = addr_hit[102] & reg_we & !reg_error; assign alert_en_shadowed_27_wd = reg_wdata[0]; - assign alert_en_shadowed_28_re = addr_hit[98] & reg_re & !reg_error; - assign alert_en_shadowed_28_we = addr_hit[98] & reg_we & !reg_error; + assign alert_en_shadowed_28_re = addr_hit[103] & reg_re & !reg_error; + assign alert_en_shadowed_28_we = addr_hit[103] & reg_we & !reg_error; assign alert_en_shadowed_28_wd = reg_wdata[0]; - assign alert_en_shadowed_29_re = addr_hit[99] & reg_re & !reg_error; - assign alert_en_shadowed_29_we = addr_hit[99] & reg_we & !reg_error; + assign alert_en_shadowed_29_re = addr_hit[104] & reg_re & !reg_error; + assign alert_en_shadowed_29_we = addr_hit[104] & reg_we & !reg_error; assign alert_en_shadowed_29_wd = reg_wdata[0]; - assign alert_en_shadowed_30_re = addr_hit[100] & reg_re & !reg_error; - assign alert_en_shadowed_30_we = addr_hit[100] & reg_we & !reg_error; + assign alert_en_shadowed_30_re = addr_hit[105] & reg_re & !reg_error; + assign alert_en_shadowed_30_we = addr_hit[105] & reg_we & !reg_error; assign alert_en_shadowed_30_wd = reg_wdata[0]; - assign alert_en_shadowed_31_re = addr_hit[101] & reg_re & !reg_error; - assign alert_en_shadowed_31_we = addr_hit[101] & reg_we & !reg_error; + assign alert_en_shadowed_31_re = addr_hit[106] & reg_re & !reg_error; + assign alert_en_shadowed_31_we = addr_hit[106] & reg_we & !reg_error; assign alert_en_shadowed_31_wd = reg_wdata[0]; - assign alert_en_shadowed_32_re = addr_hit[102] & reg_re & !reg_error; - assign alert_en_shadowed_32_we = addr_hit[102] & reg_we & !reg_error; + assign alert_en_shadowed_32_re = addr_hit[107] & reg_re & !reg_error; + assign alert_en_shadowed_32_we = addr_hit[107] & reg_we & !reg_error; assign alert_en_shadowed_32_wd = reg_wdata[0]; - assign alert_en_shadowed_33_re = addr_hit[103] & reg_re & !reg_error; - assign alert_en_shadowed_33_we = addr_hit[103] & reg_we & !reg_error; + assign alert_en_shadowed_33_re = addr_hit[108] & reg_re & !reg_error; + assign alert_en_shadowed_33_we = addr_hit[108] & reg_we & !reg_error; assign alert_en_shadowed_33_wd = reg_wdata[0]; - assign alert_en_shadowed_34_re = addr_hit[104] & reg_re & !reg_error; - assign alert_en_shadowed_34_we = addr_hit[104] & reg_we & !reg_error; + assign alert_en_shadowed_34_re = addr_hit[109] & reg_re & !reg_error; + assign alert_en_shadowed_34_we = addr_hit[109] & reg_we & !reg_error; assign alert_en_shadowed_34_wd = reg_wdata[0]; - assign alert_en_shadowed_35_re = addr_hit[105] & reg_re & !reg_error; - assign alert_en_shadowed_35_we = addr_hit[105] & reg_we & !reg_error; + assign alert_en_shadowed_35_re = addr_hit[110] & reg_re & !reg_error; + assign alert_en_shadowed_35_we = addr_hit[110] & reg_we & !reg_error; assign alert_en_shadowed_35_wd = reg_wdata[0]; - assign alert_en_shadowed_36_re = addr_hit[106] & reg_re & !reg_error; - assign alert_en_shadowed_36_we = addr_hit[106] & reg_we & !reg_error; + assign alert_en_shadowed_36_re = addr_hit[111] & reg_re & !reg_error; + assign alert_en_shadowed_36_we = addr_hit[111] & reg_we & !reg_error; assign alert_en_shadowed_36_wd = reg_wdata[0]; - assign alert_en_shadowed_37_re = addr_hit[107] & reg_re & !reg_error; - assign alert_en_shadowed_37_we = addr_hit[107] & reg_we & !reg_error; + assign alert_en_shadowed_37_re = addr_hit[112] & reg_re & !reg_error; + assign alert_en_shadowed_37_we = addr_hit[112] & reg_we & !reg_error; assign alert_en_shadowed_37_wd = reg_wdata[0]; - assign alert_en_shadowed_38_re = addr_hit[108] & reg_re & !reg_error; - assign alert_en_shadowed_38_we = addr_hit[108] & reg_we & !reg_error; + assign alert_en_shadowed_38_re = addr_hit[113] & reg_re & !reg_error; + assign alert_en_shadowed_38_we = addr_hit[113] & reg_we & !reg_error; assign alert_en_shadowed_38_wd = reg_wdata[0]; - assign alert_en_shadowed_39_re = addr_hit[109] & reg_re & !reg_error; - assign alert_en_shadowed_39_we = addr_hit[109] & reg_we & !reg_error; + assign alert_en_shadowed_39_re = addr_hit[114] & reg_re & !reg_error; + assign alert_en_shadowed_39_we = addr_hit[114] & reg_we & !reg_error; assign alert_en_shadowed_39_wd = reg_wdata[0]; - assign alert_en_shadowed_40_re = addr_hit[110] & reg_re & !reg_error; - assign alert_en_shadowed_40_we = addr_hit[110] & reg_we & !reg_error; + assign alert_en_shadowed_40_re = addr_hit[115] & reg_re & !reg_error; + assign alert_en_shadowed_40_we = addr_hit[115] & reg_we & !reg_error; assign alert_en_shadowed_40_wd = reg_wdata[0]; - assign alert_en_shadowed_41_re = addr_hit[111] & reg_re & !reg_error; - assign alert_en_shadowed_41_we = addr_hit[111] & reg_we & !reg_error; + assign alert_en_shadowed_41_re = addr_hit[116] & reg_re & !reg_error; + assign alert_en_shadowed_41_we = addr_hit[116] & reg_we & !reg_error; assign alert_en_shadowed_41_wd = reg_wdata[0]; - assign alert_en_shadowed_42_re = addr_hit[112] & reg_re & !reg_error; - assign alert_en_shadowed_42_we = addr_hit[112] & reg_we & !reg_error; + assign alert_en_shadowed_42_re = addr_hit[117] & reg_re & !reg_error; + assign alert_en_shadowed_42_we = addr_hit[117] & reg_we & !reg_error; assign alert_en_shadowed_42_wd = reg_wdata[0]; - assign alert_en_shadowed_43_re = addr_hit[113] & reg_re & !reg_error; - assign alert_en_shadowed_43_we = addr_hit[113] & reg_we & !reg_error; + assign alert_en_shadowed_43_re = addr_hit[118] & reg_re & !reg_error; + assign alert_en_shadowed_43_we = addr_hit[118] & reg_we & !reg_error; assign alert_en_shadowed_43_wd = reg_wdata[0]; - assign alert_en_shadowed_44_re = addr_hit[114] & reg_re & !reg_error; - assign alert_en_shadowed_44_we = addr_hit[114] & reg_we & !reg_error; + assign alert_en_shadowed_44_re = addr_hit[119] & reg_re & !reg_error; + assign alert_en_shadowed_44_we = addr_hit[119] & reg_we & !reg_error; assign alert_en_shadowed_44_wd = reg_wdata[0]; - assign alert_en_shadowed_45_re = addr_hit[115] & reg_re & !reg_error; - assign alert_en_shadowed_45_we = addr_hit[115] & reg_we & !reg_error; + assign alert_en_shadowed_45_re = addr_hit[120] & reg_re & !reg_error; + assign alert_en_shadowed_45_we = addr_hit[120] & reg_we & !reg_error; assign alert_en_shadowed_45_wd = reg_wdata[0]; - assign alert_en_shadowed_46_re = addr_hit[116] & reg_re & !reg_error; - assign alert_en_shadowed_46_we = addr_hit[116] & reg_we & !reg_error; + assign alert_en_shadowed_46_re = addr_hit[121] & reg_re & !reg_error; + assign alert_en_shadowed_46_we = addr_hit[121] & reg_we & !reg_error; assign alert_en_shadowed_46_wd = reg_wdata[0]; - assign alert_en_shadowed_47_re = addr_hit[117] & reg_re & !reg_error; - assign alert_en_shadowed_47_we = addr_hit[117] & reg_we & !reg_error; + assign alert_en_shadowed_47_re = addr_hit[122] & reg_re & !reg_error; + assign alert_en_shadowed_47_we = addr_hit[122] & reg_we & !reg_error; assign alert_en_shadowed_47_wd = reg_wdata[0]; - assign alert_en_shadowed_48_re = addr_hit[118] & reg_re & !reg_error; - assign alert_en_shadowed_48_we = addr_hit[118] & reg_we & !reg_error; + assign alert_en_shadowed_48_re = addr_hit[123] & reg_re & !reg_error; + assign alert_en_shadowed_48_we = addr_hit[123] & reg_we & !reg_error; assign alert_en_shadowed_48_wd = reg_wdata[0]; - assign alert_en_shadowed_49_re = addr_hit[119] & reg_re & !reg_error; - assign alert_en_shadowed_49_we = addr_hit[119] & reg_we & !reg_error; + assign alert_en_shadowed_49_re = addr_hit[124] & reg_re & !reg_error; + assign alert_en_shadowed_49_we = addr_hit[124] & reg_we & !reg_error; assign alert_en_shadowed_49_wd = reg_wdata[0]; - assign alert_en_shadowed_50_re = addr_hit[120] & reg_re & !reg_error; - assign alert_en_shadowed_50_we = addr_hit[120] & reg_we & !reg_error; + assign alert_en_shadowed_50_re = addr_hit[125] & reg_re & !reg_error; + assign alert_en_shadowed_50_we = addr_hit[125] & reg_we & !reg_error; assign alert_en_shadowed_50_wd = reg_wdata[0]; - assign alert_en_shadowed_51_re = addr_hit[121] & reg_re & !reg_error; - assign alert_en_shadowed_51_we = addr_hit[121] & reg_we & !reg_error; + assign alert_en_shadowed_51_re = addr_hit[126] & reg_re & !reg_error; + assign alert_en_shadowed_51_we = addr_hit[126] & reg_we & !reg_error; assign alert_en_shadowed_51_wd = reg_wdata[0]; - assign alert_en_shadowed_52_re = addr_hit[122] & reg_re & !reg_error; - assign alert_en_shadowed_52_we = addr_hit[122] & reg_we & !reg_error; + assign alert_en_shadowed_52_re = addr_hit[127] & reg_re & !reg_error; + assign alert_en_shadowed_52_we = addr_hit[127] & reg_we & !reg_error; assign alert_en_shadowed_52_wd = reg_wdata[0]; - assign alert_en_shadowed_53_re = addr_hit[123] & reg_re & !reg_error; - assign alert_en_shadowed_53_we = addr_hit[123] & reg_we & !reg_error; + assign alert_en_shadowed_53_re = addr_hit[128] & reg_re & !reg_error; + assign alert_en_shadowed_53_we = addr_hit[128] & reg_we & !reg_error; assign alert_en_shadowed_53_wd = reg_wdata[0]; - assign alert_en_shadowed_54_re = addr_hit[124] & reg_re & !reg_error; - assign alert_en_shadowed_54_we = addr_hit[124] & reg_we & !reg_error; + assign alert_en_shadowed_54_re = addr_hit[129] & reg_re & !reg_error; + assign alert_en_shadowed_54_we = addr_hit[129] & reg_we & !reg_error; assign alert_en_shadowed_54_wd = reg_wdata[0]; - assign alert_en_shadowed_55_re = addr_hit[125] & reg_re & !reg_error; - assign alert_en_shadowed_55_we = addr_hit[125] & reg_we & !reg_error; + assign alert_en_shadowed_55_re = addr_hit[130] & reg_re & !reg_error; + assign alert_en_shadowed_55_we = addr_hit[130] & reg_we & !reg_error; assign alert_en_shadowed_55_wd = reg_wdata[0]; - assign alert_en_shadowed_56_re = addr_hit[126] & reg_re & !reg_error; - assign alert_en_shadowed_56_we = addr_hit[126] & reg_we & !reg_error; + assign alert_en_shadowed_56_re = addr_hit[131] & reg_re & !reg_error; + assign alert_en_shadowed_56_we = addr_hit[131] & reg_we & !reg_error; assign alert_en_shadowed_56_wd = reg_wdata[0]; - assign alert_en_shadowed_57_re = addr_hit[127] & reg_re & !reg_error; - assign alert_en_shadowed_57_we = addr_hit[127] & reg_we & !reg_error; + assign alert_en_shadowed_57_re = addr_hit[132] & reg_re & !reg_error; + assign alert_en_shadowed_57_we = addr_hit[132] & reg_we & !reg_error; assign alert_en_shadowed_57_wd = reg_wdata[0]; - assign alert_en_shadowed_58_re = addr_hit[128] & reg_re & !reg_error; - assign alert_en_shadowed_58_we = addr_hit[128] & reg_we & !reg_error; + assign alert_en_shadowed_58_re = addr_hit[133] & reg_re & !reg_error; + assign alert_en_shadowed_58_we = addr_hit[133] & reg_we & !reg_error; assign alert_en_shadowed_58_wd = reg_wdata[0]; - assign alert_en_shadowed_59_re = addr_hit[129] & reg_re & !reg_error; - assign alert_en_shadowed_59_we = addr_hit[129] & reg_we & !reg_error; + assign alert_en_shadowed_59_re = addr_hit[134] & reg_re & !reg_error; + assign alert_en_shadowed_59_we = addr_hit[134] & reg_we & !reg_error; assign alert_en_shadowed_59_wd = reg_wdata[0]; - assign alert_en_shadowed_60_re = addr_hit[130] & reg_re & !reg_error; - assign alert_en_shadowed_60_we = addr_hit[130] & reg_we & !reg_error; + assign alert_en_shadowed_60_re = addr_hit[135] & reg_re & !reg_error; + assign alert_en_shadowed_60_we = addr_hit[135] & reg_we & !reg_error; assign alert_en_shadowed_60_wd = reg_wdata[0]; - assign alert_en_shadowed_61_re = addr_hit[131] & reg_re & !reg_error; - assign alert_en_shadowed_61_we = addr_hit[131] & reg_we & !reg_error; + assign alert_en_shadowed_61_re = addr_hit[136] & reg_re & !reg_error; + assign alert_en_shadowed_61_we = addr_hit[136] & reg_we & !reg_error; assign alert_en_shadowed_61_wd = reg_wdata[0]; - assign alert_en_shadowed_62_re = addr_hit[132] & reg_re & !reg_error; - assign alert_en_shadowed_62_we = addr_hit[132] & reg_we & !reg_error; + assign alert_en_shadowed_62_re = addr_hit[137] & reg_re & !reg_error; + assign alert_en_shadowed_62_we = addr_hit[137] & reg_we & !reg_error; assign alert_en_shadowed_62_wd = reg_wdata[0]; - assign alert_en_shadowed_63_re = addr_hit[133] & reg_re & !reg_error; - assign alert_en_shadowed_63_we = addr_hit[133] & reg_we & !reg_error; + assign alert_en_shadowed_63_re = addr_hit[138] & reg_re & !reg_error; + assign alert_en_shadowed_63_we = addr_hit[138] & reg_we & !reg_error; assign alert_en_shadowed_63_wd = reg_wdata[0]; - assign alert_class_shadowed_0_re = addr_hit[134] & reg_re & !reg_error; - assign alert_class_shadowed_0_we = addr_hit[134] & reg_we & !reg_error; + assign alert_en_shadowed_64_re = addr_hit[139] & reg_re & !reg_error; + assign alert_en_shadowed_64_we = addr_hit[139] & reg_we & !reg_error; + + assign alert_en_shadowed_64_wd = reg_wdata[0]; + assign alert_en_shadowed_65_re = addr_hit[140] & reg_re & !reg_error; + assign alert_en_shadowed_65_we = addr_hit[140] & reg_we & !reg_error; + + assign alert_en_shadowed_65_wd = reg_wdata[0]; + assign alert_en_shadowed_66_re = addr_hit[141] & reg_re & !reg_error; + assign alert_en_shadowed_66_we = addr_hit[141] & reg_we & !reg_error; + + assign alert_en_shadowed_66_wd = reg_wdata[0]; + assign alert_en_shadowed_67_re = addr_hit[142] & reg_re & !reg_error; + assign alert_en_shadowed_67_we = addr_hit[142] & reg_we & !reg_error; + + assign alert_en_shadowed_67_wd = reg_wdata[0]; + assign alert_en_shadowed_68_re = addr_hit[143] & reg_re & !reg_error; + assign alert_en_shadowed_68_we = addr_hit[143] & reg_we & !reg_error; + + assign alert_en_shadowed_68_wd = reg_wdata[0]; + assign alert_class_shadowed_0_re = addr_hit[144] & reg_re & !reg_error; + assign alert_class_shadowed_0_we = addr_hit[144] & reg_we & !reg_error; assign alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign alert_class_shadowed_1_re = addr_hit[135] & reg_re & !reg_error; - assign alert_class_shadowed_1_we = addr_hit[135] & reg_we & !reg_error; + assign alert_class_shadowed_1_re = addr_hit[145] & reg_re & !reg_error; + assign alert_class_shadowed_1_we = addr_hit[145] & reg_we & !reg_error; assign alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign alert_class_shadowed_2_re = addr_hit[136] & reg_re & !reg_error; - assign alert_class_shadowed_2_we = addr_hit[136] & reg_we & !reg_error; + assign alert_class_shadowed_2_re = addr_hit[146] & reg_re & !reg_error; + assign alert_class_shadowed_2_we = addr_hit[146] & reg_we & !reg_error; assign alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign alert_class_shadowed_3_re = addr_hit[137] & reg_re & !reg_error; - assign alert_class_shadowed_3_we = addr_hit[137] & reg_we & !reg_error; + assign alert_class_shadowed_3_re = addr_hit[147] & reg_re & !reg_error; + assign alert_class_shadowed_3_we = addr_hit[147] & reg_we & !reg_error; assign alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign alert_class_shadowed_4_re = addr_hit[138] & reg_re & !reg_error; - assign alert_class_shadowed_4_we = addr_hit[138] & reg_we & !reg_error; + assign alert_class_shadowed_4_re = addr_hit[148] & reg_re & !reg_error; + assign alert_class_shadowed_4_we = addr_hit[148] & reg_we & !reg_error; assign alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign alert_class_shadowed_5_re = addr_hit[139] & reg_re & !reg_error; - assign alert_class_shadowed_5_we = addr_hit[139] & reg_we & !reg_error; + assign alert_class_shadowed_5_re = addr_hit[149] & reg_re & !reg_error; + assign alert_class_shadowed_5_we = addr_hit[149] & reg_we & !reg_error; assign alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign alert_class_shadowed_6_re = addr_hit[140] & reg_re & !reg_error; - assign alert_class_shadowed_6_we = addr_hit[140] & reg_we & !reg_error; + assign alert_class_shadowed_6_re = addr_hit[150] & reg_re & !reg_error; + assign alert_class_shadowed_6_we = addr_hit[150] & reg_we & !reg_error; assign alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign alert_class_shadowed_7_re = addr_hit[141] & reg_re & !reg_error; - assign alert_class_shadowed_7_we = addr_hit[141] & reg_we & !reg_error; + assign alert_class_shadowed_7_re = addr_hit[151] & reg_re & !reg_error; + assign alert_class_shadowed_7_we = addr_hit[151] & reg_we & !reg_error; assign alert_class_shadowed_7_wd = reg_wdata[1:0]; - assign alert_class_shadowed_8_re = addr_hit[142] & reg_re & !reg_error; - assign alert_class_shadowed_8_we = addr_hit[142] & reg_we & !reg_error; + assign alert_class_shadowed_8_re = addr_hit[152] & reg_re & !reg_error; + assign alert_class_shadowed_8_we = addr_hit[152] & reg_we & !reg_error; assign alert_class_shadowed_8_wd = reg_wdata[1:0]; - assign alert_class_shadowed_9_re = addr_hit[143] & reg_re & !reg_error; - assign alert_class_shadowed_9_we = addr_hit[143] & reg_we & !reg_error; + assign alert_class_shadowed_9_re = addr_hit[153] & reg_re & !reg_error; + assign alert_class_shadowed_9_we = addr_hit[153] & reg_we & !reg_error; assign alert_class_shadowed_9_wd = reg_wdata[1:0]; - assign alert_class_shadowed_10_re = addr_hit[144] & reg_re & !reg_error; - assign alert_class_shadowed_10_we = addr_hit[144] & reg_we & !reg_error; + assign alert_class_shadowed_10_re = addr_hit[154] & reg_re & !reg_error; + assign alert_class_shadowed_10_we = addr_hit[154] & reg_we & !reg_error; assign alert_class_shadowed_10_wd = reg_wdata[1:0]; - assign alert_class_shadowed_11_re = addr_hit[145] & reg_re & !reg_error; - assign alert_class_shadowed_11_we = addr_hit[145] & reg_we & !reg_error; + assign alert_class_shadowed_11_re = addr_hit[155] & reg_re & !reg_error; + assign alert_class_shadowed_11_we = addr_hit[155] & reg_we & !reg_error; assign alert_class_shadowed_11_wd = reg_wdata[1:0]; - assign alert_class_shadowed_12_re = addr_hit[146] & reg_re & !reg_error; - assign alert_class_shadowed_12_we = addr_hit[146] & reg_we & !reg_error; + assign alert_class_shadowed_12_re = addr_hit[156] & reg_re & !reg_error; + assign alert_class_shadowed_12_we = addr_hit[156] & reg_we & !reg_error; assign alert_class_shadowed_12_wd = reg_wdata[1:0]; - assign alert_class_shadowed_13_re = addr_hit[147] & reg_re & !reg_error; - assign alert_class_shadowed_13_we = addr_hit[147] & reg_we & !reg_error; + assign alert_class_shadowed_13_re = addr_hit[157] & reg_re & !reg_error; + assign alert_class_shadowed_13_we = addr_hit[157] & reg_we & !reg_error; assign alert_class_shadowed_13_wd = reg_wdata[1:0]; - assign alert_class_shadowed_14_re = addr_hit[148] & reg_re & !reg_error; - assign alert_class_shadowed_14_we = addr_hit[148] & reg_we & !reg_error; + assign alert_class_shadowed_14_re = addr_hit[158] & reg_re & !reg_error; + assign alert_class_shadowed_14_we = addr_hit[158] & reg_we & !reg_error; assign alert_class_shadowed_14_wd = reg_wdata[1:0]; - assign alert_class_shadowed_15_re = addr_hit[149] & reg_re & !reg_error; - assign alert_class_shadowed_15_we = addr_hit[149] & reg_we & !reg_error; + assign alert_class_shadowed_15_re = addr_hit[159] & reg_re & !reg_error; + assign alert_class_shadowed_15_we = addr_hit[159] & reg_we & !reg_error; assign alert_class_shadowed_15_wd = reg_wdata[1:0]; - assign alert_class_shadowed_16_re = addr_hit[150] & reg_re & !reg_error; - assign alert_class_shadowed_16_we = addr_hit[150] & reg_we & !reg_error; + assign alert_class_shadowed_16_re = addr_hit[160] & reg_re & !reg_error; + assign alert_class_shadowed_16_we = addr_hit[160] & reg_we & !reg_error; assign alert_class_shadowed_16_wd = reg_wdata[1:0]; - assign alert_class_shadowed_17_re = addr_hit[151] & reg_re & !reg_error; - assign alert_class_shadowed_17_we = addr_hit[151] & reg_we & !reg_error; + assign alert_class_shadowed_17_re = addr_hit[161] & reg_re & !reg_error; + assign alert_class_shadowed_17_we = addr_hit[161] & reg_we & !reg_error; assign alert_class_shadowed_17_wd = reg_wdata[1:0]; - assign alert_class_shadowed_18_re = addr_hit[152] & reg_re & !reg_error; - assign alert_class_shadowed_18_we = addr_hit[152] & reg_we & !reg_error; + assign alert_class_shadowed_18_re = addr_hit[162] & reg_re & !reg_error; + assign alert_class_shadowed_18_we = addr_hit[162] & reg_we & !reg_error; assign alert_class_shadowed_18_wd = reg_wdata[1:0]; - assign alert_class_shadowed_19_re = addr_hit[153] & reg_re & !reg_error; - assign alert_class_shadowed_19_we = addr_hit[153] & reg_we & !reg_error; + assign alert_class_shadowed_19_re = addr_hit[163] & reg_re & !reg_error; + assign alert_class_shadowed_19_we = addr_hit[163] & reg_we & !reg_error; assign alert_class_shadowed_19_wd = reg_wdata[1:0]; - assign alert_class_shadowed_20_re = addr_hit[154] & reg_re & !reg_error; - assign alert_class_shadowed_20_we = addr_hit[154] & reg_we & !reg_error; + assign alert_class_shadowed_20_re = addr_hit[164] & reg_re & !reg_error; + assign alert_class_shadowed_20_we = addr_hit[164] & reg_we & !reg_error; assign alert_class_shadowed_20_wd = reg_wdata[1:0]; - assign alert_class_shadowed_21_re = addr_hit[155] & reg_re & !reg_error; - assign alert_class_shadowed_21_we = addr_hit[155] & reg_we & !reg_error; + assign alert_class_shadowed_21_re = addr_hit[165] & reg_re & !reg_error; + assign alert_class_shadowed_21_we = addr_hit[165] & reg_we & !reg_error; assign alert_class_shadowed_21_wd = reg_wdata[1:0]; - assign alert_class_shadowed_22_re = addr_hit[156] & reg_re & !reg_error; - assign alert_class_shadowed_22_we = addr_hit[156] & reg_we & !reg_error; + assign alert_class_shadowed_22_re = addr_hit[166] & reg_re & !reg_error; + assign alert_class_shadowed_22_we = addr_hit[166] & reg_we & !reg_error; assign alert_class_shadowed_22_wd = reg_wdata[1:0]; - assign alert_class_shadowed_23_re = addr_hit[157] & reg_re & !reg_error; - assign alert_class_shadowed_23_we = addr_hit[157] & reg_we & !reg_error; + assign alert_class_shadowed_23_re = addr_hit[167] & reg_re & !reg_error; + assign alert_class_shadowed_23_we = addr_hit[167] & reg_we & !reg_error; assign alert_class_shadowed_23_wd = reg_wdata[1:0]; - assign alert_class_shadowed_24_re = addr_hit[158] & reg_re & !reg_error; - assign alert_class_shadowed_24_we = addr_hit[158] & reg_we & !reg_error; + assign alert_class_shadowed_24_re = addr_hit[168] & reg_re & !reg_error; + assign alert_class_shadowed_24_we = addr_hit[168] & reg_we & !reg_error; assign alert_class_shadowed_24_wd = reg_wdata[1:0]; - assign alert_class_shadowed_25_re = addr_hit[159] & reg_re & !reg_error; - assign alert_class_shadowed_25_we = addr_hit[159] & reg_we & !reg_error; + assign alert_class_shadowed_25_re = addr_hit[169] & reg_re & !reg_error; + assign alert_class_shadowed_25_we = addr_hit[169] & reg_we & !reg_error; assign alert_class_shadowed_25_wd = reg_wdata[1:0]; - assign alert_class_shadowed_26_re = addr_hit[160] & reg_re & !reg_error; - assign alert_class_shadowed_26_we = addr_hit[160] & reg_we & !reg_error; + assign alert_class_shadowed_26_re = addr_hit[170] & reg_re & !reg_error; + assign alert_class_shadowed_26_we = addr_hit[170] & reg_we & !reg_error; assign alert_class_shadowed_26_wd = reg_wdata[1:0]; - assign alert_class_shadowed_27_re = addr_hit[161] & reg_re & !reg_error; - assign alert_class_shadowed_27_we = addr_hit[161] & reg_we & !reg_error; + assign alert_class_shadowed_27_re = addr_hit[171] & reg_re & !reg_error; + assign alert_class_shadowed_27_we = addr_hit[171] & reg_we & !reg_error; assign alert_class_shadowed_27_wd = reg_wdata[1:0]; - assign alert_class_shadowed_28_re = addr_hit[162] & reg_re & !reg_error; - assign alert_class_shadowed_28_we = addr_hit[162] & reg_we & !reg_error; + assign alert_class_shadowed_28_re = addr_hit[172] & reg_re & !reg_error; + assign alert_class_shadowed_28_we = addr_hit[172] & reg_we & !reg_error; assign alert_class_shadowed_28_wd = reg_wdata[1:0]; - assign alert_class_shadowed_29_re = addr_hit[163] & reg_re & !reg_error; - assign alert_class_shadowed_29_we = addr_hit[163] & reg_we & !reg_error; + assign alert_class_shadowed_29_re = addr_hit[173] & reg_re & !reg_error; + assign alert_class_shadowed_29_we = addr_hit[173] & reg_we & !reg_error; assign alert_class_shadowed_29_wd = reg_wdata[1:0]; - assign alert_class_shadowed_30_re = addr_hit[164] & reg_re & !reg_error; - assign alert_class_shadowed_30_we = addr_hit[164] & reg_we & !reg_error; + assign alert_class_shadowed_30_re = addr_hit[174] & reg_re & !reg_error; + assign alert_class_shadowed_30_we = addr_hit[174] & reg_we & !reg_error; assign alert_class_shadowed_30_wd = reg_wdata[1:0]; - assign alert_class_shadowed_31_re = addr_hit[165] & reg_re & !reg_error; - assign alert_class_shadowed_31_we = addr_hit[165] & reg_we & !reg_error; + assign alert_class_shadowed_31_re = addr_hit[175] & reg_re & !reg_error; + assign alert_class_shadowed_31_we = addr_hit[175] & reg_we & !reg_error; assign alert_class_shadowed_31_wd = reg_wdata[1:0]; - assign alert_class_shadowed_32_re = addr_hit[166] & reg_re & !reg_error; - assign alert_class_shadowed_32_we = addr_hit[166] & reg_we & !reg_error; + assign alert_class_shadowed_32_re = addr_hit[176] & reg_re & !reg_error; + assign alert_class_shadowed_32_we = addr_hit[176] & reg_we & !reg_error; assign alert_class_shadowed_32_wd = reg_wdata[1:0]; - assign alert_class_shadowed_33_re = addr_hit[167] & reg_re & !reg_error; - assign alert_class_shadowed_33_we = addr_hit[167] & reg_we & !reg_error; + assign alert_class_shadowed_33_re = addr_hit[177] & reg_re & !reg_error; + assign alert_class_shadowed_33_we = addr_hit[177] & reg_we & !reg_error; assign alert_class_shadowed_33_wd = reg_wdata[1:0]; - assign alert_class_shadowed_34_re = addr_hit[168] & reg_re & !reg_error; - assign alert_class_shadowed_34_we = addr_hit[168] & reg_we & !reg_error; + assign alert_class_shadowed_34_re = addr_hit[178] & reg_re & !reg_error; + assign alert_class_shadowed_34_we = addr_hit[178] & reg_we & !reg_error; assign alert_class_shadowed_34_wd = reg_wdata[1:0]; - assign alert_class_shadowed_35_re = addr_hit[169] & reg_re & !reg_error; - assign alert_class_shadowed_35_we = addr_hit[169] & reg_we & !reg_error; + assign alert_class_shadowed_35_re = addr_hit[179] & reg_re & !reg_error; + assign alert_class_shadowed_35_we = addr_hit[179] & reg_we & !reg_error; assign alert_class_shadowed_35_wd = reg_wdata[1:0]; - assign alert_class_shadowed_36_re = addr_hit[170] & reg_re & !reg_error; - assign alert_class_shadowed_36_we = addr_hit[170] & reg_we & !reg_error; + assign alert_class_shadowed_36_re = addr_hit[180] & reg_re & !reg_error; + assign alert_class_shadowed_36_we = addr_hit[180] & reg_we & !reg_error; assign alert_class_shadowed_36_wd = reg_wdata[1:0]; - assign alert_class_shadowed_37_re = addr_hit[171] & reg_re & !reg_error; - assign alert_class_shadowed_37_we = addr_hit[171] & reg_we & !reg_error; + assign alert_class_shadowed_37_re = addr_hit[181] & reg_re & !reg_error; + assign alert_class_shadowed_37_we = addr_hit[181] & reg_we & !reg_error; assign alert_class_shadowed_37_wd = reg_wdata[1:0]; - assign alert_class_shadowed_38_re = addr_hit[172] & reg_re & !reg_error; - assign alert_class_shadowed_38_we = addr_hit[172] & reg_we & !reg_error; + assign alert_class_shadowed_38_re = addr_hit[182] & reg_re & !reg_error; + assign alert_class_shadowed_38_we = addr_hit[182] & reg_we & !reg_error; assign alert_class_shadowed_38_wd = reg_wdata[1:0]; - assign alert_class_shadowed_39_re = addr_hit[173] & reg_re & !reg_error; - assign alert_class_shadowed_39_we = addr_hit[173] & reg_we & !reg_error; + assign alert_class_shadowed_39_re = addr_hit[183] & reg_re & !reg_error; + assign alert_class_shadowed_39_we = addr_hit[183] & reg_we & !reg_error; assign alert_class_shadowed_39_wd = reg_wdata[1:0]; - assign alert_class_shadowed_40_re = addr_hit[174] & reg_re & !reg_error; - assign alert_class_shadowed_40_we = addr_hit[174] & reg_we & !reg_error; + assign alert_class_shadowed_40_re = addr_hit[184] & reg_re & !reg_error; + assign alert_class_shadowed_40_we = addr_hit[184] & reg_we & !reg_error; assign alert_class_shadowed_40_wd = reg_wdata[1:0]; - assign alert_class_shadowed_41_re = addr_hit[175] & reg_re & !reg_error; - assign alert_class_shadowed_41_we = addr_hit[175] & reg_we & !reg_error; + assign alert_class_shadowed_41_re = addr_hit[185] & reg_re & !reg_error; + assign alert_class_shadowed_41_we = addr_hit[185] & reg_we & !reg_error; assign alert_class_shadowed_41_wd = reg_wdata[1:0]; - assign alert_class_shadowed_42_re = addr_hit[176] & reg_re & !reg_error; - assign alert_class_shadowed_42_we = addr_hit[176] & reg_we & !reg_error; + assign alert_class_shadowed_42_re = addr_hit[186] & reg_re & !reg_error; + assign alert_class_shadowed_42_we = addr_hit[186] & reg_we & !reg_error; assign alert_class_shadowed_42_wd = reg_wdata[1:0]; - assign alert_class_shadowed_43_re = addr_hit[177] & reg_re & !reg_error; - assign alert_class_shadowed_43_we = addr_hit[177] & reg_we & !reg_error; + assign alert_class_shadowed_43_re = addr_hit[187] & reg_re & !reg_error; + assign alert_class_shadowed_43_we = addr_hit[187] & reg_we & !reg_error; assign alert_class_shadowed_43_wd = reg_wdata[1:0]; - assign alert_class_shadowed_44_re = addr_hit[178] & reg_re & !reg_error; - assign alert_class_shadowed_44_we = addr_hit[178] & reg_we & !reg_error; + assign alert_class_shadowed_44_re = addr_hit[188] & reg_re & !reg_error; + assign alert_class_shadowed_44_we = addr_hit[188] & reg_we & !reg_error; assign alert_class_shadowed_44_wd = reg_wdata[1:0]; - assign alert_class_shadowed_45_re = addr_hit[179] & reg_re & !reg_error; - assign alert_class_shadowed_45_we = addr_hit[179] & reg_we & !reg_error; + assign alert_class_shadowed_45_re = addr_hit[189] & reg_re & !reg_error; + assign alert_class_shadowed_45_we = addr_hit[189] & reg_we & !reg_error; assign alert_class_shadowed_45_wd = reg_wdata[1:0]; - assign alert_class_shadowed_46_re = addr_hit[180] & reg_re & !reg_error; - assign alert_class_shadowed_46_we = addr_hit[180] & reg_we & !reg_error; + assign alert_class_shadowed_46_re = addr_hit[190] & reg_re & !reg_error; + assign alert_class_shadowed_46_we = addr_hit[190] & reg_we & !reg_error; assign alert_class_shadowed_46_wd = reg_wdata[1:0]; - assign alert_class_shadowed_47_re = addr_hit[181] & reg_re & !reg_error; - assign alert_class_shadowed_47_we = addr_hit[181] & reg_we & !reg_error; + assign alert_class_shadowed_47_re = addr_hit[191] & reg_re & !reg_error; + assign alert_class_shadowed_47_we = addr_hit[191] & reg_we & !reg_error; assign alert_class_shadowed_47_wd = reg_wdata[1:0]; - assign alert_class_shadowed_48_re = addr_hit[182] & reg_re & !reg_error; - assign alert_class_shadowed_48_we = addr_hit[182] & reg_we & !reg_error; + assign alert_class_shadowed_48_re = addr_hit[192] & reg_re & !reg_error; + assign alert_class_shadowed_48_we = addr_hit[192] & reg_we & !reg_error; assign alert_class_shadowed_48_wd = reg_wdata[1:0]; - assign alert_class_shadowed_49_re = addr_hit[183] & reg_re & !reg_error; - assign alert_class_shadowed_49_we = addr_hit[183] & reg_we & !reg_error; + assign alert_class_shadowed_49_re = addr_hit[193] & reg_re & !reg_error; + assign alert_class_shadowed_49_we = addr_hit[193] & reg_we & !reg_error; assign alert_class_shadowed_49_wd = reg_wdata[1:0]; - assign alert_class_shadowed_50_re = addr_hit[184] & reg_re & !reg_error; - assign alert_class_shadowed_50_we = addr_hit[184] & reg_we & !reg_error; + assign alert_class_shadowed_50_re = addr_hit[194] & reg_re & !reg_error; + assign alert_class_shadowed_50_we = addr_hit[194] & reg_we & !reg_error; assign alert_class_shadowed_50_wd = reg_wdata[1:0]; - assign alert_class_shadowed_51_re = addr_hit[185] & reg_re & !reg_error; - assign alert_class_shadowed_51_we = addr_hit[185] & reg_we & !reg_error; + assign alert_class_shadowed_51_re = addr_hit[195] & reg_re & !reg_error; + assign alert_class_shadowed_51_we = addr_hit[195] & reg_we & !reg_error; assign alert_class_shadowed_51_wd = reg_wdata[1:0]; - assign alert_class_shadowed_52_re = addr_hit[186] & reg_re & !reg_error; - assign alert_class_shadowed_52_we = addr_hit[186] & reg_we & !reg_error; + assign alert_class_shadowed_52_re = addr_hit[196] & reg_re & !reg_error; + assign alert_class_shadowed_52_we = addr_hit[196] & reg_we & !reg_error; assign alert_class_shadowed_52_wd = reg_wdata[1:0]; - assign alert_class_shadowed_53_re = addr_hit[187] & reg_re & !reg_error; - assign alert_class_shadowed_53_we = addr_hit[187] & reg_we & !reg_error; + assign alert_class_shadowed_53_re = addr_hit[197] & reg_re & !reg_error; + assign alert_class_shadowed_53_we = addr_hit[197] & reg_we & !reg_error; assign alert_class_shadowed_53_wd = reg_wdata[1:0]; - assign alert_class_shadowed_54_re = addr_hit[188] & reg_re & !reg_error; - assign alert_class_shadowed_54_we = addr_hit[188] & reg_we & !reg_error; + assign alert_class_shadowed_54_re = addr_hit[198] & reg_re & !reg_error; + assign alert_class_shadowed_54_we = addr_hit[198] & reg_we & !reg_error; assign alert_class_shadowed_54_wd = reg_wdata[1:0]; - assign alert_class_shadowed_55_re = addr_hit[189] & reg_re & !reg_error; - assign alert_class_shadowed_55_we = addr_hit[189] & reg_we & !reg_error; + assign alert_class_shadowed_55_re = addr_hit[199] & reg_re & !reg_error; + assign alert_class_shadowed_55_we = addr_hit[199] & reg_we & !reg_error; assign alert_class_shadowed_55_wd = reg_wdata[1:0]; - assign alert_class_shadowed_56_re = addr_hit[190] & reg_re & !reg_error; - assign alert_class_shadowed_56_we = addr_hit[190] & reg_we & !reg_error; + assign alert_class_shadowed_56_re = addr_hit[200] & reg_re & !reg_error; + assign alert_class_shadowed_56_we = addr_hit[200] & reg_we & !reg_error; assign alert_class_shadowed_56_wd = reg_wdata[1:0]; - assign alert_class_shadowed_57_re = addr_hit[191] & reg_re & !reg_error; - assign alert_class_shadowed_57_we = addr_hit[191] & reg_we & !reg_error; + assign alert_class_shadowed_57_re = addr_hit[201] & reg_re & !reg_error; + assign alert_class_shadowed_57_we = addr_hit[201] & reg_we & !reg_error; assign alert_class_shadowed_57_wd = reg_wdata[1:0]; - assign alert_class_shadowed_58_re = addr_hit[192] & reg_re & !reg_error; - assign alert_class_shadowed_58_we = addr_hit[192] & reg_we & !reg_error; + assign alert_class_shadowed_58_re = addr_hit[202] & reg_re & !reg_error; + assign alert_class_shadowed_58_we = addr_hit[202] & reg_we & !reg_error; assign alert_class_shadowed_58_wd = reg_wdata[1:0]; - assign alert_class_shadowed_59_re = addr_hit[193] & reg_re & !reg_error; - assign alert_class_shadowed_59_we = addr_hit[193] & reg_we & !reg_error; + assign alert_class_shadowed_59_re = addr_hit[203] & reg_re & !reg_error; + assign alert_class_shadowed_59_we = addr_hit[203] & reg_we & !reg_error; assign alert_class_shadowed_59_wd = reg_wdata[1:0]; - assign alert_class_shadowed_60_re = addr_hit[194] & reg_re & !reg_error; - assign alert_class_shadowed_60_we = addr_hit[194] & reg_we & !reg_error; + assign alert_class_shadowed_60_re = addr_hit[204] & reg_re & !reg_error; + assign alert_class_shadowed_60_we = addr_hit[204] & reg_we & !reg_error; assign alert_class_shadowed_60_wd = reg_wdata[1:0]; - assign alert_class_shadowed_61_re = addr_hit[195] & reg_re & !reg_error; - assign alert_class_shadowed_61_we = addr_hit[195] & reg_we & !reg_error; + assign alert_class_shadowed_61_re = addr_hit[205] & reg_re & !reg_error; + assign alert_class_shadowed_61_we = addr_hit[205] & reg_we & !reg_error; assign alert_class_shadowed_61_wd = reg_wdata[1:0]; - assign alert_class_shadowed_62_re = addr_hit[196] & reg_re & !reg_error; - assign alert_class_shadowed_62_we = addr_hit[196] & reg_we & !reg_error; + assign alert_class_shadowed_62_re = addr_hit[206] & reg_re & !reg_error; + assign alert_class_shadowed_62_we = addr_hit[206] & reg_we & !reg_error; assign alert_class_shadowed_62_wd = reg_wdata[1:0]; - assign alert_class_shadowed_63_re = addr_hit[197] & reg_re & !reg_error; - assign alert_class_shadowed_63_we = addr_hit[197] & reg_we & !reg_error; + assign alert_class_shadowed_63_re = addr_hit[207] & reg_re & !reg_error; + assign alert_class_shadowed_63_we = addr_hit[207] & reg_we & !reg_error; assign alert_class_shadowed_63_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[198] & reg_we & !reg_error; + assign alert_class_shadowed_64_re = addr_hit[208] & reg_re & !reg_error; + assign alert_class_shadowed_64_we = addr_hit[208] & reg_we & !reg_error; + + assign alert_class_shadowed_64_wd = reg_wdata[1:0]; + assign alert_class_shadowed_65_re = addr_hit[209] & reg_re & !reg_error; + assign alert_class_shadowed_65_we = addr_hit[209] & reg_we & !reg_error; + + assign alert_class_shadowed_65_wd = reg_wdata[1:0]; + assign alert_class_shadowed_66_re = addr_hit[210] & reg_re & !reg_error; + assign alert_class_shadowed_66_we = addr_hit[210] & reg_we & !reg_error; + + assign alert_class_shadowed_66_wd = reg_wdata[1:0]; + assign alert_class_shadowed_67_re = addr_hit[211] & reg_re & !reg_error; + assign alert_class_shadowed_67_we = addr_hit[211] & reg_we & !reg_error; + + assign alert_class_shadowed_67_wd = reg_wdata[1:0]; + assign alert_class_shadowed_68_re = addr_hit[212] & reg_re & !reg_error; + assign alert_class_shadowed_68_we = addr_hit[212] & reg_we & !reg_error; + + assign alert_class_shadowed_68_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[213] & reg_we & !reg_error; assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[199] & reg_we & !reg_error; + assign alert_cause_1_we = addr_hit[214] & reg_we & !reg_error; assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[200] & reg_we & !reg_error; + assign alert_cause_2_we = addr_hit[215] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[201] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[216] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[202] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[217] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[203] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[218] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[204] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[219] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[205] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[220] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[206] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[221] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[207] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[222] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[208] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[223] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[209] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[224] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[210] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[225] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[211] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[226] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[212] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[227] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[213] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[228] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[214] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[229] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[215] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[230] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[216] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[231] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[217] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[232] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[218] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[233] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[219] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[234] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[220] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[235] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[221] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[236] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[222] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[237] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[223] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[238] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[224] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[239] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[225] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[240] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[226] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[241] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[227] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[242] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[228] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[243] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign alert_cause_31_we = addr_hit[229] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[244] & reg_we & !reg_error; assign alert_cause_31_wd = reg_wdata[0]; - assign alert_cause_32_we = addr_hit[230] & reg_we & !reg_error; + assign alert_cause_32_we = addr_hit[245] & reg_we & !reg_error; assign alert_cause_32_wd = reg_wdata[0]; - assign alert_cause_33_we = addr_hit[231] & reg_we & !reg_error; + assign alert_cause_33_we = addr_hit[246] & reg_we & !reg_error; assign alert_cause_33_wd = reg_wdata[0]; - assign alert_cause_34_we = addr_hit[232] & reg_we & !reg_error; + assign alert_cause_34_we = addr_hit[247] & reg_we & !reg_error; assign alert_cause_34_wd = reg_wdata[0]; - assign alert_cause_35_we = addr_hit[233] & reg_we & !reg_error; + assign alert_cause_35_we = addr_hit[248] & reg_we & !reg_error; assign alert_cause_35_wd = reg_wdata[0]; - assign alert_cause_36_we = addr_hit[234] & reg_we & !reg_error; + assign alert_cause_36_we = addr_hit[249] & reg_we & !reg_error; assign alert_cause_36_wd = reg_wdata[0]; - assign alert_cause_37_we = addr_hit[235] & reg_we & !reg_error; + assign alert_cause_37_we = addr_hit[250] & reg_we & !reg_error; assign alert_cause_37_wd = reg_wdata[0]; - assign alert_cause_38_we = addr_hit[236] & reg_we & !reg_error; + assign alert_cause_38_we = addr_hit[251] & reg_we & !reg_error; assign alert_cause_38_wd = reg_wdata[0]; - assign alert_cause_39_we = addr_hit[237] & reg_we & !reg_error; + assign alert_cause_39_we = addr_hit[252] & reg_we & !reg_error; assign alert_cause_39_wd = reg_wdata[0]; - assign alert_cause_40_we = addr_hit[238] & reg_we & !reg_error; + assign alert_cause_40_we = addr_hit[253] & reg_we & !reg_error; assign alert_cause_40_wd = reg_wdata[0]; - assign alert_cause_41_we = addr_hit[239] & reg_we & !reg_error; + assign alert_cause_41_we = addr_hit[254] & reg_we & !reg_error; assign alert_cause_41_wd = reg_wdata[0]; - assign alert_cause_42_we = addr_hit[240] & reg_we & !reg_error; + assign alert_cause_42_we = addr_hit[255] & reg_we & !reg_error; assign alert_cause_42_wd = reg_wdata[0]; - assign alert_cause_43_we = addr_hit[241] & reg_we & !reg_error; + assign alert_cause_43_we = addr_hit[256] & reg_we & !reg_error; assign alert_cause_43_wd = reg_wdata[0]; - assign alert_cause_44_we = addr_hit[242] & reg_we & !reg_error; + assign alert_cause_44_we = addr_hit[257] & reg_we & !reg_error; assign alert_cause_44_wd = reg_wdata[0]; - assign alert_cause_45_we = addr_hit[243] & reg_we & !reg_error; + assign alert_cause_45_we = addr_hit[258] & reg_we & !reg_error; assign alert_cause_45_wd = reg_wdata[0]; - assign alert_cause_46_we = addr_hit[244] & reg_we & !reg_error; + assign alert_cause_46_we = addr_hit[259] & reg_we & !reg_error; assign alert_cause_46_wd = reg_wdata[0]; - assign alert_cause_47_we = addr_hit[245] & reg_we & !reg_error; + assign alert_cause_47_we = addr_hit[260] & reg_we & !reg_error; assign alert_cause_47_wd = reg_wdata[0]; - assign alert_cause_48_we = addr_hit[246] & reg_we & !reg_error; + assign alert_cause_48_we = addr_hit[261] & reg_we & !reg_error; assign alert_cause_48_wd = reg_wdata[0]; - assign alert_cause_49_we = addr_hit[247] & reg_we & !reg_error; + assign alert_cause_49_we = addr_hit[262] & reg_we & !reg_error; assign alert_cause_49_wd = reg_wdata[0]; - assign alert_cause_50_we = addr_hit[248] & reg_we & !reg_error; + assign alert_cause_50_we = addr_hit[263] & reg_we & !reg_error; assign alert_cause_50_wd = reg_wdata[0]; - assign alert_cause_51_we = addr_hit[249] & reg_we & !reg_error; + assign alert_cause_51_we = addr_hit[264] & reg_we & !reg_error; assign alert_cause_51_wd = reg_wdata[0]; - assign alert_cause_52_we = addr_hit[250] & reg_we & !reg_error; + assign alert_cause_52_we = addr_hit[265] & reg_we & !reg_error; assign alert_cause_52_wd = reg_wdata[0]; - assign alert_cause_53_we = addr_hit[251] & reg_we & !reg_error; + assign alert_cause_53_we = addr_hit[266] & reg_we & !reg_error; assign alert_cause_53_wd = reg_wdata[0]; - assign alert_cause_54_we = addr_hit[252] & reg_we & !reg_error; + assign alert_cause_54_we = addr_hit[267] & reg_we & !reg_error; assign alert_cause_54_wd = reg_wdata[0]; - assign alert_cause_55_we = addr_hit[253] & reg_we & !reg_error; + assign alert_cause_55_we = addr_hit[268] & reg_we & !reg_error; assign alert_cause_55_wd = reg_wdata[0]; - assign alert_cause_56_we = addr_hit[254] & reg_we & !reg_error; + assign alert_cause_56_we = addr_hit[269] & reg_we & !reg_error; assign alert_cause_56_wd = reg_wdata[0]; - assign alert_cause_57_we = addr_hit[255] & reg_we & !reg_error; + assign alert_cause_57_we = addr_hit[270] & reg_we & !reg_error; assign alert_cause_57_wd = reg_wdata[0]; - assign alert_cause_58_we = addr_hit[256] & reg_we & !reg_error; + assign alert_cause_58_we = addr_hit[271] & reg_we & !reg_error; assign alert_cause_58_wd = reg_wdata[0]; - assign alert_cause_59_we = addr_hit[257] & reg_we & !reg_error; + assign alert_cause_59_we = addr_hit[272] & reg_we & !reg_error; assign alert_cause_59_wd = reg_wdata[0]; - assign alert_cause_60_we = addr_hit[258] & reg_we & !reg_error; + assign alert_cause_60_we = addr_hit[273] & reg_we & !reg_error; assign alert_cause_60_wd = reg_wdata[0]; - assign alert_cause_61_we = addr_hit[259] & reg_we & !reg_error; + assign alert_cause_61_we = addr_hit[274] & reg_we & !reg_error; assign alert_cause_61_wd = reg_wdata[0]; - assign alert_cause_62_we = addr_hit[260] & reg_we & !reg_error; + assign alert_cause_62_we = addr_hit[275] & reg_we & !reg_error; assign alert_cause_62_wd = reg_wdata[0]; - assign alert_cause_63_we = addr_hit[261] & reg_we & !reg_error; + assign alert_cause_63_we = addr_hit[276] & reg_we & !reg_error; assign alert_cause_63_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[262] & reg_we & !reg_error; + assign alert_cause_64_we = addr_hit[277] & reg_we & !reg_error; + + assign alert_cause_64_wd = reg_wdata[0]; + assign alert_cause_65_we = addr_hit[278] & reg_we & !reg_error; + + assign alert_cause_65_wd = reg_wdata[0]; + assign alert_cause_66_we = addr_hit[279] & reg_we & !reg_error; + + assign alert_cause_66_wd = reg_wdata[0]; + assign alert_cause_67_we = addr_hit[280] & reg_we & !reg_error; + + assign alert_cause_67_wd = reg_wdata[0]; + assign alert_cause_68_we = addr_hit[281] & reg_we & !reg_error; + + assign alert_cause_68_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[282] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[263] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[283] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[264] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[284] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[265] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[285] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[266] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[286] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_regwen_5_we = addr_hit[267] & reg_we & !reg_error; + assign loc_alert_regwen_5_we = addr_hit[287] & reg_we & !reg_error; assign loc_alert_regwen_5_wd = reg_wdata[0]; - assign loc_alert_regwen_6_we = addr_hit[268] & reg_we & !reg_error; + assign loc_alert_regwen_6_we = addr_hit[288] & reg_we & !reg_error; assign loc_alert_regwen_6_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_0_re = addr_hit[269] & reg_re & !reg_error; - assign loc_alert_en_shadowed_0_we = addr_hit[269] & reg_we & !reg_error; + assign loc_alert_en_shadowed_0_re = addr_hit[289] & reg_re & !reg_error; + assign loc_alert_en_shadowed_0_we = addr_hit[289] & reg_we & !reg_error; assign loc_alert_en_shadowed_0_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_1_re = addr_hit[270] & reg_re & !reg_error; - assign loc_alert_en_shadowed_1_we = addr_hit[270] & reg_we & !reg_error; + assign loc_alert_en_shadowed_1_re = addr_hit[290] & reg_re & !reg_error; + assign loc_alert_en_shadowed_1_we = addr_hit[290] & reg_we & !reg_error; assign loc_alert_en_shadowed_1_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_2_re = addr_hit[271] & reg_re & !reg_error; - assign loc_alert_en_shadowed_2_we = addr_hit[271] & reg_we & !reg_error; + assign loc_alert_en_shadowed_2_re = addr_hit[291] & reg_re & !reg_error; + assign loc_alert_en_shadowed_2_we = addr_hit[291] & reg_we & !reg_error; assign loc_alert_en_shadowed_2_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_3_re = addr_hit[272] & reg_re & !reg_error; - assign loc_alert_en_shadowed_3_we = addr_hit[272] & reg_we & !reg_error; + assign loc_alert_en_shadowed_3_re = addr_hit[292] & reg_re & !reg_error; + assign loc_alert_en_shadowed_3_we = addr_hit[292] & reg_we & !reg_error; assign loc_alert_en_shadowed_3_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_4_re = addr_hit[273] & reg_re & !reg_error; - assign loc_alert_en_shadowed_4_we = addr_hit[273] & reg_we & !reg_error; + assign loc_alert_en_shadowed_4_re = addr_hit[293] & reg_re & !reg_error; + assign loc_alert_en_shadowed_4_we = addr_hit[293] & reg_we & !reg_error; assign loc_alert_en_shadowed_4_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_5_re = addr_hit[274] & reg_re & !reg_error; - assign loc_alert_en_shadowed_5_we = addr_hit[274] & reg_we & !reg_error; + assign loc_alert_en_shadowed_5_re = addr_hit[294] & reg_re & !reg_error; + assign loc_alert_en_shadowed_5_we = addr_hit[294] & reg_we & !reg_error; assign loc_alert_en_shadowed_5_wd = reg_wdata[0]; - assign loc_alert_en_shadowed_6_re = addr_hit[275] & reg_re & !reg_error; - assign loc_alert_en_shadowed_6_we = addr_hit[275] & reg_we & !reg_error; + assign loc_alert_en_shadowed_6_re = addr_hit[295] & reg_re & !reg_error; + assign loc_alert_en_shadowed_6_we = addr_hit[295] & reg_we & !reg_error; assign loc_alert_en_shadowed_6_wd = reg_wdata[0]; - assign loc_alert_class_shadowed_0_re = addr_hit[276] & reg_re & !reg_error; - assign loc_alert_class_shadowed_0_we = addr_hit[276] & reg_we & !reg_error; + assign loc_alert_class_shadowed_0_re = addr_hit[296] & reg_re & !reg_error; + assign loc_alert_class_shadowed_0_we = addr_hit[296] & reg_we & !reg_error; assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_1_re = addr_hit[277] & reg_re & !reg_error; - assign loc_alert_class_shadowed_1_we = addr_hit[277] & reg_we & !reg_error; + assign loc_alert_class_shadowed_1_re = addr_hit[297] & reg_re & !reg_error; + assign loc_alert_class_shadowed_1_we = addr_hit[297] & reg_we & !reg_error; assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_2_re = addr_hit[278] & reg_re & !reg_error; - assign loc_alert_class_shadowed_2_we = addr_hit[278] & reg_we & !reg_error; + assign loc_alert_class_shadowed_2_re = addr_hit[298] & reg_re & !reg_error; + assign loc_alert_class_shadowed_2_we = addr_hit[298] & reg_we & !reg_error; assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_3_re = addr_hit[279] & reg_re & !reg_error; - assign loc_alert_class_shadowed_3_we = addr_hit[279] & reg_we & !reg_error; + assign loc_alert_class_shadowed_3_re = addr_hit[299] & reg_re & !reg_error; + assign loc_alert_class_shadowed_3_we = addr_hit[299] & reg_we & !reg_error; assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_4_re = addr_hit[280] & reg_re & !reg_error; - assign loc_alert_class_shadowed_4_we = addr_hit[280] & reg_we & !reg_error; + assign loc_alert_class_shadowed_4_re = addr_hit[300] & reg_re & !reg_error; + assign loc_alert_class_shadowed_4_we = addr_hit[300] & reg_we & !reg_error; assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_5_re = addr_hit[281] & reg_re & !reg_error; - assign loc_alert_class_shadowed_5_we = addr_hit[281] & reg_we & !reg_error; + assign loc_alert_class_shadowed_5_re = addr_hit[301] & reg_re & !reg_error; + assign loc_alert_class_shadowed_5_we = addr_hit[301] & reg_we & !reg_error; assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0]; - assign loc_alert_class_shadowed_6_re = addr_hit[282] & reg_re & !reg_error; - assign loc_alert_class_shadowed_6_we = addr_hit[282] & reg_we & !reg_error; + assign loc_alert_class_shadowed_6_re = addr_hit[302] & reg_re & !reg_error; + assign loc_alert_class_shadowed_6_we = addr_hit[302] & reg_we & !reg_error; assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[283] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[303] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[284] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[304] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[285] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[305] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[286] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[306] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign loc_alert_cause_4_we = addr_hit[287] & reg_we & !reg_error; + assign loc_alert_cause_4_we = addr_hit[307] & reg_we & !reg_error; assign loc_alert_cause_4_wd = reg_wdata[0]; - assign loc_alert_cause_5_we = addr_hit[288] & reg_we & !reg_error; + assign loc_alert_cause_5_we = addr_hit[308] & reg_we & !reg_error; assign loc_alert_cause_5_wd = reg_wdata[0]; - assign loc_alert_cause_6_we = addr_hit[289] & reg_we & !reg_error; + assign loc_alert_cause_6_we = addr_hit[309] & reg_we & !reg_error; assign loc_alert_cause_6_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[290] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[310] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_shadowed_re = addr_hit[291] & reg_re & !reg_error; - assign classa_ctrl_shadowed_we = addr_hit[291] & reg_we & !reg_error; + assign classa_ctrl_shadowed_re = addr_hit[311] & reg_re & !reg_error; + assign classa_ctrl_shadowed_we = addr_hit[311] & reg_we & !reg_error; assign classa_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17165,49 +18065,49 @@ module alert_handler_reg_top ( assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[292] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[312] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_shadowed_re = addr_hit[293] & reg_re & !reg_error; - assign classa_clr_shadowed_we = addr_hit[293] & reg_we & !reg_error; + assign classa_clr_shadowed_re = addr_hit[313] & reg_re & !reg_error; + assign classa_clr_shadowed_we = addr_hit[313] & reg_we & !reg_error; assign classa_clr_shadowed_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[294] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_re = addr_hit[295] & reg_re & !reg_error; - assign classa_accum_thresh_shadowed_we = addr_hit[295] & reg_we & !reg_error; + assign classa_accum_cnt_re = addr_hit[314] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_re = addr_hit[315] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_we = addr_hit[315] & reg_we & !reg_error; assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_shadowed_re = addr_hit[296] & reg_re & !reg_error; - assign classa_timeout_cyc_shadowed_we = addr_hit[296] & reg_we & !reg_error; + assign classa_timeout_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error; + assign classa_timeout_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error; assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_crashdump_trigger_shadowed_re = addr_hit[297] & reg_re & !reg_error; - assign classa_crashdump_trigger_shadowed_we = addr_hit[297] & reg_we & !reg_error; + assign classa_crashdump_trigger_shadowed_re = addr_hit[317] & reg_re & !reg_error; + assign classa_crashdump_trigger_shadowed_we = addr_hit[317] & reg_we & !reg_error; assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classa_phase0_cyc_shadowed_re = addr_hit[298] & reg_re & !reg_error; - assign classa_phase0_cyc_shadowed_we = addr_hit[298] & reg_we & !reg_error; + assign classa_phase0_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error; + assign classa_phase0_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error; assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_shadowed_re = addr_hit[299] & reg_re & !reg_error; - assign classa_phase1_cyc_shadowed_we = addr_hit[299] & reg_we & !reg_error; + assign classa_phase1_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error; + assign classa_phase1_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error; assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error; - assign classa_phase2_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error; + assign classa_phase2_cyc_shadowed_re = addr_hit[320] & reg_re & !reg_error; + assign classa_phase2_cyc_shadowed_we = addr_hit[320] & reg_we & !reg_error; assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_shadowed_re = addr_hit[301] & reg_re & !reg_error; - assign classa_phase3_cyc_shadowed_we = addr_hit[301] & reg_we & !reg_error; + assign classa_phase3_cyc_shadowed_re = addr_hit[321] & reg_re & !reg_error; + assign classa_phase3_cyc_shadowed_we = addr_hit[321] & reg_we & !reg_error; assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[302] & reg_re & !reg_error; - assign classa_state_re = addr_hit[303] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[304] & reg_we & !reg_error; + assign classa_esc_cnt_re = addr_hit[322] & reg_re & !reg_error; + assign classa_state_re = addr_hit[323] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[324] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_shadowed_re = addr_hit[305] & reg_re & !reg_error; - assign classb_ctrl_shadowed_we = addr_hit[305] & reg_we & !reg_error; + assign classb_ctrl_shadowed_re = addr_hit[325] & reg_re & !reg_error; + assign classb_ctrl_shadowed_we = addr_hit[325] & reg_we & !reg_error; assign classb_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17228,49 +18128,49 @@ module alert_handler_reg_top ( assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[306] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[326] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_shadowed_re = addr_hit[307] & reg_re & !reg_error; - assign classb_clr_shadowed_we = addr_hit[307] & reg_we & !reg_error; + assign classb_clr_shadowed_re = addr_hit[327] & reg_re & !reg_error; + assign classb_clr_shadowed_we = addr_hit[327] & reg_we & !reg_error; assign classb_clr_shadowed_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[308] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_re = addr_hit[309] & reg_re & !reg_error; - assign classb_accum_thresh_shadowed_we = addr_hit[309] & reg_we & !reg_error; + assign classb_accum_cnt_re = addr_hit[328] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_re = addr_hit[329] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_we = addr_hit[329] & reg_we & !reg_error; assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_shadowed_re = addr_hit[310] & reg_re & !reg_error; - assign classb_timeout_cyc_shadowed_we = addr_hit[310] & reg_we & !reg_error; + assign classb_timeout_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error; + assign classb_timeout_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error; assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_crashdump_trigger_shadowed_re = addr_hit[311] & reg_re & !reg_error; - assign classb_crashdump_trigger_shadowed_we = addr_hit[311] & reg_we & !reg_error; + assign classb_crashdump_trigger_shadowed_re = addr_hit[331] & reg_re & !reg_error; + assign classb_crashdump_trigger_shadowed_we = addr_hit[331] & reg_we & !reg_error; assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classb_phase0_cyc_shadowed_re = addr_hit[312] & reg_re & !reg_error; - assign classb_phase0_cyc_shadowed_we = addr_hit[312] & reg_we & !reg_error; + assign classb_phase0_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error; + assign classb_phase0_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error; assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_shadowed_re = addr_hit[313] & reg_re & !reg_error; - assign classb_phase1_cyc_shadowed_we = addr_hit[313] & reg_we & !reg_error; + assign classb_phase1_cyc_shadowed_re = addr_hit[333] & reg_re & !reg_error; + assign classb_phase1_cyc_shadowed_we = addr_hit[333] & reg_we & !reg_error; assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error; - assign classb_phase2_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error; + assign classb_phase2_cyc_shadowed_re = addr_hit[334] & reg_re & !reg_error; + assign classb_phase2_cyc_shadowed_we = addr_hit[334] & reg_we & !reg_error; assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_shadowed_re = addr_hit[315] & reg_re & !reg_error; - assign classb_phase3_cyc_shadowed_we = addr_hit[315] & reg_we & !reg_error; + assign classb_phase3_cyc_shadowed_re = addr_hit[335] & reg_re & !reg_error; + assign classb_phase3_cyc_shadowed_we = addr_hit[335] & reg_we & !reg_error; assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[316] & reg_re & !reg_error; - assign classb_state_re = addr_hit[317] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[318] & reg_we & !reg_error; + assign classb_esc_cnt_re = addr_hit[336] & reg_re & !reg_error; + assign classb_state_re = addr_hit[337] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[338] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_shadowed_re = addr_hit[319] & reg_re & !reg_error; - assign classc_ctrl_shadowed_we = addr_hit[319] & reg_we & !reg_error; + assign classc_ctrl_shadowed_re = addr_hit[339] & reg_re & !reg_error; + assign classc_ctrl_shadowed_we = addr_hit[339] & reg_we & !reg_error; assign classc_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17291,49 +18191,49 @@ module alert_handler_reg_top ( assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[320] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[340] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_shadowed_re = addr_hit[321] & reg_re & !reg_error; - assign classc_clr_shadowed_we = addr_hit[321] & reg_we & !reg_error; + assign classc_clr_shadowed_re = addr_hit[341] & reg_re & !reg_error; + assign classc_clr_shadowed_we = addr_hit[341] & reg_we & !reg_error; assign classc_clr_shadowed_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[322] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_re = addr_hit[323] & reg_re & !reg_error; - assign classc_accum_thresh_shadowed_we = addr_hit[323] & reg_we & !reg_error; + assign classc_accum_cnt_re = addr_hit[342] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_re = addr_hit[343] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_we = addr_hit[343] & reg_we & !reg_error; assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_shadowed_re = addr_hit[324] & reg_re & !reg_error; - assign classc_timeout_cyc_shadowed_we = addr_hit[324] & reg_we & !reg_error; + assign classc_timeout_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error; + assign classc_timeout_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error; assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_crashdump_trigger_shadowed_re = addr_hit[325] & reg_re & !reg_error; - assign classc_crashdump_trigger_shadowed_we = addr_hit[325] & reg_we & !reg_error; + assign classc_crashdump_trigger_shadowed_re = addr_hit[345] & reg_re & !reg_error; + assign classc_crashdump_trigger_shadowed_we = addr_hit[345] & reg_we & !reg_error; assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classc_phase0_cyc_shadowed_re = addr_hit[326] & reg_re & !reg_error; - assign classc_phase0_cyc_shadowed_we = addr_hit[326] & reg_we & !reg_error; + assign classc_phase0_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error; + assign classc_phase0_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error; assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_shadowed_re = addr_hit[327] & reg_re & !reg_error; - assign classc_phase1_cyc_shadowed_we = addr_hit[327] & reg_we & !reg_error; + assign classc_phase1_cyc_shadowed_re = addr_hit[347] & reg_re & !reg_error; + assign classc_phase1_cyc_shadowed_we = addr_hit[347] & reg_we & !reg_error; assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error; - assign classc_phase2_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error; + assign classc_phase2_cyc_shadowed_re = addr_hit[348] & reg_re & !reg_error; + assign classc_phase2_cyc_shadowed_we = addr_hit[348] & reg_we & !reg_error; assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_shadowed_re = addr_hit[329] & reg_re & !reg_error; - assign classc_phase3_cyc_shadowed_we = addr_hit[329] & reg_we & !reg_error; + assign classc_phase3_cyc_shadowed_re = addr_hit[349] & reg_re & !reg_error; + assign classc_phase3_cyc_shadowed_we = addr_hit[349] & reg_we & !reg_error; assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[330] & reg_re & !reg_error; - assign classc_state_re = addr_hit[331] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[332] & reg_we & !reg_error; + assign classc_esc_cnt_re = addr_hit[350] & reg_re & !reg_error; + assign classc_state_re = addr_hit[351] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[352] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_shadowed_re = addr_hit[333] & reg_re & !reg_error; - assign classd_ctrl_shadowed_we = addr_hit[333] & reg_we & !reg_error; + assign classd_ctrl_shadowed_re = addr_hit[353] & reg_re & !reg_error; + assign classd_ctrl_shadowed_we = addr_hit[353] & reg_we & !reg_error; assign classd_ctrl_shadowed_en_wd = reg_wdata[0]; @@ -17354,44 +18254,44 @@ module alert_handler_reg_top ( assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[334] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[354] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_shadowed_re = addr_hit[335] & reg_re & !reg_error; - assign classd_clr_shadowed_we = addr_hit[335] & reg_we & !reg_error; + assign classd_clr_shadowed_re = addr_hit[355] & reg_re & !reg_error; + assign classd_clr_shadowed_we = addr_hit[355] & reg_we & !reg_error; assign classd_clr_shadowed_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[336] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_re = addr_hit[337] & reg_re & !reg_error; - assign classd_accum_thresh_shadowed_we = addr_hit[337] & reg_we & !reg_error; + assign classd_accum_cnt_re = addr_hit[356] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_re = addr_hit[357] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_we = addr_hit[357] & reg_we & !reg_error; assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_shadowed_re = addr_hit[338] & reg_re & !reg_error; - assign classd_timeout_cyc_shadowed_we = addr_hit[338] & reg_we & !reg_error; + assign classd_timeout_cyc_shadowed_re = addr_hit[358] & reg_re & !reg_error; + assign classd_timeout_cyc_shadowed_we = addr_hit[358] & reg_we & !reg_error; assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_crashdump_trigger_shadowed_re = addr_hit[339] & reg_re & !reg_error; - assign classd_crashdump_trigger_shadowed_we = addr_hit[339] & reg_we & !reg_error; + assign classd_crashdump_trigger_shadowed_re = addr_hit[359] & reg_re & !reg_error; + assign classd_crashdump_trigger_shadowed_we = addr_hit[359] & reg_we & !reg_error; assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; - assign classd_phase0_cyc_shadowed_re = addr_hit[340] & reg_re & !reg_error; - assign classd_phase0_cyc_shadowed_we = addr_hit[340] & reg_we & !reg_error; + assign classd_phase0_cyc_shadowed_re = addr_hit[360] & reg_re & !reg_error; + assign classd_phase0_cyc_shadowed_we = addr_hit[360] & reg_we & !reg_error; assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_shadowed_re = addr_hit[341] & reg_re & !reg_error; - assign classd_phase1_cyc_shadowed_we = addr_hit[341] & reg_we & !reg_error; + assign classd_phase1_cyc_shadowed_re = addr_hit[361] & reg_re & !reg_error; + assign classd_phase1_cyc_shadowed_we = addr_hit[361] & reg_we & !reg_error; assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error; - assign classd_phase2_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error; + assign classd_phase2_cyc_shadowed_re = addr_hit[362] & reg_re & !reg_error; + assign classd_phase2_cyc_shadowed_we = addr_hit[362] & reg_we & !reg_error; assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_shadowed_re = addr_hit[343] & reg_re & !reg_error; - assign classd_phase3_cyc_shadowed_we = addr_hit[343] & reg_we & !reg_error; + assign classd_phase3_cyc_shadowed_re = addr_hit[363] & reg_re & !reg_error; + assign classd_phase3_cyc_shadowed_we = addr_hit[363] & reg_we & !reg_error; assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[344] & reg_re & !reg_error; - assign classd_state_re = addr_hit[345] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[364] & reg_re & !reg_error; + assign classd_state_re = addr_hit[365] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -17465,282 +18365,302 @@ module alert_handler_reg_top ( reg_we_check[67] = alert_regwen_61_we; reg_we_check[68] = alert_regwen_62_we; reg_we_check[69] = alert_regwen_63_we; - reg_we_check[70] = alert_en_shadowed_0_gated_we; - reg_we_check[71] = alert_en_shadowed_1_gated_we; - reg_we_check[72] = alert_en_shadowed_2_gated_we; - reg_we_check[73] = alert_en_shadowed_3_gated_we; - reg_we_check[74] = alert_en_shadowed_4_gated_we; - reg_we_check[75] = alert_en_shadowed_5_gated_we; - reg_we_check[76] = alert_en_shadowed_6_gated_we; - reg_we_check[77] = alert_en_shadowed_7_gated_we; - reg_we_check[78] = alert_en_shadowed_8_gated_we; - reg_we_check[79] = alert_en_shadowed_9_gated_we; - reg_we_check[80] = alert_en_shadowed_10_gated_we; - reg_we_check[81] = alert_en_shadowed_11_gated_we; - reg_we_check[82] = alert_en_shadowed_12_gated_we; - reg_we_check[83] = alert_en_shadowed_13_gated_we; - reg_we_check[84] = alert_en_shadowed_14_gated_we; - reg_we_check[85] = alert_en_shadowed_15_gated_we; - reg_we_check[86] = alert_en_shadowed_16_gated_we; - reg_we_check[87] = alert_en_shadowed_17_gated_we; - reg_we_check[88] = alert_en_shadowed_18_gated_we; - reg_we_check[89] = alert_en_shadowed_19_gated_we; - reg_we_check[90] = alert_en_shadowed_20_gated_we; - reg_we_check[91] = alert_en_shadowed_21_gated_we; - reg_we_check[92] = alert_en_shadowed_22_gated_we; - reg_we_check[93] = alert_en_shadowed_23_gated_we; - reg_we_check[94] = alert_en_shadowed_24_gated_we; - reg_we_check[95] = alert_en_shadowed_25_gated_we; - reg_we_check[96] = alert_en_shadowed_26_gated_we; - reg_we_check[97] = alert_en_shadowed_27_gated_we; - reg_we_check[98] = alert_en_shadowed_28_gated_we; - reg_we_check[99] = alert_en_shadowed_29_gated_we; - reg_we_check[100] = alert_en_shadowed_30_gated_we; - reg_we_check[101] = alert_en_shadowed_31_gated_we; - reg_we_check[102] = alert_en_shadowed_32_gated_we; - reg_we_check[103] = alert_en_shadowed_33_gated_we; - reg_we_check[104] = alert_en_shadowed_34_gated_we; - reg_we_check[105] = alert_en_shadowed_35_gated_we; - reg_we_check[106] = alert_en_shadowed_36_gated_we; - reg_we_check[107] = alert_en_shadowed_37_gated_we; - reg_we_check[108] = alert_en_shadowed_38_gated_we; - reg_we_check[109] = alert_en_shadowed_39_gated_we; - reg_we_check[110] = alert_en_shadowed_40_gated_we; - reg_we_check[111] = alert_en_shadowed_41_gated_we; - reg_we_check[112] = alert_en_shadowed_42_gated_we; - reg_we_check[113] = alert_en_shadowed_43_gated_we; - reg_we_check[114] = alert_en_shadowed_44_gated_we; - reg_we_check[115] = alert_en_shadowed_45_gated_we; - reg_we_check[116] = alert_en_shadowed_46_gated_we; - reg_we_check[117] = alert_en_shadowed_47_gated_we; - reg_we_check[118] = alert_en_shadowed_48_gated_we; - reg_we_check[119] = alert_en_shadowed_49_gated_we; - reg_we_check[120] = alert_en_shadowed_50_gated_we; - reg_we_check[121] = alert_en_shadowed_51_gated_we; - reg_we_check[122] = alert_en_shadowed_52_gated_we; - reg_we_check[123] = alert_en_shadowed_53_gated_we; - reg_we_check[124] = alert_en_shadowed_54_gated_we; - reg_we_check[125] = alert_en_shadowed_55_gated_we; - reg_we_check[126] = alert_en_shadowed_56_gated_we; - reg_we_check[127] = alert_en_shadowed_57_gated_we; - reg_we_check[128] = alert_en_shadowed_58_gated_we; - reg_we_check[129] = alert_en_shadowed_59_gated_we; - reg_we_check[130] = alert_en_shadowed_60_gated_we; - reg_we_check[131] = alert_en_shadowed_61_gated_we; - reg_we_check[132] = alert_en_shadowed_62_gated_we; - reg_we_check[133] = alert_en_shadowed_63_gated_we; - reg_we_check[134] = alert_class_shadowed_0_gated_we; - reg_we_check[135] = alert_class_shadowed_1_gated_we; - reg_we_check[136] = alert_class_shadowed_2_gated_we; - reg_we_check[137] = alert_class_shadowed_3_gated_we; - reg_we_check[138] = alert_class_shadowed_4_gated_we; - reg_we_check[139] = alert_class_shadowed_5_gated_we; - reg_we_check[140] = alert_class_shadowed_6_gated_we; - reg_we_check[141] = alert_class_shadowed_7_gated_we; - reg_we_check[142] = alert_class_shadowed_8_gated_we; - reg_we_check[143] = alert_class_shadowed_9_gated_we; - reg_we_check[144] = alert_class_shadowed_10_gated_we; - reg_we_check[145] = alert_class_shadowed_11_gated_we; - reg_we_check[146] = alert_class_shadowed_12_gated_we; - reg_we_check[147] = alert_class_shadowed_13_gated_we; - reg_we_check[148] = alert_class_shadowed_14_gated_we; - reg_we_check[149] = alert_class_shadowed_15_gated_we; - reg_we_check[150] = alert_class_shadowed_16_gated_we; - reg_we_check[151] = alert_class_shadowed_17_gated_we; - reg_we_check[152] = alert_class_shadowed_18_gated_we; - reg_we_check[153] = alert_class_shadowed_19_gated_we; - reg_we_check[154] = alert_class_shadowed_20_gated_we; - reg_we_check[155] = alert_class_shadowed_21_gated_we; - reg_we_check[156] = alert_class_shadowed_22_gated_we; - reg_we_check[157] = alert_class_shadowed_23_gated_we; - reg_we_check[158] = alert_class_shadowed_24_gated_we; - reg_we_check[159] = alert_class_shadowed_25_gated_we; - reg_we_check[160] = alert_class_shadowed_26_gated_we; - reg_we_check[161] = alert_class_shadowed_27_gated_we; - reg_we_check[162] = alert_class_shadowed_28_gated_we; - reg_we_check[163] = alert_class_shadowed_29_gated_we; - reg_we_check[164] = alert_class_shadowed_30_gated_we; - reg_we_check[165] = alert_class_shadowed_31_gated_we; - reg_we_check[166] = alert_class_shadowed_32_gated_we; - reg_we_check[167] = alert_class_shadowed_33_gated_we; - reg_we_check[168] = alert_class_shadowed_34_gated_we; - reg_we_check[169] = alert_class_shadowed_35_gated_we; - reg_we_check[170] = alert_class_shadowed_36_gated_we; - reg_we_check[171] = alert_class_shadowed_37_gated_we; - reg_we_check[172] = alert_class_shadowed_38_gated_we; - reg_we_check[173] = alert_class_shadowed_39_gated_we; - reg_we_check[174] = alert_class_shadowed_40_gated_we; - reg_we_check[175] = alert_class_shadowed_41_gated_we; - reg_we_check[176] = alert_class_shadowed_42_gated_we; - reg_we_check[177] = alert_class_shadowed_43_gated_we; - reg_we_check[178] = alert_class_shadowed_44_gated_we; - reg_we_check[179] = alert_class_shadowed_45_gated_we; - reg_we_check[180] = alert_class_shadowed_46_gated_we; - reg_we_check[181] = alert_class_shadowed_47_gated_we; - reg_we_check[182] = alert_class_shadowed_48_gated_we; - reg_we_check[183] = alert_class_shadowed_49_gated_we; - reg_we_check[184] = alert_class_shadowed_50_gated_we; - reg_we_check[185] = alert_class_shadowed_51_gated_we; - reg_we_check[186] = alert_class_shadowed_52_gated_we; - reg_we_check[187] = alert_class_shadowed_53_gated_we; - reg_we_check[188] = alert_class_shadowed_54_gated_we; - reg_we_check[189] = alert_class_shadowed_55_gated_we; - reg_we_check[190] = alert_class_shadowed_56_gated_we; - reg_we_check[191] = alert_class_shadowed_57_gated_we; - reg_we_check[192] = alert_class_shadowed_58_gated_we; - reg_we_check[193] = alert_class_shadowed_59_gated_we; - reg_we_check[194] = alert_class_shadowed_60_gated_we; - reg_we_check[195] = alert_class_shadowed_61_gated_we; - reg_we_check[196] = alert_class_shadowed_62_gated_we; - reg_we_check[197] = alert_class_shadowed_63_gated_we; - reg_we_check[198] = alert_cause_0_we; - reg_we_check[199] = alert_cause_1_we; - reg_we_check[200] = alert_cause_2_we; - reg_we_check[201] = alert_cause_3_we; - reg_we_check[202] = alert_cause_4_we; - reg_we_check[203] = alert_cause_5_we; - reg_we_check[204] = alert_cause_6_we; - reg_we_check[205] = alert_cause_7_we; - reg_we_check[206] = alert_cause_8_we; - reg_we_check[207] = alert_cause_9_we; - reg_we_check[208] = alert_cause_10_we; - reg_we_check[209] = alert_cause_11_we; - reg_we_check[210] = alert_cause_12_we; - reg_we_check[211] = alert_cause_13_we; - reg_we_check[212] = alert_cause_14_we; - reg_we_check[213] = alert_cause_15_we; - reg_we_check[214] = alert_cause_16_we; - reg_we_check[215] = alert_cause_17_we; - reg_we_check[216] = alert_cause_18_we; - reg_we_check[217] = alert_cause_19_we; - reg_we_check[218] = alert_cause_20_we; - reg_we_check[219] = alert_cause_21_we; - reg_we_check[220] = alert_cause_22_we; - reg_we_check[221] = alert_cause_23_we; - reg_we_check[222] = alert_cause_24_we; - reg_we_check[223] = alert_cause_25_we; - reg_we_check[224] = alert_cause_26_we; - reg_we_check[225] = alert_cause_27_we; - reg_we_check[226] = alert_cause_28_we; - reg_we_check[227] = alert_cause_29_we; - reg_we_check[228] = alert_cause_30_we; - reg_we_check[229] = alert_cause_31_we; - reg_we_check[230] = alert_cause_32_we; - reg_we_check[231] = alert_cause_33_we; - reg_we_check[232] = alert_cause_34_we; - reg_we_check[233] = alert_cause_35_we; - reg_we_check[234] = alert_cause_36_we; - reg_we_check[235] = alert_cause_37_we; - reg_we_check[236] = alert_cause_38_we; - reg_we_check[237] = alert_cause_39_we; - reg_we_check[238] = alert_cause_40_we; - reg_we_check[239] = alert_cause_41_we; - reg_we_check[240] = alert_cause_42_we; - reg_we_check[241] = alert_cause_43_we; - reg_we_check[242] = alert_cause_44_we; - reg_we_check[243] = alert_cause_45_we; - reg_we_check[244] = alert_cause_46_we; - reg_we_check[245] = alert_cause_47_we; - reg_we_check[246] = alert_cause_48_we; - reg_we_check[247] = alert_cause_49_we; - reg_we_check[248] = alert_cause_50_we; - reg_we_check[249] = alert_cause_51_we; - reg_we_check[250] = alert_cause_52_we; - reg_we_check[251] = alert_cause_53_we; - reg_we_check[252] = alert_cause_54_we; - reg_we_check[253] = alert_cause_55_we; - reg_we_check[254] = alert_cause_56_we; - reg_we_check[255] = alert_cause_57_we; - reg_we_check[256] = alert_cause_58_we; - reg_we_check[257] = alert_cause_59_we; - reg_we_check[258] = alert_cause_60_we; - reg_we_check[259] = alert_cause_61_we; - reg_we_check[260] = alert_cause_62_we; - reg_we_check[261] = alert_cause_63_we; - reg_we_check[262] = loc_alert_regwen_0_we; - reg_we_check[263] = loc_alert_regwen_1_we; - reg_we_check[264] = loc_alert_regwen_2_we; - reg_we_check[265] = loc_alert_regwen_3_we; - reg_we_check[266] = loc_alert_regwen_4_we; - reg_we_check[267] = loc_alert_regwen_5_we; - reg_we_check[268] = loc_alert_regwen_6_we; - reg_we_check[269] = loc_alert_en_shadowed_0_gated_we; - reg_we_check[270] = loc_alert_en_shadowed_1_gated_we; - reg_we_check[271] = loc_alert_en_shadowed_2_gated_we; - reg_we_check[272] = loc_alert_en_shadowed_3_gated_we; - reg_we_check[273] = loc_alert_en_shadowed_4_gated_we; - reg_we_check[274] = loc_alert_en_shadowed_5_gated_we; - reg_we_check[275] = loc_alert_en_shadowed_6_gated_we; - reg_we_check[276] = loc_alert_class_shadowed_0_gated_we; - reg_we_check[277] = loc_alert_class_shadowed_1_gated_we; - reg_we_check[278] = loc_alert_class_shadowed_2_gated_we; - reg_we_check[279] = loc_alert_class_shadowed_3_gated_we; - reg_we_check[280] = loc_alert_class_shadowed_4_gated_we; - reg_we_check[281] = loc_alert_class_shadowed_5_gated_we; - reg_we_check[282] = loc_alert_class_shadowed_6_gated_we; - reg_we_check[283] = loc_alert_cause_0_we; - reg_we_check[284] = loc_alert_cause_1_we; - reg_we_check[285] = loc_alert_cause_2_we; - reg_we_check[286] = loc_alert_cause_3_we; - reg_we_check[287] = loc_alert_cause_4_we; - reg_we_check[288] = loc_alert_cause_5_we; - reg_we_check[289] = loc_alert_cause_6_we; - reg_we_check[290] = classa_regwen_we; - reg_we_check[291] = classa_ctrl_shadowed_gated_we; - reg_we_check[292] = classa_clr_regwen_we; - reg_we_check[293] = classa_clr_shadowed_gated_we; - reg_we_check[294] = 1'b0; - reg_we_check[295] = classa_accum_thresh_shadowed_gated_we; - reg_we_check[296] = classa_timeout_cyc_shadowed_gated_we; - reg_we_check[297] = classa_crashdump_trigger_shadowed_gated_we; - reg_we_check[298] = classa_phase0_cyc_shadowed_gated_we; - reg_we_check[299] = classa_phase1_cyc_shadowed_gated_we; - reg_we_check[300] = classa_phase2_cyc_shadowed_gated_we; - reg_we_check[301] = classa_phase3_cyc_shadowed_gated_we; - reg_we_check[302] = 1'b0; - reg_we_check[303] = 1'b0; - reg_we_check[304] = classb_regwen_we; - reg_we_check[305] = classb_ctrl_shadowed_gated_we; - reg_we_check[306] = classb_clr_regwen_we; - reg_we_check[307] = classb_clr_shadowed_gated_we; - reg_we_check[308] = 1'b0; - reg_we_check[309] = classb_accum_thresh_shadowed_gated_we; - reg_we_check[310] = classb_timeout_cyc_shadowed_gated_we; - reg_we_check[311] = classb_crashdump_trigger_shadowed_gated_we; - reg_we_check[312] = classb_phase0_cyc_shadowed_gated_we; - reg_we_check[313] = classb_phase1_cyc_shadowed_gated_we; - reg_we_check[314] = classb_phase2_cyc_shadowed_gated_we; - reg_we_check[315] = classb_phase3_cyc_shadowed_gated_we; - reg_we_check[316] = 1'b0; - reg_we_check[317] = 1'b0; - reg_we_check[318] = classc_regwen_we; - reg_we_check[319] = classc_ctrl_shadowed_gated_we; - reg_we_check[320] = classc_clr_regwen_we; - reg_we_check[321] = classc_clr_shadowed_gated_we; + reg_we_check[70] = alert_regwen_64_we; + reg_we_check[71] = alert_regwen_65_we; + reg_we_check[72] = alert_regwen_66_we; + reg_we_check[73] = alert_regwen_67_we; + reg_we_check[74] = alert_regwen_68_we; + reg_we_check[75] = alert_en_shadowed_0_gated_we; + reg_we_check[76] = alert_en_shadowed_1_gated_we; + reg_we_check[77] = alert_en_shadowed_2_gated_we; + reg_we_check[78] = alert_en_shadowed_3_gated_we; + reg_we_check[79] = alert_en_shadowed_4_gated_we; + reg_we_check[80] = alert_en_shadowed_5_gated_we; + reg_we_check[81] = alert_en_shadowed_6_gated_we; + reg_we_check[82] = alert_en_shadowed_7_gated_we; + reg_we_check[83] = alert_en_shadowed_8_gated_we; + reg_we_check[84] = alert_en_shadowed_9_gated_we; + reg_we_check[85] = alert_en_shadowed_10_gated_we; + reg_we_check[86] = alert_en_shadowed_11_gated_we; + reg_we_check[87] = alert_en_shadowed_12_gated_we; + reg_we_check[88] = alert_en_shadowed_13_gated_we; + reg_we_check[89] = alert_en_shadowed_14_gated_we; + reg_we_check[90] = alert_en_shadowed_15_gated_we; + reg_we_check[91] = alert_en_shadowed_16_gated_we; + reg_we_check[92] = alert_en_shadowed_17_gated_we; + reg_we_check[93] = alert_en_shadowed_18_gated_we; + reg_we_check[94] = alert_en_shadowed_19_gated_we; + reg_we_check[95] = alert_en_shadowed_20_gated_we; + reg_we_check[96] = alert_en_shadowed_21_gated_we; + reg_we_check[97] = alert_en_shadowed_22_gated_we; + reg_we_check[98] = alert_en_shadowed_23_gated_we; + reg_we_check[99] = alert_en_shadowed_24_gated_we; + reg_we_check[100] = alert_en_shadowed_25_gated_we; + reg_we_check[101] = alert_en_shadowed_26_gated_we; + reg_we_check[102] = alert_en_shadowed_27_gated_we; + reg_we_check[103] = alert_en_shadowed_28_gated_we; + reg_we_check[104] = alert_en_shadowed_29_gated_we; + reg_we_check[105] = alert_en_shadowed_30_gated_we; + reg_we_check[106] = alert_en_shadowed_31_gated_we; + reg_we_check[107] = alert_en_shadowed_32_gated_we; + reg_we_check[108] = alert_en_shadowed_33_gated_we; + reg_we_check[109] = alert_en_shadowed_34_gated_we; + reg_we_check[110] = alert_en_shadowed_35_gated_we; + reg_we_check[111] = alert_en_shadowed_36_gated_we; + reg_we_check[112] = alert_en_shadowed_37_gated_we; + reg_we_check[113] = alert_en_shadowed_38_gated_we; + reg_we_check[114] = alert_en_shadowed_39_gated_we; + reg_we_check[115] = alert_en_shadowed_40_gated_we; + reg_we_check[116] = alert_en_shadowed_41_gated_we; + reg_we_check[117] = alert_en_shadowed_42_gated_we; + reg_we_check[118] = alert_en_shadowed_43_gated_we; + reg_we_check[119] = alert_en_shadowed_44_gated_we; + reg_we_check[120] = alert_en_shadowed_45_gated_we; + reg_we_check[121] = alert_en_shadowed_46_gated_we; + reg_we_check[122] = alert_en_shadowed_47_gated_we; + reg_we_check[123] = alert_en_shadowed_48_gated_we; + reg_we_check[124] = alert_en_shadowed_49_gated_we; + reg_we_check[125] = alert_en_shadowed_50_gated_we; + reg_we_check[126] = alert_en_shadowed_51_gated_we; + reg_we_check[127] = alert_en_shadowed_52_gated_we; + reg_we_check[128] = alert_en_shadowed_53_gated_we; + reg_we_check[129] = alert_en_shadowed_54_gated_we; + reg_we_check[130] = alert_en_shadowed_55_gated_we; + reg_we_check[131] = alert_en_shadowed_56_gated_we; + reg_we_check[132] = alert_en_shadowed_57_gated_we; + reg_we_check[133] = alert_en_shadowed_58_gated_we; + reg_we_check[134] = alert_en_shadowed_59_gated_we; + reg_we_check[135] = alert_en_shadowed_60_gated_we; + reg_we_check[136] = alert_en_shadowed_61_gated_we; + reg_we_check[137] = alert_en_shadowed_62_gated_we; + reg_we_check[138] = alert_en_shadowed_63_gated_we; + reg_we_check[139] = alert_en_shadowed_64_gated_we; + reg_we_check[140] = alert_en_shadowed_65_gated_we; + reg_we_check[141] = alert_en_shadowed_66_gated_we; + reg_we_check[142] = alert_en_shadowed_67_gated_we; + reg_we_check[143] = alert_en_shadowed_68_gated_we; + reg_we_check[144] = alert_class_shadowed_0_gated_we; + reg_we_check[145] = alert_class_shadowed_1_gated_we; + reg_we_check[146] = alert_class_shadowed_2_gated_we; + reg_we_check[147] = alert_class_shadowed_3_gated_we; + reg_we_check[148] = alert_class_shadowed_4_gated_we; + reg_we_check[149] = alert_class_shadowed_5_gated_we; + reg_we_check[150] = alert_class_shadowed_6_gated_we; + reg_we_check[151] = alert_class_shadowed_7_gated_we; + reg_we_check[152] = alert_class_shadowed_8_gated_we; + reg_we_check[153] = alert_class_shadowed_9_gated_we; + reg_we_check[154] = alert_class_shadowed_10_gated_we; + reg_we_check[155] = alert_class_shadowed_11_gated_we; + reg_we_check[156] = alert_class_shadowed_12_gated_we; + reg_we_check[157] = alert_class_shadowed_13_gated_we; + reg_we_check[158] = alert_class_shadowed_14_gated_we; + reg_we_check[159] = alert_class_shadowed_15_gated_we; + reg_we_check[160] = alert_class_shadowed_16_gated_we; + reg_we_check[161] = alert_class_shadowed_17_gated_we; + reg_we_check[162] = alert_class_shadowed_18_gated_we; + reg_we_check[163] = alert_class_shadowed_19_gated_we; + reg_we_check[164] = alert_class_shadowed_20_gated_we; + reg_we_check[165] = alert_class_shadowed_21_gated_we; + reg_we_check[166] = alert_class_shadowed_22_gated_we; + reg_we_check[167] = alert_class_shadowed_23_gated_we; + reg_we_check[168] = alert_class_shadowed_24_gated_we; + reg_we_check[169] = alert_class_shadowed_25_gated_we; + reg_we_check[170] = alert_class_shadowed_26_gated_we; + reg_we_check[171] = alert_class_shadowed_27_gated_we; + reg_we_check[172] = alert_class_shadowed_28_gated_we; + reg_we_check[173] = alert_class_shadowed_29_gated_we; + reg_we_check[174] = alert_class_shadowed_30_gated_we; + reg_we_check[175] = alert_class_shadowed_31_gated_we; + reg_we_check[176] = alert_class_shadowed_32_gated_we; + reg_we_check[177] = alert_class_shadowed_33_gated_we; + reg_we_check[178] = alert_class_shadowed_34_gated_we; + reg_we_check[179] = alert_class_shadowed_35_gated_we; + reg_we_check[180] = alert_class_shadowed_36_gated_we; + reg_we_check[181] = alert_class_shadowed_37_gated_we; + reg_we_check[182] = alert_class_shadowed_38_gated_we; + reg_we_check[183] = alert_class_shadowed_39_gated_we; + reg_we_check[184] = alert_class_shadowed_40_gated_we; + reg_we_check[185] = alert_class_shadowed_41_gated_we; + reg_we_check[186] = alert_class_shadowed_42_gated_we; + reg_we_check[187] = alert_class_shadowed_43_gated_we; + reg_we_check[188] = alert_class_shadowed_44_gated_we; + reg_we_check[189] = alert_class_shadowed_45_gated_we; + reg_we_check[190] = alert_class_shadowed_46_gated_we; + reg_we_check[191] = alert_class_shadowed_47_gated_we; + reg_we_check[192] = alert_class_shadowed_48_gated_we; + reg_we_check[193] = alert_class_shadowed_49_gated_we; + reg_we_check[194] = alert_class_shadowed_50_gated_we; + reg_we_check[195] = alert_class_shadowed_51_gated_we; + reg_we_check[196] = alert_class_shadowed_52_gated_we; + reg_we_check[197] = alert_class_shadowed_53_gated_we; + reg_we_check[198] = alert_class_shadowed_54_gated_we; + reg_we_check[199] = alert_class_shadowed_55_gated_we; + reg_we_check[200] = alert_class_shadowed_56_gated_we; + reg_we_check[201] = alert_class_shadowed_57_gated_we; + reg_we_check[202] = alert_class_shadowed_58_gated_we; + reg_we_check[203] = alert_class_shadowed_59_gated_we; + reg_we_check[204] = alert_class_shadowed_60_gated_we; + reg_we_check[205] = alert_class_shadowed_61_gated_we; + reg_we_check[206] = alert_class_shadowed_62_gated_we; + reg_we_check[207] = alert_class_shadowed_63_gated_we; + reg_we_check[208] = alert_class_shadowed_64_gated_we; + reg_we_check[209] = alert_class_shadowed_65_gated_we; + reg_we_check[210] = alert_class_shadowed_66_gated_we; + reg_we_check[211] = alert_class_shadowed_67_gated_we; + reg_we_check[212] = alert_class_shadowed_68_gated_we; + reg_we_check[213] = alert_cause_0_we; + reg_we_check[214] = alert_cause_1_we; + reg_we_check[215] = alert_cause_2_we; + reg_we_check[216] = alert_cause_3_we; + reg_we_check[217] = alert_cause_4_we; + reg_we_check[218] = alert_cause_5_we; + reg_we_check[219] = alert_cause_6_we; + reg_we_check[220] = alert_cause_7_we; + reg_we_check[221] = alert_cause_8_we; + reg_we_check[222] = alert_cause_9_we; + reg_we_check[223] = alert_cause_10_we; + reg_we_check[224] = alert_cause_11_we; + reg_we_check[225] = alert_cause_12_we; + reg_we_check[226] = alert_cause_13_we; + reg_we_check[227] = alert_cause_14_we; + reg_we_check[228] = alert_cause_15_we; + reg_we_check[229] = alert_cause_16_we; + reg_we_check[230] = alert_cause_17_we; + reg_we_check[231] = alert_cause_18_we; + reg_we_check[232] = alert_cause_19_we; + reg_we_check[233] = alert_cause_20_we; + reg_we_check[234] = alert_cause_21_we; + reg_we_check[235] = alert_cause_22_we; + reg_we_check[236] = alert_cause_23_we; + reg_we_check[237] = alert_cause_24_we; + reg_we_check[238] = alert_cause_25_we; + reg_we_check[239] = alert_cause_26_we; + reg_we_check[240] = alert_cause_27_we; + reg_we_check[241] = alert_cause_28_we; + reg_we_check[242] = alert_cause_29_we; + reg_we_check[243] = alert_cause_30_we; + reg_we_check[244] = alert_cause_31_we; + reg_we_check[245] = alert_cause_32_we; + reg_we_check[246] = alert_cause_33_we; + reg_we_check[247] = alert_cause_34_we; + reg_we_check[248] = alert_cause_35_we; + reg_we_check[249] = alert_cause_36_we; + reg_we_check[250] = alert_cause_37_we; + reg_we_check[251] = alert_cause_38_we; + reg_we_check[252] = alert_cause_39_we; + reg_we_check[253] = alert_cause_40_we; + reg_we_check[254] = alert_cause_41_we; + reg_we_check[255] = alert_cause_42_we; + reg_we_check[256] = alert_cause_43_we; + reg_we_check[257] = alert_cause_44_we; + reg_we_check[258] = alert_cause_45_we; + reg_we_check[259] = alert_cause_46_we; + reg_we_check[260] = alert_cause_47_we; + reg_we_check[261] = alert_cause_48_we; + reg_we_check[262] = alert_cause_49_we; + reg_we_check[263] = alert_cause_50_we; + reg_we_check[264] = alert_cause_51_we; + reg_we_check[265] = alert_cause_52_we; + reg_we_check[266] = alert_cause_53_we; + reg_we_check[267] = alert_cause_54_we; + reg_we_check[268] = alert_cause_55_we; + reg_we_check[269] = alert_cause_56_we; + reg_we_check[270] = alert_cause_57_we; + reg_we_check[271] = alert_cause_58_we; + reg_we_check[272] = alert_cause_59_we; + reg_we_check[273] = alert_cause_60_we; + reg_we_check[274] = alert_cause_61_we; + reg_we_check[275] = alert_cause_62_we; + reg_we_check[276] = alert_cause_63_we; + reg_we_check[277] = alert_cause_64_we; + reg_we_check[278] = alert_cause_65_we; + reg_we_check[279] = alert_cause_66_we; + reg_we_check[280] = alert_cause_67_we; + reg_we_check[281] = alert_cause_68_we; + reg_we_check[282] = loc_alert_regwen_0_we; + reg_we_check[283] = loc_alert_regwen_1_we; + reg_we_check[284] = loc_alert_regwen_2_we; + reg_we_check[285] = loc_alert_regwen_3_we; + reg_we_check[286] = loc_alert_regwen_4_we; + reg_we_check[287] = loc_alert_regwen_5_we; + reg_we_check[288] = loc_alert_regwen_6_we; + reg_we_check[289] = loc_alert_en_shadowed_0_gated_we; + reg_we_check[290] = loc_alert_en_shadowed_1_gated_we; + reg_we_check[291] = loc_alert_en_shadowed_2_gated_we; + reg_we_check[292] = loc_alert_en_shadowed_3_gated_we; + reg_we_check[293] = loc_alert_en_shadowed_4_gated_we; + reg_we_check[294] = loc_alert_en_shadowed_5_gated_we; + reg_we_check[295] = loc_alert_en_shadowed_6_gated_we; + reg_we_check[296] = loc_alert_class_shadowed_0_gated_we; + reg_we_check[297] = loc_alert_class_shadowed_1_gated_we; + reg_we_check[298] = loc_alert_class_shadowed_2_gated_we; + reg_we_check[299] = loc_alert_class_shadowed_3_gated_we; + reg_we_check[300] = loc_alert_class_shadowed_4_gated_we; + reg_we_check[301] = loc_alert_class_shadowed_5_gated_we; + reg_we_check[302] = loc_alert_class_shadowed_6_gated_we; + reg_we_check[303] = loc_alert_cause_0_we; + reg_we_check[304] = loc_alert_cause_1_we; + reg_we_check[305] = loc_alert_cause_2_we; + reg_we_check[306] = loc_alert_cause_3_we; + reg_we_check[307] = loc_alert_cause_4_we; + reg_we_check[308] = loc_alert_cause_5_we; + reg_we_check[309] = loc_alert_cause_6_we; + reg_we_check[310] = classa_regwen_we; + reg_we_check[311] = classa_ctrl_shadowed_gated_we; + reg_we_check[312] = classa_clr_regwen_we; + reg_we_check[313] = classa_clr_shadowed_gated_we; + reg_we_check[314] = 1'b0; + reg_we_check[315] = classa_accum_thresh_shadowed_gated_we; + reg_we_check[316] = classa_timeout_cyc_shadowed_gated_we; + reg_we_check[317] = classa_crashdump_trigger_shadowed_gated_we; + reg_we_check[318] = classa_phase0_cyc_shadowed_gated_we; + reg_we_check[319] = classa_phase1_cyc_shadowed_gated_we; + reg_we_check[320] = classa_phase2_cyc_shadowed_gated_we; + reg_we_check[321] = classa_phase3_cyc_shadowed_gated_we; reg_we_check[322] = 1'b0; - reg_we_check[323] = classc_accum_thresh_shadowed_gated_we; - reg_we_check[324] = classc_timeout_cyc_shadowed_gated_we; - reg_we_check[325] = classc_crashdump_trigger_shadowed_gated_we; - reg_we_check[326] = classc_phase0_cyc_shadowed_gated_we; - reg_we_check[327] = classc_phase1_cyc_shadowed_gated_we; - reg_we_check[328] = classc_phase2_cyc_shadowed_gated_we; - reg_we_check[329] = classc_phase3_cyc_shadowed_gated_we; - reg_we_check[330] = 1'b0; - reg_we_check[331] = 1'b0; - reg_we_check[332] = classd_regwen_we; - reg_we_check[333] = classd_ctrl_shadowed_gated_we; - reg_we_check[334] = classd_clr_regwen_we; - reg_we_check[335] = classd_clr_shadowed_gated_we; + reg_we_check[323] = 1'b0; + reg_we_check[324] = classb_regwen_we; + reg_we_check[325] = classb_ctrl_shadowed_gated_we; + reg_we_check[326] = classb_clr_regwen_we; + reg_we_check[327] = classb_clr_shadowed_gated_we; + reg_we_check[328] = 1'b0; + reg_we_check[329] = classb_accum_thresh_shadowed_gated_we; + reg_we_check[330] = classb_timeout_cyc_shadowed_gated_we; + reg_we_check[331] = classb_crashdump_trigger_shadowed_gated_we; + reg_we_check[332] = classb_phase0_cyc_shadowed_gated_we; + reg_we_check[333] = classb_phase1_cyc_shadowed_gated_we; + reg_we_check[334] = classb_phase2_cyc_shadowed_gated_we; + reg_we_check[335] = classb_phase3_cyc_shadowed_gated_we; reg_we_check[336] = 1'b0; - reg_we_check[337] = classd_accum_thresh_shadowed_gated_we; - reg_we_check[338] = classd_timeout_cyc_shadowed_gated_we; - reg_we_check[339] = classd_crashdump_trigger_shadowed_gated_we; - reg_we_check[340] = classd_phase0_cyc_shadowed_gated_we; - reg_we_check[341] = classd_phase1_cyc_shadowed_gated_we; - reg_we_check[342] = classd_phase2_cyc_shadowed_gated_we; - reg_we_check[343] = classd_phase3_cyc_shadowed_gated_we; - reg_we_check[344] = 1'b0; - reg_we_check[345] = 1'b0; + reg_we_check[337] = 1'b0; + reg_we_check[338] = classc_regwen_we; + reg_we_check[339] = classc_ctrl_shadowed_gated_we; + reg_we_check[340] = classc_clr_regwen_we; + reg_we_check[341] = classc_clr_shadowed_gated_we; + reg_we_check[342] = 1'b0; + reg_we_check[343] = classc_accum_thresh_shadowed_gated_we; + reg_we_check[344] = classc_timeout_cyc_shadowed_gated_we; + reg_we_check[345] = classc_crashdump_trigger_shadowed_gated_we; + reg_we_check[346] = classc_phase0_cyc_shadowed_gated_we; + reg_we_check[347] = classc_phase1_cyc_shadowed_gated_we; + reg_we_check[348] = classc_phase2_cyc_shadowed_gated_we; + reg_we_check[349] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[350] = 1'b0; + reg_we_check[351] = 1'b0; + reg_we_check[352] = classd_regwen_we; + reg_we_check[353] = classd_ctrl_shadowed_gated_we; + reg_we_check[354] = classd_clr_regwen_we; + reg_we_check[355] = classd_clr_shadowed_gated_we; + reg_we_check[356] = 1'b0; + reg_we_check[357] = classd_accum_thresh_shadowed_gated_we; + reg_we_check[358] = classd_timeout_cyc_shadowed_gated_we; + reg_we_check[359] = classd_crashdump_trigger_shadowed_gated_we; + reg_we_check[360] = classd_phase0_cyc_shadowed_gated_we; + reg_we_check[361] = classd_phase1_cyc_shadowed_gated_we; + reg_we_check[362] = classd_phase2_cyc_shadowed_gated_we; + reg_we_check[363] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[364] = 1'b0; + reg_we_check[365] = 1'b0; end // Read data return @@ -18037,890 +18957,970 @@ module alert_handler_reg_top ( end addr_hit[70]: begin - reg_rdata_next[0] = alert_en_shadowed_0_qs; + reg_rdata_next[0] = alert_regwen_64_qs; end addr_hit[71]: begin - reg_rdata_next[0] = alert_en_shadowed_1_qs; + reg_rdata_next[0] = alert_regwen_65_qs; end addr_hit[72]: begin - reg_rdata_next[0] = alert_en_shadowed_2_qs; + reg_rdata_next[0] = alert_regwen_66_qs; end addr_hit[73]: begin - reg_rdata_next[0] = alert_en_shadowed_3_qs; + reg_rdata_next[0] = alert_regwen_67_qs; end addr_hit[74]: begin - reg_rdata_next[0] = alert_en_shadowed_4_qs; + reg_rdata_next[0] = alert_regwen_68_qs; end addr_hit[75]: begin - reg_rdata_next[0] = alert_en_shadowed_5_qs; + reg_rdata_next[0] = alert_en_shadowed_0_qs; end addr_hit[76]: begin - reg_rdata_next[0] = alert_en_shadowed_6_qs; + reg_rdata_next[0] = alert_en_shadowed_1_qs; end addr_hit[77]: begin - reg_rdata_next[0] = alert_en_shadowed_7_qs; + reg_rdata_next[0] = alert_en_shadowed_2_qs; end addr_hit[78]: begin - reg_rdata_next[0] = alert_en_shadowed_8_qs; + reg_rdata_next[0] = alert_en_shadowed_3_qs; end addr_hit[79]: begin - reg_rdata_next[0] = alert_en_shadowed_9_qs; + reg_rdata_next[0] = alert_en_shadowed_4_qs; end addr_hit[80]: begin - reg_rdata_next[0] = alert_en_shadowed_10_qs; + reg_rdata_next[0] = alert_en_shadowed_5_qs; end addr_hit[81]: begin - reg_rdata_next[0] = alert_en_shadowed_11_qs; + reg_rdata_next[0] = alert_en_shadowed_6_qs; end addr_hit[82]: begin - reg_rdata_next[0] = alert_en_shadowed_12_qs; + reg_rdata_next[0] = alert_en_shadowed_7_qs; end addr_hit[83]: begin - reg_rdata_next[0] = alert_en_shadowed_13_qs; + reg_rdata_next[0] = alert_en_shadowed_8_qs; end addr_hit[84]: begin - reg_rdata_next[0] = alert_en_shadowed_14_qs; + reg_rdata_next[0] = alert_en_shadowed_9_qs; end addr_hit[85]: begin - reg_rdata_next[0] = alert_en_shadowed_15_qs; + reg_rdata_next[0] = alert_en_shadowed_10_qs; end addr_hit[86]: begin - reg_rdata_next[0] = alert_en_shadowed_16_qs; + reg_rdata_next[0] = alert_en_shadowed_11_qs; end addr_hit[87]: begin - reg_rdata_next[0] = alert_en_shadowed_17_qs; + reg_rdata_next[0] = alert_en_shadowed_12_qs; end addr_hit[88]: begin - reg_rdata_next[0] = alert_en_shadowed_18_qs; + reg_rdata_next[0] = alert_en_shadowed_13_qs; end addr_hit[89]: begin - reg_rdata_next[0] = alert_en_shadowed_19_qs; + reg_rdata_next[0] = alert_en_shadowed_14_qs; end addr_hit[90]: begin - reg_rdata_next[0] = alert_en_shadowed_20_qs; + reg_rdata_next[0] = alert_en_shadowed_15_qs; end addr_hit[91]: begin - reg_rdata_next[0] = alert_en_shadowed_21_qs; + reg_rdata_next[0] = alert_en_shadowed_16_qs; end addr_hit[92]: begin - reg_rdata_next[0] = alert_en_shadowed_22_qs; + reg_rdata_next[0] = alert_en_shadowed_17_qs; end addr_hit[93]: begin - reg_rdata_next[0] = alert_en_shadowed_23_qs; + reg_rdata_next[0] = alert_en_shadowed_18_qs; end addr_hit[94]: begin - reg_rdata_next[0] = alert_en_shadowed_24_qs; + reg_rdata_next[0] = alert_en_shadowed_19_qs; end addr_hit[95]: begin - reg_rdata_next[0] = alert_en_shadowed_25_qs; + reg_rdata_next[0] = alert_en_shadowed_20_qs; end addr_hit[96]: begin - reg_rdata_next[0] = alert_en_shadowed_26_qs; + reg_rdata_next[0] = alert_en_shadowed_21_qs; end addr_hit[97]: begin - reg_rdata_next[0] = alert_en_shadowed_27_qs; + reg_rdata_next[0] = alert_en_shadowed_22_qs; end addr_hit[98]: begin - reg_rdata_next[0] = alert_en_shadowed_28_qs; + reg_rdata_next[0] = alert_en_shadowed_23_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_en_shadowed_29_qs; + reg_rdata_next[0] = alert_en_shadowed_24_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_en_shadowed_30_qs; + reg_rdata_next[0] = alert_en_shadowed_25_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_en_shadowed_31_qs; + reg_rdata_next[0] = alert_en_shadowed_26_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_en_shadowed_32_qs; + reg_rdata_next[0] = alert_en_shadowed_27_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_en_shadowed_33_qs; + reg_rdata_next[0] = alert_en_shadowed_28_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_en_shadowed_34_qs; + reg_rdata_next[0] = alert_en_shadowed_29_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_en_shadowed_35_qs; + reg_rdata_next[0] = alert_en_shadowed_30_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_en_shadowed_36_qs; + reg_rdata_next[0] = alert_en_shadowed_31_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_en_shadowed_37_qs; + reg_rdata_next[0] = alert_en_shadowed_32_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_en_shadowed_38_qs; + reg_rdata_next[0] = alert_en_shadowed_33_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_en_shadowed_39_qs; + reg_rdata_next[0] = alert_en_shadowed_34_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_en_shadowed_40_qs; + reg_rdata_next[0] = alert_en_shadowed_35_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_en_shadowed_41_qs; + reg_rdata_next[0] = alert_en_shadowed_36_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_en_shadowed_42_qs; + reg_rdata_next[0] = alert_en_shadowed_37_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_en_shadowed_43_qs; + reg_rdata_next[0] = alert_en_shadowed_38_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_en_shadowed_44_qs; + reg_rdata_next[0] = alert_en_shadowed_39_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_en_shadowed_45_qs; + reg_rdata_next[0] = alert_en_shadowed_40_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_en_shadowed_46_qs; + reg_rdata_next[0] = alert_en_shadowed_41_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_en_shadowed_47_qs; + reg_rdata_next[0] = alert_en_shadowed_42_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_en_shadowed_48_qs; + reg_rdata_next[0] = alert_en_shadowed_43_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_en_shadowed_49_qs; + reg_rdata_next[0] = alert_en_shadowed_44_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_en_shadowed_50_qs; + reg_rdata_next[0] = alert_en_shadowed_45_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_en_shadowed_51_qs; + reg_rdata_next[0] = alert_en_shadowed_46_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_en_shadowed_52_qs; + reg_rdata_next[0] = alert_en_shadowed_47_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_en_shadowed_53_qs; + reg_rdata_next[0] = alert_en_shadowed_48_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_en_shadowed_54_qs; + reg_rdata_next[0] = alert_en_shadowed_49_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_en_shadowed_55_qs; + reg_rdata_next[0] = alert_en_shadowed_50_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_en_shadowed_56_qs; + reg_rdata_next[0] = alert_en_shadowed_51_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_en_shadowed_57_qs; + reg_rdata_next[0] = alert_en_shadowed_52_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_en_shadowed_58_qs; + reg_rdata_next[0] = alert_en_shadowed_53_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_en_shadowed_59_qs; + reg_rdata_next[0] = alert_en_shadowed_54_qs; end addr_hit[130]: begin - reg_rdata_next[0] = alert_en_shadowed_60_qs; + reg_rdata_next[0] = alert_en_shadowed_55_qs; end addr_hit[131]: begin - reg_rdata_next[0] = alert_en_shadowed_61_qs; + reg_rdata_next[0] = alert_en_shadowed_56_qs; end addr_hit[132]: begin - reg_rdata_next[0] = alert_en_shadowed_62_qs; + reg_rdata_next[0] = alert_en_shadowed_57_qs; end addr_hit[133]: begin - reg_rdata_next[0] = alert_en_shadowed_63_qs; + reg_rdata_next[0] = alert_en_shadowed_58_qs; end addr_hit[134]: begin - reg_rdata_next[1:0] = alert_class_shadowed_0_qs; + reg_rdata_next[0] = alert_en_shadowed_59_qs; end addr_hit[135]: begin - reg_rdata_next[1:0] = alert_class_shadowed_1_qs; + reg_rdata_next[0] = alert_en_shadowed_60_qs; end addr_hit[136]: begin - reg_rdata_next[1:0] = alert_class_shadowed_2_qs; + reg_rdata_next[0] = alert_en_shadowed_61_qs; end addr_hit[137]: begin - reg_rdata_next[1:0] = alert_class_shadowed_3_qs; + reg_rdata_next[0] = alert_en_shadowed_62_qs; end addr_hit[138]: begin - reg_rdata_next[1:0] = alert_class_shadowed_4_qs; + reg_rdata_next[0] = alert_en_shadowed_63_qs; end addr_hit[139]: begin - reg_rdata_next[1:0] = alert_class_shadowed_5_qs; + reg_rdata_next[0] = alert_en_shadowed_64_qs; end addr_hit[140]: begin - reg_rdata_next[1:0] = alert_class_shadowed_6_qs; + reg_rdata_next[0] = alert_en_shadowed_65_qs; end addr_hit[141]: begin - reg_rdata_next[1:0] = alert_class_shadowed_7_qs; + reg_rdata_next[0] = alert_en_shadowed_66_qs; end addr_hit[142]: begin - reg_rdata_next[1:0] = alert_class_shadowed_8_qs; + reg_rdata_next[0] = alert_en_shadowed_67_qs; end addr_hit[143]: begin - reg_rdata_next[1:0] = alert_class_shadowed_9_qs; + reg_rdata_next[0] = alert_en_shadowed_68_qs; end addr_hit[144]: begin - reg_rdata_next[1:0] = alert_class_shadowed_10_qs; + reg_rdata_next[1:0] = alert_class_shadowed_0_qs; end addr_hit[145]: begin - reg_rdata_next[1:0] = alert_class_shadowed_11_qs; + reg_rdata_next[1:0] = alert_class_shadowed_1_qs; end addr_hit[146]: begin - reg_rdata_next[1:0] = alert_class_shadowed_12_qs; + reg_rdata_next[1:0] = alert_class_shadowed_2_qs; end addr_hit[147]: begin - reg_rdata_next[1:0] = alert_class_shadowed_13_qs; + reg_rdata_next[1:0] = alert_class_shadowed_3_qs; end addr_hit[148]: begin - reg_rdata_next[1:0] = alert_class_shadowed_14_qs; + reg_rdata_next[1:0] = alert_class_shadowed_4_qs; end addr_hit[149]: begin - reg_rdata_next[1:0] = alert_class_shadowed_15_qs; + reg_rdata_next[1:0] = alert_class_shadowed_5_qs; end addr_hit[150]: begin - reg_rdata_next[1:0] = alert_class_shadowed_16_qs; + reg_rdata_next[1:0] = alert_class_shadowed_6_qs; end addr_hit[151]: begin - reg_rdata_next[1:0] = alert_class_shadowed_17_qs; + reg_rdata_next[1:0] = alert_class_shadowed_7_qs; end addr_hit[152]: begin - reg_rdata_next[1:0] = alert_class_shadowed_18_qs; + reg_rdata_next[1:0] = alert_class_shadowed_8_qs; end addr_hit[153]: begin - reg_rdata_next[1:0] = alert_class_shadowed_19_qs; + reg_rdata_next[1:0] = alert_class_shadowed_9_qs; end addr_hit[154]: begin - reg_rdata_next[1:0] = alert_class_shadowed_20_qs; + reg_rdata_next[1:0] = alert_class_shadowed_10_qs; end addr_hit[155]: begin - reg_rdata_next[1:0] = alert_class_shadowed_21_qs; + reg_rdata_next[1:0] = alert_class_shadowed_11_qs; end addr_hit[156]: begin - reg_rdata_next[1:0] = alert_class_shadowed_22_qs; + reg_rdata_next[1:0] = alert_class_shadowed_12_qs; end addr_hit[157]: begin - reg_rdata_next[1:0] = alert_class_shadowed_23_qs; + reg_rdata_next[1:0] = alert_class_shadowed_13_qs; end addr_hit[158]: begin - reg_rdata_next[1:0] = alert_class_shadowed_24_qs; + reg_rdata_next[1:0] = alert_class_shadowed_14_qs; end addr_hit[159]: begin - reg_rdata_next[1:0] = alert_class_shadowed_25_qs; + reg_rdata_next[1:0] = alert_class_shadowed_15_qs; end addr_hit[160]: begin - reg_rdata_next[1:0] = alert_class_shadowed_26_qs; + reg_rdata_next[1:0] = alert_class_shadowed_16_qs; end addr_hit[161]: begin - reg_rdata_next[1:0] = alert_class_shadowed_27_qs; + reg_rdata_next[1:0] = alert_class_shadowed_17_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = alert_class_shadowed_28_qs; + reg_rdata_next[1:0] = alert_class_shadowed_18_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = alert_class_shadowed_29_qs; + reg_rdata_next[1:0] = alert_class_shadowed_19_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = alert_class_shadowed_30_qs; + reg_rdata_next[1:0] = alert_class_shadowed_20_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = alert_class_shadowed_31_qs; + reg_rdata_next[1:0] = alert_class_shadowed_21_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = alert_class_shadowed_32_qs; + reg_rdata_next[1:0] = alert_class_shadowed_22_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = alert_class_shadowed_33_qs; + reg_rdata_next[1:0] = alert_class_shadowed_23_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = alert_class_shadowed_34_qs; + reg_rdata_next[1:0] = alert_class_shadowed_24_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = alert_class_shadowed_35_qs; + reg_rdata_next[1:0] = alert_class_shadowed_25_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = alert_class_shadowed_36_qs; + reg_rdata_next[1:0] = alert_class_shadowed_26_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = alert_class_shadowed_37_qs; + reg_rdata_next[1:0] = alert_class_shadowed_27_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = alert_class_shadowed_38_qs; + reg_rdata_next[1:0] = alert_class_shadowed_28_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = alert_class_shadowed_39_qs; + reg_rdata_next[1:0] = alert_class_shadowed_29_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = alert_class_shadowed_40_qs; + reg_rdata_next[1:0] = alert_class_shadowed_30_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = alert_class_shadowed_41_qs; + reg_rdata_next[1:0] = alert_class_shadowed_31_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = alert_class_shadowed_42_qs; + reg_rdata_next[1:0] = alert_class_shadowed_32_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = alert_class_shadowed_43_qs; + reg_rdata_next[1:0] = alert_class_shadowed_33_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = alert_class_shadowed_44_qs; + reg_rdata_next[1:0] = alert_class_shadowed_34_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = alert_class_shadowed_45_qs; + reg_rdata_next[1:0] = alert_class_shadowed_35_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = alert_class_shadowed_46_qs; + reg_rdata_next[1:0] = alert_class_shadowed_36_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = alert_class_shadowed_47_qs; + reg_rdata_next[1:0] = alert_class_shadowed_37_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = alert_class_shadowed_48_qs; + reg_rdata_next[1:0] = alert_class_shadowed_38_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = alert_class_shadowed_49_qs; + reg_rdata_next[1:0] = alert_class_shadowed_39_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = alert_class_shadowed_50_qs; + reg_rdata_next[1:0] = alert_class_shadowed_40_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = alert_class_shadowed_51_qs; + reg_rdata_next[1:0] = alert_class_shadowed_41_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = alert_class_shadowed_52_qs; + reg_rdata_next[1:0] = alert_class_shadowed_42_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = alert_class_shadowed_53_qs; + reg_rdata_next[1:0] = alert_class_shadowed_43_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = alert_class_shadowed_54_qs; + reg_rdata_next[1:0] = alert_class_shadowed_44_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = alert_class_shadowed_55_qs; + reg_rdata_next[1:0] = alert_class_shadowed_45_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = alert_class_shadowed_56_qs; + reg_rdata_next[1:0] = alert_class_shadowed_46_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = alert_class_shadowed_57_qs; + reg_rdata_next[1:0] = alert_class_shadowed_47_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = alert_class_shadowed_58_qs; + reg_rdata_next[1:0] = alert_class_shadowed_48_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = alert_class_shadowed_59_qs; + reg_rdata_next[1:0] = alert_class_shadowed_49_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = alert_class_shadowed_60_qs; + reg_rdata_next[1:0] = alert_class_shadowed_50_qs; end addr_hit[195]: begin - reg_rdata_next[1:0] = alert_class_shadowed_61_qs; + reg_rdata_next[1:0] = alert_class_shadowed_51_qs; end addr_hit[196]: begin - reg_rdata_next[1:0] = alert_class_shadowed_62_qs; + reg_rdata_next[1:0] = alert_class_shadowed_52_qs; end addr_hit[197]: begin - reg_rdata_next[1:0] = alert_class_shadowed_63_qs; + reg_rdata_next[1:0] = alert_class_shadowed_53_qs; end addr_hit[198]: begin - reg_rdata_next[0] = alert_cause_0_qs; + reg_rdata_next[1:0] = alert_class_shadowed_54_qs; end addr_hit[199]: begin - reg_rdata_next[0] = alert_cause_1_qs; + reg_rdata_next[1:0] = alert_class_shadowed_55_qs; end addr_hit[200]: begin - reg_rdata_next[0] = alert_cause_2_qs; + reg_rdata_next[1:0] = alert_class_shadowed_56_qs; end addr_hit[201]: begin - reg_rdata_next[0] = alert_cause_3_qs; + reg_rdata_next[1:0] = alert_class_shadowed_57_qs; end addr_hit[202]: begin - reg_rdata_next[0] = alert_cause_4_qs; + reg_rdata_next[1:0] = alert_class_shadowed_58_qs; end addr_hit[203]: begin - reg_rdata_next[0] = alert_cause_5_qs; + reg_rdata_next[1:0] = alert_class_shadowed_59_qs; end addr_hit[204]: begin - reg_rdata_next[0] = alert_cause_6_qs; + reg_rdata_next[1:0] = alert_class_shadowed_60_qs; end addr_hit[205]: begin - reg_rdata_next[0] = alert_cause_7_qs; + reg_rdata_next[1:0] = alert_class_shadowed_61_qs; end addr_hit[206]: begin - reg_rdata_next[0] = alert_cause_8_qs; + reg_rdata_next[1:0] = alert_class_shadowed_62_qs; end addr_hit[207]: begin - reg_rdata_next[0] = alert_cause_9_qs; + reg_rdata_next[1:0] = alert_class_shadowed_63_qs; end addr_hit[208]: begin - reg_rdata_next[0] = alert_cause_10_qs; + reg_rdata_next[1:0] = alert_class_shadowed_64_qs; end addr_hit[209]: begin - reg_rdata_next[0] = alert_cause_11_qs; + reg_rdata_next[1:0] = alert_class_shadowed_65_qs; end addr_hit[210]: begin - reg_rdata_next[0] = alert_cause_12_qs; + reg_rdata_next[1:0] = alert_class_shadowed_66_qs; end addr_hit[211]: begin - reg_rdata_next[0] = alert_cause_13_qs; + reg_rdata_next[1:0] = alert_class_shadowed_67_qs; end addr_hit[212]: begin - reg_rdata_next[0] = alert_cause_14_qs; + reg_rdata_next[1:0] = alert_class_shadowed_68_qs; end addr_hit[213]: begin - reg_rdata_next[0] = alert_cause_15_qs; + reg_rdata_next[0] = alert_cause_0_qs; end addr_hit[214]: begin - reg_rdata_next[0] = alert_cause_16_qs; + reg_rdata_next[0] = alert_cause_1_qs; end addr_hit[215]: begin - reg_rdata_next[0] = alert_cause_17_qs; + reg_rdata_next[0] = alert_cause_2_qs; end addr_hit[216]: begin - reg_rdata_next[0] = alert_cause_18_qs; + reg_rdata_next[0] = alert_cause_3_qs; end addr_hit[217]: begin - reg_rdata_next[0] = alert_cause_19_qs; + reg_rdata_next[0] = alert_cause_4_qs; end addr_hit[218]: begin - reg_rdata_next[0] = alert_cause_20_qs; + reg_rdata_next[0] = alert_cause_5_qs; end addr_hit[219]: begin - reg_rdata_next[0] = alert_cause_21_qs; + reg_rdata_next[0] = alert_cause_6_qs; end addr_hit[220]: begin - reg_rdata_next[0] = alert_cause_22_qs; + reg_rdata_next[0] = alert_cause_7_qs; end addr_hit[221]: begin - reg_rdata_next[0] = alert_cause_23_qs; + reg_rdata_next[0] = alert_cause_8_qs; end addr_hit[222]: begin - reg_rdata_next[0] = alert_cause_24_qs; + reg_rdata_next[0] = alert_cause_9_qs; end addr_hit[223]: begin - reg_rdata_next[0] = alert_cause_25_qs; + reg_rdata_next[0] = alert_cause_10_qs; end addr_hit[224]: begin - reg_rdata_next[0] = alert_cause_26_qs; + reg_rdata_next[0] = alert_cause_11_qs; end addr_hit[225]: begin - reg_rdata_next[0] = alert_cause_27_qs; + reg_rdata_next[0] = alert_cause_12_qs; end addr_hit[226]: begin - reg_rdata_next[0] = alert_cause_28_qs; + reg_rdata_next[0] = alert_cause_13_qs; end addr_hit[227]: begin - reg_rdata_next[0] = alert_cause_29_qs; + reg_rdata_next[0] = alert_cause_14_qs; end addr_hit[228]: begin - reg_rdata_next[0] = alert_cause_30_qs; + reg_rdata_next[0] = alert_cause_15_qs; end addr_hit[229]: begin - reg_rdata_next[0] = alert_cause_31_qs; + reg_rdata_next[0] = alert_cause_16_qs; end addr_hit[230]: begin - reg_rdata_next[0] = alert_cause_32_qs; + reg_rdata_next[0] = alert_cause_17_qs; end addr_hit[231]: begin - reg_rdata_next[0] = alert_cause_33_qs; + reg_rdata_next[0] = alert_cause_18_qs; end addr_hit[232]: begin - reg_rdata_next[0] = alert_cause_34_qs; + reg_rdata_next[0] = alert_cause_19_qs; end addr_hit[233]: begin - reg_rdata_next[0] = alert_cause_35_qs; + reg_rdata_next[0] = alert_cause_20_qs; end addr_hit[234]: begin - reg_rdata_next[0] = alert_cause_36_qs; + reg_rdata_next[0] = alert_cause_21_qs; end addr_hit[235]: begin - reg_rdata_next[0] = alert_cause_37_qs; + reg_rdata_next[0] = alert_cause_22_qs; end addr_hit[236]: begin - reg_rdata_next[0] = alert_cause_38_qs; + reg_rdata_next[0] = alert_cause_23_qs; end addr_hit[237]: begin - reg_rdata_next[0] = alert_cause_39_qs; + reg_rdata_next[0] = alert_cause_24_qs; end addr_hit[238]: begin - reg_rdata_next[0] = alert_cause_40_qs; + reg_rdata_next[0] = alert_cause_25_qs; end addr_hit[239]: begin - reg_rdata_next[0] = alert_cause_41_qs; + reg_rdata_next[0] = alert_cause_26_qs; end addr_hit[240]: begin - reg_rdata_next[0] = alert_cause_42_qs; + reg_rdata_next[0] = alert_cause_27_qs; end addr_hit[241]: begin - reg_rdata_next[0] = alert_cause_43_qs; + reg_rdata_next[0] = alert_cause_28_qs; end addr_hit[242]: begin - reg_rdata_next[0] = alert_cause_44_qs; + reg_rdata_next[0] = alert_cause_29_qs; end addr_hit[243]: begin - reg_rdata_next[0] = alert_cause_45_qs; + reg_rdata_next[0] = alert_cause_30_qs; end addr_hit[244]: begin - reg_rdata_next[0] = alert_cause_46_qs; + reg_rdata_next[0] = alert_cause_31_qs; end addr_hit[245]: begin - reg_rdata_next[0] = alert_cause_47_qs; + reg_rdata_next[0] = alert_cause_32_qs; end addr_hit[246]: begin - reg_rdata_next[0] = alert_cause_48_qs; + reg_rdata_next[0] = alert_cause_33_qs; end addr_hit[247]: begin - reg_rdata_next[0] = alert_cause_49_qs; + reg_rdata_next[0] = alert_cause_34_qs; end addr_hit[248]: begin - reg_rdata_next[0] = alert_cause_50_qs; + reg_rdata_next[0] = alert_cause_35_qs; end addr_hit[249]: begin - reg_rdata_next[0] = alert_cause_51_qs; + reg_rdata_next[0] = alert_cause_36_qs; end addr_hit[250]: begin - reg_rdata_next[0] = alert_cause_52_qs; + reg_rdata_next[0] = alert_cause_37_qs; end addr_hit[251]: begin - reg_rdata_next[0] = alert_cause_53_qs; + reg_rdata_next[0] = alert_cause_38_qs; end addr_hit[252]: begin - reg_rdata_next[0] = alert_cause_54_qs; + reg_rdata_next[0] = alert_cause_39_qs; end addr_hit[253]: begin - reg_rdata_next[0] = alert_cause_55_qs; + reg_rdata_next[0] = alert_cause_40_qs; end addr_hit[254]: begin - reg_rdata_next[0] = alert_cause_56_qs; + reg_rdata_next[0] = alert_cause_41_qs; end addr_hit[255]: begin - reg_rdata_next[0] = alert_cause_57_qs; + reg_rdata_next[0] = alert_cause_42_qs; end addr_hit[256]: begin - reg_rdata_next[0] = alert_cause_58_qs; + reg_rdata_next[0] = alert_cause_43_qs; end addr_hit[257]: begin - reg_rdata_next[0] = alert_cause_59_qs; + reg_rdata_next[0] = alert_cause_44_qs; end addr_hit[258]: begin - reg_rdata_next[0] = alert_cause_60_qs; + reg_rdata_next[0] = alert_cause_45_qs; end addr_hit[259]: begin - reg_rdata_next[0] = alert_cause_61_qs; + reg_rdata_next[0] = alert_cause_46_qs; end addr_hit[260]: begin - reg_rdata_next[0] = alert_cause_62_qs; + reg_rdata_next[0] = alert_cause_47_qs; end addr_hit[261]: begin - reg_rdata_next[0] = alert_cause_63_qs; + reg_rdata_next[0] = alert_cause_48_qs; end addr_hit[262]: begin - reg_rdata_next[0] = loc_alert_regwen_0_qs; + reg_rdata_next[0] = alert_cause_49_qs; end addr_hit[263]: begin - reg_rdata_next[0] = loc_alert_regwen_1_qs; + reg_rdata_next[0] = alert_cause_50_qs; end addr_hit[264]: begin - reg_rdata_next[0] = loc_alert_regwen_2_qs; + reg_rdata_next[0] = alert_cause_51_qs; end addr_hit[265]: begin - reg_rdata_next[0] = loc_alert_regwen_3_qs; + reg_rdata_next[0] = alert_cause_52_qs; end addr_hit[266]: begin - reg_rdata_next[0] = loc_alert_regwen_4_qs; + reg_rdata_next[0] = alert_cause_53_qs; end addr_hit[267]: begin - reg_rdata_next[0] = loc_alert_regwen_5_qs; + reg_rdata_next[0] = alert_cause_54_qs; end addr_hit[268]: begin - reg_rdata_next[0] = loc_alert_regwen_6_qs; + reg_rdata_next[0] = alert_cause_55_qs; end addr_hit[269]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; + reg_rdata_next[0] = alert_cause_56_qs; end addr_hit[270]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; + reg_rdata_next[0] = alert_cause_57_qs; end addr_hit[271]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; + reg_rdata_next[0] = alert_cause_58_qs; end addr_hit[272]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; + reg_rdata_next[0] = alert_cause_59_qs; end addr_hit[273]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; + reg_rdata_next[0] = alert_cause_60_qs; end addr_hit[274]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; + reg_rdata_next[0] = alert_cause_61_qs; end addr_hit[275]: begin - reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; + reg_rdata_next[0] = alert_cause_62_qs; end addr_hit[276]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; + reg_rdata_next[0] = alert_cause_63_qs; end addr_hit[277]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; + reg_rdata_next[0] = alert_cause_64_qs; end addr_hit[278]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; + reg_rdata_next[0] = alert_cause_65_qs; end addr_hit[279]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; + reg_rdata_next[0] = alert_cause_66_qs; end addr_hit[280]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; + reg_rdata_next[0] = alert_cause_67_qs; end addr_hit[281]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; + reg_rdata_next[0] = alert_cause_68_qs; end addr_hit[282]: begin - reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; + reg_rdata_next[0] = loc_alert_regwen_0_qs; end addr_hit[283]: begin - reg_rdata_next[0] = loc_alert_cause_0_qs; + reg_rdata_next[0] = loc_alert_regwen_1_qs; end addr_hit[284]: begin - reg_rdata_next[0] = loc_alert_cause_1_qs; + reg_rdata_next[0] = loc_alert_regwen_2_qs; end addr_hit[285]: begin - reg_rdata_next[0] = loc_alert_cause_2_qs; + reg_rdata_next[0] = loc_alert_regwen_3_qs; end addr_hit[286]: begin - reg_rdata_next[0] = loc_alert_cause_3_qs; + reg_rdata_next[0] = loc_alert_regwen_4_qs; end addr_hit[287]: begin - reg_rdata_next[0] = loc_alert_cause_4_qs; + reg_rdata_next[0] = loc_alert_regwen_5_qs; end addr_hit[288]: begin - reg_rdata_next[0] = loc_alert_cause_5_qs; + reg_rdata_next[0] = loc_alert_regwen_6_qs; end addr_hit[289]: begin - reg_rdata_next[0] = loc_alert_cause_6_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; end addr_hit[290]: begin - reg_rdata_next[0] = classa_regwen_qs; + reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; end addr_hit[291]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; + end + + addr_hit[292]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; + end + + addr_hit[293]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; + end + + addr_hit[294]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; + end + + addr_hit[295]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; + end + + addr_hit[296]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; + end + + addr_hit[297]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; + end + + addr_hit[298]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; + end + + addr_hit[299]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; + end + + addr_hit[300]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; + end + + addr_hit[301]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; + end + + addr_hit[302]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; + end + + addr_hit[303]: begin + reg_rdata_next[0] = loc_alert_cause_0_qs; + end + + addr_hit[304]: begin + reg_rdata_next[0] = loc_alert_cause_1_qs; + end + + addr_hit[305]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[306]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[307]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[308]: begin + reg_rdata_next[0] = loc_alert_cause_5_qs; + end + + addr_hit[309]: begin + reg_rdata_next[0] = loc_alert_cause_6_qs; + end + + addr_hit[310]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[311]: begin reg_rdata_next[0] = classa_ctrl_shadowed_en_qs; reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs; @@ -18933,59 +19933,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs; end - addr_hit[292]: begin + addr_hit[312]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[293]: begin + addr_hit[313]: begin reg_rdata_next[0] = classa_clr_shadowed_qs; end - addr_hit[294]: begin + addr_hit[314]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[295]: begin + addr_hit[315]: begin reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs; end - addr_hit[296]: begin + addr_hit[316]: begin reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs; end - addr_hit[297]: begin + addr_hit[317]: begin reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs; end - addr_hit[298]: begin + addr_hit[318]: begin reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs; end - addr_hit[299]: begin + addr_hit[319]: begin reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs; end - addr_hit[300]: begin + addr_hit[320]: begin reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs; end - addr_hit[301]: begin + addr_hit[321]: begin reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs; end - addr_hit[302]: begin + addr_hit[322]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[303]: begin + addr_hit[323]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[304]: begin + addr_hit[324]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[305]: begin + addr_hit[325]: begin reg_rdata_next[0] = classb_ctrl_shadowed_en_qs; reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs; @@ -18998,59 +19998,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs; end - addr_hit[306]: begin + addr_hit[326]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[307]: begin + addr_hit[327]: begin reg_rdata_next[0] = classb_clr_shadowed_qs; end - addr_hit[308]: begin + addr_hit[328]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[309]: begin + addr_hit[329]: begin reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs; end - addr_hit[310]: begin + addr_hit[330]: begin reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs; end - addr_hit[311]: begin + addr_hit[331]: begin reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs; end - addr_hit[312]: begin + addr_hit[332]: begin reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs; end - addr_hit[313]: begin + addr_hit[333]: begin reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs; end - addr_hit[314]: begin + addr_hit[334]: begin reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs; end - addr_hit[315]: begin + addr_hit[335]: begin reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs; end - addr_hit[316]: begin + addr_hit[336]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[317]: begin + addr_hit[337]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[318]: begin + addr_hit[338]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[319]: begin + addr_hit[339]: begin reg_rdata_next[0] = classc_ctrl_shadowed_en_qs; reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs; @@ -19063,59 +20063,59 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs; end - addr_hit[320]: begin + addr_hit[340]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[321]: begin + addr_hit[341]: begin reg_rdata_next[0] = classc_clr_shadowed_qs; end - addr_hit[322]: begin + addr_hit[342]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[323]: begin + addr_hit[343]: begin reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs; end - addr_hit[324]: begin + addr_hit[344]: begin reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs; end - addr_hit[325]: begin + addr_hit[345]: begin reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs; end - addr_hit[326]: begin + addr_hit[346]: begin reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs; end - addr_hit[327]: begin + addr_hit[347]: begin reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs; end - addr_hit[328]: begin + addr_hit[348]: begin reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs; end - addr_hit[329]: begin + addr_hit[349]: begin reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs; end - addr_hit[330]: begin + addr_hit[350]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[331]: begin + addr_hit[351]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[332]: begin + addr_hit[352]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[333]: begin + addr_hit[353]: begin reg_rdata_next[0] = classd_ctrl_shadowed_en_qs; reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs; reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs; @@ -19128,51 +20128,51 @@ module alert_handler_reg_top ( reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs; end - addr_hit[334]: begin + addr_hit[354]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[335]: begin + addr_hit[355]: begin reg_rdata_next[0] = classd_clr_shadowed_qs; end - addr_hit[336]: begin + addr_hit[356]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[337]: begin + addr_hit[357]: begin reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs; end - addr_hit[338]: begin + addr_hit[358]: begin reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs; end - addr_hit[339]: begin + addr_hit[359]: begin reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs; end - addr_hit[340]: begin + addr_hit[360]: begin reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs; end - addr_hit[341]: begin + addr_hit[361]: begin reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs; end - addr_hit[342]: begin + addr_hit[362]: begin reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs; end - addr_hit[343]: begin + addr_hit[363]: begin reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs; end - addr_hit[344]: begin + addr_hit[364]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[345]: begin + addr_hit[365]: begin reg_rdata_next[2:0] = classd_state_qs; end @@ -19273,6 +20273,11 @@ module alert_handler_reg_top ( alert_en_shadowed_61_storage_err, alert_en_shadowed_62_storage_err, alert_en_shadowed_63_storage_err, + alert_en_shadowed_64_storage_err, + alert_en_shadowed_65_storage_err, + alert_en_shadowed_66_storage_err, + alert_en_shadowed_67_storage_err, + alert_en_shadowed_68_storage_err, alert_class_shadowed_0_storage_err, alert_class_shadowed_1_storage_err, alert_class_shadowed_2_storage_err, @@ -19337,6 +20342,11 @@ module alert_handler_reg_top ( alert_class_shadowed_61_storage_err, alert_class_shadowed_62_storage_err, alert_class_shadowed_63_storage_err, + alert_class_shadowed_64_storage_err, + alert_class_shadowed_65_storage_err, + alert_class_shadowed_66_storage_err, + alert_class_shadowed_67_storage_err, + alert_class_shadowed_68_storage_err, loc_alert_en_shadowed_0_storage_err, loc_alert_en_shadowed_1_storage_err, loc_alert_en_shadowed_2_storage_err, @@ -19491,6 +20501,11 @@ module alert_handler_reg_top ( alert_en_shadowed_61_update_err, alert_en_shadowed_62_update_err, alert_en_shadowed_63_update_err, + alert_en_shadowed_64_update_err, + alert_en_shadowed_65_update_err, + alert_en_shadowed_66_update_err, + alert_en_shadowed_67_update_err, + alert_en_shadowed_68_update_err, alert_class_shadowed_0_update_err, alert_class_shadowed_1_update_err, alert_class_shadowed_2_update_err, @@ -19555,6 +20570,11 @@ module alert_handler_reg_top ( alert_class_shadowed_61_update_err, alert_class_shadowed_62_update_err, alert_class_shadowed_63_update_err, + alert_class_shadowed_64_update_err, + alert_class_shadowed_65_update_err, + alert_class_shadowed_66_update_err, + alert_class_shadowed_67_update_err, + alert_class_shadowed_68_update_err, loc_alert_en_shadowed_0_update_err, loc_alert_en_shadowed_1_update_err, loc_alert_en_shadowed_2_update_err, diff --git a/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson b/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson index f4bcb97b67b5b..d8d4abdf74ce5 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson +++ b/hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson @@ -349,13 +349,13 @@ { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", - default: "57", + default: "60", local: "true" }, { name: "NMioPeriphOut", desc: "Number of muxed peripheral outputs", type: "int", - default: "65", + default: "66", local: "true" }, { name: "NMioPads", diff --git a/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson index d778e7f04ac66..f5a5380ff08cc 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson @@ -8,8 +8,8 @@ n_wkup_detect: 8 wkup_cnt_width: 8 n_mio_pads: 47 - n_mio_periph_in: 57 - n_mio_periph_out: 65 + n_mio_periph_in: 60 + n_mio_periph_out: 66 n_dio_pads: 16 n_dio_periph_in: 14 n_dio_periph_out: 14 diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md index f3f659e76e453..fed97f11c22a4 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md @@ -146,6 +146,9 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTck

|

| |

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTms

|

| |

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| +|

rram_macro_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTck

|

| +|

rram_macro_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTms

|

| +|

rram_macro_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTdi

|

| |

sysrst_ctrl_ac_present

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent

|

| |

sysrst_ctrl_key0_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In

|

| |

sysrst_ctrl_key1_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In

|

| @@ -162,6 +165,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| |

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| +|

rram_macro_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselRramMacroTdo / -

|

| |

sensor_ctrl_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 / -

|

| |

sensor_ctrl_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 / -

|

| |

sensor_ctrl_ast_debug_out[2]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 / -

|

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md index c56d55794a705..cf390004c8c18 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md @@ -150,6 +150,9 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTck

|

| |

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTms

|

| |

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| +|

rram_macro_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTck

|

| +|

rram_macro_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTms

|

| +|

rram_macro_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTdi

|

| |

sysrst_ctrl_ac_present

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent

|

| |

sysrst_ctrl_key0_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In

|

| |

sysrst_ctrl_key1_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In

|

| @@ -166,6 +169,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| |

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| +|

rram_macro_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselRramMacroTdo / -

|

| |

sensor_ctrl_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 / -

|

| |

sensor_ctrl_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 / -

|

| |

sensor_ctrl_ast_debug_out[2]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 / -

|

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md index 3f38e039b26e7..1c3a77c33fb5c 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md @@ -146,6 +146,9 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTck

|

| |

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTms

|

| |

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| +|

rram_macro_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTck

|

| +|

rram_macro_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTms

|

| +|

rram_macro_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInRramMacroTdi

|

| |

sysrst_ctrl_ac_present

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent

|

| |

sysrst_ctrl_key0_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In

|

| |

sysrst_ctrl_key1_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In

|

| @@ -162,6 +165,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| |

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| +|

rram_macro_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselRramMacroTdo / -

|

| |

sensor_ctrl_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 / -

|

| |

sensor_ctrl_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 / -

|

| |

sensor_ctrl_ast_debug_out[2]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 / -

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| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md index ec01c4628b2c1..f2781465dabab 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/registers.md @@ -63,516 +63,522 @@ | pinmux.[`MIO_PERIPH_INSEL_REGWEN_54`](#mio_periph_insel_regwen) | 0xdc | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_55`](#mio_periph_insel_regwen) | 0xe0 | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_56`](#mio_periph_insel_regwen) | 0xe4 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0xe8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xec | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xf0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0x134 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0x138 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0x13c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0x140 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0x144 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0x148 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x14c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x150 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x154 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x158 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x15c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x160 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x164 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x168 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x16c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x170 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x174 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x178 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x17c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_38`](#mio_periph_insel) | 0x180 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_39`](#mio_periph_insel) | 0x184 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_40`](#mio_periph_insel) | 0x188 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_41`](#mio_periph_insel) | 0x18c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_42`](#mio_periph_insel) | 0x190 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_43`](#mio_periph_insel) | 0x194 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_44`](#mio_periph_insel) | 0x198 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_45`](#mio_periph_insel) | 0x19c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_46`](#mio_periph_insel) | 0x1a0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_47`](#mio_periph_insel) | 0x1a4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_48`](#mio_periph_insel) | 0x1a8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_49`](#mio_periph_insel) | 0x1ac | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_50`](#mio_periph_insel) | 0x1b0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_51`](#mio_periph_insel) | 0x1b4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_52`](#mio_periph_insel) | 0x1b8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_53`](#mio_periph_insel) | 0x1bc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_54`](#mio_periph_insel) | 0x1c0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_55`](#mio_periph_insel) | 0x1c4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_56`](#mio_periph_insel) | 0x1c8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x1cc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x1d0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x1d4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x1d8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x1dc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x1e0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x1f0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x1f4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x1f8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x1fc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x200 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x204 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x208 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x20c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x210 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x214 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x218 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x21c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x220 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x224 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x228 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x22c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x230 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x234 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x238 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x23c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x240 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x244 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x248 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x24c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x250 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x254 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x258 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x25c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x260 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x264 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x268 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x26c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x270 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x274 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x278 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x27c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x280 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x284 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x288 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x28c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x290 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x294 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x298 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x29c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x2ac | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x2b0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x2b4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x2b8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x2bc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x2c0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x2c4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x2c8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x2cc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x2d0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x2d4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x2d8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x2dc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x2e0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x2e4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x2e8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x2ec | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x2f0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x2f4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x2f8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x2fc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x300 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x304 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x308 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x30c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x310 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x314 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x318 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x31c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x320 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x324 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x328 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x32c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x330 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x334 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x338 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x33c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x340 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x344 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x348 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x34c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x350 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x354 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x358 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x368 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x36c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x370 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x374 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x378 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x37c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x380 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x384 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x388 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x38c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x390 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x394 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x398 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x39c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x3a0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x3a4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x3a8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x3ac | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x3b0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x3b4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x3b8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x3bc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x3c0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x3c4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x3c8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x3cc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x3d0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x3d4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x3d8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x3dc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x3e0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x3e4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x3e8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x3ec | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x3f0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x3f4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x3f8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x3fc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x400 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x404 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x408 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x40c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x410 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x414 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x424 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x428 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x42c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x430 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x434 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x438 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x43c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x440 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x444 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x448 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x44c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x450 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x454 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x458 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x45c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x460 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x464 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x468 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x46c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x470 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x474 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x478 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x47c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x480 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x484 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x488 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x48c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x490 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x494 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x498 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x49c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x4a0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x4a4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x4a8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x4ac | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x4b0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x4b4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x4b8 | 4 | Muxed pad attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x4bc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x4c0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x4c4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x4c8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x4cc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x4d0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x4d4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x4d8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x4dc | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x4e0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x4e4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x4e8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x4ec | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x4f0 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x4f4 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x4f8 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x4fc | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x500 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x504 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x508 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x50c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x510 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x514 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x518 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x51c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x520 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x524 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x528 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x52c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x530 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x534 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x538 | 4 | Dedicated pad attributes. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#mio_pad_sleep_status_0) | 0x53c | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#mio_pad_sleep_status_1) | 0x540 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x544 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x548 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x54c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x550 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x554 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x558 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x55c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x560 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x564 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x568 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x56c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x570 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x574 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x578 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x57c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x580 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x584 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x588 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x58c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x590 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x594 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x598 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x59c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x5a0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x5a4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x5a8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x5ac | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x5b0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x5b4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x5b8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x5bc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x5c0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x5c4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x5c8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x5cc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x5d0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x5d4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x5d8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x5dc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x5e0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x5e4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x5e8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x5ec | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x5f0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x5f4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x5f8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x5fc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x600 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x604 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x608 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x60c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x614 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x618 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x61c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x620 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x624 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x628 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x62c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x630 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x634 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x638 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x63c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x640 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x644 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x648 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x64c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x650 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x654 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x658 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x65c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x660 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x664 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x668 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x66c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x670 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x674 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x678 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x67c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x680 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x684 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x688 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x68c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x690 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x694 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x698 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x69c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x6a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x6a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x6a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x6ac | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x6b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x6b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x6b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x6bc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x6c0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x6c4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x6c8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x6d0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) | 0x778 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x77c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x780 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x784 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x788 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x78c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x790 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x794 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x798 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x79c | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x7a0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x7a4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x7a8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x7ac | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x7b0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x7b4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x7b8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x7bc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x7c0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x7c4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x7c8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x7cc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x7d0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x7d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x7d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x7dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x7e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x7e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x7e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x7ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x7f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x7f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x7f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x7fc | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x800 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x804 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x808 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x80c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x810 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x814 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x818 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x81c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x820 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x824 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x828 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x82c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x830 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x834 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x838 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x83c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x840 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x844 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x848 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x84c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x850 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x854 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x858 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x85c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x860 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x864 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x868 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x86c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x870 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x874 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x878 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x87c | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x880 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x884 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x888 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x88c | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x890 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x894 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x898 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x89c | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x8a0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x8a4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x8a8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x8ac | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x8b0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x8b4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x8b8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x8bc | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x8c0 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x8c4 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x8c8 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x8cc | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x8d0 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x8d4 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x8d8 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x8dc | 4 | Cause registers for wakeup detectors. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_57`](#mio_periph_insel_regwen) | 0xe8 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_58`](#mio_periph_insel_regwen) | 0xec | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_59`](#mio_periph_insel_regwen) | 0xf0 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0x134 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0x138 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0x13c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0x140 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0x144 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0x148 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0x14c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0x150 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0x154 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x158 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x15c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x160 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x164 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x168 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x16c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x170 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x174 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x178 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x17c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x180 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x184 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x188 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_38`](#mio_periph_insel) | 0x18c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_39`](#mio_periph_insel) | 0x190 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_40`](#mio_periph_insel) | 0x194 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_41`](#mio_periph_insel) | 0x198 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_42`](#mio_periph_insel) | 0x19c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_43`](#mio_periph_insel) | 0x1a0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_44`](#mio_periph_insel) | 0x1a4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_45`](#mio_periph_insel) | 0x1a8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_46`](#mio_periph_insel) | 0x1ac | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_47`](#mio_periph_insel) | 0x1b0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_48`](#mio_periph_insel) | 0x1b4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_49`](#mio_periph_insel) | 0x1b8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_50`](#mio_periph_insel) | 0x1bc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_51`](#mio_periph_insel) | 0x1c0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_52`](#mio_periph_insel) | 0x1c4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_53`](#mio_periph_insel) | 0x1c8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_54`](#mio_periph_insel) | 0x1cc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_55`](#mio_periph_insel) | 0x1d0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_56`](#mio_periph_insel) | 0x1d4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_57`](#mio_periph_insel) | 0x1d8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_58`](#mio_periph_insel) | 0x1dc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_59`](#mio_periph_insel) | 0x1e0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x1f0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x1f4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x1f8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x1fc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x200 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x204 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x208 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x20c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x210 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x214 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x218 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x21c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x220 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x224 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x228 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x22c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x230 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x234 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x238 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x23c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x240 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x244 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x248 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x24c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x250 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x254 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x258 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x25c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x260 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x264 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x268 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x26c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x270 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x274 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x278 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x27c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x280 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x284 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x288 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x28c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x290 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x294 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x298 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x29c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x2ac | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x2b0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x2b4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x2b8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x2bc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x2c0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x2c4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x2c8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x2cc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x2d0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x2d4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x2d8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x2dc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x2e0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x2e4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x2e8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x2ec | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x2f0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x2f4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x2f8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x2fc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x300 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x304 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x308 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x30c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x310 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x314 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x318 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x31c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x320 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x324 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x328 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x32c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x330 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x334 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x338 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x33c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x340 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x344 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x348 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x34c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x350 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x354 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x358 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x368 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x36c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x370 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x374 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x378 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x37c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x380 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x384 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x388 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x38c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x390 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x394 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x398 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x39c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x3a0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x3a4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x3a8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x3ac | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x3b0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x3b4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x3b8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x3bc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x3c0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x3c4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x3c8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x3cc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x3d0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x3d4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x3d8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x3dc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x3e0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x3e4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x3e8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x3ec | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x3f0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x3f4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x3f8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x3fc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x400 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x404 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x408 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x40c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x410 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x414 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x424 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x428 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x42c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x430 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x434 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x438 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x43c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x440 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x444 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x448 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x44c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x450 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x454 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x458 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x45c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x460 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x464 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x468 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x46c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x470 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x474 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x478 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x47c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x480 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x484 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x488 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x48c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x490 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x494 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x498 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x49c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x4a0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x4a4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x4a8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x4ac | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x4b0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x4b4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x4b8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x4bc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x4c0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x4c4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x4c8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x4cc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x4d0 | 4 | Muxed pad attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x4d4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x4d8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x4dc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x4e0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x4e4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x4e8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x4ec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x4f0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x4f4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x4f8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x4fc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x500 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x504 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x508 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x50c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x510 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x514 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x518 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x51c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x520 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x524 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x528 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x52c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x530 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x534 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x538 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x53c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x540 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x544 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x548 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x54c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x550 | 4 | Dedicated pad attributes. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#mio_pad_sleep_status_0) | 0x554 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#mio_pad_sleep_status_1) | 0x558 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x55c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x560 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x564 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x568 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x56c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x570 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x574 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x578 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x57c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x580 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x584 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x588 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x58c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x590 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x594 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x598 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x59c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x5a0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x5a4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x5a8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x5ac | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x5b0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x5b4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x5b8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x5bc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x5c0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x5c4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x5c8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x5cc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x5d0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x5d4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x5d8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x5dc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x5e0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x5e4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x5e8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x5ec | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x5f0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x5f4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x5f8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x5fc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x600 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x604 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x608 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x60c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x610 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x614 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x618 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x61c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x620 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x624 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x628 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x62c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x630 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x634 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x638 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x63c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x640 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x644 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x648 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x64c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x650 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x654 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x658 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x65c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x660 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x664 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x668 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x66c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x670 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x674 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x678 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x67c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x680 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x684 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x688 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x68c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x690 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x694 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x698 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x69c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x6a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x6a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x6a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x6ac | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x6b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x6b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x6b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x6bc | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x6c0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x6c4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x6c8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x6cc | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x6d0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x778 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x77c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x780 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x784 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x788 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x78c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) | 0x790 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x794 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x798 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x79c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x7a0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x7a4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x7a8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x7ac | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x7b0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x7b4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x7b8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x7bc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x7c0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x7c4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x7c8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x7cc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x7d0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x7d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x7d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x7dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x7e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x7e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x7e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x7ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x7f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x7f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x7f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x7fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x800 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x804 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x808 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x80c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x810 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x814 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x818 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x81c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x820 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x824 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x828 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x82c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x830 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x834 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x838 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x83c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x840 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x844 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x848 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x84c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x850 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x854 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x858 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x85c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x860 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x864 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x868 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x86c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x870 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x874 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x878 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x87c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x880 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x884 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x888 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x88c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x890 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x894 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x898 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x89c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x8a0 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x8a4 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x8a8 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x8ac | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x8b0 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x8b4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x8b8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x8bc | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x8c0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x8c4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x8c8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x8cc | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x8d0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x8d4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x8d8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x8dc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x8e0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x8e4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x8e8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x8ec | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x8f0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x8f4 | 4 | Cause registers for wakeup detectors. | ## ALERT_TEST Alert Test Register @@ -657,6 +663,9 @@ Register write enable for MIO peripheral input selects. | MIO_PERIPH_INSEL_REGWEN_54 | 0xdc | | MIO_PERIPH_INSEL_REGWEN_55 | 0xe0 | | MIO_PERIPH_INSEL_REGWEN_56 | 0xe4 | +| MIO_PERIPH_INSEL_REGWEN_57 | 0xe8 | +| MIO_PERIPH_INSEL_REGWEN_58 | 0xec | +| MIO_PERIPH_INSEL_REGWEN_59 | 0xf0 | ### Fields @@ -680,63 +689,66 @@ For each peripheral input, this selects the muxable pad input. | Name | Offset | |:--------------------|:---------| -| MIO_PERIPH_INSEL_0 | 0xe8 | -| MIO_PERIPH_INSEL_1 | 0xec | -| MIO_PERIPH_INSEL_2 | 0xf0 | -| MIO_PERIPH_INSEL_3 | 0xf4 | -| MIO_PERIPH_INSEL_4 | 0xf8 | -| MIO_PERIPH_INSEL_5 | 0xfc | -| MIO_PERIPH_INSEL_6 | 0x100 | -| MIO_PERIPH_INSEL_7 | 0x104 | -| MIO_PERIPH_INSEL_8 | 0x108 | -| MIO_PERIPH_INSEL_9 | 0x10c | -| MIO_PERIPH_INSEL_10 | 0x110 | -| MIO_PERIPH_INSEL_11 | 0x114 | -| MIO_PERIPH_INSEL_12 | 0x118 | -| MIO_PERIPH_INSEL_13 | 0x11c | -| MIO_PERIPH_INSEL_14 | 0x120 | -| MIO_PERIPH_INSEL_15 | 0x124 | -| MIO_PERIPH_INSEL_16 | 0x128 | -| MIO_PERIPH_INSEL_17 | 0x12c | -| MIO_PERIPH_INSEL_18 | 0x130 | -| MIO_PERIPH_INSEL_19 | 0x134 | -| MIO_PERIPH_INSEL_20 | 0x138 | -| MIO_PERIPH_INSEL_21 | 0x13c | -| MIO_PERIPH_INSEL_22 | 0x140 | -| MIO_PERIPH_INSEL_23 | 0x144 | -| MIO_PERIPH_INSEL_24 | 0x148 | -| MIO_PERIPH_INSEL_25 | 0x14c | -| MIO_PERIPH_INSEL_26 | 0x150 | -| MIO_PERIPH_INSEL_27 | 0x154 | -| MIO_PERIPH_INSEL_28 | 0x158 | -| MIO_PERIPH_INSEL_29 | 0x15c | -| MIO_PERIPH_INSEL_30 | 0x160 | -| MIO_PERIPH_INSEL_31 | 0x164 | -| MIO_PERIPH_INSEL_32 | 0x168 | -| MIO_PERIPH_INSEL_33 | 0x16c | -| MIO_PERIPH_INSEL_34 | 0x170 | -| MIO_PERIPH_INSEL_35 | 0x174 | -| MIO_PERIPH_INSEL_36 | 0x178 | -| MIO_PERIPH_INSEL_37 | 0x17c | -| MIO_PERIPH_INSEL_38 | 0x180 | -| MIO_PERIPH_INSEL_39 | 0x184 | -| MIO_PERIPH_INSEL_40 | 0x188 | -| MIO_PERIPH_INSEL_41 | 0x18c | -| MIO_PERIPH_INSEL_42 | 0x190 | -| MIO_PERIPH_INSEL_43 | 0x194 | -| MIO_PERIPH_INSEL_44 | 0x198 | -| MIO_PERIPH_INSEL_45 | 0x19c | -| MIO_PERIPH_INSEL_46 | 0x1a0 | -| MIO_PERIPH_INSEL_47 | 0x1a4 | -| MIO_PERIPH_INSEL_48 | 0x1a8 | -| MIO_PERIPH_INSEL_49 | 0x1ac | -| MIO_PERIPH_INSEL_50 | 0x1b0 | -| MIO_PERIPH_INSEL_51 | 0x1b4 | -| MIO_PERIPH_INSEL_52 | 0x1b8 | -| MIO_PERIPH_INSEL_53 | 0x1bc | -| MIO_PERIPH_INSEL_54 | 0x1c0 | -| MIO_PERIPH_INSEL_55 | 0x1c4 | -| MIO_PERIPH_INSEL_56 | 0x1c8 | +| MIO_PERIPH_INSEL_0 | 0xf4 | +| MIO_PERIPH_INSEL_1 | 0xf8 | +| MIO_PERIPH_INSEL_2 | 0xfc | +| MIO_PERIPH_INSEL_3 | 0x100 | +| MIO_PERIPH_INSEL_4 | 0x104 | +| MIO_PERIPH_INSEL_5 | 0x108 | +| MIO_PERIPH_INSEL_6 | 0x10c | +| MIO_PERIPH_INSEL_7 | 0x110 | +| MIO_PERIPH_INSEL_8 | 0x114 | +| MIO_PERIPH_INSEL_9 | 0x118 | +| MIO_PERIPH_INSEL_10 | 0x11c | +| MIO_PERIPH_INSEL_11 | 0x120 | +| MIO_PERIPH_INSEL_12 | 0x124 | +| MIO_PERIPH_INSEL_13 | 0x128 | +| MIO_PERIPH_INSEL_14 | 0x12c | +| MIO_PERIPH_INSEL_15 | 0x130 | +| MIO_PERIPH_INSEL_16 | 0x134 | +| MIO_PERIPH_INSEL_17 | 0x138 | +| MIO_PERIPH_INSEL_18 | 0x13c | +| MIO_PERIPH_INSEL_19 | 0x140 | +| MIO_PERIPH_INSEL_20 | 0x144 | +| MIO_PERIPH_INSEL_21 | 0x148 | +| MIO_PERIPH_INSEL_22 | 0x14c | +| MIO_PERIPH_INSEL_23 | 0x150 | +| MIO_PERIPH_INSEL_24 | 0x154 | +| MIO_PERIPH_INSEL_25 | 0x158 | +| MIO_PERIPH_INSEL_26 | 0x15c | +| MIO_PERIPH_INSEL_27 | 0x160 | +| MIO_PERIPH_INSEL_28 | 0x164 | +| MIO_PERIPH_INSEL_29 | 0x168 | +| MIO_PERIPH_INSEL_30 | 0x16c | +| MIO_PERIPH_INSEL_31 | 0x170 | +| MIO_PERIPH_INSEL_32 | 0x174 | +| MIO_PERIPH_INSEL_33 | 0x178 | +| MIO_PERIPH_INSEL_34 | 0x17c | +| MIO_PERIPH_INSEL_35 | 0x180 | +| MIO_PERIPH_INSEL_36 | 0x184 | +| MIO_PERIPH_INSEL_37 | 0x188 | +| MIO_PERIPH_INSEL_38 | 0x18c | +| MIO_PERIPH_INSEL_39 | 0x190 | +| MIO_PERIPH_INSEL_40 | 0x194 | +| MIO_PERIPH_INSEL_41 | 0x198 | +| MIO_PERIPH_INSEL_42 | 0x19c | +| MIO_PERIPH_INSEL_43 | 0x1a0 | +| MIO_PERIPH_INSEL_44 | 0x1a4 | +| MIO_PERIPH_INSEL_45 | 0x1a8 | +| MIO_PERIPH_INSEL_46 | 0x1ac | +| MIO_PERIPH_INSEL_47 | 0x1b0 | +| MIO_PERIPH_INSEL_48 | 0x1b4 | +| MIO_PERIPH_INSEL_49 | 0x1b8 | +| MIO_PERIPH_INSEL_50 | 0x1bc | +| MIO_PERIPH_INSEL_51 | 0x1c0 | +| MIO_PERIPH_INSEL_52 | 0x1c4 | +| MIO_PERIPH_INSEL_53 | 0x1c8 | +| MIO_PERIPH_INSEL_54 | 0x1cc | +| MIO_PERIPH_INSEL_55 | 0x1d0 | +| MIO_PERIPH_INSEL_56 | 0x1d4 | +| MIO_PERIPH_INSEL_57 | 0x1d8 | +| MIO_PERIPH_INSEL_58 | 0x1dc | +| MIO_PERIPH_INSEL_59 | 0x1e0 | ### Fields @@ -759,53 +771,53 @@ Register write enable for MIO output selects. | Name | Offset | |:---------------------|:---------| -| MIO_OUTSEL_REGWEN_0 | 0x1cc | -| MIO_OUTSEL_REGWEN_1 | 0x1d0 | -| MIO_OUTSEL_REGWEN_2 | 0x1d4 | -| MIO_OUTSEL_REGWEN_3 | 0x1d8 | -| MIO_OUTSEL_REGWEN_4 | 0x1dc | -| MIO_OUTSEL_REGWEN_5 | 0x1e0 | -| MIO_OUTSEL_REGWEN_6 | 0x1e4 | -| MIO_OUTSEL_REGWEN_7 | 0x1e8 | -| MIO_OUTSEL_REGWEN_8 | 0x1ec | -| MIO_OUTSEL_REGWEN_9 | 0x1f0 | -| MIO_OUTSEL_REGWEN_10 | 0x1f4 | -| MIO_OUTSEL_REGWEN_11 | 0x1f8 | -| MIO_OUTSEL_REGWEN_12 | 0x1fc | -| MIO_OUTSEL_REGWEN_13 | 0x200 | -| MIO_OUTSEL_REGWEN_14 | 0x204 | -| MIO_OUTSEL_REGWEN_15 | 0x208 | -| MIO_OUTSEL_REGWEN_16 | 0x20c | -| MIO_OUTSEL_REGWEN_17 | 0x210 | -| MIO_OUTSEL_REGWEN_18 | 0x214 | -| MIO_OUTSEL_REGWEN_19 | 0x218 | -| MIO_OUTSEL_REGWEN_20 | 0x21c | -| MIO_OUTSEL_REGWEN_21 | 0x220 | -| MIO_OUTSEL_REGWEN_22 | 0x224 | -| MIO_OUTSEL_REGWEN_23 | 0x228 | -| MIO_OUTSEL_REGWEN_24 | 0x22c | -| MIO_OUTSEL_REGWEN_25 | 0x230 | -| MIO_OUTSEL_REGWEN_26 | 0x234 | -| MIO_OUTSEL_REGWEN_27 | 0x238 | -| MIO_OUTSEL_REGWEN_28 | 0x23c | -| MIO_OUTSEL_REGWEN_29 | 0x240 | -| MIO_OUTSEL_REGWEN_30 | 0x244 | -| MIO_OUTSEL_REGWEN_31 | 0x248 | -| MIO_OUTSEL_REGWEN_32 | 0x24c | -| MIO_OUTSEL_REGWEN_33 | 0x250 | -| MIO_OUTSEL_REGWEN_34 | 0x254 | -| MIO_OUTSEL_REGWEN_35 | 0x258 | -| MIO_OUTSEL_REGWEN_36 | 0x25c | -| MIO_OUTSEL_REGWEN_37 | 0x260 | -| MIO_OUTSEL_REGWEN_38 | 0x264 | -| MIO_OUTSEL_REGWEN_39 | 0x268 | -| MIO_OUTSEL_REGWEN_40 | 0x26c | -| MIO_OUTSEL_REGWEN_41 | 0x270 | -| MIO_OUTSEL_REGWEN_42 | 0x274 | -| MIO_OUTSEL_REGWEN_43 | 0x278 | -| MIO_OUTSEL_REGWEN_44 | 0x27c | -| MIO_OUTSEL_REGWEN_45 | 0x280 | -| MIO_OUTSEL_REGWEN_46 | 0x284 | +| MIO_OUTSEL_REGWEN_0 | 0x1e4 | +| MIO_OUTSEL_REGWEN_1 | 0x1e8 | +| MIO_OUTSEL_REGWEN_2 | 0x1ec | +| MIO_OUTSEL_REGWEN_3 | 0x1f0 | +| MIO_OUTSEL_REGWEN_4 | 0x1f4 | +| MIO_OUTSEL_REGWEN_5 | 0x1f8 | +| MIO_OUTSEL_REGWEN_6 | 0x1fc | +| MIO_OUTSEL_REGWEN_7 | 0x200 | +| MIO_OUTSEL_REGWEN_8 | 0x204 | +| MIO_OUTSEL_REGWEN_9 | 0x208 | +| MIO_OUTSEL_REGWEN_10 | 0x20c | +| MIO_OUTSEL_REGWEN_11 | 0x210 | +| MIO_OUTSEL_REGWEN_12 | 0x214 | +| MIO_OUTSEL_REGWEN_13 | 0x218 | +| MIO_OUTSEL_REGWEN_14 | 0x21c | +| MIO_OUTSEL_REGWEN_15 | 0x220 | +| MIO_OUTSEL_REGWEN_16 | 0x224 | +| MIO_OUTSEL_REGWEN_17 | 0x228 | +| MIO_OUTSEL_REGWEN_18 | 0x22c | +| MIO_OUTSEL_REGWEN_19 | 0x230 | +| MIO_OUTSEL_REGWEN_20 | 0x234 | +| MIO_OUTSEL_REGWEN_21 | 0x238 | +| MIO_OUTSEL_REGWEN_22 | 0x23c | +| MIO_OUTSEL_REGWEN_23 | 0x240 | +| MIO_OUTSEL_REGWEN_24 | 0x244 | +| MIO_OUTSEL_REGWEN_25 | 0x248 | +| MIO_OUTSEL_REGWEN_26 | 0x24c | +| MIO_OUTSEL_REGWEN_27 | 0x250 | +| MIO_OUTSEL_REGWEN_28 | 0x254 | +| MIO_OUTSEL_REGWEN_29 | 0x258 | +| MIO_OUTSEL_REGWEN_30 | 0x25c | +| MIO_OUTSEL_REGWEN_31 | 0x260 | +| MIO_OUTSEL_REGWEN_32 | 0x264 | +| MIO_OUTSEL_REGWEN_33 | 0x268 | +| MIO_OUTSEL_REGWEN_34 | 0x26c | +| MIO_OUTSEL_REGWEN_35 | 0x270 | +| MIO_OUTSEL_REGWEN_36 | 0x274 | +| MIO_OUTSEL_REGWEN_37 | 0x278 | +| MIO_OUTSEL_REGWEN_38 | 0x27c | +| MIO_OUTSEL_REGWEN_39 | 0x280 | +| MIO_OUTSEL_REGWEN_40 | 0x284 | +| MIO_OUTSEL_REGWEN_41 | 0x288 | +| MIO_OUTSEL_REGWEN_42 | 0x28c | +| MIO_OUTSEL_REGWEN_43 | 0x290 | +| MIO_OUTSEL_REGWEN_44 | 0x294 | +| MIO_OUTSEL_REGWEN_45 | 0x298 | +| MIO_OUTSEL_REGWEN_46 | 0x29c | ### Fields @@ -829,53 +841,53 @@ For each muxable pad, this selects the peripheral output. | Name | Offset | |:--------------|:---------| -| MIO_OUTSEL_0 | 0x288 | -| MIO_OUTSEL_1 | 0x28c | -| MIO_OUTSEL_2 | 0x290 | -| MIO_OUTSEL_3 | 0x294 | -| MIO_OUTSEL_4 | 0x298 | -| MIO_OUTSEL_5 | 0x29c | -| MIO_OUTSEL_6 | 0x2a0 | -| MIO_OUTSEL_7 | 0x2a4 | -| MIO_OUTSEL_8 | 0x2a8 | -| MIO_OUTSEL_9 | 0x2ac | -| MIO_OUTSEL_10 | 0x2b0 | -| MIO_OUTSEL_11 | 0x2b4 | -| MIO_OUTSEL_12 | 0x2b8 | -| MIO_OUTSEL_13 | 0x2bc | -| MIO_OUTSEL_14 | 0x2c0 | -| MIO_OUTSEL_15 | 0x2c4 | -| MIO_OUTSEL_16 | 0x2c8 | -| MIO_OUTSEL_17 | 0x2cc | -| MIO_OUTSEL_18 | 0x2d0 | -| MIO_OUTSEL_19 | 0x2d4 | -| MIO_OUTSEL_20 | 0x2d8 | -| MIO_OUTSEL_21 | 0x2dc | -| MIO_OUTSEL_22 | 0x2e0 | -| MIO_OUTSEL_23 | 0x2e4 | -| MIO_OUTSEL_24 | 0x2e8 | -| MIO_OUTSEL_25 | 0x2ec | -| MIO_OUTSEL_26 | 0x2f0 | -| MIO_OUTSEL_27 | 0x2f4 | -| MIO_OUTSEL_28 | 0x2f8 | -| MIO_OUTSEL_29 | 0x2fc | -| MIO_OUTSEL_30 | 0x300 | -| MIO_OUTSEL_31 | 0x304 | -| MIO_OUTSEL_32 | 0x308 | -| MIO_OUTSEL_33 | 0x30c | -| MIO_OUTSEL_34 | 0x310 | -| MIO_OUTSEL_35 | 0x314 | -| MIO_OUTSEL_36 | 0x318 | -| MIO_OUTSEL_37 | 0x31c | -| MIO_OUTSEL_38 | 0x320 | -| MIO_OUTSEL_39 | 0x324 | -| MIO_OUTSEL_40 | 0x328 | -| MIO_OUTSEL_41 | 0x32c | -| MIO_OUTSEL_42 | 0x330 | -| MIO_OUTSEL_43 | 0x334 | -| MIO_OUTSEL_44 | 0x338 | -| MIO_OUTSEL_45 | 0x33c | -| MIO_OUTSEL_46 | 0x340 | +| MIO_OUTSEL_0 | 0x2a0 | +| MIO_OUTSEL_1 | 0x2a4 | +| MIO_OUTSEL_2 | 0x2a8 | +| MIO_OUTSEL_3 | 0x2ac | +| MIO_OUTSEL_4 | 0x2b0 | +| MIO_OUTSEL_5 | 0x2b4 | +| MIO_OUTSEL_6 | 0x2b8 | +| MIO_OUTSEL_7 | 0x2bc | +| MIO_OUTSEL_8 | 0x2c0 | +| MIO_OUTSEL_9 | 0x2c4 | +| MIO_OUTSEL_10 | 0x2c8 | +| MIO_OUTSEL_11 | 0x2cc | +| MIO_OUTSEL_12 | 0x2d0 | +| MIO_OUTSEL_13 | 0x2d4 | +| MIO_OUTSEL_14 | 0x2d8 | +| MIO_OUTSEL_15 | 0x2dc | +| MIO_OUTSEL_16 | 0x2e0 | +| MIO_OUTSEL_17 | 0x2e4 | +| MIO_OUTSEL_18 | 0x2e8 | +| MIO_OUTSEL_19 | 0x2ec | +| MIO_OUTSEL_20 | 0x2f0 | +| MIO_OUTSEL_21 | 0x2f4 | +| MIO_OUTSEL_22 | 0x2f8 | +| MIO_OUTSEL_23 | 0x2fc | +| MIO_OUTSEL_24 | 0x300 | +| MIO_OUTSEL_25 | 0x304 | +| MIO_OUTSEL_26 | 0x308 | +| MIO_OUTSEL_27 | 0x30c | +| MIO_OUTSEL_28 | 0x310 | +| MIO_OUTSEL_29 | 0x314 | +| MIO_OUTSEL_30 | 0x318 | +| MIO_OUTSEL_31 | 0x31c | +| MIO_OUTSEL_32 | 0x320 | +| MIO_OUTSEL_33 | 0x324 | +| MIO_OUTSEL_34 | 0x328 | +| MIO_OUTSEL_35 | 0x32c | +| MIO_OUTSEL_36 | 0x330 | +| MIO_OUTSEL_37 | 0x334 | +| MIO_OUTSEL_38 | 0x338 | +| MIO_OUTSEL_39 | 0x33c | +| MIO_OUTSEL_40 | 0x340 | +| MIO_OUTSEL_41 | 0x344 | +| MIO_OUTSEL_42 | 0x348 | +| MIO_OUTSEL_43 | 0x34c | +| MIO_OUTSEL_44 | 0x350 | +| MIO_OUTSEL_45 | 0x354 | +| MIO_OUTSEL_46 | 0x358 | ### Fields @@ -898,53 +910,53 @@ Register write enable for MIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| MIO_PAD_ATTR_REGWEN_0 | 0x344 | -| MIO_PAD_ATTR_REGWEN_1 | 0x348 | -| MIO_PAD_ATTR_REGWEN_2 | 0x34c | -| MIO_PAD_ATTR_REGWEN_3 | 0x350 | -| MIO_PAD_ATTR_REGWEN_4 | 0x354 | -| MIO_PAD_ATTR_REGWEN_5 | 0x358 | -| MIO_PAD_ATTR_REGWEN_6 | 0x35c | -| MIO_PAD_ATTR_REGWEN_7 | 0x360 | -| MIO_PAD_ATTR_REGWEN_8 | 0x364 | -| MIO_PAD_ATTR_REGWEN_9 | 0x368 | -| MIO_PAD_ATTR_REGWEN_10 | 0x36c | -| MIO_PAD_ATTR_REGWEN_11 | 0x370 | -| MIO_PAD_ATTR_REGWEN_12 | 0x374 | -| MIO_PAD_ATTR_REGWEN_13 | 0x378 | -| MIO_PAD_ATTR_REGWEN_14 | 0x37c | -| MIO_PAD_ATTR_REGWEN_15 | 0x380 | -| MIO_PAD_ATTR_REGWEN_16 | 0x384 | -| MIO_PAD_ATTR_REGWEN_17 | 0x388 | -| MIO_PAD_ATTR_REGWEN_18 | 0x38c | -| MIO_PAD_ATTR_REGWEN_19 | 0x390 | -| MIO_PAD_ATTR_REGWEN_20 | 0x394 | -| MIO_PAD_ATTR_REGWEN_21 | 0x398 | -| MIO_PAD_ATTR_REGWEN_22 | 0x39c | -| MIO_PAD_ATTR_REGWEN_23 | 0x3a0 | -| MIO_PAD_ATTR_REGWEN_24 | 0x3a4 | -| MIO_PAD_ATTR_REGWEN_25 | 0x3a8 | -| MIO_PAD_ATTR_REGWEN_26 | 0x3ac | -| MIO_PAD_ATTR_REGWEN_27 | 0x3b0 | -| MIO_PAD_ATTR_REGWEN_28 | 0x3b4 | -| MIO_PAD_ATTR_REGWEN_29 | 0x3b8 | -| MIO_PAD_ATTR_REGWEN_30 | 0x3bc | -| MIO_PAD_ATTR_REGWEN_31 | 0x3c0 | -| MIO_PAD_ATTR_REGWEN_32 | 0x3c4 | -| MIO_PAD_ATTR_REGWEN_33 | 0x3c8 | -| MIO_PAD_ATTR_REGWEN_34 | 0x3cc | -| MIO_PAD_ATTR_REGWEN_35 | 0x3d0 | -| MIO_PAD_ATTR_REGWEN_36 | 0x3d4 | -| MIO_PAD_ATTR_REGWEN_37 | 0x3d8 | -| MIO_PAD_ATTR_REGWEN_38 | 0x3dc | -| MIO_PAD_ATTR_REGWEN_39 | 0x3e0 | -| MIO_PAD_ATTR_REGWEN_40 | 0x3e4 | -| MIO_PAD_ATTR_REGWEN_41 | 0x3e8 | -| MIO_PAD_ATTR_REGWEN_42 | 0x3ec | -| MIO_PAD_ATTR_REGWEN_43 | 0x3f0 | -| MIO_PAD_ATTR_REGWEN_44 | 0x3f4 | -| MIO_PAD_ATTR_REGWEN_45 | 0x3f8 | -| MIO_PAD_ATTR_REGWEN_46 | 0x3fc | +| MIO_PAD_ATTR_REGWEN_0 | 0x35c | +| MIO_PAD_ATTR_REGWEN_1 | 0x360 | +| MIO_PAD_ATTR_REGWEN_2 | 0x364 | +| MIO_PAD_ATTR_REGWEN_3 | 0x368 | +| MIO_PAD_ATTR_REGWEN_4 | 0x36c | +| MIO_PAD_ATTR_REGWEN_5 | 0x370 | +| MIO_PAD_ATTR_REGWEN_6 | 0x374 | +| MIO_PAD_ATTR_REGWEN_7 | 0x378 | +| MIO_PAD_ATTR_REGWEN_8 | 0x37c | +| MIO_PAD_ATTR_REGWEN_9 | 0x380 | +| MIO_PAD_ATTR_REGWEN_10 | 0x384 | +| MIO_PAD_ATTR_REGWEN_11 | 0x388 | +| MIO_PAD_ATTR_REGWEN_12 | 0x38c | +| MIO_PAD_ATTR_REGWEN_13 | 0x390 | +| MIO_PAD_ATTR_REGWEN_14 | 0x394 | +| MIO_PAD_ATTR_REGWEN_15 | 0x398 | +| MIO_PAD_ATTR_REGWEN_16 | 0x39c | +| MIO_PAD_ATTR_REGWEN_17 | 0x3a0 | +| MIO_PAD_ATTR_REGWEN_18 | 0x3a4 | +| MIO_PAD_ATTR_REGWEN_19 | 0x3a8 | +| MIO_PAD_ATTR_REGWEN_20 | 0x3ac | +| MIO_PAD_ATTR_REGWEN_21 | 0x3b0 | +| MIO_PAD_ATTR_REGWEN_22 | 0x3b4 | +| MIO_PAD_ATTR_REGWEN_23 | 0x3b8 | +| MIO_PAD_ATTR_REGWEN_24 | 0x3bc | +| MIO_PAD_ATTR_REGWEN_25 | 0x3c0 | +| MIO_PAD_ATTR_REGWEN_26 | 0x3c4 | +| MIO_PAD_ATTR_REGWEN_27 | 0x3c8 | +| MIO_PAD_ATTR_REGWEN_28 | 0x3cc | +| MIO_PAD_ATTR_REGWEN_29 | 0x3d0 | +| MIO_PAD_ATTR_REGWEN_30 | 0x3d4 | +| MIO_PAD_ATTR_REGWEN_31 | 0x3d8 | +| MIO_PAD_ATTR_REGWEN_32 | 0x3dc | +| MIO_PAD_ATTR_REGWEN_33 | 0x3e0 | +| MIO_PAD_ATTR_REGWEN_34 | 0x3e4 | +| MIO_PAD_ATTR_REGWEN_35 | 0x3e8 | +| MIO_PAD_ATTR_REGWEN_36 | 0x3ec | +| MIO_PAD_ATTR_REGWEN_37 | 0x3f0 | +| MIO_PAD_ATTR_REGWEN_38 | 0x3f4 | +| MIO_PAD_ATTR_REGWEN_39 | 0x3f8 | +| MIO_PAD_ATTR_REGWEN_40 | 0x3fc | +| MIO_PAD_ATTR_REGWEN_41 | 0x400 | +| MIO_PAD_ATTR_REGWEN_42 | 0x404 | +| MIO_PAD_ATTR_REGWEN_43 | 0x408 | +| MIO_PAD_ATTR_REGWEN_44 | 0x40c | +| MIO_PAD_ATTR_REGWEN_45 | 0x410 | +| MIO_PAD_ATTR_REGWEN_46 | 0x414 | ### Fields @@ -971,53 +983,53 @@ The muxed pad that is used for TAP strap 0 has a different reset value, with `pu | Name | Offset | |:----------------|:---------| -| MIO_PAD_ATTR_0 | 0x400 | -| MIO_PAD_ATTR_1 | 0x404 | -| MIO_PAD_ATTR_2 | 0x408 | -| MIO_PAD_ATTR_3 | 0x40c | -| MIO_PAD_ATTR_4 | 0x410 | -| MIO_PAD_ATTR_5 | 0x414 | -| MIO_PAD_ATTR_6 | 0x418 | -| MIO_PAD_ATTR_7 | 0x41c | -| MIO_PAD_ATTR_8 | 0x420 | -| MIO_PAD_ATTR_9 | 0x424 | -| MIO_PAD_ATTR_10 | 0x428 | -| MIO_PAD_ATTR_11 | 0x42c | -| MIO_PAD_ATTR_12 | 0x430 | -| MIO_PAD_ATTR_13 | 0x434 | -| MIO_PAD_ATTR_14 | 0x438 | -| MIO_PAD_ATTR_15 | 0x43c | -| MIO_PAD_ATTR_16 | 0x440 | -| MIO_PAD_ATTR_17 | 0x444 | -| MIO_PAD_ATTR_18 | 0x448 | -| MIO_PAD_ATTR_19 | 0x44c | -| MIO_PAD_ATTR_20 | 0x450 | -| MIO_PAD_ATTR_21 | 0x454 | -| MIO_PAD_ATTR_22 | 0x458 | -| MIO_PAD_ATTR_23 | 0x45c | -| MIO_PAD_ATTR_24 | 0x460 | -| MIO_PAD_ATTR_25 | 0x464 | -| MIO_PAD_ATTR_26 | 0x468 | -| MIO_PAD_ATTR_27 | 0x46c | -| MIO_PAD_ATTR_28 | 0x470 | -| MIO_PAD_ATTR_29 | 0x474 | -| MIO_PAD_ATTR_30 | 0x478 | -| MIO_PAD_ATTR_31 | 0x47c | -| MIO_PAD_ATTR_32 | 0x480 | -| MIO_PAD_ATTR_33 | 0x484 | -| MIO_PAD_ATTR_34 | 0x488 | -| MIO_PAD_ATTR_35 | 0x48c | -| MIO_PAD_ATTR_36 | 0x490 | -| MIO_PAD_ATTR_37 | 0x494 | -| MIO_PAD_ATTR_38 | 0x498 | -| MIO_PAD_ATTR_39 | 0x49c | -| MIO_PAD_ATTR_40 | 0x4a0 | -| MIO_PAD_ATTR_41 | 0x4a4 | -| MIO_PAD_ATTR_42 | 0x4a8 | -| MIO_PAD_ATTR_43 | 0x4ac | -| MIO_PAD_ATTR_44 | 0x4b0 | -| MIO_PAD_ATTR_45 | 0x4b4 | -| MIO_PAD_ATTR_46 | 0x4b8 | +| MIO_PAD_ATTR_0 | 0x418 | +| MIO_PAD_ATTR_1 | 0x41c | +| MIO_PAD_ATTR_2 | 0x420 | +| MIO_PAD_ATTR_3 | 0x424 | +| MIO_PAD_ATTR_4 | 0x428 | +| MIO_PAD_ATTR_5 | 0x42c | +| MIO_PAD_ATTR_6 | 0x430 | +| MIO_PAD_ATTR_7 | 0x434 | +| MIO_PAD_ATTR_8 | 0x438 | +| MIO_PAD_ATTR_9 | 0x43c | +| MIO_PAD_ATTR_10 | 0x440 | +| MIO_PAD_ATTR_11 | 0x444 | +| MIO_PAD_ATTR_12 | 0x448 | +| MIO_PAD_ATTR_13 | 0x44c | +| MIO_PAD_ATTR_14 | 0x450 | +| MIO_PAD_ATTR_15 | 0x454 | +| MIO_PAD_ATTR_16 | 0x458 | +| MIO_PAD_ATTR_17 | 0x45c | +| MIO_PAD_ATTR_18 | 0x460 | +| MIO_PAD_ATTR_19 | 0x464 | +| MIO_PAD_ATTR_20 | 0x468 | +| MIO_PAD_ATTR_21 | 0x46c | +| MIO_PAD_ATTR_22 | 0x470 | +| MIO_PAD_ATTR_23 | 0x474 | +| MIO_PAD_ATTR_24 | 0x478 | +| MIO_PAD_ATTR_25 | 0x47c | +| MIO_PAD_ATTR_26 | 0x480 | +| MIO_PAD_ATTR_27 | 0x484 | +| MIO_PAD_ATTR_28 | 0x488 | +| MIO_PAD_ATTR_29 | 0x48c | +| MIO_PAD_ATTR_30 | 0x490 | +| MIO_PAD_ATTR_31 | 0x494 | +| MIO_PAD_ATTR_32 | 0x498 | +| MIO_PAD_ATTR_33 | 0x49c | +| MIO_PAD_ATTR_34 | 0x4a0 | +| MIO_PAD_ATTR_35 | 0x4a4 | +| MIO_PAD_ATTR_36 | 0x4a8 | +| MIO_PAD_ATTR_37 | 0x4ac | +| MIO_PAD_ATTR_38 | 0x4b0 | +| MIO_PAD_ATTR_39 | 0x4b4 | +| MIO_PAD_ATTR_40 | 0x4b8 | +| MIO_PAD_ATTR_41 | 0x4bc | +| MIO_PAD_ATTR_42 | 0x4c0 | +| MIO_PAD_ATTR_43 | 0x4c4 | +| MIO_PAD_ATTR_44 | 0x4c8 | +| MIO_PAD_ATTR_45 | 0x4cc | +| MIO_PAD_ATTR_46 | 0x4d0 | ### Fields @@ -1088,22 +1100,22 @@ Register write enable for DIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| DIO_PAD_ATTR_REGWEN_0 | 0x4bc | -| DIO_PAD_ATTR_REGWEN_1 | 0x4c0 | -| DIO_PAD_ATTR_REGWEN_2 | 0x4c4 | -| DIO_PAD_ATTR_REGWEN_3 | 0x4c8 | -| DIO_PAD_ATTR_REGWEN_4 | 0x4cc | -| DIO_PAD_ATTR_REGWEN_5 | 0x4d0 | -| DIO_PAD_ATTR_REGWEN_6 | 0x4d4 | -| DIO_PAD_ATTR_REGWEN_7 | 0x4d8 | -| DIO_PAD_ATTR_REGWEN_8 | 0x4dc | -| DIO_PAD_ATTR_REGWEN_9 | 0x4e0 | -| DIO_PAD_ATTR_REGWEN_10 | 0x4e4 | -| DIO_PAD_ATTR_REGWEN_11 | 0x4e8 | -| DIO_PAD_ATTR_REGWEN_12 | 0x4ec | -| DIO_PAD_ATTR_REGWEN_13 | 0x4f0 | -| DIO_PAD_ATTR_REGWEN_14 | 0x4f4 | -| DIO_PAD_ATTR_REGWEN_15 | 0x4f8 | +| DIO_PAD_ATTR_REGWEN_0 | 0x4d4 | +| DIO_PAD_ATTR_REGWEN_1 | 0x4d8 | +| DIO_PAD_ATTR_REGWEN_2 | 0x4dc | +| DIO_PAD_ATTR_REGWEN_3 | 0x4e0 | +| DIO_PAD_ATTR_REGWEN_4 | 0x4e4 | +| DIO_PAD_ATTR_REGWEN_5 | 0x4e8 | +| DIO_PAD_ATTR_REGWEN_6 | 0x4ec | +| DIO_PAD_ATTR_REGWEN_7 | 0x4f0 | +| DIO_PAD_ATTR_REGWEN_8 | 0x4f4 | +| DIO_PAD_ATTR_REGWEN_9 | 0x4f8 | +| DIO_PAD_ATTR_REGWEN_10 | 0x4fc | +| DIO_PAD_ATTR_REGWEN_11 | 0x500 | +| DIO_PAD_ATTR_REGWEN_12 | 0x504 | +| DIO_PAD_ATTR_REGWEN_13 | 0x508 | +| DIO_PAD_ATTR_REGWEN_14 | 0x50c | +| DIO_PAD_ATTR_REGWEN_15 | 0x510 | ### Fields @@ -1129,22 +1141,22 @@ all attributes. | Name | Offset | |:----------------|:---------| -| DIO_PAD_ATTR_0 | 0x4fc | -| DIO_PAD_ATTR_1 | 0x500 | -| DIO_PAD_ATTR_2 | 0x504 | -| DIO_PAD_ATTR_3 | 0x508 | -| DIO_PAD_ATTR_4 | 0x50c | -| DIO_PAD_ATTR_5 | 0x510 | -| DIO_PAD_ATTR_6 | 0x514 | -| DIO_PAD_ATTR_7 | 0x518 | -| DIO_PAD_ATTR_8 | 0x51c | -| DIO_PAD_ATTR_9 | 0x520 | -| DIO_PAD_ATTR_10 | 0x524 | -| DIO_PAD_ATTR_11 | 0x528 | -| DIO_PAD_ATTR_12 | 0x52c | -| DIO_PAD_ATTR_13 | 0x530 | -| DIO_PAD_ATTR_14 | 0x534 | -| DIO_PAD_ATTR_15 | 0x538 | +| DIO_PAD_ATTR_0 | 0x514 | +| DIO_PAD_ATTR_1 | 0x518 | +| DIO_PAD_ATTR_2 | 0x51c | +| DIO_PAD_ATTR_3 | 0x520 | +| DIO_PAD_ATTR_4 | 0x524 | +| DIO_PAD_ATTR_5 | 0x528 | +| DIO_PAD_ATTR_6 | 0x52c | +| DIO_PAD_ATTR_7 | 0x530 | +| DIO_PAD_ATTR_8 | 0x534 | +| DIO_PAD_ATTR_9 | 0x538 | +| DIO_PAD_ATTR_10 | 0x53c | +| DIO_PAD_ATTR_11 | 0x540 | +| DIO_PAD_ATTR_12 | 0x544 | +| DIO_PAD_ATTR_13 | 0x548 | +| DIO_PAD_ATTR_14 | 0x54c | +| DIO_PAD_ATTR_15 | 0x550 | ### Fields @@ -1208,7 +1220,7 @@ Invert input and output levels. ## MIO_PAD_SLEEP_STATUS_0 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x53c` +- Offset: `0x554` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -1255,7 +1267,7 @@ Register indicating whether the corresponding pad is in sleep mode. ## MIO_PAD_SLEEP_STATUS_1 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x540` +- Offset: `0x558` - Reset default: `0x0` - Reset mask: `0x7fff` @@ -1293,53 +1305,53 @@ Register write enable for MIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| MIO_PAD_SLEEP_REGWEN_0 | 0x544 | -| MIO_PAD_SLEEP_REGWEN_1 | 0x548 | -| MIO_PAD_SLEEP_REGWEN_2 | 0x54c | -| MIO_PAD_SLEEP_REGWEN_3 | 0x550 | -| MIO_PAD_SLEEP_REGWEN_4 | 0x554 | -| MIO_PAD_SLEEP_REGWEN_5 | 0x558 | -| MIO_PAD_SLEEP_REGWEN_6 | 0x55c | -| MIO_PAD_SLEEP_REGWEN_7 | 0x560 | -| MIO_PAD_SLEEP_REGWEN_8 | 0x564 | -| MIO_PAD_SLEEP_REGWEN_9 | 0x568 | -| MIO_PAD_SLEEP_REGWEN_10 | 0x56c | -| MIO_PAD_SLEEP_REGWEN_11 | 0x570 | -| MIO_PAD_SLEEP_REGWEN_12 | 0x574 | -| MIO_PAD_SLEEP_REGWEN_13 | 0x578 | -| MIO_PAD_SLEEP_REGWEN_14 | 0x57c | -| MIO_PAD_SLEEP_REGWEN_15 | 0x580 | -| MIO_PAD_SLEEP_REGWEN_16 | 0x584 | -| MIO_PAD_SLEEP_REGWEN_17 | 0x588 | -| MIO_PAD_SLEEP_REGWEN_18 | 0x58c | -| MIO_PAD_SLEEP_REGWEN_19 | 0x590 | -| MIO_PAD_SLEEP_REGWEN_20 | 0x594 | -| MIO_PAD_SLEEP_REGWEN_21 | 0x598 | -| MIO_PAD_SLEEP_REGWEN_22 | 0x59c | -| MIO_PAD_SLEEP_REGWEN_23 | 0x5a0 | -| MIO_PAD_SLEEP_REGWEN_24 | 0x5a4 | -| MIO_PAD_SLEEP_REGWEN_25 | 0x5a8 | -| MIO_PAD_SLEEP_REGWEN_26 | 0x5ac | -| MIO_PAD_SLEEP_REGWEN_27 | 0x5b0 | -| MIO_PAD_SLEEP_REGWEN_28 | 0x5b4 | -| MIO_PAD_SLEEP_REGWEN_29 | 0x5b8 | -| MIO_PAD_SLEEP_REGWEN_30 | 0x5bc | -| MIO_PAD_SLEEP_REGWEN_31 | 0x5c0 | -| MIO_PAD_SLEEP_REGWEN_32 | 0x5c4 | -| MIO_PAD_SLEEP_REGWEN_33 | 0x5c8 | -| MIO_PAD_SLEEP_REGWEN_34 | 0x5cc | -| MIO_PAD_SLEEP_REGWEN_35 | 0x5d0 | -| MIO_PAD_SLEEP_REGWEN_36 | 0x5d4 | -| MIO_PAD_SLEEP_REGWEN_37 | 0x5d8 | -| MIO_PAD_SLEEP_REGWEN_38 | 0x5dc | -| MIO_PAD_SLEEP_REGWEN_39 | 0x5e0 | -| MIO_PAD_SLEEP_REGWEN_40 | 0x5e4 | -| MIO_PAD_SLEEP_REGWEN_41 | 0x5e8 | -| MIO_PAD_SLEEP_REGWEN_42 | 0x5ec | -| MIO_PAD_SLEEP_REGWEN_43 | 0x5f0 | -| MIO_PAD_SLEEP_REGWEN_44 | 0x5f4 | -| MIO_PAD_SLEEP_REGWEN_45 | 0x5f8 | -| MIO_PAD_SLEEP_REGWEN_46 | 0x5fc | +| MIO_PAD_SLEEP_REGWEN_0 | 0x55c | +| MIO_PAD_SLEEP_REGWEN_1 | 0x560 | +| MIO_PAD_SLEEP_REGWEN_2 | 0x564 | +| MIO_PAD_SLEEP_REGWEN_3 | 0x568 | +| MIO_PAD_SLEEP_REGWEN_4 | 0x56c | +| MIO_PAD_SLEEP_REGWEN_5 | 0x570 | +| MIO_PAD_SLEEP_REGWEN_6 | 0x574 | +| MIO_PAD_SLEEP_REGWEN_7 | 0x578 | +| MIO_PAD_SLEEP_REGWEN_8 | 0x57c | +| MIO_PAD_SLEEP_REGWEN_9 | 0x580 | +| MIO_PAD_SLEEP_REGWEN_10 | 0x584 | +| MIO_PAD_SLEEP_REGWEN_11 | 0x588 | +| MIO_PAD_SLEEP_REGWEN_12 | 0x58c | +| MIO_PAD_SLEEP_REGWEN_13 | 0x590 | +| MIO_PAD_SLEEP_REGWEN_14 | 0x594 | +| MIO_PAD_SLEEP_REGWEN_15 | 0x598 | +| MIO_PAD_SLEEP_REGWEN_16 | 0x59c | +| MIO_PAD_SLEEP_REGWEN_17 | 0x5a0 | +| MIO_PAD_SLEEP_REGWEN_18 | 0x5a4 | +| MIO_PAD_SLEEP_REGWEN_19 | 0x5a8 | +| MIO_PAD_SLEEP_REGWEN_20 | 0x5ac | +| MIO_PAD_SLEEP_REGWEN_21 | 0x5b0 | +| MIO_PAD_SLEEP_REGWEN_22 | 0x5b4 | +| MIO_PAD_SLEEP_REGWEN_23 | 0x5b8 | +| MIO_PAD_SLEEP_REGWEN_24 | 0x5bc | +| MIO_PAD_SLEEP_REGWEN_25 | 0x5c0 | +| MIO_PAD_SLEEP_REGWEN_26 | 0x5c4 | +| MIO_PAD_SLEEP_REGWEN_27 | 0x5c8 | +| MIO_PAD_SLEEP_REGWEN_28 | 0x5cc | +| MIO_PAD_SLEEP_REGWEN_29 | 0x5d0 | +| MIO_PAD_SLEEP_REGWEN_30 | 0x5d4 | +| MIO_PAD_SLEEP_REGWEN_31 | 0x5d8 | +| MIO_PAD_SLEEP_REGWEN_32 | 0x5dc | +| MIO_PAD_SLEEP_REGWEN_33 | 0x5e0 | +| MIO_PAD_SLEEP_REGWEN_34 | 0x5e4 | +| MIO_PAD_SLEEP_REGWEN_35 | 0x5e8 | +| MIO_PAD_SLEEP_REGWEN_36 | 0x5ec | +| MIO_PAD_SLEEP_REGWEN_37 | 0x5f0 | +| MIO_PAD_SLEEP_REGWEN_38 | 0x5f4 | +| MIO_PAD_SLEEP_REGWEN_39 | 0x5f8 | +| MIO_PAD_SLEEP_REGWEN_40 | 0x5fc | +| MIO_PAD_SLEEP_REGWEN_41 | 0x600 | +| MIO_PAD_SLEEP_REGWEN_42 | 0x604 | +| MIO_PAD_SLEEP_REGWEN_43 | 0x608 | +| MIO_PAD_SLEEP_REGWEN_44 | 0x60c | +| MIO_PAD_SLEEP_REGWEN_45 | 0x610 | +| MIO_PAD_SLEEP_REGWEN_46 | 0x614 | ### Fields @@ -1363,53 +1375,53 @@ Enables the sleep mode of the corresponding muxed pad. | Name | Offset | |:--------------------|:---------| -| MIO_PAD_SLEEP_EN_0 | 0x600 | -| MIO_PAD_SLEEP_EN_1 | 0x604 | -| MIO_PAD_SLEEP_EN_2 | 0x608 | -| MIO_PAD_SLEEP_EN_3 | 0x60c | -| MIO_PAD_SLEEP_EN_4 | 0x610 | -| MIO_PAD_SLEEP_EN_5 | 0x614 | -| MIO_PAD_SLEEP_EN_6 | 0x618 | -| MIO_PAD_SLEEP_EN_7 | 0x61c | -| MIO_PAD_SLEEP_EN_8 | 0x620 | -| MIO_PAD_SLEEP_EN_9 | 0x624 | -| MIO_PAD_SLEEP_EN_10 | 0x628 | -| MIO_PAD_SLEEP_EN_11 | 0x62c | -| MIO_PAD_SLEEP_EN_12 | 0x630 | -| MIO_PAD_SLEEP_EN_13 | 0x634 | -| MIO_PAD_SLEEP_EN_14 | 0x638 | -| MIO_PAD_SLEEP_EN_15 | 0x63c | -| MIO_PAD_SLEEP_EN_16 | 0x640 | -| MIO_PAD_SLEEP_EN_17 | 0x644 | -| MIO_PAD_SLEEP_EN_18 | 0x648 | -| MIO_PAD_SLEEP_EN_19 | 0x64c | -| MIO_PAD_SLEEP_EN_20 | 0x650 | -| MIO_PAD_SLEEP_EN_21 | 0x654 | -| MIO_PAD_SLEEP_EN_22 | 0x658 | -| MIO_PAD_SLEEP_EN_23 | 0x65c | -| MIO_PAD_SLEEP_EN_24 | 0x660 | -| MIO_PAD_SLEEP_EN_25 | 0x664 | -| MIO_PAD_SLEEP_EN_26 | 0x668 | -| MIO_PAD_SLEEP_EN_27 | 0x66c | -| MIO_PAD_SLEEP_EN_28 | 0x670 | -| MIO_PAD_SLEEP_EN_29 | 0x674 | -| MIO_PAD_SLEEP_EN_30 | 0x678 | -| MIO_PAD_SLEEP_EN_31 | 0x67c | -| MIO_PAD_SLEEP_EN_32 | 0x680 | -| MIO_PAD_SLEEP_EN_33 | 0x684 | -| MIO_PAD_SLEEP_EN_34 | 0x688 | -| MIO_PAD_SLEEP_EN_35 | 0x68c | -| MIO_PAD_SLEEP_EN_36 | 0x690 | -| MIO_PAD_SLEEP_EN_37 | 0x694 | -| MIO_PAD_SLEEP_EN_38 | 0x698 | -| MIO_PAD_SLEEP_EN_39 | 0x69c | -| MIO_PAD_SLEEP_EN_40 | 0x6a0 | -| MIO_PAD_SLEEP_EN_41 | 0x6a4 | -| MIO_PAD_SLEEP_EN_42 | 0x6a8 | -| MIO_PAD_SLEEP_EN_43 | 0x6ac | -| MIO_PAD_SLEEP_EN_44 | 0x6b0 | -| MIO_PAD_SLEEP_EN_45 | 0x6b4 | -| MIO_PAD_SLEEP_EN_46 | 0x6b8 | +| MIO_PAD_SLEEP_EN_0 | 0x618 | +| MIO_PAD_SLEEP_EN_1 | 0x61c | +| MIO_PAD_SLEEP_EN_2 | 0x620 | +| MIO_PAD_SLEEP_EN_3 | 0x624 | +| MIO_PAD_SLEEP_EN_4 | 0x628 | +| MIO_PAD_SLEEP_EN_5 | 0x62c | +| MIO_PAD_SLEEP_EN_6 | 0x630 | +| MIO_PAD_SLEEP_EN_7 | 0x634 | +| MIO_PAD_SLEEP_EN_8 | 0x638 | +| MIO_PAD_SLEEP_EN_9 | 0x63c | +| MIO_PAD_SLEEP_EN_10 | 0x640 | +| MIO_PAD_SLEEP_EN_11 | 0x644 | +| MIO_PAD_SLEEP_EN_12 | 0x648 | +| MIO_PAD_SLEEP_EN_13 | 0x64c | +| MIO_PAD_SLEEP_EN_14 | 0x650 | +| MIO_PAD_SLEEP_EN_15 | 0x654 | +| MIO_PAD_SLEEP_EN_16 | 0x658 | +| MIO_PAD_SLEEP_EN_17 | 0x65c | +| MIO_PAD_SLEEP_EN_18 | 0x660 | +| MIO_PAD_SLEEP_EN_19 | 0x664 | +| MIO_PAD_SLEEP_EN_20 | 0x668 | +| MIO_PAD_SLEEP_EN_21 | 0x66c | +| MIO_PAD_SLEEP_EN_22 | 0x670 | +| MIO_PAD_SLEEP_EN_23 | 0x674 | +| MIO_PAD_SLEEP_EN_24 | 0x678 | +| MIO_PAD_SLEEP_EN_25 | 0x67c | +| MIO_PAD_SLEEP_EN_26 | 0x680 | +| MIO_PAD_SLEEP_EN_27 | 0x684 | +| MIO_PAD_SLEEP_EN_28 | 0x688 | +| MIO_PAD_SLEEP_EN_29 | 0x68c | +| MIO_PAD_SLEEP_EN_30 | 0x690 | +| MIO_PAD_SLEEP_EN_31 | 0x694 | +| MIO_PAD_SLEEP_EN_32 | 0x698 | +| MIO_PAD_SLEEP_EN_33 | 0x69c | +| MIO_PAD_SLEEP_EN_34 | 0x6a0 | +| MIO_PAD_SLEEP_EN_35 | 0x6a4 | +| MIO_PAD_SLEEP_EN_36 | 0x6a8 | +| MIO_PAD_SLEEP_EN_37 | 0x6ac | +| MIO_PAD_SLEEP_EN_38 | 0x6b0 | +| MIO_PAD_SLEEP_EN_39 | 0x6b4 | +| MIO_PAD_SLEEP_EN_40 | 0x6b8 | +| MIO_PAD_SLEEP_EN_41 | 0x6bc | +| MIO_PAD_SLEEP_EN_42 | 0x6c0 | +| MIO_PAD_SLEEP_EN_43 | 0x6c4 | +| MIO_PAD_SLEEP_EN_44 | 0x6c8 | +| MIO_PAD_SLEEP_EN_45 | 0x6cc | +| MIO_PAD_SLEEP_EN_46 | 0x6d0 | ### Fields @@ -1443,53 +1455,53 @@ Defines sleep behavior of the corresponding muxed pad. | Name | Offset | |:----------------------|:---------| -| MIO_PAD_SLEEP_MODE_0 | 0x6bc | -| MIO_PAD_SLEEP_MODE_1 | 0x6c0 | -| MIO_PAD_SLEEP_MODE_2 | 0x6c4 | -| MIO_PAD_SLEEP_MODE_3 | 0x6c8 | -| MIO_PAD_SLEEP_MODE_4 | 0x6cc | -| MIO_PAD_SLEEP_MODE_5 | 0x6d0 | -| MIO_PAD_SLEEP_MODE_6 | 0x6d4 | -| MIO_PAD_SLEEP_MODE_7 | 0x6d8 | -| MIO_PAD_SLEEP_MODE_8 | 0x6dc | -| MIO_PAD_SLEEP_MODE_9 | 0x6e0 | -| MIO_PAD_SLEEP_MODE_10 | 0x6e4 | -| MIO_PAD_SLEEP_MODE_11 | 0x6e8 | -| MIO_PAD_SLEEP_MODE_12 | 0x6ec | -| MIO_PAD_SLEEP_MODE_13 | 0x6f0 | -| MIO_PAD_SLEEP_MODE_14 | 0x6f4 | -| MIO_PAD_SLEEP_MODE_15 | 0x6f8 | -| MIO_PAD_SLEEP_MODE_16 | 0x6fc | -| MIO_PAD_SLEEP_MODE_17 | 0x700 | -| MIO_PAD_SLEEP_MODE_18 | 0x704 | -| MIO_PAD_SLEEP_MODE_19 | 0x708 | -| MIO_PAD_SLEEP_MODE_20 | 0x70c | -| MIO_PAD_SLEEP_MODE_21 | 0x710 | -| MIO_PAD_SLEEP_MODE_22 | 0x714 | -| MIO_PAD_SLEEP_MODE_23 | 0x718 | -| MIO_PAD_SLEEP_MODE_24 | 0x71c | -| MIO_PAD_SLEEP_MODE_25 | 0x720 | -| MIO_PAD_SLEEP_MODE_26 | 0x724 | -| MIO_PAD_SLEEP_MODE_27 | 0x728 | -| MIO_PAD_SLEEP_MODE_28 | 0x72c | -| MIO_PAD_SLEEP_MODE_29 | 0x730 | -| MIO_PAD_SLEEP_MODE_30 | 0x734 | -| MIO_PAD_SLEEP_MODE_31 | 0x738 | -| MIO_PAD_SLEEP_MODE_32 | 0x73c | -| MIO_PAD_SLEEP_MODE_33 | 0x740 | -| MIO_PAD_SLEEP_MODE_34 | 0x744 | -| MIO_PAD_SLEEP_MODE_35 | 0x748 | -| MIO_PAD_SLEEP_MODE_36 | 0x74c | -| MIO_PAD_SLEEP_MODE_37 | 0x750 | -| MIO_PAD_SLEEP_MODE_38 | 0x754 | -| MIO_PAD_SLEEP_MODE_39 | 0x758 | -| MIO_PAD_SLEEP_MODE_40 | 0x75c | -| MIO_PAD_SLEEP_MODE_41 | 0x760 | -| MIO_PAD_SLEEP_MODE_42 | 0x764 | -| MIO_PAD_SLEEP_MODE_43 | 0x768 | -| MIO_PAD_SLEEP_MODE_44 | 0x76c | -| MIO_PAD_SLEEP_MODE_45 | 0x770 | -| MIO_PAD_SLEEP_MODE_46 | 0x774 | +| MIO_PAD_SLEEP_MODE_0 | 0x6d4 | +| MIO_PAD_SLEEP_MODE_1 | 0x6d8 | +| MIO_PAD_SLEEP_MODE_2 | 0x6dc | +| MIO_PAD_SLEEP_MODE_3 | 0x6e0 | +| MIO_PAD_SLEEP_MODE_4 | 0x6e4 | +| MIO_PAD_SLEEP_MODE_5 | 0x6e8 | +| MIO_PAD_SLEEP_MODE_6 | 0x6ec | +| MIO_PAD_SLEEP_MODE_7 | 0x6f0 | +| MIO_PAD_SLEEP_MODE_8 | 0x6f4 | +| MIO_PAD_SLEEP_MODE_9 | 0x6f8 | +| MIO_PAD_SLEEP_MODE_10 | 0x6fc | +| MIO_PAD_SLEEP_MODE_11 | 0x700 | +| MIO_PAD_SLEEP_MODE_12 | 0x704 | +| MIO_PAD_SLEEP_MODE_13 | 0x708 | +| MIO_PAD_SLEEP_MODE_14 | 0x70c | +| MIO_PAD_SLEEP_MODE_15 | 0x710 | +| MIO_PAD_SLEEP_MODE_16 | 0x714 | +| MIO_PAD_SLEEP_MODE_17 | 0x718 | +| MIO_PAD_SLEEP_MODE_18 | 0x71c | +| MIO_PAD_SLEEP_MODE_19 | 0x720 | +| MIO_PAD_SLEEP_MODE_20 | 0x724 | +| MIO_PAD_SLEEP_MODE_21 | 0x728 | +| MIO_PAD_SLEEP_MODE_22 | 0x72c | +| MIO_PAD_SLEEP_MODE_23 | 0x730 | +| MIO_PAD_SLEEP_MODE_24 | 0x734 | +| MIO_PAD_SLEEP_MODE_25 | 0x738 | +| MIO_PAD_SLEEP_MODE_26 | 0x73c | +| MIO_PAD_SLEEP_MODE_27 | 0x740 | +| MIO_PAD_SLEEP_MODE_28 | 0x744 | +| MIO_PAD_SLEEP_MODE_29 | 0x748 | +| MIO_PAD_SLEEP_MODE_30 | 0x74c | +| MIO_PAD_SLEEP_MODE_31 | 0x750 | +| MIO_PAD_SLEEP_MODE_32 | 0x754 | +| MIO_PAD_SLEEP_MODE_33 | 0x758 | +| MIO_PAD_SLEEP_MODE_34 | 0x75c | +| MIO_PAD_SLEEP_MODE_35 | 0x760 | +| MIO_PAD_SLEEP_MODE_36 | 0x764 | +| MIO_PAD_SLEEP_MODE_37 | 0x768 | +| MIO_PAD_SLEEP_MODE_38 | 0x76c | +| MIO_PAD_SLEEP_MODE_39 | 0x770 | +| MIO_PAD_SLEEP_MODE_40 | 0x774 | +| MIO_PAD_SLEEP_MODE_41 | 0x778 | +| MIO_PAD_SLEEP_MODE_42 | 0x77c | +| MIO_PAD_SLEEP_MODE_43 | 0x780 | +| MIO_PAD_SLEEP_MODE_44 | 0x784 | +| MIO_PAD_SLEEP_MODE_45 | 0x788 | +| MIO_PAD_SLEEP_MODE_46 | 0x78c | ### Fields @@ -1516,7 +1528,7 @@ Value to drive in deep sleep. ## DIO_PAD_SLEEP_STATUS Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x778` +- Offset: `0x790` - Reset default: `0x0` - Reset mask: `0xffff` @@ -1555,22 +1567,22 @@ Register write enable for DIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| DIO_PAD_SLEEP_REGWEN_0 | 0x77c | -| DIO_PAD_SLEEP_REGWEN_1 | 0x780 | -| DIO_PAD_SLEEP_REGWEN_2 | 0x784 | -| DIO_PAD_SLEEP_REGWEN_3 | 0x788 | -| DIO_PAD_SLEEP_REGWEN_4 | 0x78c | -| DIO_PAD_SLEEP_REGWEN_5 | 0x790 | -| DIO_PAD_SLEEP_REGWEN_6 | 0x794 | -| DIO_PAD_SLEEP_REGWEN_7 | 0x798 | -| DIO_PAD_SLEEP_REGWEN_8 | 0x79c | -| DIO_PAD_SLEEP_REGWEN_9 | 0x7a0 | -| DIO_PAD_SLEEP_REGWEN_10 | 0x7a4 | -| DIO_PAD_SLEEP_REGWEN_11 | 0x7a8 | -| DIO_PAD_SLEEP_REGWEN_12 | 0x7ac | -| DIO_PAD_SLEEP_REGWEN_13 | 0x7b0 | -| DIO_PAD_SLEEP_REGWEN_14 | 0x7b4 | -| DIO_PAD_SLEEP_REGWEN_15 | 0x7b8 | +| DIO_PAD_SLEEP_REGWEN_0 | 0x794 | +| DIO_PAD_SLEEP_REGWEN_1 | 0x798 | +| DIO_PAD_SLEEP_REGWEN_2 | 0x79c | +| DIO_PAD_SLEEP_REGWEN_3 | 0x7a0 | +| DIO_PAD_SLEEP_REGWEN_4 | 0x7a4 | +| DIO_PAD_SLEEP_REGWEN_5 | 0x7a8 | +| DIO_PAD_SLEEP_REGWEN_6 | 0x7ac | +| DIO_PAD_SLEEP_REGWEN_7 | 0x7b0 | +| DIO_PAD_SLEEP_REGWEN_8 | 0x7b4 | +| DIO_PAD_SLEEP_REGWEN_9 | 0x7b8 | +| DIO_PAD_SLEEP_REGWEN_10 | 0x7bc | +| DIO_PAD_SLEEP_REGWEN_11 | 0x7c0 | +| DIO_PAD_SLEEP_REGWEN_12 | 0x7c4 | +| DIO_PAD_SLEEP_REGWEN_13 | 0x7c8 | +| DIO_PAD_SLEEP_REGWEN_14 | 0x7cc | +| DIO_PAD_SLEEP_REGWEN_15 | 0x7d0 | ### Fields @@ -1594,22 +1606,22 @@ Enables the sleep mode of the corresponding dedicated pad. | Name | Offset | |:--------------------|:---------| -| DIO_PAD_SLEEP_EN_0 | 0x7bc | -| DIO_PAD_SLEEP_EN_1 | 0x7c0 | -| DIO_PAD_SLEEP_EN_2 | 0x7c4 | -| DIO_PAD_SLEEP_EN_3 | 0x7c8 | -| DIO_PAD_SLEEP_EN_4 | 0x7cc | -| DIO_PAD_SLEEP_EN_5 | 0x7d0 | -| DIO_PAD_SLEEP_EN_6 | 0x7d4 | -| DIO_PAD_SLEEP_EN_7 | 0x7d8 | -| DIO_PAD_SLEEP_EN_8 | 0x7dc | -| DIO_PAD_SLEEP_EN_9 | 0x7e0 | -| DIO_PAD_SLEEP_EN_10 | 0x7e4 | -| DIO_PAD_SLEEP_EN_11 | 0x7e8 | -| DIO_PAD_SLEEP_EN_12 | 0x7ec | -| DIO_PAD_SLEEP_EN_13 | 0x7f0 | -| DIO_PAD_SLEEP_EN_14 | 0x7f4 | -| DIO_PAD_SLEEP_EN_15 | 0x7f8 | +| DIO_PAD_SLEEP_EN_0 | 0x7d4 | +| DIO_PAD_SLEEP_EN_1 | 0x7d8 | +| DIO_PAD_SLEEP_EN_2 | 0x7dc | +| DIO_PAD_SLEEP_EN_3 | 0x7e0 | +| DIO_PAD_SLEEP_EN_4 | 0x7e4 | +| DIO_PAD_SLEEP_EN_5 | 0x7e8 | +| DIO_PAD_SLEEP_EN_6 | 0x7ec | +| DIO_PAD_SLEEP_EN_7 | 0x7f0 | +| DIO_PAD_SLEEP_EN_8 | 0x7f4 | +| DIO_PAD_SLEEP_EN_9 | 0x7f8 | +| DIO_PAD_SLEEP_EN_10 | 0x7fc | +| DIO_PAD_SLEEP_EN_11 | 0x800 | +| DIO_PAD_SLEEP_EN_12 | 0x804 | +| DIO_PAD_SLEEP_EN_13 | 0x808 | +| DIO_PAD_SLEEP_EN_14 | 0x80c | +| DIO_PAD_SLEEP_EN_15 | 0x810 | ### Fields @@ -1643,22 +1655,22 @@ Defines sleep behavior of the corresponding dedicated pad. | Name | Offset | |:----------------------|:---------| -| DIO_PAD_SLEEP_MODE_0 | 0x7fc | -| DIO_PAD_SLEEP_MODE_1 | 0x800 | -| DIO_PAD_SLEEP_MODE_2 | 0x804 | -| DIO_PAD_SLEEP_MODE_3 | 0x808 | -| DIO_PAD_SLEEP_MODE_4 | 0x80c | -| DIO_PAD_SLEEP_MODE_5 | 0x810 | -| DIO_PAD_SLEEP_MODE_6 | 0x814 | -| DIO_PAD_SLEEP_MODE_7 | 0x818 | -| DIO_PAD_SLEEP_MODE_8 | 0x81c | -| DIO_PAD_SLEEP_MODE_9 | 0x820 | -| DIO_PAD_SLEEP_MODE_10 | 0x824 | -| DIO_PAD_SLEEP_MODE_11 | 0x828 | -| DIO_PAD_SLEEP_MODE_12 | 0x82c | -| DIO_PAD_SLEEP_MODE_13 | 0x830 | -| DIO_PAD_SLEEP_MODE_14 | 0x834 | -| DIO_PAD_SLEEP_MODE_15 | 0x838 | +| DIO_PAD_SLEEP_MODE_0 | 0x814 | +| DIO_PAD_SLEEP_MODE_1 | 0x818 | +| DIO_PAD_SLEEP_MODE_2 | 0x81c | +| DIO_PAD_SLEEP_MODE_3 | 0x820 | +| DIO_PAD_SLEEP_MODE_4 | 0x824 | +| DIO_PAD_SLEEP_MODE_5 | 0x828 | +| DIO_PAD_SLEEP_MODE_6 | 0x82c | +| DIO_PAD_SLEEP_MODE_7 | 0x830 | +| DIO_PAD_SLEEP_MODE_8 | 0x834 | +| DIO_PAD_SLEEP_MODE_9 | 0x838 | +| DIO_PAD_SLEEP_MODE_10 | 0x83c | +| DIO_PAD_SLEEP_MODE_11 | 0x840 | +| DIO_PAD_SLEEP_MODE_12 | 0x844 | +| DIO_PAD_SLEEP_MODE_13 | 0x848 | +| DIO_PAD_SLEEP_MODE_14 | 0x84c | +| DIO_PAD_SLEEP_MODE_15 | 0x850 | ### Fields @@ -1692,14 +1704,14 @@ Register write enable for wakeup detectors. | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_REGWEN_0 | 0x83c | -| WKUP_DETECTOR_REGWEN_1 | 0x840 | -| WKUP_DETECTOR_REGWEN_2 | 0x844 | -| WKUP_DETECTOR_REGWEN_3 | 0x848 | -| WKUP_DETECTOR_REGWEN_4 | 0x84c | -| WKUP_DETECTOR_REGWEN_5 | 0x850 | -| WKUP_DETECTOR_REGWEN_6 | 0x854 | -| WKUP_DETECTOR_REGWEN_7 | 0x858 | +| WKUP_DETECTOR_REGWEN_0 | 0x854 | +| WKUP_DETECTOR_REGWEN_1 | 0x858 | +| WKUP_DETECTOR_REGWEN_2 | 0x85c | +| WKUP_DETECTOR_REGWEN_3 | 0x860 | +| WKUP_DETECTOR_REGWEN_4 | 0x864 | +| WKUP_DETECTOR_REGWEN_5 | 0x868 | +| WKUP_DETECTOR_REGWEN_6 | 0x86c | +| WKUP_DETECTOR_REGWEN_7 | 0x870 | ### Fields @@ -1726,14 +1738,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-------------------|:---------| -| WKUP_DETECTOR_EN_0 | 0x85c | -| WKUP_DETECTOR_EN_1 | 0x860 | -| WKUP_DETECTOR_EN_2 | 0x864 | -| WKUP_DETECTOR_EN_3 | 0x868 | -| WKUP_DETECTOR_EN_4 | 0x86c | -| WKUP_DETECTOR_EN_5 | 0x870 | -| WKUP_DETECTOR_EN_6 | 0x874 | -| WKUP_DETECTOR_EN_7 | 0x878 | +| WKUP_DETECTOR_EN_0 | 0x874 | +| WKUP_DETECTOR_EN_1 | 0x878 | +| WKUP_DETECTOR_EN_2 | 0x87c | +| WKUP_DETECTOR_EN_3 | 0x880 | +| WKUP_DETECTOR_EN_4 | 0x884 | +| WKUP_DETECTOR_EN_5 | 0x888 | +| WKUP_DETECTOR_EN_6 | 0x88c | +| WKUP_DETECTOR_EN_7 | 0x890 | ### Fields @@ -1763,14 +1775,14 @@ The reason for that is that the pulse width counter is NOT cleared upon a mode c | Name | Offset | |:----------------|:---------| -| WKUP_DETECTOR_0 | 0x87c | -| WKUP_DETECTOR_1 | 0x880 | -| WKUP_DETECTOR_2 | 0x884 | -| WKUP_DETECTOR_3 | 0x888 | -| WKUP_DETECTOR_4 | 0x88c | -| WKUP_DETECTOR_5 | 0x890 | -| WKUP_DETECTOR_6 | 0x894 | -| WKUP_DETECTOR_7 | 0x898 | +| WKUP_DETECTOR_0 | 0x894 | +| WKUP_DETECTOR_1 | 0x898 | +| WKUP_DETECTOR_2 | 0x89c | +| WKUP_DETECTOR_3 | 0x8a0 | +| WKUP_DETECTOR_4 | 0x8a4 | +| WKUP_DETECTOR_5 | 0x8a8 | +| WKUP_DETECTOR_6 | 0x8ac | +| WKUP_DETECTOR_7 | 0x8b0 | ### Fields @@ -1821,14 +1833,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_CNT_TH_0 | 0x89c | -| WKUP_DETECTOR_CNT_TH_1 | 0x8a0 | -| WKUP_DETECTOR_CNT_TH_2 | 0x8a4 | -| WKUP_DETECTOR_CNT_TH_3 | 0x8a8 | -| WKUP_DETECTOR_CNT_TH_4 | 0x8ac | -| WKUP_DETECTOR_CNT_TH_5 | 0x8b0 | -| WKUP_DETECTOR_CNT_TH_6 | 0x8b4 | -| WKUP_DETECTOR_CNT_TH_7 | 0x8b8 | +| WKUP_DETECTOR_CNT_TH_0 | 0x8b4 | +| WKUP_DETECTOR_CNT_TH_1 | 0x8b8 | +| WKUP_DETECTOR_CNT_TH_2 | 0x8bc | +| WKUP_DETECTOR_CNT_TH_3 | 0x8c0 | +| WKUP_DETECTOR_CNT_TH_4 | 0x8c4 | +| WKUP_DETECTOR_CNT_TH_5 | 0x8c8 | +| WKUP_DETECTOR_CNT_TH_6 | 0x8cc | +| WKUP_DETECTOR_CNT_TH_7 | 0x8d0 | ### Fields @@ -1853,14 +1865,14 @@ This register is NOT synced to the AON domain since the muxing mechanism is impl | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_PADSEL_0 | 0x8bc | -| WKUP_DETECTOR_PADSEL_1 | 0x8c0 | -| WKUP_DETECTOR_PADSEL_2 | 0x8c4 | -| WKUP_DETECTOR_PADSEL_3 | 0x8c8 | -| WKUP_DETECTOR_PADSEL_4 | 0x8cc | -| WKUP_DETECTOR_PADSEL_5 | 0x8d0 | -| WKUP_DETECTOR_PADSEL_6 | 0x8d4 | -| WKUP_DETECTOR_PADSEL_7 | 0x8d8 | +| WKUP_DETECTOR_PADSEL_0 | 0x8d4 | +| WKUP_DETECTOR_PADSEL_1 | 0x8d8 | +| WKUP_DETECTOR_PADSEL_2 | 0x8dc | +| WKUP_DETECTOR_PADSEL_3 | 0x8e0 | +| WKUP_DETECTOR_PADSEL_4 | 0x8e4 | +| WKUP_DETECTOR_PADSEL_5 | 0x8e8 | +| WKUP_DETECTOR_PADSEL_6 | 0x8ec | +| WKUP_DETECTOR_PADSEL_7 | 0x8f0 | ### Fields @@ -1885,7 +1897,7 @@ Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed. -- Offset: `0x8dc` +- Offset: `0x8f4` - Reset default: `0x0` - Reset mask: `0xff` diff --git a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv index e180640b59916..c1757c54201c0 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv @@ -7,8 +7,8 @@ package pinmux_reg_pkg; // Param list - parameter int NMioPeriphIn = 57; - parameter int NMioPeriphOut = 65; + parameter int NMioPeriphIn = 60; + parameter int NMioPeriphOut = 66; parameter int NMioPads = 47; parameter int NDioPads = 16; parameter int NWkupDetect = 8; @@ -19,7 +19,7 @@ package pinmux_reg_pkg; parameter int BlockAw = 12; // Number of registers for every interface - parameter int NumRegs = 568; + parameter int NumRegs = 574; // Alert indices typedef enum int { @@ -264,8 +264,8 @@ package pinmux_reg_pkg; // Register -> HW type typedef struct packed { - pinmux_reg2hw_alert_test_reg_t alert_test; // [2604:2603] - pinmux_reg2hw_mio_periph_insel_mreg_t [56:0] mio_periph_insel; // [2602:2261] + pinmux_reg2hw_alert_test_reg_t alert_test; // [2622:2621] + pinmux_reg2hw_mio_periph_insel_mreg_t [59:0] mio_periph_insel; // [2620:2261] pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [2260:1932] pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1931:804] pinmux_reg2hw_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [803:420] @@ -350,516 +350,522 @@ package pinmux_reg_pkg; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h dc; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET = 12'h e0; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET = 12'h e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 100; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 104; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 108; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 10c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 110; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 114; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 118; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 11c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 120; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 124; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 128; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 12c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 130; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 134; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 138; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 13c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 140; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 144; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 148; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 14c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 150; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 154; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 158; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 15c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 160; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 164; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 168; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 16c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 170; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 174; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 178; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 17c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 180; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 184; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 188; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 18c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 190; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 194; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 198; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 19c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 1f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 1fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 200; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 204; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 208; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 20c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 210; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 214; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 218; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 21c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 220; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 224; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 228; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 22c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 230; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 234; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 238; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 23c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 240; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 304; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 308; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 30c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 310; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 314; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 318; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 31c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 320; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 324; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 328; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 32c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 330; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 334; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 338; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 33c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 340; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 344; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 348; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 34c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 350; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 354; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 358; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 35c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 360; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 364; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 368; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 36c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 370; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 374; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 378; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 37c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 380; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 384; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 388; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 38c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 390; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 394; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 398; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 39c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 400; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 404; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 408; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 40c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 410; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 414; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 418; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 41c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 420; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 424; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 428; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 42c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 430; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 434; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 438; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 43c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 440; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 444; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 448; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 44c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 450; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 454; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 458; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 45c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 460; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 464; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 468; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 46c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 470; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 474; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 478; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 47c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 480; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 484; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 488; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 48c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 490; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 494; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 498; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 49c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 4fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 500; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 504; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 508; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 50c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 510; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 514; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 518; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 51c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 520; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 524; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 528; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 52c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 530; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 534; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 538; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 53c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 540; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 544; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 548; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 54c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 550; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 554; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 558; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 55c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 560; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 564; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 568; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 56c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 570; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 574; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 578; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 57c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 580; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 584; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 588; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 58c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 590; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 594; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 598; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 59c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 5d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 5d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 5dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 5e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 5e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 5e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 5ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 5f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 5f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 5f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 5fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 600; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 604; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 608; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 60c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 610; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 614; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 618; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 61c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 620; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 624; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 628; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 62c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 630; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 634; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 638; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 63c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 640; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 644; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 648; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 64c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 650; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 654; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 658; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 65c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 660; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 664; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 668; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 66c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 670; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 674; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 678; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 67c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 680; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 684; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 688; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 68c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 690; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 694; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 698; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 69c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 6e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 6ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 6f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 6f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 6f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 6fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 700; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 704; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 708; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 70c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 710; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 714; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 718; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 71c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 720; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 724; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 728; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 72c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 730; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 734; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 738; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 73c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 740; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 744; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 748; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 74c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 750; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 754; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 758; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 75c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 760; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 764; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 768; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 76c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 770; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 774; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 778; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 77c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 780; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 784; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 788; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 78c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 790; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 794; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 798; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 79c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7a0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7a4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7a8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7ac; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7b0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7b4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7b8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7bc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7c0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7c4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7c8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 7e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 7ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 7f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 7f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 7f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 7fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 800; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 804; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 808; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 80c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 810; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 814; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 818; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 81c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 820; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 824; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 828; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 82c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 830; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 834; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 838; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 83c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 840; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 844; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 848; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 84c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 850; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 854; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 858; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 85c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 860; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 864; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 868; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 86c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 870; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 874; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 878; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 87c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 880; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 884; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 888; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 88c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 890; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 894; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 898; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 89c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8a0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8a4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8a8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8ac; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8b0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8b4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8b8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 8bc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 8c0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 8c4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 8c8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 8cc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 8d0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 8d4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 8d8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 8dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET = 12'h e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET = 12'h ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_59_OFFSET = 12'h f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h 100; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h 104; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h 108; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 10c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 110; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 114; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 118; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 11c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 120; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 124; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 128; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 12c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 130; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 134; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 138; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 13c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 140; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 144; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 148; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 14c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 150; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 154; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 158; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 15c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 160; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 164; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 168; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 16c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 170; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 174; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 178; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 17c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 180; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 184; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 188; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 18c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 190; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 194; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 198; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 19c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_57_OFFSET = 12'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_58_OFFSET = 12'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_59_OFFSET = 12'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 200; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 204; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 208; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 20c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 210; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 214; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 218; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 21c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 220; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 224; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 228; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 22c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 230; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 234; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 238; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 23c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 240; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 244; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 304; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 308; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 30c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 310; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 314; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 318; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 31c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 320; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 324; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 408; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 40c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 410; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 414; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 418; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 41c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 420; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 424; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 428; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 42c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 430; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 434; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 438; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 43c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 440; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 444; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 448; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 44c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 450; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 454; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 458; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 45c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 460; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 464; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 468; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 46c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 470; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 474; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 500; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 504; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 538; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 53c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 548; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 54c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 550; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 554; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 558; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 55c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 560; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 564; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 568; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 56c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 570; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 574; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 578; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 57c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 580; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 584; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 588; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 58c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 590; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 594; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 598; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 59c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 600; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 604; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 608; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 60c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 610; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 614; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 618; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 61c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 620; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 624; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 628; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 62c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 630; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 634; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 638; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 63c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 640; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 644; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 648; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 64c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 650; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 654; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 658; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 65c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 660; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 664; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 668; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 66c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 670; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 674; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 678; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 67c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 680; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 684; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 688; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 68c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 690; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 694; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 698; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 69c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 700; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 704; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 708; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 70c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 710; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 714; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 718; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 71c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 720; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 724; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 728; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 72c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 730; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 734; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 738; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 73c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 740; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 744; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 748; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 74c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 750; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 754; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 758; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 75c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 760; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 764; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 768; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 76c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 770; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 774; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 778; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 77c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 780; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 784; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 788; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 78c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 790; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 794; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 798; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 79c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 800; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 804; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 808; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 80c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 810; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 814; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 818; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 81c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 820; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 824; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 828; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 82c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 830; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 834; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 838; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 83c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 840; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 844; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 848; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 84c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 850; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 854; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 858; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 85c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 860; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 864; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 868; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 86c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 870; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 874; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 878; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 87c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 880; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 884; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 888; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 88c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 890; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 894; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 898; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 89c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 8a0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 8a4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 8a8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 8ac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 8b0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 8b4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8b8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8bc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8c0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8c4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8c8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 8d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 8d8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 8dc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 8e0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 8e4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 8e8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 8ec; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 8f0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 8f4; // Reset values for hwext registers and their fields parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; @@ -1618,6 +1624,9 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_REGWEN_54, PINMUX_MIO_PERIPH_INSEL_REGWEN_55, PINMUX_MIO_PERIPH_INSEL_REGWEN_56, + PINMUX_MIO_PERIPH_INSEL_REGWEN_57, + PINMUX_MIO_PERIPH_INSEL_REGWEN_58, + PINMUX_MIO_PERIPH_INSEL_REGWEN_59, PINMUX_MIO_PERIPH_INSEL_0, PINMUX_MIO_PERIPH_INSEL_1, PINMUX_MIO_PERIPH_INSEL_2, @@ -1675,6 +1684,9 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_54, PINMUX_MIO_PERIPH_INSEL_55, PINMUX_MIO_PERIPH_INSEL_56, + PINMUX_MIO_PERIPH_INSEL_57, + PINMUX_MIO_PERIPH_INSEL_58, + PINMUX_MIO_PERIPH_INSEL_59, PINMUX_MIO_OUTSEL_REGWEN_0, PINMUX_MIO_OUTSEL_REGWEN_1, PINMUX_MIO_OUTSEL_REGWEN_2, @@ -2131,7 +2143,7 @@ package pinmux_reg_pkg; } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [568] = '{ + parameter logic [3:0] PINMUX_PERMIT [574] = '{ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 @@ -2190,516 +2202,522 @@ package pinmux_reg_pkg; 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_REGWEN_54 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_REGWEN_55 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_REGWEN_56 - 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_0 - 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_1 - 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_2 - 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_3 - 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_4 - 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_5 - 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_6 - 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_7 - 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_8 - 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_9 - 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_10 - 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_11 - 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_12 - 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_13 - 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_14 - 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_15 - 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_16 - 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_17 - 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_18 - 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_19 - 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_20 - 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_21 - 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_22 - 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_23 - 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_24 - 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_25 - 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_26 - 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_27 - 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_28 - 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_29 - 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_30 - 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_31 - 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_32 - 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_33 - 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_34 - 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_35 - 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_36 - 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_37 - 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_38 - 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_39 - 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_40 - 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_41 - 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_42 - 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_43 - 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_44 - 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_45 - 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_46 - 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_47 - 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_48 - 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_49 - 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_50 - 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_51 - 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_52 - 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_53 - 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_54 - 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_55 - 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_56 - 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_0 - 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_1 - 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_2 - 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_3 - 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_4 - 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_5 - 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_6 - 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_7 - 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_8 - 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_9 - 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_10 - 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_11 - 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_12 - 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_13 - 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_14 - 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_15 - 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_16 - 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_17 - 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_18 - 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_19 - 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_20 - 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_21 - 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_22 - 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_23 - 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_24 - 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_25 - 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_26 - 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_27 - 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_28 - 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_29 - 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_30 - 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_31 - 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_32 - 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_33 - 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_34 - 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_35 - 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_36 - 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_37 - 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_38 - 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_39 - 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_40 - 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_41 - 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_42 - 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_43 - 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_44 - 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_45 - 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_46 - 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_0 - 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_1 - 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_2 - 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_3 - 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_4 - 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_5 - 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_6 - 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_7 - 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_8 - 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_9 - 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_10 - 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_11 - 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_12 - 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_13 - 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_14 - 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_15 - 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_16 - 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_17 - 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_18 - 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_19 - 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_20 - 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_21 - 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_22 - 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_23 - 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_24 - 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_25 - 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_26 - 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_27 - 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_28 - 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_29 - 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_30 - 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_32 - 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_33 - 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_34 - 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_35 - 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_36 - 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_37 - 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_38 - 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_39 - 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_40 - 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_41 - 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_42 - 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_43 - 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_44 - 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_45 - 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_46 - 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_15 - 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_16 - 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_17 - 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_18 - 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_19 - 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_20 - 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_21 - 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_22 - 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_23 - 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_24 - 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_25 - 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_26 - 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_27 - 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_28 - 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_29 - 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_30 - 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_31 - 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_32 - 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_33 - 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_34 - 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_35 - 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_36 - 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_37 - 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_38 - 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_39 - 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_40 - 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_41 - 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_42 - 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_43 - 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_44 - 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_45 - 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_46 - 4'b 0111, // index[256] PINMUX_MIO_PAD_ATTR_0 - 4'b 0111, // index[257] PINMUX_MIO_PAD_ATTR_1 - 4'b 0111, // index[258] PINMUX_MIO_PAD_ATTR_2 - 4'b 0111, // index[259] PINMUX_MIO_PAD_ATTR_3 - 4'b 0111, // index[260] PINMUX_MIO_PAD_ATTR_4 - 4'b 0111, // index[261] PINMUX_MIO_PAD_ATTR_5 - 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_6 - 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_7 - 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_8 - 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_9 - 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_10 - 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_11 - 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_12 - 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_13 - 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_14 - 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_15 - 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_16 - 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_17 - 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_18 - 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_19 - 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_20 - 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_21 - 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_22 - 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_23 - 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_24 - 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_25 - 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_26 - 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_27 - 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_28 - 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_29 - 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_30 - 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_31 - 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_32 - 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_33 - 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_34 - 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_35 - 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_36 - 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_37 - 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_38 - 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_39 - 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_40 - 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_41 - 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_42 - 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_43 - 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_44 - 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_45 - 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_46 - 4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_15 - 4'b 0111, // index[319] PINMUX_DIO_PAD_ATTR_0 - 4'b 0111, // index[320] PINMUX_DIO_PAD_ATTR_1 - 4'b 0111, // index[321] PINMUX_DIO_PAD_ATTR_2 - 4'b 0111, // index[322] PINMUX_DIO_PAD_ATTR_3 - 4'b 0111, // index[323] PINMUX_DIO_PAD_ATTR_4 - 4'b 0111, // index[324] PINMUX_DIO_PAD_ATTR_5 - 4'b 0111, // index[325] PINMUX_DIO_PAD_ATTR_6 - 4'b 0111, // index[326] PINMUX_DIO_PAD_ATTR_7 - 4'b 0111, // index[327] PINMUX_DIO_PAD_ATTR_8 - 4'b 0111, // index[328] PINMUX_DIO_PAD_ATTR_9 - 4'b 0111, // index[329] PINMUX_DIO_PAD_ATTR_10 - 4'b 0111, // index[330] PINMUX_DIO_PAD_ATTR_11 - 4'b 0111, // index[331] PINMUX_DIO_PAD_ATTR_12 - 4'b 0111, // index[332] PINMUX_DIO_PAD_ATTR_13 - 4'b 0111, // index[333] PINMUX_DIO_PAD_ATTR_14 - 4'b 0111, // index[334] PINMUX_DIO_PAD_ATTR_15 - 4'b 1111, // index[335] PINMUX_MIO_PAD_SLEEP_STATUS_0 - 4'b 0011, // index[336] PINMUX_MIO_PAD_SLEEP_STATUS_1 - 4'b 0001, // index[337] PINMUX_MIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[338] PINMUX_MIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[339] PINMUX_MIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[340] PINMUX_MIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_16 - 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_17 - 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_18 - 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_19 - 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_20 - 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_21 - 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_22 - 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_23 - 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_24 - 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_25 - 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_26 - 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_27 - 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_28 - 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_29 - 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_30 - 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_31 - 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_32 - 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_33 - 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_34 - 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_35 - 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_36 - 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_37 - 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_38 - 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_39 - 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_40 - 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_41 - 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_42 - 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_43 - 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_44 - 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_45 - 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_46 - 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_16 - 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_17 - 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_18 - 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_19 - 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_20 - 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_21 - 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_22 - 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_23 - 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_24 - 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_25 - 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_26 - 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_27 - 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_28 - 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_29 - 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_30 - 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_31 - 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_32 - 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_33 - 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_34 - 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_35 - 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_36 - 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_37 - 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_38 - 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_39 - 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_40 - 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_41 - 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_42 - 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_43 - 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_44 - 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_45 - 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_46 - 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_16 - 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_17 - 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_18 - 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_19 - 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_20 - 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_21 - 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_22 - 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_23 - 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_24 - 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_25 - 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_26 - 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_27 - 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_28 - 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_29 - 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_30 - 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_31 - 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_32 - 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_33 - 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_34 - 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_35 - 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_36 - 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_37 - 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_38 - 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_39 - 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_40 - 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_41 - 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_42 - 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_43 - 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_44 - 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_45 - 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_46 - 4'b 0011, // index[478] PINMUX_DIO_PAD_SLEEP_STATUS - 4'b 0001, // index[479] PINMUX_DIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[480] PINMUX_DIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[481] PINMUX_DIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[482] PINMUX_DIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[483] PINMUX_DIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[484] PINMUX_DIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[527] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[528] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[529] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[530] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[531] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[532] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[533] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[534] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[535] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[536] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[537] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[538] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[539] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[540] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[541] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[542] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[543] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[567] PINMUX_WKUP_CAUSE + 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_REGWEN_57 + 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_REGWEN_58 + 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_REGWEN_59 + 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_4 + 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_5 + 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_6 + 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_7 + 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_8 + 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_9 + 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_10 + 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_11 + 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_12 + 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_13 + 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_14 + 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_15 + 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_16 + 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_17 + 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_18 + 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_19 + 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_20 + 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_21 + 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_22 + 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_23 + 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_24 + 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_25 + 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_26 + 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_27 + 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_28 + 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_29 + 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_30 + 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_31 + 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_32 + 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_33 + 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_34 + 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_35 + 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_36 + 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_37 + 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_38 + 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_39 + 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_40 + 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_41 + 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_42 + 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_43 + 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_44 + 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_45 + 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_46 + 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_47 + 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_48 + 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_49 + 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_50 + 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_51 + 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_52 + 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_53 + 4'b 0001, // index[115] PINMUX_MIO_PERIPH_INSEL_54 + 4'b 0001, // index[116] PINMUX_MIO_PERIPH_INSEL_55 + 4'b 0001, // index[117] PINMUX_MIO_PERIPH_INSEL_56 + 4'b 0001, // index[118] PINMUX_MIO_PERIPH_INSEL_57 + 4'b 0001, // index[119] PINMUX_MIO_PERIPH_INSEL_58 + 4'b 0001, // index[120] PINMUX_MIO_PERIPH_INSEL_59 + 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_12 + 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_13 + 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_14 + 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_15 + 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_16 + 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_17 + 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_18 + 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_19 + 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_20 + 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_21 + 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_22 + 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_23 + 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_24 + 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_25 + 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_26 + 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_27 + 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_28 + 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_29 + 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_30 + 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_31 + 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_32 + 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_33 + 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_34 + 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_35 + 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_36 + 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_37 + 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_38 + 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_39 + 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_40 + 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_REGWEN_41 + 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_REGWEN_42 + 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_REGWEN_43 + 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_REGWEN_44 + 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_REGWEN_45 + 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_REGWEN_46 + 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_12 + 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_13 + 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_14 + 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_15 + 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_16 + 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_17 + 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_18 + 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_19 + 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_20 + 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_21 + 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_22 + 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_23 + 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_24 + 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_25 + 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_26 + 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_27 + 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_28 + 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_29 + 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_30 + 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_31 + 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_32 + 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_33 + 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_34 + 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_35 + 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_36 + 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_37 + 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_38 + 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_39 + 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_40 + 4'b 0001, // index[209] PINMUX_MIO_OUTSEL_41 + 4'b 0001, // index[210] PINMUX_MIO_OUTSEL_42 + 4'b 0001, // index[211] PINMUX_MIO_OUTSEL_43 + 4'b 0001, // index[212] PINMUX_MIO_OUTSEL_44 + 4'b 0001, // index[213] PINMUX_MIO_OUTSEL_45 + 4'b 0001, // index[214] PINMUX_MIO_OUTSEL_46 + 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[256] PINMUX_MIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[257] PINMUX_MIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[258] PINMUX_MIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[259] PINMUX_MIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[260] PINMUX_MIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[261] PINMUX_MIO_PAD_ATTR_REGWEN_46 + 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[265] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[266] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[267] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[268] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[269] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[270] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[271] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[272] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[273] PINMUX_MIO_PAD_ATTR_11 + 4'b 0111, // index[274] PINMUX_MIO_PAD_ATTR_12 + 4'b 0111, // index[275] PINMUX_MIO_PAD_ATTR_13 + 4'b 0111, // index[276] PINMUX_MIO_PAD_ATTR_14 + 4'b 0111, // index[277] PINMUX_MIO_PAD_ATTR_15 + 4'b 0111, // index[278] PINMUX_MIO_PAD_ATTR_16 + 4'b 0111, // index[279] PINMUX_MIO_PAD_ATTR_17 + 4'b 0111, // index[280] PINMUX_MIO_PAD_ATTR_18 + 4'b 0111, // index[281] PINMUX_MIO_PAD_ATTR_19 + 4'b 0111, // index[282] PINMUX_MIO_PAD_ATTR_20 + 4'b 0111, // index[283] PINMUX_MIO_PAD_ATTR_21 + 4'b 0111, // index[284] PINMUX_MIO_PAD_ATTR_22 + 4'b 0111, // index[285] PINMUX_MIO_PAD_ATTR_23 + 4'b 0111, // index[286] PINMUX_MIO_PAD_ATTR_24 + 4'b 0111, // index[287] PINMUX_MIO_PAD_ATTR_25 + 4'b 0111, // index[288] PINMUX_MIO_PAD_ATTR_26 + 4'b 0111, // index[289] PINMUX_MIO_PAD_ATTR_27 + 4'b 0111, // index[290] PINMUX_MIO_PAD_ATTR_28 + 4'b 0111, // index[291] PINMUX_MIO_PAD_ATTR_29 + 4'b 0111, // index[292] PINMUX_MIO_PAD_ATTR_30 + 4'b 0111, // index[293] PINMUX_MIO_PAD_ATTR_31 + 4'b 0111, // index[294] PINMUX_MIO_PAD_ATTR_32 + 4'b 0111, // index[295] PINMUX_MIO_PAD_ATTR_33 + 4'b 0111, // index[296] PINMUX_MIO_PAD_ATTR_34 + 4'b 0111, // index[297] PINMUX_MIO_PAD_ATTR_35 + 4'b 0111, // index[298] PINMUX_MIO_PAD_ATTR_36 + 4'b 0111, // index[299] PINMUX_MIO_PAD_ATTR_37 + 4'b 0111, // index[300] PINMUX_MIO_PAD_ATTR_38 + 4'b 0111, // index[301] PINMUX_MIO_PAD_ATTR_39 + 4'b 0111, // index[302] PINMUX_MIO_PAD_ATTR_40 + 4'b 0111, // index[303] PINMUX_MIO_PAD_ATTR_41 + 4'b 0111, // index[304] PINMUX_MIO_PAD_ATTR_42 + 4'b 0111, // index[305] PINMUX_MIO_PAD_ATTR_43 + 4'b 0111, // index[306] PINMUX_MIO_PAD_ATTR_44 + 4'b 0111, // index[307] PINMUX_MIO_PAD_ATTR_45 + 4'b 0111, // index[308] PINMUX_MIO_PAD_ATTR_46 + 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[323] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[324] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0111, // index[325] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[326] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[327] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[328] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[329] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[330] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[331] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[332] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[333] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[334] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[335] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[336] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[337] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[338] PINMUX_DIO_PAD_ATTR_13 + 4'b 0111, // index[339] PINMUX_DIO_PAD_ATTR_14 + 4'b 0111, // index[340] PINMUX_DIO_PAD_ATTR_15 + 4'b 1111, // index[341] PINMUX_MIO_PAD_SLEEP_STATUS_0 + 4'b 0011, // index[342] PINMUX_MIO_PAD_SLEEP_STATUS_1 + 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_MODE_46 + 4'b 0011, // index[484] PINMUX_DIO_PAD_SLEEP_STATUS + 4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[531] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[532] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[533] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[534] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[535] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[536] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[537] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[538] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[539] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[540] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[541] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[542] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[543] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[567] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[568] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[569] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[570] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[571] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[572] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[573] PINMUX_WKUP_CAUSE }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv index c55fd381d5485..6f0634c6474b1 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux_reg_top.sv @@ -54,9 +54,9 @@ module pinmux_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [567:0] reg_we_check; + logic [573:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(568) + .OneHotWidth(574) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -296,6 +296,15 @@ module pinmux_reg_top ( logic mio_periph_insel_regwen_56_we; logic mio_periph_insel_regwen_56_qs; logic mio_periph_insel_regwen_56_wd; + logic mio_periph_insel_regwen_57_we; + logic mio_periph_insel_regwen_57_qs; + logic mio_periph_insel_regwen_57_wd; + logic mio_periph_insel_regwen_58_we; + logic mio_periph_insel_regwen_58_qs; + logic mio_periph_insel_regwen_58_wd; + logic mio_periph_insel_regwen_59_we; + logic mio_periph_insel_regwen_59_qs; + logic mio_periph_insel_regwen_59_wd; logic mio_periph_insel_0_we; logic [5:0] mio_periph_insel_0_qs; logic [5:0] mio_periph_insel_0_wd; @@ -467,6 +476,15 @@ module pinmux_reg_top ( logic mio_periph_insel_56_we; logic [5:0] mio_periph_insel_56_qs; logic [5:0] mio_periph_insel_56_wd; + logic mio_periph_insel_57_we; + logic [5:0] mio_periph_insel_57_qs; + logic [5:0] mio_periph_insel_57_wd; + logic mio_periph_insel_58_we; + logic [5:0] mio_periph_insel_58_qs; + logic [5:0] mio_periph_insel_58_wd; + logic mio_periph_insel_59_we; + logic [5:0] mio_periph_insel_59_qs; + logic [5:0] mio_periph_insel_59_wd; logic mio_outsel_regwen_0_we; logic mio_outsel_regwen_0_qs; logic mio_outsel_regwen_0_wd; @@ -5859,6 +5877,93 @@ module pinmux_reg_top ( ); + // Subregister 57 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_57_we), + .wd (mio_periph_insel_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_57_qs) + ); + + + // Subregister 58 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_58_we), + .wd (mio_periph_insel_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_58_qs) + ); + + + // Subregister 59 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_59_we), + .wd (mio_periph_insel_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_59_qs) + ); + + // Subregister 0 of Multireg mio_periph_insel // R[mio_periph_insel_0]: V(False) // Create REGWEN-gated WE signal @@ -7683,6 +7788,102 @@ module pinmux_reg_top ( ); + // Subregister 57 of Multireg mio_periph_insel + // R[mio_periph_insel_57]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_57_gated_we; + assign mio_periph_insel_57_gated_we = mio_periph_insel_57_we & mio_periph_insel_regwen_57_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_57_gated_we), + .wd (mio_periph_insel_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[57].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_57_qs) + ); + + + // Subregister 58 of Multireg mio_periph_insel + // R[mio_periph_insel_58]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_58_gated_we; + assign mio_periph_insel_58_gated_we = mio_periph_insel_58_we & mio_periph_insel_regwen_58_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_58_gated_we), + .wd (mio_periph_insel_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[58].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_58_qs) + ); + + + // Subregister 59 of Multireg mio_periph_insel + // R[mio_periph_insel_59]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_59_gated_we; + assign mio_periph_insel_59_gated_we = mio_periph_insel_59_we & mio_periph_insel_regwen_59_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_59_gated_we), + .wd (mio_periph_insel_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[59].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_59_qs) + ); + + // Subregister 0 of Multireg mio_outsel_regwen // R[mio_outsel_regwen_0]: V(False) prim_subreg #( @@ -32527,7 +32728,7 @@ module pinmux_reg_top ( - logic [567:0] addr_hit; + logic [573:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); @@ -32587,516 +32788,522 @@ module pinmux_reg_top ( addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET); addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET); addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET); - addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); - addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); - addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); - addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); - addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); - addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); - addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); - addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); - addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); - addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); - addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); - addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); - addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); - addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); - addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); - addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); - addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); - addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); - addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); - addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); - addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); - addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); - addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); - addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); - addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); - addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); - addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); - addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); - addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); - addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); - addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); - addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); - addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); - addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); - addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); - addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); - addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); - addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); - addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); - addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); - addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); - addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); - addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); - addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); - addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); - addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); - addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); - addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); - addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); - addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); - addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); - addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); - addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); - addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); - addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); - addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); - addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); - addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); - addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); - addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); - addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); - addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); - addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); - addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); - addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); - addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); - addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); - addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); - addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); - addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); - addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); - addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); - addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); - addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); - addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); - addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); - addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); - addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); - addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); - addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); - addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); - addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); - addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); - addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); - addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); - addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); - addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); - addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); - addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); - addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); - addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); - addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); - addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); - addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); - addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); - addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); - addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); - addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); - addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); - addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); - addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); - addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); - addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); - addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); - addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); - addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); - addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); - addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); - addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); - addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); - addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); - addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); - addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); - addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); - addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); - addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); - addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); - addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); - addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); - addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); - addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); - addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); - addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); - addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); - addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); - addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); - addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); - addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); - addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); - addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); - addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); - addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); - addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); - addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); - addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); - addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); - addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); - addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); - addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); - addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); - addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); - addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); - addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); - addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); - addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); - addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); - addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); - addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); - addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); - addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); - addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); - addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); - addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); - addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); - addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); - addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); - addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); - addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); - addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); - addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); - addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); - addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); - addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); - addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); - addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); - addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); - addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); - addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); - addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); - addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); - addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); - addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); - addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); - addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); - addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); - addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); - addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); - addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); - addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); - addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); - addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); - addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); - addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); - addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); - addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); - addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); - addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); - addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); - addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); - addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); - addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); - addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); - addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); - addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); - addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); - addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); - addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); - addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); - addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); - addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); - addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); - addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); - addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); - addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); - addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); - addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); - addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); - addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); - addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); - addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); - addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); - addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); - addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); - addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); - addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); - addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); - addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); - addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); - addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); - addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); - addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); - addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); - addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); - addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); - addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); - addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); - addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); - addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); - addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); - addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); - addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); - addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); - addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); - addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); - addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); - addr_hit[478] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); - addr_hit[479] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[480] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[481] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[482] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[483] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[527] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[528] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[529] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[530] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[531] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[532] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[567] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_59_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_57_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_58_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_59_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[531] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[567] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[568] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[569] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[570] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[571] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[572] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[573] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -33671,7 +33878,13 @@ module pinmux_reg_top ( (addr_hit[564] & (|(PINMUX_PERMIT[564] & ~reg_be))) | (addr_hit[565] & (|(PINMUX_PERMIT[565] & ~reg_be))) | (addr_hit[566] & (|(PINMUX_PERMIT[566] & ~reg_be))) | - (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))))); + (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))) | + (addr_hit[568] & (|(PINMUX_PERMIT[568] & ~reg_be))) | + (addr_hit[569] & (|(PINMUX_PERMIT[569] & ~reg_be))) | + (addr_hit[570] & (|(PINMUX_PERMIT[570] & ~reg_be))) | + (addr_hit[571] & (|(PINMUX_PERMIT[571] & ~reg_be))) | + (addr_hit[572] & (|(PINMUX_PERMIT[572] & ~reg_be))) | + (addr_hit[573] & (|(PINMUX_PERMIT[573] & ~reg_be))))); end // Generate write-enables @@ -33849,602 +34062,620 @@ module pinmux_reg_top ( assign mio_periph_insel_regwen_56_we = addr_hit[57] & reg_we & !reg_error; assign mio_periph_insel_regwen_56_wd = reg_wdata[0]; - assign mio_periph_insel_0_we = addr_hit[58] & reg_we & !reg_error; + assign mio_periph_insel_regwen_57_we = addr_hit[58] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_57_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_58_we = addr_hit[59] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_58_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_59_we = addr_hit[60] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_59_wd = reg_wdata[0]; + assign mio_periph_insel_0_we = addr_hit[61] & reg_we & !reg_error; assign mio_periph_insel_0_wd = reg_wdata[5:0]; - assign mio_periph_insel_1_we = addr_hit[59] & reg_we & !reg_error; + assign mio_periph_insel_1_we = addr_hit[62] & reg_we & !reg_error; assign mio_periph_insel_1_wd = reg_wdata[5:0]; - assign mio_periph_insel_2_we = addr_hit[60] & reg_we & !reg_error; + assign mio_periph_insel_2_we = addr_hit[63] & reg_we & !reg_error; assign mio_periph_insel_2_wd = reg_wdata[5:0]; - assign mio_periph_insel_3_we = addr_hit[61] & reg_we & !reg_error; + assign mio_periph_insel_3_we = addr_hit[64] & reg_we & !reg_error; assign mio_periph_insel_3_wd = reg_wdata[5:0]; - assign mio_periph_insel_4_we = addr_hit[62] & reg_we & !reg_error; + assign mio_periph_insel_4_we = addr_hit[65] & reg_we & !reg_error; assign mio_periph_insel_4_wd = reg_wdata[5:0]; - assign mio_periph_insel_5_we = addr_hit[63] & reg_we & !reg_error; + assign mio_periph_insel_5_we = addr_hit[66] & reg_we & !reg_error; assign mio_periph_insel_5_wd = reg_wdata[5:0]; - assign mio_periph_insel_6_we = addr_hit[64] & reg_we & !reg_error; + assign mio_periph_insel_6_we = addr_hit[67] & reg_we & !reg_error; assign mio_periph_insel_6_wd = reg_wdata[5:0]; - assign mio_periph_insel_7_we = addr_hit[65] & reg_we & !reg_error; + assign mio_periph_insel_7_we = addr_hit[68] & reg_we & !reg_error; assign mio_periph_insel_7_wd = reg_wdata[5:0]; - assign mio_periph_insel_8_we = addr_hit[66] & reg_we & !reg_error; + assign mio_periph_insel_8_we = addr_hit[69] & reg_we & !reg_error; assign mio_periph_insel_8_wd = reg_wdata[5:0]; - assign mio_periph_insel_9_we = addr_hit[67] & reg_we & !reg_error; + assign mio_periph_insel_9_we = addr_hit[70] & reg_we & !reg_error; assign mio_periph_insel_9_wd = reg_wdata[5:0]; - assign mio_periph_insel_10_we = addr_hit[68] & reg_we & !reg_error; + assign mio_periph_insel_10_we = addr_hit[71] & reg_we & !reg_error; assign mio_periph_insel_10_wd = reg_wdata[5:0]; - assign mio_periph_insel_11_we = addr_hit[69] & reg_we & !reg_error; + assign mio_periph_insel_11_we = addr_hit[72] & reg_we & !reg_error; assign mio_periph_insel_11_wd = reg_wdata[5:0]; - assign mio_periph_insel_12_we = addr_hit[70] & reg_we & !reg_error; + assign mio_periph_insel_12_we = addr_hit[73] & reg_we & !reg_error; assign mio_periph_insel_12_wd = reg_wdata[5:0]; - assign mio_periph_insel_13_we = addr_hit[71] & reg_we & !reg_error; + assign mio_periph_insel_13_we = addr_hit[74] & reg_we & !reg_error; assign mio_periph_insel_13_wd = reg_wdata[5:0]; - assign mio_periph_insel_14_we = addr_hit[72] & reg_we & !reg_error; + assign mio_periph_insel_14_we = addr_hit[75] & reg_we & !reg_error; assign mio_periph_insel_14_wd = reg_wdata[5:0]; - assign mio_periph_insel_15_we = addr_hit[73] & reg_we & !reg_error; + assign mio_periph_insel_15_we = addr_hit[76] & reg_we & !reg_error; assign mio_periph_insel_15_wd = reg_wdata[5:0]; - assign mio_periph_insel_16_we = addr_hit[74] & reg_we & !reg_error; + assign mio_periph_insel_16_we = addr_hit[77] & reg_we & !reg_error; assign mio_periph_insel_16_wd = reg_wdata[5:0]; - assign mio_periph_insel_17_we = addr_hit[75] & reg_we & !reg_error; + assign mio_periph_insel_17_we = addr_hit[78] & reg_we & !reg_error; assign mio_periph_insel_17_wd = reg_wdata[5:0]; - assign mio_periph_insel_18_we = addr_hit[76] & reg_we & !reg_error; + assign mio_periph_insel_18_we = addr_hit[79] & reg_we & !reg_error; assign mio_periph_insel_18_wd = reg_wdata[5:0]; - assign mio_periph_insel_19_we = addr_hit[77] & reg_we & !reg_error; + assign mio_periph_insel_19_we = addr_hit[80] & reg_we & !reg_error; assign mio_periph_insel_19_wd = reg_wdata[5:0]; - assign mio_periph_insel_20_we = addr_hit[78] & reg_we & !reg_error; + assign mio_periph_insel_20_we = addr_hit[81] & reg_we & !reg_error; assign mio_periph_insel_20_wd = reg_wdata[5:0]; - assign mio_periph_insel_21_we = addr_hit[79] & reg_we & !reg_error; + assign mio_periph_insel_21_we = addr_hit[82] & reg_we & !reg_error; assign mio_periph_insel_21_wd = reg_wdata[5:0]; - assign mio_periph_insel_22_we = addr_hit[80] & reg_we & !reg_error; + assign mio_periph_insel_22_we = addr_hit[83] & reg_we & !reg_error; assign mio_periph_insel_22_wd = reg_wdata[5:0]; - assign mio_periph_insel_23_we = addr_hit[81] & reg_we & !reg_error; + assign mio_periph_insel_23_we = addr_hit[84] & reg_we & !reg_error; assign mio_periph_insel_23_wd = reg_wdata[5:0]; - assign mio_periph_insel_24_we = addr_hit[82] & reg_we & !reg_error; + assign mio_periph_insel_24_we = addr_hit[85] & reg_we & !reg_error; assign mio_periph_insel_24_wd = reg_wdata[5:0]; - assign mio_periph_insel_25_we = addr_hit[83] & reg_we & !reg_error; + assign mio_periph_insel_25_we = addr_hit[86] & reg_we & !reg_error; assign mio_periph_insel_25_wd = reg_wdata[5:0]; - assign mio_periph_insel_26_we = addr_hit[84] & reg_we & !reg_error; + assign mio_periph_insel_26_we = addr_hit[87] & reg_we & !reg_error; assign mio_periph_insel_26_wd = reg_wdata[5:0]; - assign mio_periph_insel_27_we = addr_hit[85] & reg_we & !reg_error; + assign mio_periph_insel_27_we = addr_hit[88] & reg_we & !reg_error; assign mio_periph_insel_27_wd = reg_wdata[5:0]; - assign mio_periph_insel_28_we = addr_hit[86] & reg_we & !reg_error; + assign mio_periph_insel_28_we = addr_hit[89] & reg_we & !reg_error; assign mio_periph_insel_28_wd = reg_wdata[5:0]; - assign mio_periph_insel_29_we = addr_hit[87] & reg_we & !reg_error; + assign mio_periph_insel_29_we = addr_hit[90] & reg_we & !reg_error; assign mio_periph_insel_29_wd = reg_wdata[5:0]; - assign mio_periph_insel_30_we = addr_hit[88] & reg_we & !reg_error; + assign mio_periph_insel_30_we = addr_hit[91] & reg_we & !reg_error; assign mio_periph_insel_30_wd = reg_wdata[5:0]; - assign mio_periph_insel_31_we = addr_hit[89] & reg_we & !reg_error; + assign mio_periph_insel_31_we = addr_hit[92] & reg_we & !reg_error; assign mio_periph_insel_31_wd = reg_wdata[5:0]; - assign mio_periph_insel_32_we = addr_hit[90] & reg_we & !reg_error; + assign mio_periph_insel_32_we = addr_hit[93] & reg_we & !reg_error; assign mio_periph_insel_32_wd = reg_wdata[5:0]; - assign mio_periph_insel_33_we = addr_hit[91] & reg_we & !reg_error; + assign mio_periph_insel_33_we = addr_hit[94] & reg_we & !reg_error; assign mio_periph_insel_33_wd = reg_wdata[5:0]; - assign mio_periph_insel_34_we = addr_hit[92] & reg_we & !reg_error; + assign mio_periph_insel_34_we = addr_hit[95] & reg_we & !reg_error; assign mio_periph_insel_34_wd = reg_wdata[5:0]; - assign mio_periph_insel_35_we = addr_hit[93] & reg_we & !reg_error; + assign mio_periph_insel_35_we = addr_hit[96] & reg_we & !reg_error; assign mio_periph_insel_35_wd = reg_wdata[5:0]; - assign mio_periph_insel_36_we = addr_hit[94] & reg_we & !reg_error; + assign mio_periph_insel_36_we = addr_hit[97] & reg_we & !reg_error; assign mio_periph_insel_36_wd = reg_wdata[5:0]; - assign mio_periph_insel_37_we = addr_hit[95] & reg_we & !reg_error; + assign mio_periph_insel_37_we = addr_hit[98] & reg_we & !reg_error; assign mio_periph_insel_37_wd = reg_wdata[5:0]; - assign mio_periph_insel_38_we = addr_hit[96] & reg_we & !reg_error; + assign mio_periph_insel_38_we = addr_hit[99] & reg_we & !reg_error; assign mio_periph_insel_38_wd = reg_wdata[5:0]; - assign mio_periph_insel_39_we = addr_hit[97] & reg_we & !reg_error; + assign mio_periph_insel_39_we = addr_hit[100] & reg_we & !reg_error; assign mio_periph_insel_39_wd = reg_wdata[5:0]; - assign mio_periph_insel_40_we = addr_hit[98] & reg_we & !reg_error; + assign mio_periph_insel_40_we = addr_hit[101] & reg_we & !reg_error; assign mio_periph_insel_40_wd = reg_wdata[5:0]; - assign mio_periph_insel_41_we = addr_hit[99] & reg_we & !reg_error; + assign mio_periph_insel_41_we = addr_hit[102] & reg_we & !reg_error; assign mio_periph_insel_41_wd = reg_wdata[5:0]; - assign mio_periph_insel_42_we = addr_hit[100] & reg_we & !reg_error; + assign mio_periph_insel_42_we = addr_hit[103] & reg_we & !reg_error; assign mio_periph_insel_42_wd = reg_wdata[5:0]; - assign mio_periph_insel_43_we = addr_hit[101] & reg_we & !reg_error; + assign mio_periph_insel_43_we = addr_hit[104] & reg_we & !reg_error; assign mio_periph_insel_43_wd = reg_wdata[5:0]; - assign mio_periph_insel_44_we = addr_hit[102] & reg_we & !reg_error; + assign mio_periph_insel_44_we = addr_hit[105] & reg_we & !reg_error; assign mio_periph_insel_44_wd = reg_wdata[5:0]; - assign mio_periph_insel_45_we = addr_hit[103] & reg_we & !reg_error; + assign mio_periph_insel_45_we = addr_hit[106] & reg_we & !reg_error; assign mio_periph_insel_45_wd = reg_wdata[5:0]; - assign mio_periph_insel_46_we = addr_hit[104] & reg_we & !reg_error; + assign mio_periph_insel_46_we = addr_hit[107] & reg_we & !reg_error; assign mio_periph_insel_46_wd = reg_wdata[5:0]; - assign mio_periph_insel_47_we = addr_hit[105] & reg_we & !reg_error; + assign mio_periph_insel_47_we = addr_hit[108] & reg_we & !reg_error; assign mio_periph_insel_47_wd = reg_wdata[5:0]; - assign mio_periph_insel_48_we = addr_hit[106] & reg_we & !reg_error; + assign mio_periph_insel_48_we = addr_hit[109] & reg_we & !reg_error; assign mio_periph_insel_48_wd = reg_wdata[5:0]; - assign mio_periph_insel_49_we = addr_hit[107] & reg_we & !reg_error; + assign mio_periph_insel_49_we = addr_hit[110] & reg_we & !reg_error; assign mio_periph_insel_49_wd = reg_wdata[5:0]; - assign mio_periph_insel_50_we = addr_hit[108] & reg_we & !reg_error; + assign mio_periph_insel_50_we = addr_hit[111] & reg_we & !reg_error; assign mio_periph_insel_50_wd = reg_wdata[5:0]; - assign mio_periph_insel_51_we = addr_hit[109] & reg_we & !reg_error; + assign mio_periph_insel_51_we = addr_hit[112] & reg_we & !reg_error; assign mio_periph_insel_51_wd = reg_wdata[5:0]; - assign mio_periph_insel_52_we = addr_hit[110] & reg_we & !reg_error; + assign mio_periph_insel_52_we = addr_hit[113] & reg_we & !reg_error; assign mio_periph_insel_52_wd = reg_wdata[5:0]; - assign mio_periph_insel_53_we = addr_hit[111] & reg_we & !reg_error; + assign mio_periph_insel_53_we = addr_hit[114] & reg_we & !reg_error; assign mio_periph_insel_53_wd = reg_wdata[5:0]; - assign mio_periph_insel_54_we = addr_hit[112] & reg_we & !reg_error; + assign mio_periph_insel_54_we = addr_hit[115] & reg_we & !reg_error; assign mio_periph_insel_54_wd = reg_wdata[5:0]; - assign mio_periph_insel_55_we = addr_hit[113] & reg_we & !reg_error; + assign mio_periph_insel_55_we = addr_hit[116] & reg_we & !reg_error; assign mio_periph_insel_55_wd = reg_wdata[5:0]; - assign mio_periph_insel_56_we = addr_hit[114] & reg_we & !reg_error; + assign mio_periph_insel_56_we = addr_hit[117] & reg_we & !reg_error; assign mio_periph_insel_56_wd = reg_wdata[5:0]; - assign mio_outsel_regwen_0_we = addr_hit[115] & reg_we & !reg_error; + assign mio_periph_insel_57_we = addr_hit[118] & reg_we & !reg_error; + + assign mio_periph_insel_57_wd = reg_wdata[5:0]; + assign mio_periph_insel_58_we = addr_hit[119] & reg_we & !reg_error; + + assign mio_periph_insel_58_wd = reg_wdata[5:0]; + assign mio_periph_insel_59_we = addr_hit[120] & reg_we & !reg_error; + + assign mio_periph_insel_59_wd = reg_wdata[5:0]; + assign mio_outsel_regwen_0_we = addr_hit[121] & reg_we & !reg_error; assign mio_outsel_regwen_0_wd = reg_wdata[0]; - assign mio_outsel_regwen_1_we = addr_hit[116] & reg_we & !reg_error; + assign mio_outsel_regwen_1_we = addr_hit[122] & reg_we & !reg_error; assign mio_outsel_regwen_1_wd = reg_wdata[0]; - assign mio_outsel_regwen_2_we = addr_hit[117] & reg_we & !reg_error; + assign mio_outsel_regwen_2_we = addr_hit[123] & reg_we & !reg_error; assign mio_outsel_regwen_2_wd = reg_wdata[0]; - assign mio_outsel_regwen_3_we = addr_hit[118] & reg_we & !reg_error; + assign mio_outsel_regwen_3_we = addr_hit[124] & reg_we & !reg_error; assign mio_outsel_regwen_3_wd = reg_wdata[0]; - assign mio_outsel_regwen_4_we = addr_hit[119] & reg_we & !reg_error; + assign mio_outsel_regwen_4_we = addr_hit[125] & reg_we & !reg_error; assign mio_outsel_regwen_4_wd = reg_wdata[0]; - assign mio_outsel_regwen_5_we = addr_hit[120] & reg_we & !reg_error; + assign mio_outsel_regwen_5_we = addr_hit[126] & reg_we & !reg_error; assign mio_outsel_regwen_5_wd = reg_wdata[0]; - assign mio_outsel_regwen_6_we = addr_hit[121] & reg_we & !reg_error; + assign mio_outsel_regwen_6_we = addr_hit[127] & reg_we & !reg_error; assign mio_outsel_regwen_6_wd = reg_wdata[0]; - assign mio_outsel_regwen_7_we = addr_hit[122] & reg_we & !reg_error; + assign mio_outsel_regwen_7_we = addr_hit[128] & reg_we & !reg_error; assign mio_outsel_regwen_7_wd = reg_wdata[0]; - assign mio_outsel_regwen_8_we = addr_hit[123] & reg_we & !reg_error; + assign mio_outsel_regwen_8_we = addr_hit[129] & reg_we & !reg_error; assign mio_outsel_regwen_8_wd = reg_wdata[0]; - assign mio_outsel_regwen_9_we = addr_hit[124] & reg_we & !reg_error; + assign mio_outsel_regwen_9_we = addr_hit[130] & reg_we & !reg_error; assign mio_outsel_regwen_9_wd = reg_wdata[0]; - assign mio_outsel_regwen_10_we = addr_hit[125] & reg_we & !reg_error; + assign mio_outsel_regwen_10_we = addr_hit[131] & reg_we & !reg_error; assign mio_outsel_regwen_10_wd = reg_wdata[0]; - assign mio_outsel_regwen_11_we = addr_hit[126] & reg_we & !reg_error; + assign mio_outsel_regwen_11_we = addr_hit[132] & reg_we & !reg_error; assign mio_outsel_regwen_11_wd = reg_wdata[0]; - assign mio_outsel_regwen_12_we = addr_hit[127] & reg_we & !reg_error; + assign mio_outsel_regwen_12_we = addr_hit[133] & reg_we & !reg_error; assign mio_outsel_regwen_12_wd = reg_wdata[0]; - assign mio_outsel_regwen_13_we = addr_hit[128] & reg_we & !reg_error; + assign mio_outsel_regwen_13_we = addr_hit[134] & reg_we & !reg_error; assign mio_outsel_regwen_13_wd = reg_wdata[0]; - assign mio_outsel_regwen_14_we = addr_hit[129] & reg_we & !reg_error; + assign mio_outsel_regwen_14_we = addr_hit[135] & reg_we & !reg_error; assign mio_outsel_regwen_14_wd = reg_wdata[0]; - assign mio_outsel_regwen_15_we = addr_hit[130] & reg_we & !reg_error; + assign mio_outsel_regwen_15_we = addr_hit[136] & reg_we & !reg_error; assign mio_outsel_regwen_15_wd = reg_wdata[0]; - assign mio_outsel_regwen_16_we = addr_hit[131] & reg_we & !reg_error; + assign mio_outsel_regwen_16_we = addr_hit[137] & reg_we & !reg_error; assign mio_outsel_regwen_16_wd = reg_wdata[0]; - assign mio_outsel_regwen_17_we = addr_hit[132] & reg_we & !reg_error; + assign mio_outsel_regwen_17_we = addr_hit[138] & reg_we & !reg_error; assign mio_outsel_regwen_17_wd = reg_wdata[0]; - assign mio_outsel_regwen_18_we = addr_hit[133] & reg_we & !reg_error; + assign mio_outsel_regwen_18_we = addr_hit[139] & reg_we & !reg_error; assign mio_outsel_regwen_18_wd = reg_wdata[0]; - assign mio_outsel_regwen_19_we = addr_hit[134] & reg_we & !reg_error; + assign mio_outsel_regwen_19_we = addr_hit[140] & reg_we & !reg_error; assign mio_outsel_regwen_19_wd = reg_wdata[0]; - assign mio_outsel_regwen_20_we = addr_hit[135] & reg_we & !reg_error; + assign mio_outsel_regwen_20_we = addr_hit[141] & reg_we & !reg_error; assign mio_outsel_regwen_20_wd = reg_wdata[0]; - assign mio_outsel_regwen_21_we = addr_hit[136] & reg_we & !reg_error; + assign mio_outsel_regwen_21_we = addr_hit[142] & reg_we & !reg_error; assign mio_outsel_regwen_21_wd = reg_wdata[0]; - assign mio_outsel_regwen_22_we = addr_hit[137] & reg_we & !reg_error; + assign mio_outsel_regwen_22_we = addr_hit[143] & reg_we & !reg_error; assign mio_outsel_regwen_22_wd = reg_wdata[0]; - assign mio_outsel_regwen_23_we = addr_hit[138] & reg_we & !reg_error; + assign mio_outsel_regwen_23_we = addr_hit[144] & reg_we & !reg_error; assign mio_outsel_regwen_23_wd = reg_wdata[0]; - assign mio_outsel_regwen_24_we = addr_hit[139] & reg_we & !reg_error; + assign mio_outsel_regwen_24_we = addr_hit[145] & reg_we & !reg_error; assign mio_outsel_regwen_24_wd = reg_wdata[0]; - assign mio_outsel_regwen_25_we = addr_hit[140] & reg_we & !reg_error; + assign mio_outsel_regwen_25_we = addr_hit[146] & reg_we & !reg_error; assign mio_outsel_regwen_25_wd = reg_wdata[0]; - assign mio_outsel_regwen_26_we = addr_hit[141] & reg_we & !reg_error; + assign mio_outsel_regwen_26_we = addr_hit[147] & reg_we & !reg_error; assign mio_outsel_regwen_26_wd = reg_wdata[0]; - assign mio_outsel_regwen_27_we = addr_hit[142] & reg_we & !reg_error; + assign mio_outsel_regwen_27_we = addr_hit[148] & reg_we & !reg_error; assign mio_outsel_regwen_27_wd = reg_wdata[0]; - assign mio_outsel_regwen_28_we = addr_hit[143] & reg_we & !reg_error; + assign mio_outsel_regwen_28_we = addr_hit[149] & reg_we & !reg_error; assign mio_outsel_regwen_28_wd = reg_wdata[0]; - assign mio_outsel_regwen_29_we = addr_hit[144] & reg_we & !reg_error; + assign mio_outsel_regwen_29_we = addr_hit[150] & reg_we & !reg_error; assign mio_outsel_regwen_29_wd = reg_wdata[0]; - assign mio_outsel_regwen_30_we = addr_hit[145] & reg_we & !reg_error; + assign mio_outsel_regwen_30_we = addr_hit[151] & reg_we & !reg_error; assign mio_outsel_regwen_30_wd = reg_wdata[0]; - assign mio_outsel_regwen_31_we = addr_hit[146] & reg_we & !reg_error; + assign mio_outsel_regwen_31_we = addr_hit[152] & reg_we & !reg_error; assign mio_outsel_regwen_31_wd = reg_wdata[0]; - assign mio_outsel_regwen_32_we = addr_hit[147] & reg_we & !reg_error; + assign mio_outsel_regwen_32_we = addr_hit[153] & reg_we & !reg_error; assign mio_outsel_regwen_32_wd = reg_wdata[0]; - assign mio_outsel_regwen_33_we = addr_hit[148] & reg_we & !reg_error; + assign mio_outsel_regwen_33_we = addr_hit[154] & reg_we & !reg_error; assign mio_outsel_regwen_33_wd = reg_wdata[0]; - assign mio_outsel_regwen_34_we = addr_hit[149] & reg_we & !reg_error; + assign mio_outsel_regwen_34_we = addr_hit[155] & reg_we & !reg_error; assign mio_outsel_regwen_34_wd = reg_wdata[0]; - assign mio_outsel_regwen_35_we = addr_hit[150] & reg_we & !reg_error; + assign mio_outsel_regwen_35_we = addr_hit[156] & reg_we & !reg_error; assign mio_outsel_regwen_35_wd = reg_wdata[0]; - assign mio_outsel_regwen_36_we = addr_hit[151] & reg_we & !reg_error; + assign mio_outsel_regwen_36_we = addr_hit[157] & reg_we & !reg_error; assign mio_outsel_regwen_36_wd = reg_wdata[0]; - assign mio_outsel_regwen_37_we = addr_hit[152] & reg_we & !reg_error; + assign mio_outsel_regwen_37_we = addr_hit[158] & reg_we & !reg_error; assign mio_outsel_regwen_37_wd = reg_wdata[0]; - assign mio_outsel_regwen_38_we = addr_hit[153] & reg_we & !reg_error; + assign mio_outsel_regwen_38_we = addr_hit[159] & reg_we & !reg_error; assign mio_outsel_regwen_38_wd = reg_wdata[0]; - assign mio_outsel_regwen_39_we = addr_hit[154] & reg_we & !reg_error; + assign mio_outsel_regwen_39_we = addr_hit[160] & reg_we & !reg_error; assign mio_outsel_regwen_39_wd = reg_wdata[0]; - assign mio_outsel_regwen_40_we = addr_hit[155] & reg_we & !reg_error; + assign mio_outsel_regwen_40_we = addr_hit[161] & reg_we & !reg_error; assign mio_outsel_regwen_40_wd = reg_wdata[0]; - assign mio_outsel_regwen_41_we = addr_hit[156] & reg_we & !reg_error; + assign mio_outsel_regwen_41_we = addr_hit[162] & reg_we & !reg_error; assign mio_outsel_regwen_41_wd = reg_wdata[0]; - assign mio_outsel_regwen_42_we = addr_hit[157] & reg_we & !reg_error; + assign mio_outsel_regwen_42_we = addr_hit[163] & reg_we & !reg_error; assign mio_outsel_regwen_42_wd = reg_wdata[0]; - assign mio_outsel_regwen_43_we = addr_hit[158] & reg_we & !reg_error; + assign mio_outsel_regwen_43_we = addr_hit[164] & reg_we & !reg_error; assign mio_outsel_regwen_43_wd = reg_wdata[0]; - assign mio_outsel_regwen_44_we = addr_hit[159] & reg_we & !reg_error; + assign mio_outsel_regwen_44_we = addr_hit[165] & reg_we & !reg_error; assign mio_outsel_regwen_44_wd = reg_wdata[0]; - assign mio_outsel_regwen_45_we = addr_hit[160] & reg_we & !reg_error; + assign mio_outsel_regwen_45_we = addr_hit[166] & reg_we & !reg_error; assign mio_outsel_regwen_45_wd = reg_wdata[0]; - assign mio_outsel_regwen_46_we = addr_hit[161] & reg_we & !reg_error; + assign mio_outsel_regwen_46_we = addr_hit[167] & reg_we & !reg_error; assign mio_outsel_regwen_46_wd = reg_wdata[0]; - assign mio_outsel_0_we = addr_hit[162] & reg_we & !reg_error; + assign mio_outsel_0_we = addr_hit[168] & reg_we & !reg_error; assign mio_outsel_0_wd = reg_wdata[6:0]; - assign mio_outsel_1_we = addr_hit[163] & reg_we & !reg_error; + assign mio_outsel_1_we = addr_hit[169] & reg_we & !reg_error; assign mio_outsel_1_wd = reg_wdata[6:0]; - assign mio_outsel_2_we = addr_hit[164] & reg_we & !reg_error; + assign mio_outsel_2_we = addr_hit[170] & reg_we & !reg_error; assign mio_outsel_2_wd = reg_wdata[6:0]; - assign mio_outsel_3_we = addr_hit[165] & reg_we & !reg_error; + assign mio_outsel_3_we = addr_hit[171] & reg_we & !reg_error; assign mio_outsel_3_wd = reg_wdata[6:0]; - assign mio_outsel_4_we = addr_hit[166] & reg_we & !reg_error; + assign mio_outsel_4_we = addr_hit[172] & reg_we & !reg_error; assign mio_outsel_4_wd = reg_wdata[6:0]; - assign mio_outsel_5_we = addr_hit[167] & reg_we & !reg_error; + assign mio_outsel_5_we = addr_hit[173] & reg_we & !reg_error; assign mio_outsel_5_wd = reg_wdata[6:0]; - assign mio_outsel_6_we = addr_hit[168] & reg_we & !reg_error; + assign mio_outsel_6_we = addr_hit[174] & reg_we & !reg_error; assign mio_outsel_6_wd = reg_wdata[6:0]; - assign mio_outsel_7_we = addr_hit[169] & reg_we & !reg_error; + assign mio_outsel_7_we = addr_hit[175] & reg_we & !reg_error; assign mio_outsel_7_wd = reg_wdata[6:0]; - assign mio_outsel_8_we = addr_hit[170] & reg_we & !reg_error; + assign mio_outsel_8_we = addr_hit[176] & reg_we & !reg_error; assign mio_outsel_8_wd = reg_wdata[6:0]; - assign mio_outsel_9_we = addr_hit[171] & reg_we & !reg_error; + assign mio_outsel_9_we = addr_hit[177] & reg_we & !reg_error; assign mio_outsel_9_wd = reg_wdata[6:0]; - assign mio_outsel_10_we = addr_hit[172] & reg_we & !reg_error; + assign mio_outsel_10_we = addr_hit[178] & reg_we & !reg_error; assign mio_outsel_10_wd = reg_wdata[6:0]; - assign mio_outsel_11_we = addr_hit[173] & reg_we & !reg_error; + assign mio_outsel_11_we = addr_hit[179] & reg_we & !reg_error; assign mio_outsel_11_wd = reg_wdata[6:0]; - assign mio_outsel_12_we = addr_hit[174] & reg_we & !reg_error; + assign mio_outsel_12_we = addr_hit[180] & reg_we & !reg_error; assign mio_outsel_12_wd = reg_wdata[6:0]; - assign mio_outsel_13_we = addr_hit[175] & reg_we & !reg_error; + assign mio_outsel_13_we = addr_hit[181] & reg_we & !reg_error; assign mio_outsel_13_wd = reg_wdata[6:0]; - assign mio_outsel_14_we = addr_hit[176] & reg_we & !reg_error; + assign mio_outsel_14_we = addr_hit[182] & reg_we & !reg_error; assign mio_outsel_14_wd = reg_wdata[6:0]; - assign mio_outsel_15_we = addr_hit[177] & reg_we & !reg_error; + assign mio_outsel_15_we = addr_hit[183] & reg_we & !reg_error; assign mio_outsel_15_wd = reg_wdata[6:0]; - assign mio_outsel_16_we = addr_hit[178] & reg_we & !reg_error; + assign mio_outsel_16_we = addr_hit[184] & reg_we & !reg_error; assign mio_outsel_16_wd = reg_wdata[6:0]; - assign mio_outsel_17_we = addr_hit[179] & reg_we & !reg_error; + assign mio_outsel_17_we = addr_hit[185] & reg_we & !reg_error; assign mio_outsel_17_wd = reg_wdata[6:0]; - assign mio_outsel_18_we = addr_hit[180] & reg_we & !reg_error; + assign mio_outsel_18_we = addr_hit[186] & reg_we & !reg_error; assign mio_outsel_18_wd = reg_wdata[6:0]; - assign mio_outsel_19_we = addr_hit[181] & reg_we & !reg_error; + assign mio_outsel_19_we = addr_hit[187] & reg_we & !reg_error; assign mio_outsel_19_wd = reg_wdata[6:0]; - assign mio_outsel_20_we = addr_hit[182] & reg_we & !reg_error; + assign mio_outsel_20_we = addr_hit[188] & reg_we & !reg_error; assign mio_outsel_20_wd = reg_wdata[6:0]; - assign mio_outsel_21_we = addr_hit[183] & reg_we & !reg_error; + assign mio_outsel_21_we = addr_hit[189] & reg_we & !reg_error; assign mio_outsel_21_wd = reg_wdata[6:0]; - assign mio_outsel_22_we = addr_hit[184] & reg_we & !reg_error; + assign mio_outsel_22_we = addr_hit[190] & reg_we & !reg_error; assign mio_outsel_22_wd = reg_wdata[6:0]; - assign mio_outsel_23_we = addr_hit[185] & reg_we & !reg_error; + assign mio_outsel_23_we = addr_hit[191] & reg_we & !reg_error; assign mio_outsel_23_wd = reg_wdata[6:0]; - assign mio_outsel_24_we = addr_hit[186] & reg_we & !reg_error; + assign mio_outsel_24_we = addr_hit[192] & reg_we & !reg_error; assign mio_outsel_24_wd = reg_wdata[6:0]; - assign mio_outsel_25_we = addr_hit[187] & reg_we & !reg_error; + assign mio_outsel_25_we = addr_hit[193] & reg_we & !reg_error; assign mio_outsel_25_wd = reg_wdata[6:0]; - assign mio_outsel_26_we = addr_hit[188] & reg_we & !reg_error; + assign mio_outsel_26_we = addr_hit[194] & reg_we & !reg_error; assign mio_outsel_26_wd = reg_wdata[6:0]; - assign mio_outsel_27_we = addr_hit[189] & reg_we & !reg_error; + assign mio_outsel_27_we = addr_hit[195] & reg_we & !reg_error; assign mio_outsel_27_wd = reg_wdata[6:0]; - assign mio_outsel_28_we = addr_hit[190] & reg_we & !reg_error; + assign mio_outsel_28_we = addr_hit[196] & reg_we & !reg_error; assign mio_outsel_28_wd = reg_wdata[6:0]; - assign mio_outsel_29_we = addr_hit[191] & reg_we & !reg_error; + assign mio_outsel_29_we = addr_hit[197] & reg_we & !reg_error; assign mio_outsel_29_wd = reg_wdata[6:0]; - assign mio_outsel_30_we = addr_hit[192] & reg_we & !reg_error; + assign mio_outsel_30_we = addr_hit[198] & reg_we & !reg_error; assign mio_outsel_30_wd = reg_wdata[6:0]; - assign mio_outsel_31_we = addr_hit[193] & reg_we & !reg_error; + assign mio_outsel_31_we = addr_hit[199] & reg_we & !reg_error; assign mio_outsel_31_wd = reg_wdata[6:0]; - assign mio_outsel_32_we = addr_hit[194] & reg_we & !reg_error; + assign mio_outsel_32_we = addr_hit[200] & reg_we & !reg_error; assign mio_outsel_32_wd = reg_wdata[6:0]; - assign mio_outsel_33_we = addr_hit[195] & reg_we & !reg_error; + assign mio_outsel_33_we = addr_hit[201] & reg_we & !reg_error; assign mio_outsel_33_wd = reg_wdata[6:0]; - assign mio_outsel_34_we = addr_hit[196] & reg_we & !reg_error; + assign mio_outsel_34_we = addr_hit[202] & reg_we & !reg_error; assign mio_outsel_34_wd = reg_wdata[6:0]; - assign mio_outsel_35_we = addr_hit[197] & reg_we & !reg_error; + assign mio_outsel_35_we = addr_hit[203] & reg_we & !reg_error; assign mio_outsel_35_wd = reg_wdata[6:0]; - assign mio_outsel_36_we = addr_hit[198] & reg_we & !reg_error; + assign mio_outsel_36_we = addr_hit[204] & reg_we & !reg_error; assign mio_outsel_36_wd = reg_wdata[6:0]; - assign mio_outsel_37_we = addr_hit[199] & reg_we & !reg_error; + assign mio_outsel_37_we = addr_hit[205] & reg_we & !reg_error; assign mio_outsel_37_wd = reg_wdata[6:0]; - assign mio_outsel_38_we = addr_hit[200] & reg_we & !reg_error; + assign mio_outsel_38_we = addr_hit[206] & reg_we & !reg_error; assign mio_outsel_38_wd = reg_wdata[6:0]; - assign mio_outsel_39_we = addr_hit[201] & reg_we & !reg_error; + assign mio_outsel_39_we = addr_hit[207] & reg_we & !reg_error; assign mio_outsel_39_wd = reg_wdata[6:0]; - assign mio_outsel_40_we = addr_hit[202] & reg_we & !reg_error; + assign mio_outsel_40_we = addr_hit[208] & reg_we & !reg_error; assign mio_outsel_40_wd = reg_wdata[6:0]; - assign mio_outsel_41_we = addr_hit[203] & reg_we & !reg_error; + assign mio_outsel_41_we = addr_hit[209] & reg_we & !reg_error; assign mio_outsel_41_wd = reg_wdata[6:0]; - assign mio_outsel_42_we = addr_hit[204] & reg_we & !reg_error; + assign mio_outsel_42_we = addr_hit[210] & reg_we & !reg_error; assign mio_outsel_42_wd = reg_wdata[6:0]; - assign mio_outsel_43_we = addr_hit[205] & reg_we & !reg_error; + assign mio_outsel_43_we = addr_hit[211] & reg_we & !reg_error; assign mio_outsel_43_wd = reg_wdata[6:0]; - assign mio_outsel_44_we = addr_hit[206] & reg_we & !reg_error; + assign mio_outsel_44_we = addr_hit[212] & reg_we & !reg_error; assign mio_outsel_44_wd = reg_wdata[6:0]; - assign mio_outsel_45_we = addr_hit[207] & reg_we & !reg_error; + assign mio_outsel_45_we = addr_hit[213] & reg_we & !reg_error; assign mio_outsel_45_wd = reg_wdata[6:0]; - assign mio_outsel_46_we = addr_hit[208] & reg_we & !reg_error; + assign mio_outsel_46_we = addr_hit[214] & reg_we & !reg_error; assign mio_outsel_46_wd = reg_wdata[6:0]; - assign mio_pad_attr_regwen_0_we = addr_hit[209] & reg_we & !reg_error; + assign mio_pad_attr_regwen_0_we = addr_hit[215] & reg_we & !reg_error; assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_1_we = addr_hit[210] & reg_we & !reg_error; + assign mio_pad_attr_regwen_1_we = addr_hit[216] & reg_we & !reg_error; assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_2_we = addr_hit[211] & reg_we & !reg_error; + assign mio_pad_attr_regwen_2_we = addr_hit[217] & reg_we & !reg_error; assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_3_we = addr_hit[212] & reg_we & !reg_error; + assign mio_pad_attr_regwen_3_we = addr_hit[218] & reg_we & !reg_error; assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_4_we = addr_hit[213] & reg_we & !reg_error; + assign mio_pad_attr_regwen_4_we = addr_hit[219] & reg_we & !reg_error; assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_5_we = addr_hit[214] & reg_we & !reg_error; + assign mio_pad_attr_regwen_5_we = addr_hit[220] & reg_we & !reg_error; assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_6_we = addr_hit[215] & reg_we & !reg_error; + assign mio_pad_attr_regwen_6_we = addr_hit[221] & reg_we & !reg_error; assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_7_we = addr_hit[216] & reg_we & !reg_error; + assign mio_pad_attr_regwen_7_we = addr_hit[222] & reg_we & !reg_error; assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_8_we = addr_hit[217] & reg_we & !reg_error; + assign mio_pad_attr_regwen_8_we = addr_hit[223] & reg_we & !reg_error; assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_9_we = addr_hit[218] & reg_we & !reg_error; + assign mio_pad_attr_regwen_9_we = addr_hit[224] & reg_we & !reg_error; assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_10_we = addr_hit[219] & reg_we & !reg_error; + assign mio_pad_attr_regwen_10_we = addr_hit[225] & reg_we & !reg_error; assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_11_we = addr_hit[220] & reg_we & !reg_error; + assign mio_pad_attr_regwen_11_we = addr_hit[226] & reg_we & !reg_error; assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_12_we = addr_hit[221] & reg_we & !reg_error; + assign mio_pad_attr_regwen_12_we = addr_hit[227] & reg_we & !reg_error; assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_13_we = addr_hit[222] & reg_we & !reg_error; + assign mio_pad_attr_regwen_13_we = addr_hit[228] & reg_we & !reg_error; assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_14_we = addr_hit[223] & reg_we & !reg_error; + assign mio_pad_attr_regwen_14_we = addr_hit[229] & reg_we & !reg_error; assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_15_we = addr_hit[224] & reg_we & !reg_error; + assign mio_pad_attr_regwen_15_we = addr_hit[230] & reg_we & !reg_error; assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_16_we = addr_hit[225] & reg_we & !reg_error; + assign mio_pad_attr_regwen_16_we = addr_hit[231] & reg_we & !reg_error; assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_17_we = addr_hit[226] & reg_we & !reg_error; + assign mio_pad_attr_regwen_17_we = addr_hit[232] & reg_we & !reg_error; assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_18_we = addr_hit[227] & reg_we & !reg_error; + assign mio_pad_attr_regwen_18_we = addr_hit[233] & reg_we & !reg_error; assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_19_we = addr_hit[228] & reg_we & !reg_error; + assign mio_pad_attr_regwen_19_we = addr_hit[234] & reg_we & !reg_error; assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_20_we = addr_hit[229] & reg_we & !reg_error; + assign mio_pad_attr_regwen_20_we = addr_hit[235] & reg_we & !reg_error; assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_21_we = addr_hit[230] & reg_we & !reg_error; + assign mio_pad_attr_regwen_21_we = addr_hit[236] & reg_we & !reg_error; assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_22_we = addr_hit[231] & reg_we & !reg_error; + assign mio_pad_attr_regwen_22_we = addr_hit[237] & reg_we & !reg_error; assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_23_we = addr_hit[232] & reg_we & !reg_error; + assign mio_pad_attr_regwen_23_we = addr_hit[238] & reg_we & !reg_error; assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_24_we = addr_hit[233] & reg_we & !reg_error; + assign mio_pad_attr_regwen_24_we = addr_hit[239] & reg_we & !reg_error; assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_25_we = addr_hit[234] & reg_we & !reg_error; + assign mio_pad_attr_regwen_25_we = addr_hit[240] & reg_we & !reg_error; assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_26_we = addr_hit[235] & reg_we & !reg_error; + assign mio_pad_attr_regwen_26_we = addr_hit[241] & reg_we & !reg_error; assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_27_we = addr_hit[236] & reg_we & !reg_error; + assign mio_pad_attr_regwen_27_we = addr_hit[242] & reg_we & !reg_error; assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_28_we = addr_hit[237] & reg_we & !reg_error; + assign mio_pad_attr_regwen_28_we = addr_hit[243] & reg_we & !reg_error; assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_29_we = addr_hit[238] & reg_we & !reg_error; + assign mio_pad_attr_regwen_29_we = addr_hit[244] & reg_we & !reg_error; assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_30_we = addr_hit[239] & reg_we & !reg_error; + assign mio_pad_attr_regwen_30_we = addr_hit[245] & reg_we & !reg_error; assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_31_we = addr_hit[240] & reg_we & !reg_error; + assign mio_pad_attr_regwen_31_we = addr_hit[246] & reg_we & !reg_error; assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_32_we = addr_hit[241] & reg_we & !reg_error; + assign mio_pad_attr_regwen_32_we = addr_hit[247] & reg_we & !reg_error; assign mio_pad_attr_regwen_32_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_33_we = addr_hit[242] & reg_we & !reg_error; + assign mio_pad_attr_regwen_33_we = addr_hit[248] & reg_we & !reg_error; assign mio_pad_attr_regwen_33_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_34_we = addr_hit[243] & reg_we & !reg_error; + assign mio_pad_attr_regwen_34_we = addr_hit[249] & reg_we & !reg_error; assign mio_pad_attr_regwen_34_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_35_we = addr_hit[244] & reg_we & !reg_error; + assign mio_pad_attr_regwen_35_we = addr_hit[250] & reg_we & !reg_error; assign mio_pad_attr_regwen_35_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_36_we = addr_hit[245] & reg_we & !reg_error; + assign mio_pad_attr_regwen_36_we = addr_hit[251] & reg_we & !reg_error; assign mio_pad_attr_regwen_36_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_37_we = addr_hit[246] & reg_we & !reg_error; + assign mio_pad_attr_regwen_37_we = addr_hit[252] & reg_we & !reg_error; assign mio_pad_attr_regwen_37_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_38_we = addr_hit[247] & reg_we & !reg_error; + assign mio_pad_attr_regwen_38_we = addr_hit[253] & reg_we & !reg_error; assign mio_pad_attr_regwen_38_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_39_we = addr_hit[248] & reg_we & !reg_error; + assign mio_pad_attr_regwen_39_we = addr_hit[254] & reg_we & !reg_error; assign mio_pad_attr_regwen_39_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_40_we = addr_hit[249] & reg_we & !reg_error; + assign mio_pad_attr_regwen_40_we = addr_hit[255] & reg_we & !reg_error; assign mio_pad_attr_regwen_40_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_41_we = addr_hit[250] & reg_we & !reg_error; + assign mio_pad_attr_regwen_41_we = addr_hit[256] & reg_we & !reg_error; assign mio_pad_attr_regwen_41_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_42_we = addr_hit[251] & reg_we & !reg_error; + assign mio_pad_attr_regwen_42_we = addr_hit[257] & reg_we & !reg_error; assign mio_pad_attr_regwen_42_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_43_we = addr_hit[252] & reg_we & !reg_error; + assign mio_pad_attr_regwen_43_we = addr_hit[258] & reg_we & !reg_error; assign mio_pad_attr_regwen_43_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_44_we = addr_hit[253] & reg_we & !reg_error; + assign mio_pad_attr_regwen_44_we = addr_hit[259] & reg_we & !reg_error; assign mio_pad_attr_regwen_44_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_45_we = addr_hit[254] & reg_we & !reg_error; + assign mio_pad_attr_regwen_45_we = addr_hit[260] & reg_we & !reg_error; assign mio_pad_attr_regwen_45_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_46_we = addr_hit[255] & reg_we & !reg_error; + assign mio_pad_attr_regwen_46_we = addr_hit[261] & reg_we & !reg_error; assign mio_pad_attr_regwen_46_wd = reg_wdata[0]; - assign mio_pad_attr_0_re = addr_hit[256] & reg_re & !reg_error; - assign mio_pad_attr_0_we = addr_hit[256] & reg_we & !reg_error; + assign mio_pad_attr_0_re = addr_hit[262] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[262] & reg_we & !reg_error; assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -34465,8 +34696,8 @@ module pinmux_reg_top ( assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign mio_pad_attr_1_re = addr_hit[257] & reg_re & !reg_error; - assign mio_pad_attr_1_we = addr_hit[257] & reg_we & !reg_error; + assign mio_pad_attr_1_re = addr_hit[263] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[263] & reg_we & !reg_error; assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -34487,8 +34718,8 @@ module pinmux_reg_top ( assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign mio_pad_attr_2_re = addr_hit[258] & reg_re & !reg_error; - assign mio_pad_attr_2_we = addr_hit[258] & reg_we & !reg_error; + assign mio_pad_attr_2_re = addr_hit[264] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[264] & reg_we & !reg_error; assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -34509,8 +34740,8 @@ module pinmux_reg_top ( assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign mio_pad_attr_3_re = addr_hit[259] & reg_re & !reg_error; - assign mio_pad_attr_3_we = addr_hit[259] & reg_we & !reg_error; + assign mio_pad_attr_3_re = addr_hit[265] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[265] & reg_we & !reg_error; assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -34531,8 +34762,8 @@ module pinmux_reg_top ( assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign mio_pad_attr_4_re = addr_hit[260] & reg_re & !reg_error; - assign mio_pad_attr_4_we = addr_hit[260] & reg_we & !reg_error; + assign mio_pad_attr_4_re = addr_hit[266] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[266] & reg_we & !reg_error; assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -34553,8 +34784,8 @@ module pinmux_reg_top ( assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign mio_pad_attr_5_re = addr_hit[261] & reg_re & !reg_error; - assign mio_pad_attr_5_we = addr_hit[261] & reg_we & !reg_error; + assign mio_pad_attr_5_re = addr_hit[267] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[267] & reg_we & !reg_error; assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -34575,8 +34806,8 @@ module pinmux_reg_top ( assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign mio_pad_attr_6_re = addr_hit[262] & reg_re & !reg_error; - assign mio_pad_attr_6_we = addr_hit[262] & reg_we & !reg_error; + assign mio_pad_attr_6_re = addr_hit[268] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[268] & reg_we & !reg_error; assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -34597,8 +34828,8 @@ module pinmux_reg_top ( assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign mio_pad_attr_7_re = addr_hit[263] & reg_re & !reg_error; - assign mio_pad_attr_7_we = addr_hit[263] & reg_we & !reg_error; + assign mio_pad_attr_7_re = addr_hit[269] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[269] & reg_we & !reg_error; assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -34619,8 +34850,8 @@ module pinmux_reg_top ( assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign mio_pad_attr_8_re = addr_hit[264] & reg_re & !reg_error; - assign mio_pad_attr_8_we = addr_hit[264] & reg_we & !reg_error; + assign mio_pad_attr_8_re = addr_hit[270] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[270] & reg_we & !reg_error; assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -34641,8 +34872,8 @@ module pinmux_reg_top ( assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign mio_pad_attr_9_re = addr_hit[265] & reg_re & !reg_error; - assign mio_pad_attr_9_we = addr_hit[265] & reg_we & !reg_error; + assign mio_pad_attr_9_re = addr_hit[271] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[271] & reg_we & !reg_error; assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -34663,8 +34894,8 @@ module pinmux_reg_top ( assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign mio_pad_attr_10_re = addr_hit[266] & reg_re & !reg_error; - assign mio_pad_attr_10_we = addr_hit[266] & reg_we & !reg_error; + assign mio_pad_attr_10_re = addr_hit[272] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[272] & reg_we & !reg_error; assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -34685,8 +34916,8 @@ module pinmux_reg_top ( assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign mio_pad_attr_11_re = addr_hit[267] & reg_re & !reg_error; - assign mio_pad_attr_11_we = addr_hit[267] & reg_we & !reg_error; + assign mio_pad_attr_11_re = addr_hit[273] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[273] & reg_we & !reg_error; assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -34707,8 +34938,8 @@ module pinmux_reg_top ( assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign mio_pad_attr_12_re = addr_hit[268] & reg_re & !reg_error; - assign mio_pad_attr_12_we = addr_hit[268] & reg_we & !reg_error; + assign mio_pad_attr_12_re = addr_hit[274] & reg_re & !reg_error; + assign mio_pad_attr_12_we = addr_hit[274] & reg_we & !reg_error; assign mio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -34729,8 +34960,8 @@ module pinmux_reg_top ( assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign mio_pad_attr_13_re = addr_hit[269] & reg_re & !reg_error; - assign mio_pad_attr_13_we = addr_hit[269] & reg_we & !reg_error; + assign mio_pad_attr_13_re = addr_hit[275] & reg_re & !reg_error; + assign mio_pad_attr_13_we = addr_hit[275] & reg_we & !reg_error; assign mio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -34751,8 +34982,8 @@ module pinmux_reg_top ( assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign mio_pad_attr_14_re = addr_hit[270] & reg_re & !reg_error; - assign mio_pad_attr_14_we = addr_hit[270] & reg_we & !reg_error; + assign mio_pad_attr_14_re = addr_hit[276] & reg_re & !reg_error; + assign mio_pad_attr_14_we = addr_hit[276] & reg_we & !reg_error; assign mio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -34773,8 +35004,8 @@ module pinmux_reg_top ( assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign mio_pad_attr_15_re = addr_hit[271] & reg_re & !reg_error; - assign mio_pad_attr_15_we = addr_hit[271] & reg_we & !reg_error; + assign mio_pad_attr_15_re = addr_hit[277] & reg_re & !reg_error; + assign mio_pad_attr_15_we = addr_hit[277] & reg_we & !reg_error; assign mio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -34795,8 +35026,8 @@ module pinmux_reg_top ( assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_attr_16_re = addr_hit[272] & reg_re & !reg_error; - assign mio_pad_attr_16_we = addr_hit[272] & reg_we & !reg_error; + assign mio_pad_attr_16_re = addr_hit[278] & reg_re & !reg_error; + assign mio_pad_attr_16_we = addr_hit[278] & reg_we & !reg_error; assign mio_pad_attr_16_invert_16_wd = reg_wdata[0]; @@ -34817,8 +35048,8 @@ module pinmux_reg_top ( assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; - assign mio_pad_attr_17_re = addr_hit[273] & reg_re & !reg_error; - assign mio_pad_attr_17_we = addr_hit[273] & reg_we & !reg_error; + assign mio_pad_attr_17_re = addr_hit[279] & reg_re & !reg_error; + assign mio_pad_attr_17_we = addr_hit[279] & reg_we & !reg_error; assign mio_pad_attr_17_invert_17_wd = reg_wdata[0]; @@ -34839,8 +35070,8 @@ module pinmux_reg_top ( assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; - assign mio_pad_attr_18_re = addr_hit[274] & reg_re & !reg_error; - assign mio_pad_attr_18_we = addr_hit[274] & reg_we & !reg_error; + assign mio_pad_attr_18_re = addr_hit[280] & reg_re & !reg_error; + assign mio_pad_attr_18_we = addr_hit[280] & reg_we & !reg_error; assign mio_pad_attr_18_invert_18_wd = reg_wdata[0]; @@ -34861,8 +35092,8 @@ module pinmux_reg_top ( assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; - assign mio_pad_attr_19_re = addr_hit[275] & reg_re & !reg_error; - assign mio_pad_attr_19_we = addr_hit[275] & reg_we & !reg_error; + assign mio_pad_attr_19_re = addr_hit[281] & reg_re & !reg_error; + assign mio_pad_attr_19_we = addr_hit[281] & reg_we & !reg_error; assign mio_pad_attr_19_invert_19_wd = reg_wdata[0]; @@ -34883,8 +35114,8 @@ module pinmux_reg_top ( assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; - assign mio_pad_attr_20_re = addr_hit[276] & reg_re & !reg_error; - assign mio_pad_attr_20_we = addr_hit[276] & reg_we & !reg_error; + assign mio_pad_attr_20_re = addr_hit[282] & reg_re & !reg_error; + assign mio_pad_attr_20_we = addr_hit[282] & reg_we & !reg_error; assign mio_pad_attr_20_invert_20_wd = reg_wdata[0]; @@ -34905,8 +35136,8 @@ module pinmux_reg_top ( assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; - assign mio_pad_attr_21_re = addr_hit[277] & reg_re & !reg_error; - assign mio_pad_attr_21_we = addr_hit[277] & reg_we & !reg_error; + assign mio_pad_attr_21_re = addr_hit[283] & reg_re & !reg_error; + assign mio_pad_attr_21_we = addr_hit[283] & reg_we & !reg_error; assign mio_pad_attr_21_invert_21_wd = reg_wdata[0]; @@ -34927,8 +35158,8 @@ module pinmux_reg_top ( assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; - assign mio_pad_attr_22_re = addr_hit[278] & reg_re & !reg_error; - assign mio_pad_attr_22_we = addr_hit[278] & reg_we & !reg_error; + assign mio_pad_attr_22_re = addr_hit[284] & reg_re & !reg_error; + assign mio_pad_attr_22_we = addr_hit[284] & reg_we & !reg_error; assign mio_pad_attr_22_invert_22_wd = reg_wdata[0]; @@ -34949,8 +35180,8 @@ module pinmux_reg_top ( assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; - assign mio_pad_attr_23_re = addr_hit[279] & reg_re & !reg_error; - assign mio_pad_attr_23_we = addr_hit[279] & reg_we & !reg_error; + assign mio_pad_attr_23_re = addr_hit[285] & reg_re & !reg_error; + assign mio_pad_attr_23_we = addr_hit[285] & reg_we & !reg_error; assign mio_pad_attr_23_invert_23_wd = reg_wdata[0]; @@ -34971,8 +35202,8 @@ module pinmux_reg_top ( assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; - assign mio_pad_attr_24_re = addr_hit[280] & reg_re & !reg_error; - assign mio_pad_attr_24_we = addr_hit[280] & reg_we & !reg_error; + assign mio_pad_attr_24_re = addr_hit[286] & reg_re & !reg_error; + assign mio_pad_attr_24_we = addr_hit[286] & reg_we & !reg_error; assign mio_pad_attr_24_invert_24_wd = reg_wdata[0]; @@ -34993,8 +35224,8 @@ module pinmux_reg_top ( assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; - assign mio_pad_attr_25_re = addr_hit[281] & reg_re & !reg_error; - assign mio_pad_attr_25_we = addr_hit[281] & reg_we & !reg_error; + assign mio_pad_attr_25_re = addr_hit[287] & reg_re & !reg_error; + assign mio_pad_attr_25_we = addr_hit[287] & reg_we & !reg_error; assign mio_pad_attr_25_invert_25_wd = reg_wdata[0]; @@ -35015,8 +35246,8 @@ module pinmux_reg_top ( assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; - assign mio_pad_attr_26_re = addr_hit[282] & reg_re & !reg_error; - assign mio_pad_attr_26_we = addr_hit[282] & reg_we & !reg_error; + assign mio_pad_attr_26_re = addr_hit[288] & reg_re & !reg_error; + assign mio_pad_attr_26_we = addr_hit[288] & reg_we & !reg_error; assign mio_pad_attr_26_invert_26_wd = reg_wdata[0]; @@ -35037,8 +35268,8 @@ module pinmux_reg_top ( assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; - assign mio_pad_attr_27_re = addr_hit[283] & reg_re & !reg_error; - assign mio_pad_attr_27_we = addr_hit[283] & reg_we & !reg_error; + assign mio_pad_attr_27_re = addr_hit[289] & reg_re & !reg_error; + assign mio_pad_attr_27_we = addr_hit[289] & reg_we & !reg_error; assign mio_pad_attr_27_invert_27_wd = reg_wdata[0]; @@ -35059,8 +35290,8 @@ module pinmux_reg_top ( assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; - assign mio_pad_attr_28_re = addr_hit[284] & reg_re & !reg_error; - assign mio_pad_attr_28_we = addr_hit[284] & reg_we & !reg_error; + assign mio_pad_attr_28_re = addr_hit[290] & reg_re & !reg_error; + assign mio_pad_attr_28_we = addr_hit[290] & reg_we & !reg_error; assign mio_pad_attr_28_invert_28_wd = reg_wdata[0]; @@ -35081,8 +35312,8 @@ module pinmux_reg_top ( assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; - assign mio_pad_attr_29_re = addr_hit[285] & reg_re & !reg_error; - assign mio_pad_attr_29_we = addr_hit[285] & reg_we & !reg_error; + assign mio_pad_attr_29_re = addr_hit[291] & reg_re & !reg_error; + assign mio_pad_attr_29_we = addr_hit[291] & reg_we & !reg_error; assign mio_pad_attr_29_invert_29_wd = reg_wdata[0]; @@ -35103,8 +35334,8 @@ module pinmux_reg_top ( assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; - assign mio_pad_attr_30_re = addr_hit[286] & reg_re & !reg_error; - assign mio_pad_attr_30_we = addr_hit[286] & reg_we & !reg_error; + assign mio_pad_attr_30_re = addr_hit[292] & reg_re & !reg_error; + assign mio_pad_attr_30_we = addr_hit[292] & reg_we & !reg_error; assign mio_pad_attr_30_invert_30_wd = reg_wdata[0]; @@ -35125,8 +35356,8 @@ module pinmux_reg_top ( assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; - assign mio_pad_attr_31_re = addr_hit[287] & reg_re & !reg_error; - assign mio_pad_attr_31_we = addr_hit[287] & reg_we & !reg_error; + assign mio_pad_attr_31_re = addr_hit[293] & reg_re & !reg_error; + assign mio_pad_attr_31_we = addr_hit[293] & reg_we & !reg_error; assign mio_pad_attr_31_invert_31_wd = reg_wdata[0]; @@ -35147,8 +35378,8 @@ module pinmux_reg_top ( assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; - assign mio_pad_attr_32_re = addr_hit[288] & reg_re & !reg_error; - assign mio_pad_attr_32_we = addr_hit[288] & reg_we & !reg_error; + assign mio_pad_attr_32_re = addr_hit[294] & reg_re & !reg_error; + assign mio_pad_attr_32_we = addr_hit[294] & reg_we & !reg_error; assign mio_pad_attr_32_invert_32_wd = reg_wdata[0]; @@ -35169,8 +35400,8 @@ module pinmux_reg_top ( assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; - assign mio_pad_attr_33_re = addr_hit[289] & reg_re & !reg_error; - assign mio_pad_attr_33_we = addr_hit[289] & reg_we & !reg_error; + assign mio_pad_attr_33_re = addr_hit[295] & reg_re & !reg_error; + assign mio_pad_attr_33_we = addr_hit[295] & reg_we & !reg_error; assign mio_pad_attr_33_invert_33_wd = reg_wdata[0]; @@ -35191,8 +35422,8 @@ module pinmux_reg_top ( assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; - assign mio_pad_attr_34_re = addr_hit[290] & reg_re & !reg_error; - assign mio_pad_attr_34_we = addr_hit[290] & reg_we & !reg_error; + assign mio_pad_attr_34_re = addr_hit[296] & reg_re & !reg_error; + assign mio_pad_attr_34_we = addr_hit[296] & reg_we & !reg_error; assign mio_pad_attr_34_invert_34_wd = reg_wdata[0]; @@ -35213,8 +35444,8 @@ module pinmux_reg_top ( assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; - assign mio_pad_attr_35_re = addr_hit[291] & reg_re & !reg_error; - assign mio_pad_attr_35_we = addr_hit[291] & reg_we & !reg_error; + assign mio_pad_attr_35_re = addr_hit[297] & reg_re & !reg_error; + assign mio_pad_attr_35_we = addr_hit[297] & reg_we & !reg_error; assign mio_pad_attr_35_invert_35_wd = reg_wdata[0]; @@ -35235,8 +35466,8 @@ module pinmux_reg_top ( assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; - assign mio_pad_attr_36_re = addr_hit[292] & reg_re & !reg_error; - assign mio_pad_attr_36_we = addr_hit[292] & reg_we & !reg_error; + assign mio_pad_attr_36_re = addr_hit[298] & reg_re & !reg_error; + assign mio_pad_attr_36_we = addr_hit[298] & reg_we & !reg_error; assign mio_pad_attr_36_invert_36_wd = reg_wdata[0]; @@ -35257,8 +35488,8 @@ module pinmux_reg_top ( assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; - assign mio_pad_attr_37_re = addr_hit[293] & reg_re & !reg_error; - assign mio_pad_attr_37_we = addr_hit[293] & reg_we & !reg_error; + assign mio_pad_attr_37_re = addr_hit[299] & reg_re & !reg_error; + assign mio_pad_attr_37_we = addr_hit[299] & reg_we & !reg_error; assign mio_pad_attr_37_invert_37_wd = reg_wdata[0]; @@ -35279,8 +35510,8 @@ module pinmux_reg_top ( assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; - assign mio_pad_attr_38_re = addr_hit[294] & reg_re & !reg_error; - assign mio_pad_attr_38_we = addr_hit[294] & reg_we & !reg_error; + assign mio_pad_attr_38_re = addr_hit[300] & reg_re & !reg_error; + assign mio_pad_attr_38_we = addr_hit[300] & reg_we & !reg_error; assign mio_pad_attr_38_invert_38_wd = reg_wdata[0]; @@ -35301,8 +35532,8 @@ module pinmux_reg_top ( assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; - assign mio_pad_attr_39_re = addr_hit[295] & reg_re & !reg_error; - assign mio_pad_attr_39_we = addr_hit[295] & reg_we & !reg_error; + assign mio_pad_attr_39_re = addr_hit[301] & reg_re & !reg_error; + assign mio_pad_attr_39_we = addr_hit[301] & reg_we & !reg_error; assign mio_pad_attr_39_invert_39_wd = reg_wdata[0]; @@ -35323,8 +35554,8 @@ module pinmux_reg_top ( assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; - assign mio_pad_attr_40_re = addr_hit[296] & reg_re & !reg_error; - assign mio_pad_attr_40_we = addr_hit[296] & reg_we & !reg_error; + assign mio_pad_attr_40_re = addr_hit[302] & reg_re & !reg_error; + assign mio_pad_attr_40_we = addr_hit[302] & reg_we & !reg_error; assign mio_pad_attr_40_invert_40_wd = reg_wdata[0]; @@ -35345,8 +35576,8 @@ module pinmux_reg_top ( assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; - assign mio_pad_attr_41_re = addr_hit[297] & reg_re & !reg_error; - assign mio_pad_attr_41_we = addr_hit[297] & reg_we & !reg_error; + assign mio_pad_attr_41_re = addr_hit[303] & reg_re & !reg_error; + assign mio_pad_attr_41_we = addr_hit[303] & reg_we & !reg_error; assign mio_pad_attr_41_invert_41_wd = reg_wdata[0]; @@ -35367,8 +35598,8 @@ module pinmux_reg_top ( assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; - assign mio_pad_attr_42_re = addr_hit[298] & reg_re & !reg_error; - assign mio_pad_attr_42_we = addr_hit[298] & reg_we & !reg_error; + assign mio_pad_attr_42_re = addr_hit[304] & reg_re & !reg_error; + assign mio_pad_attr_42_we = addr_hit[304] & reg_we & !reg_error; assign mio_pad_attr_42_invert_42_wd = reg_wdata[0]; @@ -35389,8 +35620,8 @@ module pinmux_reg_top ( assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; - assign mio_pad_attr_43_re = addr_hit[299] & reg_re & !reg_error; - assign mio_pad_attr_43_we = addr_hit[299] & reg_we & !reg_error; + assign mio_pad_attr_43_re = addr_hit[305] & reg_re & !reg_error; + assign mio_pad_attr_43_we = addr_hit[305] & reg_we & !reg_error; assign mio_pad_attr_43_invert_43_wd = reg_wdata[0]; @@ -35411,8 +35642,8 @@ module pinmux_reg_top ( assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; - assign mio_pad_attr_44_re = addr_hit[300] & reg_re & !reg_error; - assign mio_pad_attr_44_we = addr_hit[300] & reg_we & !reg_error; + assign mio_pad_attr_44_re = addr_hit[306] & reg_re & !reg_error; + assign mio_pad_attr_44_we = addr_hit[306] & reg_we & !reg_error; assign mio_pad_attr_44_invert_44_wd = reg_wdata[0]; @@ -35433,8 +35664,8 @@ module pinmux_reg_top ( assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; - assign mio_pad_attr_45_re = addr_hit[301] & reg_re & !reg_error; - assign mio_pad_attr_45_we = addr_hit[301] & reg_we & !reg_error; + assign mio_pad_attr_45_re = addr_hit[307] & reg_re & !reg_error; + assign mio_pad_attr_45_we = addr_hit[307] & reg_we & !reg_error; assign mio_pad_attr_45_invert_45_wd = reg_wdata[0]; @@ -35455,8 +35686,8 @@ module pinmux_reg_top ( assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; - assign mio_pad_attr_46_re = addr_hit[302] & reg_re & !reg_error; - assign mio_pad_attr_46_we = addr_hit[302] & reg_we & !reg_error; + assign mio_pad_attr_46_re = addr_hit[308] & reg_re & !reg_error; + assign mio_pad_attr_46_we = addr_hit[308] & reg_we & !reg_error; assign mio_pad_attr_46_invert_46_wd = reg_wdata[0]; @@ -35477,56 +35708,56 @@ module pinmux_reg_top ( assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; - assign dio_pad_attr_regwen_0_we = addr_hit[303] & reg_we & !reg_error; + assign dio_pad_attr_regwen_0_we = addr_hit[309] & reg_we & !reg_error; assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_1_we = addr_hit[304] & reg_we & !reg_error; + assign dio_pad_attr_regwen_1_we = addr_hit[310] & reg_we & !reg_error; assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_2_we = addr_hit[305] & reg_we & !reg_error; + assign dio_pad_attr_regwen_2_we = addr_hit[311] & reg_we & !reg_error; assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_3_we = addr_hit[306] & reg_we & !reg_error; + assign dio_pad_attr_regwen_3_we = addr_hit[312] & reg_we & !reg_error; assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_4_we = addr_hit[307] & reg_we & !reg_error; + assign dio_pad_attr_regwen_4_we = addr_hit[313] & reg_we & !reg_error; assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_5_we = addr_hit[308] & reg_we & !reg_error; + assign dio_pad_attr_regwen_5_we = addr_hit[314] & reg_we & !reg_error; assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_6_we = addr_hit[309] & reg_we & !reg_error; + assign dio_pad_attr_regwen_6_we = addr_hit[315] & reg_we & !reg_error; assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_7_we = addr_hit[310] & reg_we & !reg_error; + assign dio_pad_attr_regwen_7_we = addr_hit[316] & reg_we & !reg_error; assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_8_we = addr_hit[311] & reg_we & !reg_error; + assign dio_pad_attr_regwen_8_we = addr_hit[317] & reg_we & !reg_error; assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_9_we = addr_hit[312] & reg_we & !reg_error; + assign dio_pad_attr_regwen_9_we = addr_hit[318] & reg_we & !reg_error; assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_10_we = addr_hit[313] & reg_we & !reg_error; + assign dio_pad_attr_regwen_10_we = addr_hit[319] & reg_we & !reg_error; assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_11_we = addr_hit[314] & reg_we & !reg_error; + assign dio_pad_attr_regwen_11_we = addr_hit[320] & reg_we & !reg_error; assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_12_we = addr_hit[315] & reg_we & !reg_error; + assign dio_pad_attr_regwen_12_we = addr_hit[321] & reg_we & !reg_error; assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_13_we = addr_hit[316] & reg_we & !reg_error; + assign dio_pad_attr_regwen_13_we = addr_hit[322] & reg_we & !reg_error; assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_14_we = addr_hit[317] & reg_we & !reg_error; + assign dio_pad_attr_regwen_14_we = addr_hit[323] & reg_we & !reg_error; assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_15_we = addr_hit[318] & reg_we & !reg_error; + assign dio_pad_attr_regwen_15_we = addr_hit[324] & reg_we & !reg_error; assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign dio_pad_attr_0_re = addr_hit[319] & reg_re & !reg_error; - assign dio_pad_attr_0_we = addr_hit[319] & reg_we & !reg_error; + assign dio_pad_attr_0_re = addr_hit[325] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[325] & reg_we & !reg_error; assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -35547,8 +35778,8 @@ module pinmux_reg_top ( assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign dio_pad_attr_1_re = addr_hit[320] & reg_re & !reg_error; - assign dio_pad_attr_1_we = addr_hit[320] & reg_we & !reg_error; + assign dio_pad_attr_1_re = addr_hit[326] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[326] & reg_we & !reg_error; assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -35569,8 +35800,8 @@ module pinmux_reg_top ( assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign dio_pad_attr_2_re = addr_hit[321] & reg_re & !reg_error; - assign dio_pad_attr_2_we = addr_hit[321] & reg_we & !reg_error; + assign dio_pad_attr_2_re = addr_hit[327] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[327] & reg_we & !reg_error; assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -35591,8 +35822,8 @@ module pinmux_reg_top ( assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign dio_pad_attr_3_re = addr_hit[322] & reg_re & !reg_error; - assign dio_pad_attr_3_we = addr_hit[322] & reg_we & !reg_error; + assign dio_pad_attr_3_re = addr_hit[328] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[328] & reg_we & !reg_error; assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -35613,8 +35844,8 @@ module pinmux_reg_top ( assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign dio_pad_attr_4_re = addr_hit[323] & reg_re & !reg_error; - assign dio_pad_attr_4_we = addr_hit[323] & reg_we & !reg_error; + assign dio_pad_attr_4_re = addr_hit[329] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[329] & reg_we & !reg_error; assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -35635,8 +35866,8 @@ module pinmux_reg_top ( assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign dio_pad_attr_5_re = addr_hit[324] & reg_re & !reg_error; - assign dio_pad_attr_5_we = addr_hit[324] & reg_we & !reg_error; + assign dio_pad_attr_5_re = addr_hit[330] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[330] & reg_we & !reg_error; assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -35657,8 +35888,8 @@ module pinmux_reg_top ( assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign dio_pad_attr_6_re = addr_hit[325] & reg_re & !reg_error; - assign dio_pad_attr_6_we = addr_hit[325] & reg_we & !reg_error; + assign dio_pad_attr_6_re = addr_hit[331] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[331] & reg_we & !reg_error; assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -35679,8 +35910,8 @@ module pinmux_reg_top ( assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign dio_pad_attr_7_re = addr_hit[326] & reg_re & !reg_error; - assign dio_pad_attr_7_we = addr_hit[326] & reg_we & !reg_error; + assign dio_pad_attr_7_re = addr_hit[332] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[332] & reg_we & !reg_error; assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -35701,8 +35932,8 @@ module pinmux_reg_top ( assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign dio_pad_attr_8_re = addr_hit[327] & reg_re & !reg_error; - assign dio_pad_attr_8_we = addr_hit[327] & reg_we & !reg_error; + assign dio_pad_attr_8_re = addr_hit[333] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[333] & reg_we & !reg_error; assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -35723,8 +35954,8 @@ module pinmux_reg_top ( assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign dio_pad_attr_9_re = addr_hit[328] & reg_re & !reg_error; - assign dio_pad_attr_9_we = addr_hit[328] & reg_we & !reg_error; + assign dio_pad_attr_9_re = addr_hit[334] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[334] & reg_we & !reg_error; assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -35745,8 +35976,8 @@ module pinmux_reg_top ( assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign dio_pad_attr_10_re = addr_hit[329] & reg_re & !reg_error; - assign dio_pad_attr_10_we = addr_hit[329] & reg_we & !reg_error; + assign dio_pad_attr_10_re = addr_hit[335] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[335] & reg_we & !reg_error; assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -35767,8 +35998,8 @@ module pinmux_reg_top ( assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign dio_pad_attr_11_re = addr_hit[330] & reg_re & !reg_error; - assign dio_pad_attr_11_we = addr_hit[330] & reg_we & !reg_error; + assign dio_pad_attr_11_re = addr_hit[336] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[336] & reg_we & !reg_error; assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -35789,8 +36020,8 @@ module pinmux_reg_top ( assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign dio_pad_attr_12_re = addr_hit[331] & reg_re & !reg_error; - assign dio_pad_attr_12_we = addr_hit[331] & reg_we & !reg_error; + assign dio_pad_attr_12_re = addr_hit[337] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[337] & reg_we & !reg_error; assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -35811,8 +36042,8 @@ module pinmux_reg_top ( assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign dio_pad_attr_13_re = addr_hit[332] & reg_re & !reg_error; - assign dio_pad_attr_13_we = addr_hit[332] & reg_we & !reg_error; + assign dio_pad_attr_13_re = addr_hit[338] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[338] & reg_we & !reg_error; assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -35833,8 +36064,8 @@ module pinmux_reg_top ( assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign dio_pad_attr_14_re = addr_hit[333] & reg_re & !reg_error; - assign dio_pad_attr_14_we = addr_hit[333] & reg_we & !reg_error; + assign dio_pad_attr_14_re = addr_hit[339] & reg_re & !reg_error; + assign dio_pad_attr_14_we = addr_hit[339] & reg_we & !reg_error; assign dio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -35855,8 +36086,8 @@ module pinmux_reg_top ( assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign dio_pad_attr_15_re = addr_hit[334] & reg_re & !reg_error; - assign dio_pad_attr_15_we = addr_hit[334] & reg_we & !reg_error; + assign dio_pad_attr_15_re = addr_hit[340] & reg_re & !reg_error; + assign dio_pad_attr_15_we = addr_hit[340] & reg_we & !reg_error; assign dio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -35877,7 +36108,7 @@ module pinmux_reg_top ( assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_sleep_status_0_we = addr_hit[335] & reg_we & !reg_error; + assign mio_pad_sleep_status_0_we = addr_hit[341] & reg_we & !reg_error; assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; @@ -35942,7 +36173,7 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; - assign mio_pad_sleep_status_1_we = addr_hit[336] & reg_we & !reg_error; + assign mio_pad_sleep_status_1_we = addr_hit[342] & reg_we & !reg_error; assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; @@ -35973,430 +36204,430 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; - assign mio_pad_sleep_regwen_0_we = addr_hit[337] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_0_we = addr_hit[343] & reg_we & !reg_error; assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_1_we = addr_hit[338] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_1_we = addr_hit[344] & reg_we & !reg_error; assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_2_we = addr_hit[339] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_2_we = addr_hit[345] & reg_we & !reg_error; assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_3_we = addr_hit[340] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_3_we = addr_hit[346] & reg_we & !reg_error; assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_4_we = addr_hit[341] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_4_we = addr_hit[347] & reg_we & !reg_error; assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_5_we = addr_hit[342] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_5_we = addr_hit[348] & reg_we & !reg_error; assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_6_we = addr_hit[343] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_6_we = addr_hit[349] & reg_we & !reg_error; assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_7_we = addr_hit[344] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_7_we = addr_hit[350] & reg_we & !reg_error; assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_8_we = addr_hit[345] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_8_we = addr_hit[351] & reg_we & !reg_error; assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_9_we = addr_hit[346] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_9_we = addr_hit[352] & reg_we & !reg_error; assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_10_we = addr_hit[347] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_10_we = addr_hit[353] & reg_we & !reg_error; assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_11_we = addr_hit[348] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_11_we = addr_hit[354] & reg_we & !reg_error; assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_12_we = addr_hit[349] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_12_we = addr_hit[355] & reg_we & !reg_error; assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_13_we = addr_hit[350] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_13_we = addr_hit[356] & reg_we & !reg_error; assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_14_we = addr_hit[351] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_14_we = addr_hit[357] & reg_we & !reg_error; assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_15_we = addr_hit[352] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_15_we = addr_hit[358] & reg_we & !reg_error; assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_16_we = addr_hit[353] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_16_we = addr_hit[359] & reg_we & !reg_error; assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_17_we = addr_hit[354] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_17_we = addr_hit[360] & reg_we & !reg_error; assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_18_we = addr_hit[355] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_18_we = addr_hit[361] & reg_we & !reg_error; assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_19_we = addr_hit[356] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_19_we = addr_hit[362] & reg_we & !reg_error; assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_20_we = addr_hit[357] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_20_we = addr_hit[363] & reg_we & !reg_error; assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_21_we = addr_hit[358] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_21_we = addr_hit[364] & reg_we & !reg_error; assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_22_we = addr_hit[359] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_22_we = addr_hit[365] & reg_we & !reg_error; assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_23_we = addr_hit[360] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_23_we = addr_hit[366] & reg_we & !reg_error; assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_24_we = addr_hit[361] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_24_we = addr_hit[367] & reg_we & !reg_error; assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_25_we = addr_hit[362] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_25_we = addr_hit[368] & reg_we & !reg_error; assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_26_we = addr_hit[363] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_26_we = addr_hit[369] & reg_we & !reg_error; assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_27_we = addr_hit[364] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_27_we = addr_hit[370] & reg_we & !reg_error; assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_28_we = addr_hit[365] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_28_we = addr_hit[371] & reg_we & !reg_error; assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_29_we = addr_hit[366] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_29_we = addr_hit[372] & reg_we & !reg_error; assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_30_we = addr_hit[367] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_30_we = addr_hit[373] & reg_we & !reg_error; assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_31_we = addr_hit[368] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_31_we = addr_hit[374] & reg_we & !reg_error; assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_32_we = addr_hit[369] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_32_we = addr_hit[375] & reg_we & !reg_error; assign mio_pad_sleep_regwen_32_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_33_we = addr_hit[370] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_33_we = addr_hit[376] & reg_we & !reg_error; assign mio_pad_sleep_regwen_33_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_34_we = addr_hit[371] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_34_we = addr_hit[377] & reg_we & !reg_error; assign mio_pad_sleep_regwen_34_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_35_we = addr_hit[372] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_35_we = addr_hit[378] & reg_we & !reg_error; assign mio_pad_sleep_regwen_35_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_36_we = addr_hit[373] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_36_we = addr_hit[379] & reg_we & !reg_error; assign mio_pad_sleep_regwen_36_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_37_we = addr_hit[374] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_37_we = addr_hit[380] & reg_we & !reg_error; assign mio_pad_sleep_regwen_37_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_38_we = addr_hit[375] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_38_we = addr_hit[381] & reg_we & !reg_error; assign mio_pad_sleep_regwen_38_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_39_we = addr_hit[376] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_39_we = addr_hit[382] & reg_we & !reg_error; assign mio_pad_sleep_regwen_39_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_40_we = addr_hit[377] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_40_we = addr_hit[383] & reg_we & !reg_error; assign mio_pad_sleep_regwen_40_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_41_we = addr_hit[378] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_41_we = addr_hit[384] & reg_we & !reg_error; assign mio_pad_sleep_regwen_41_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_42_we = addr_hit[379] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_42_we = addr_hit[385] & reg_we & !reg_error; assign mio_pad_sleep_regwen_42_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_43_we = addr_hit[380] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_43_we = addr_hit[386] & reg_we & !reg_error; assign mio_pad_sleep_regwen_43_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_44_we = addr_hit[381] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_44_we = addr_hit[387] & reg_we & !reg_error; assign mio_pad_sleep_regwen_44_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_45_we = addr_hit[382] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_45_we = addr_hit[388] & reg_we & !reg_error; assign mio_pad_sleep_regwen_45_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_46_we = addr_hit[383] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_46_we = addr_hit[389] & reg_we & !reg_error; assign mio_pad_sleep_regwen_46_wd = reg_wdata[0]; - assign mio_pad_sleep_en_0_we = addr_hit[384] & reg_we & !reg_error; + assign mio_pad_sleep_en_0_we = addr_hit[390] & reg_we & !reg_error; assign mio_pad_sleep_en_0_wd = reg_wdata[0]; - assign mio_pad_sleep_en_1_we = addr_hit[385] & reg_we & !reg_error; + assign mio_pad_sleep_en_1_we = addr_hit[391] & reg_we & !reg_error; assign mio_pad_sleep_en_1_wd = reg_wdata[0]; - assign mio_pad_sleep_en_2_we = addr_hit[386] & reg_we & !reg_error; + assign mio_pad_sleep_en_2_we = addr_hit[392] & reg_we & !reg_error; assign mio_pad_sleep_en_2_wd = reg_wdata[0]; - assign mio_pad_sleep_en_3_we = addr_hit[387] & reg_we & !reg_error; + assign mio_pad_sleep_en_3_we = addr_hit[393] & reg_we & !reg_error; assign mio_pad_sleep_en_3_wd = reg_wdata[0]; - assign mio_pad_sleep_en_4_we = addr_hit[388] & reg_we & !reg_error; + assign mio_pad_sleep_en_4_we = addr_hit[394] & reg_we & !reg_error; assign mio_pad_sleep_en_4_wd = reg_wdata[0]; - assign mio_pad_sleep_en_5_we = addr_hit[389] & reg_we & !reg_error; + assign mio_pad_sleep_en_5_we = addr_hit[395] & reg_we & !reg_error; assign mio_pad_sleep_en_5_wd = reg_wdata[0]; - assign mio_pad_sleep_en_6_we = addr_hit[390] & reg_we & !reg_error; + assign mio_pad_sleep_en_6_we = addr_hit[396] & reg_we & !reg_error; assign mio_pad_sleep_en_6_wd = reg_wdata[0]; - assign mio_pad_sleep_en_7_we = addr_hit[391] & reg_we & !reg_error; + assign mio_pad_sleep_en_7_we = addr_hit[397] & reg_we & !reg_error; assign mio_pad_sleep_en_7_wd = reg_wdata[0]; - assign mio_pad_sleep_en_8_we = addr_hit[392] & reg_we & !reg_error; + assign mio_pad_sleep_en_8_we = addr_hit[398] & reg_we & !reg_error; assign mio_pad_sleep_en_8_wd = reg_wdata[0]; - assign mio_pad_sleep_en_9_we = addr_hit[393] & reg_we & !reg_error; + assign mio_pad_sleep_en_9_we = addr_hit[399] & reg_we & !reg_error; assign mio_pad_sleep_en_9_wd = reg_wdata[0]; - assign mio_pad_sleep_en_10_we = addr_hit[394] & reg_we & !reg_error; + assign mio_pad_sleep_en_10_we = addr_hit[400] & reg_we & !reg_error; assign mio_pad_sleep_en_10_wd = reg_wdata[0]; - assign mio_pad_sleep_en_11_we = addr_hit[395] & reg_we & !reg_error; + assign mio_pad_sleep_en_11_we = addr_hit[401] & reg_we & !reg_error; assign mio_pad_sleep_en_11_wd = reg_wdata[0]; - assign mio_pad_sleep_en_12_we = addr_hit[396] & reg_we & !reg_error; + assign mio_pad_sleep_en_12_we = addr_hit[402] & reg_we & !reg_error; assign mio_pad_sleep_en_12_wd = reg_wdata[0]; - assign mio_pad_sleep_en_13_we = addr_hit[397] & reg_we & !reg_error; + assign mio_pad_sleep_en_13_we = addr_hit[403] & reg_we & !reg_error; assign mio_pad_sleep_en_13_wd = reg_wdata[0]; - assign mio_pad_sleep_en_14_we = addr_hit[398] & reg_we & !reg_error; + assign mio_pad_sleep_en_14_we = addr_hit[404] & reg_we & !reg_error; assign mio_pad_sleep_en_14_wd = reg_wdata[0]; - assign mio_pad_sleep_en_15_we = addr_hit[399] & reg_we & !reg_error; + assign mio_pad_sleep_en_15_we = addr_hit[405] & reg_we & !reg_error; assign mio_pad_sleep_en_15_wd = reg_wdata[0]; - assign mio_pad_sleep_en_16_we = addr_hit[400] & reg_we & !reg_error; + assign mio_pad_sleep_en_16_we = addr_hit[406] & reg_we & !reg_error; assign mio_pad_sleep_en_16_wd = reg_wdata[0]; - assign mio_pad_sleep_en_17_we = addr_hit[401] & reg_we & !reg_error; + assign mio_pad_sleep_en_17_we = addr_hit[407] & reg_we & !reg_error; assign mio_pad_sleep_en_17_wd = reg_wdata[0]; - assign mio_pad_sleep_en_18_we = addr_hit[402] & reg_we & !reg_error; + assign mio_pad_sleep_en_18_we = addr_hit[408] & reg_we & !reg_error; assign mio_pad_sleep_en_18_wd = reg_wdata[0]; - assign mio_pad_sleep_en_19_we = addr_hit[403] & reg_we & !reg_error; + assign mio_pad_sleep_en_19_we = addr_hit[409] & reg_we & !reg_error; assign mio_pad_sleep_en_19_wd = reg_wdata[0]; - assign mio_pad_sleep_en_20_we = addr_hit[404] & reg_we & !reg_error; + assign mio_pad_sleep_en_20_we = addr_hit[410] & reg_we & !reg_error; assign mio_pad_sleep_en_20_wd = reg_wdata[0]; - assign mio_pad_sleep_en_21_we = addr_hit[405] & reg_we & !reg_error; + assign mio_pad_sleep_en_21_we = addr_hit[411] & reg_we & !reg_error; assign mio_pad_sleep_en_21_wd = reg_wdata[0]; - assign mio_pad_sleep_en_22_we = addr_hit[406] & reg_we & !reg_error; + assign mio_pad_sleep_en_22_we = addr_hit[412] & reg_we & !reg_error; assign mio_pad_sleep_en_22_wd = reg_wdata[0]; - assign mio_pad_sleep_en_23_we = addr_hit[407] & reg_we & !reg_error; + assign mio_pad_sleep_en_23_we = addr_hit[413] & reg_we & !reg_error; assign mio_pad_sleep_en_23_wd = reg_wdata[0]; - assign mio_pad_sleep_en_24_we = addr_hit[408] & reg_we & !reg_error; + assign mio_pad_sleep_en_24_we = addr_hit[414] & reg_we & !reg_error; assign mio_pad_sleep_en_24_wd = reg_wdata[0]; - assign mio_pad_sleep_en_25_we = addr_hit[409] & reg_we & !reg_error; + assign mio_pad_sleep_en_25_we = addr_hit[415] & reg_we & !reg_error; assign mio_pad_sleep_en_25_wd = reg_wdata[0]; - assign mio_pad_sleep_en_26_we = addr_hit[410] & reg_we & !reg_error; + assign mio_pad_sleep_en_26_we = addr_hit[416] & reg_we & !reg_error; assign mio_pad_sleep_en_26_wd = reg_wdata[0]; - assign mio_pad_sleep_en_27_we = addr_hit[411] & reg_we & !reg_error; + assign mio_pad_sleep_en_27_we = addr_hit[417] & reg_we & !reg_error; assign mio_pad_sleep_en_27_wd = reg_wdata[0]; - assign mio_pad_sleep_en_28_we = addr_hit[412] & reg_we & !reg_error; + assign mio_pad_sleep_en_28_we = addr_hit[418] & reg_we & !reg_error; assign mio_pad_sleep_en_28_wd = reg_wdata[0]; - assign mio_pad_sleep_en_29_we = addr_hit[413] & reg_we & !reg_error; + assign mio_pad_sleep_en_29_we = addr_hit[419] & reg_we & !reg_error; assign mio_pad_sleep_en_29_wd = reg_wdata[0]; - assign mio_pad_sleep_en_30_we = addr_hit[414] & reg_we & !reg_error; + assign mio_pad_sleep_en_30_we = addr_hit[420] & reg_we & !reg_error; assign mio_pad_sleep_en_30_wd = reg_wdata[0]; - assign mio_pad_sleep_en_31_we = addr_hit[415] & reg_we & !reg_error; + assign mio_pad_sleep_en_31_we = addr_hit[421] & reg_we & !reg_error; assign mio_pad_sleep_en_31_wd = reg_wdata[0]; - assign mio_pad_sleep_en_32_we = addr_hit[416] & reg_we & !reg_error; + assign mio_pad_sleep_en_32_we = addr_hit[422] & reg_we & !reg_error; assign mio_pad_sleep_en_32_wd = reg_wdata[0]; - assign mio_pad_sleep_en_33_we = addr_hit[417] & reg_we & !reg_error; + assign mio_pad_sleep_en_33_we = addr_hit[423] & reg_we & !reg_error; assign mio_pad_sleep_en_33_wd = reg_wdata[0]; - assign mio_pad_sleep_en_34_we = addr_hit[418] & reg_we & !reg_error; + assign mio_pad_sleep_en_34_we = addr_hit[424] & reg_we & !reg_error; assign mio_pad_sleep_en_34_wd = reg_wdata[0]; - assign mio_pad_sleep_en_35_we = addr_hit[419] & reg_we & !reg_error; + assign mio_pad_sleep_en_35_we = addr_hit[425] & reg_we & !reg_error; assign mio_pad_sleep_en_35_wd = reg_wdata[0]; - assign mio_pad_sleep_en_36_we = addr_hit[420] & reg_we & !reg_error; + assign mio_pad_sleep_en_36_we = addr_hit[426] & reg_we & !reg_error; assign mio_pad_sleep_en_36_wd = reg_wdata[0]; - assign mio_pad_sleep_en_37_we = addr_hit[421] & reg_we & !reg_error; + assign mio_pad_sleep_en_37_we = addr_hit[427] & reg_we & !reg_error; assign mio_pad_sleep_en_37_wd = reg_wdata[0]; - assign mio_pad_sleep_en_38_we = addr_hit[422] & reg_we & !reg_error; + assign mio_pad_sleep_en_38_we = addr_hit[428] & reg_we & !reg_error; assign mio_pad_sleep_en_38_wd = reg_wdata[0]; - assign mio_pad_sleep_en_39_we = addr_hit[423] & reg_we & !reg_error; + assign mio_pad_sleep_en_39_we = addr_hit[429] & reg_we & !reg_error; assign mio_pad_sleep_en_39_wd = reg_wdata[0]; - assign mio_pad_sleep_en_40_we = addr_hit[424] & reg_we & !reg_error; + assign mio_pad_sleep_en_40_we = addr_hit[430] & reg_we & !reg_error; assign mio_pad_sleep_en_40_wd = reg_wdata[0]; - assign mio_pad_sleep_en_41_we = addr_hit[425] & reg_we & !reg_error; + assign mio_pad_sleep_en_41_we = addr_hit[431] & reg_we & !reg_error; assign mio_pad_sleep_en_41_wd = reg_wdata[0]; - assign mio_pad_sleep_en_42_we = addr_hit[426] & reg_we & !reg_error; + assign mio_pad_sleep_en_42_we = addr_hit[432] & reg_we & !reg_error; assign mio_pad_sleep_en_42_wd = reg_wdata[0]; - assign mio_pad_sleep_en_43_we = addr_hit[427] & reg_we & !reg_error; + assign mio_pad_sleep_en_43_we = addr_hit[433] & reg_we & !reg_error; assign mio_pad_sleep_en_43_wd = reg_wdata[0]; - assign mio_pad_sleep_en_44_we = addr_hit[428] & reg_we & !reg_error; + assign mio_pad_sleep_en_44_we = addr_hit[434] & reg_we & !reg_error; assign mio_pad_sleep_en_44_wd = reg_wdata[0]; - assign mio_pad_sleep_en_45_we = addr_hit[429] & reg_we & !reg_error; + assign mio_pad_sleep_en_45_we = addr_hit[435] & reg_we & !reg_error; assign mio_pad_sleep_en_45_wd = reg_wdata[0]; - assign mio_pad_sleep_en_46_we = addr_hit[430] & reg_we & !reg_error; + assign mio_pad_sleep_en_46_we = addr_hit[436] & reg_we & !reg_error; assign mio_pad_sleep_en_46_wd = reg_wdata[0]; - assign mio_pad_sleep_mode_0_we = addr_hit[431] & reg_we & !reg_error; + assign mio_pad_sleep_mode_0_we = addr_hit[437] & reg_we & !reg_error; assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_1_we = addr_hit[432] & reg_we & !reg_error; + assign mio_pad_sleep_mode_1_we = addr_hit[438] & reg_we & !reg_error; assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_2_we = addr_hit[433] & reg_we & !reg_error; + assign mio_pad_sleep_mode_2_we = addr_hit[439] & reg_we & !reg_error; assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_3_we = addr_hit[434] & reg_we & !reg_error; + assign mio_pad_sleep_mode_3_we = addr_hit[440] & reg_we & !reg_error; assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_4_we = addr_hit[435] & reg_we & !reg_error; + assign mio_pad_sleep_mode_4_we = addr_hit[441] & reg_we & !reg_error; assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_5_we = addr_hit[436] & reg_we & !reg_error; + assign mio_pad_sleep_mode_5_we = addr_hit[442] & reg_we & !reg_error; assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_6_we = addr_hit[437] & reg_we & !reg_error; + assign mio_pad_sleep_mode_6_we = addr_hit[443] & reg_we & !reg_error; assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_7_we = addr_hit[438] & reg_we & !reg_error; + assign mio_pad_sleep_mode_7_we = addr_hit[444] & reg_we & !reg_error; assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_8_we = addr_hit[439] & reg_we & !reg_error; + assign mio_pad_sleep_mode_8_we = addr_hit[445] & reg_we & !reg_error; assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_9_we = addr_hit[440] & reg_we & !reg_error; + assign mio_pad_sleep_mode_9_we = addr_hit[446] & reg_we & !reg_error; assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_10_we = addr_hit[441] & reg_we & !reg_error; + assign mio_pad_sleep_mode_10_we = addr_hit[447] & reg_we & !reg_error; assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_11_we = addr_hit[442] & reg_we & !reg_error; + assign mio_pad_sleep_mode_11_we = addr_hit[448] & reg_we & !reg_error; assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_12_we = addr_hit[443] & reg_we & !reg_error; + assign mio_pad_sleep_mode_12_we = addr_hit[449] & reg_we & !reg_error; assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_13_we = addr_hit[444] & reg_we & !reg_error; + assign mio_pad_sleep_mode_13_we = addr_hit[450] & reg_we & !reg_error; assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_14_we = addr_hit[445] & reg_we & !reg_error; + assign mio_pad_sleep_mode_14_we = addr_hit[451] & reg_we & !reg_error; assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_15_we = addr_hit[446] & reg_we & !reg_error; + assign mio_pad_sleep_mode_15_we = addr_hit[452] & reg_we & !reg_error; assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_16_we = addr_hit[447] & reg_we & !reg_error; + assign mio_pad_sleep_mode_16_we = addr_hit[453] & reg_we & !reg_error; assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_17_we = addr_hit[448] & reg_we & !reg_error; + assign mio_pad_sleep_mode_17_we = addr_hit[454] & reg_we & !reg_error; assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_18_we = addr_hit[449] & reg_we & !reg_error; + assign mio_pad_sleep_mode_18_we = addr_hit[455] & reg_we & !reg_error; assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_19_we = addr_hit[450] & reg_we & !reg_error; + assign mio_pad_sleep_mode_19_we = addr_hit[456] & reg_we & !reg_error; assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_20_we = addr_hit[451] & reg_we & !reg_error; + assign mio_pad_sleep_mode_20_we = addr_hit[457] & reg_we & !reg_error; assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_21_we = addr_hit[452] & reg_we & !reg_error; + assign mio_pad_sleep_mode_21_we = addr_hit[458] & reg_we & !reg_error; assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_22_we = addr_hit[453] & reg_we & !reg_error; + assign mio_pad_sleep_mode_22_we = addr_hit[459] & reg_we & !reg_error; assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_23_we = addr_hit[454] & reg_we & !reg_error; + assign mio_pad_sleep_mode_23_we = addr_hit[460] & reg_we & !reg_error; assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_24_we = addr_hit[455] & reg_we & !reg_error; + assign mio_pad_sleep_mode_24_we = addr_hit[461] & reg_we & !reg_error; assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_25_we = addr_hit[456] & reg_we & !reg_error; + assign mio_pad_sleep_mode_25_we = addr_hit[462] & reg_we & !reg_error; assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_26_we = addr_hit[457] & reg_we & !reg_error; + assign mio_pad_sleep_mode_26_we = addr_hit[463] & reg_we & !reg_error; assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_27_we = addr_hit[458] & reg_we & !reg_error; + assign mio_pad_sleep_mode_27_we = addr_hit[464] & reg_we & !reg_error; assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_28_we = addr_hit[459] & reg_we & !reg_error; + assign mio_pad_sleep_mode_28_we = addr_hit[465] & reg_we & !reg_error; assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_29_we = addr_hit[460] & reg_we & !reg_error; + assign mio_pad_sleep_mode_29_we = addr_hit[466] & reg_we & !reg_error; assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_30_we = addr_hit[461] & reg_we & !reg_error; + assign mio_pad_sleep_mode_30_we = addr_hit[467] & reg_we & !reg_error; assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_31_we = addr_hit[462] & reg_we & !reg_error; + assign mio_pad_sleep_mode_31_we = addr_hit[468] & reg_we & !reg_error; assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_32_we = addr_hit[463] & reg_we & !reg_error; + assign mio_pad_sleep_mode_32_we = addr_hit[469] & reg_we & !reg_error; assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_33_we = addr_hit[464] & reg_we & !reg_error; + assign mio_pad_sleep_mode_33_we = addr_hit[470] & reg_we & !reg_error; assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_34_we = addr_hit[465] & reg_we & !reg_error; + assign mio_pad_sleep_mode_34_we = addr_hit[471] & reg_we & !reg_error; assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_35_we = addr_hit[466] & reg_we & !reg_error; + assign mio_pad_sleep_mode_35_we = addr_hit[472] & reg_we & !reg_error; assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_36_we = addr_hit[467] & reg_we & !reg_error; + assign mio_pad_sleep_mode_36_we = addr_hit[473] & reg_we & !reg_error; assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_37_we = addr_hit[468] & reg_we & !reg_error; + assign mio_pad_sleep_mode_37_we = addr_hit[474] & reg_we & !reg_error; assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_38_we = addr_hit[469] & reg_we & !reg_error; + assign mio_pad_sleep_mode_38_we = addr_hit[475] & reg_we & !reg_error; assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_39_we = addr_hit[470] & reg_we & !reg_error; + assign mio_pad_sleep_mode_39_we = addr_hit[476] & reg_we & !reg_error; assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_40_we = addr_hit[471] & reg_we & !reg_error; + assign mio_pad_sleep_mode_40_we = addr_hit[477] & reg_we & !reg_error; assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_41_we = addr_hit[472] & reg_we & !reg_error; + assign mio_pad_sleep_mode_41_we = addr_hit[478] & reg_we & !reg_error; assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_42_we = addr_hit[473] & reg_we & !reg_error; + assign mio_pad_sleep_mode_42_we = addr_hit[479] & reg_we & !reg_error; assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_43_we = addr_hit[474] & reg_we & !reg_error; + assign mio_pad_sleep_mode_43_we = addr_hit[480] & reg_we & !reg_error; assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_44_we = addr_hit[475] & reg_we & !reg_error; + assign mio_pad_sleep_mode_44_we = addr_hit[481] & reg_we & !reg_error; assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_45_we = addr_hit[476] & reg_we & !reg_error; + assign mio_pad_sleep_mode_45_we = addr_hit[482] & reg_we & !reg_error; assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_46_we = addr_hit[477] & reg_we & !reg_error; + assign mio_pad_sleep_mode_46_we = addr_hit[483] & reg_we & !reg_error; assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0]; - assign dio_pad_sleep_status_we = addr_hit[478] & reg_we & !reg_error; + assign dio_pad_sleep_status_we = addr_hit[484] & reg_we & !reg_error; assign dio_pad_sleep_status_en_0_wd = reg_wdata[0]; @@ -36429,263 +36660,263 @@ module pinmux_reg_top ( assign dio_pad_sleep_status_en_14_wd = reg_wdata[14]; assign dio_pad_sleep_status_en_15_wd = reg_wdata[15]; - assign dio_pad_sleep_regwen_0_we = addr_hit[479] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_0_we = addr_hit[485] & reg_we & !reg_error; assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_1_we = addr_hit[480] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_1_we = addr_hit[486] & reg_we & !reg_error; assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_2_we = addr_hit[481] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_2_we = addr_hit[487] & reg_we & !reg_error; assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_3_we = addr_hit[482] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_3_we = addr_hit[488] & reg_we & !reg_error; assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_4_we = addr_hit[483] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_4_we = addr_hit[489] & reg_we & !reg_error; assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_5_we = addr_hit[484] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_5_we = addr_hit[490] & reg_we & !reg_error; assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_6_we = addr_hit[485] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_6_we = addr_hit[491] & reg_we & !reg_error; assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_7_we = addr_hit[486] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_7_we = addr_hit[492] & reg_we & !reg_error; assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_8_we = addr_hit[487] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_8_we = addr_hit[493] & reg_we & !reg_error; assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_9_we = addr_hit[488] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_9_we = addr_hit[494] & reg_we & !reg_error; assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_10_we = addr_hit[489] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_10_we = addr_hit[495] & reg_we & !reg_error; assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_11_we = addr_hit[490] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_11_we = addr_hit[496] & reg_we & !reg_error; assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_12_we = addr_hit[491] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_12_we = addr_hit[497] & reg_we & !reg_error; assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_13_we = addr_hit[492] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_13_we = addr_hit[498] & reg_we & !reg_error; assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_14_we = addr_hit[493] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_14_we = addr_hit[499] & reg_we & !reg_error; assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_15_we = addr_hit[494] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_15_we = addr_hit[500] & reg_we & !reg_error; assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign dio_pad_sleep_en_0_we = addr_hit[495] & reg_we & !reg_error; + assign dio_pad_sleep_en_0_we = addr_hit[501] & reg_we & !reg_error; assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_pad_sleep_en_1_we = addr_hit[496] & reg_we & !reg_error; + assign dio_pad_sleep_en_1_we = addr_hit[502] & reg_we & !reg_error; assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_pad_sleep_en_2_we = addr_hit[497] & reg_we & !reg_error; + assign dio_pad_sleep_en_2_we = addr_hit[503] & reg_we & !reg_error; assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_pad_sleep_en_3_we = addr_hit[498] & reg_we & !reg_error; + assign dio_pad_sleep_en_3_we = addr_hit[504] & reg_we & !reg_error; assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_pad_sleep_en_4_we = addr_hit[499] & reg_we & !reg_error; + assign dio_pad_sleep_en_4_we = addr_hit[505] & reg_we & !reg_error; assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_pad_sleep_en_5_we = addr_hit[500] & reg_we & !reg_error; + assign dio_pad_sleep_en_5_we = addr_hit[506] & reg_we & !reg_error; assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_pad_sleep_en_6_we = addr_hit[501] & reg_we & !reg_error; + assign dio_pad_sleep_en_6_we = addr_hit[507] & reg_we & !reg_error; assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_pad_sleep_en_7_we = addr_hit[502] & reg_we & !reg_error; + assign dio_pad_sleep_en_7_we = addr_hit[508] & reg_we & !reg_error; assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_pad_sleep_en_8_we = addr_hit[503] & reg_we & !reg_error; + assign dio_pad_sleep_en_8_we = addr_hit[509] & reg_we & !reg_error; assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_pad_sleep_en_9_we = addr_hit[504] & reg_we & !reg_error; + assign dio_pad_sleep_en_9_we = addr_hit[510] & reg_we & !reg_error; assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_pad_sleep_en_10_we = addr_hit[505] & reg_we & !reg_error; + assign dio_pad_sleep_en_10_we = addr_hit[511] & reg_we & !reg_error; assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_pad_sleep_en_11_we = addr_hit[506] & reg_we & !reg_error; + assign dio_pad_sleep_en_11_we = addr_hit[512] & reg_we & !reg_error; assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_pad_sleep_en_12_we = addr_hit[507] & reg_we & !reg_error; + assign dio_pad_sleep_en_12_we = addr_hit[513] & reg_we & !reg_error; assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_pad_sleep_en_13_we = addr_hit[508] & reg_we & !reg_error; + assign dio_pad_sleep_en_13_we = addr_hit[514] & reg_we & !reg_error; assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_pad_sleep_en_14_we = addr_hit[509] & reg_we & !reg_error; + assign dio_pad_sleep_en_14_we = addr_hit[515] & reg_we & !reg_error; assign dio_pad_sleep_en_14_wd = reg_wdata[0]; - assign dio_pad_sleep_en_15_we = addr_hit[510] & reg_we & !reg_error; + assign dio_pad_sleep_en_15_we = addr_hit[516] & reg_we & !reg_error; assign dio_pad_sleep_en_15_wd = reg_wdata[0]; - assign dio_pad_sleep_mode_0_we = addr_hit[511] & reg_we & !reg_error; + assign dio_pad_sleep_mode_0_we = addr_hit[517] & reg_we & !reg_error; assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_1_we = addr_hit[512] & reg_we & !reg_error; + assign dio_pad_sleep_mode_1_we = addr_hit[518] & reg_we & !reg_error; assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_2_we = addr_hit[513] & reg_we & !reg_error; + assign dio_pad_sleep_mode_2_we = addr_hit[519] & reg_we & !reg_error; assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_3_we = addr_hit[514] & reg_we & !reg_error; + assign dio_pad_sleep_mode_3_we = addr_hit[520] & reg_we & !reg_error; assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_4_we = addr_hit[515] & reg_we & !reg_error; + assign dio_pad_sleep_mode_4_we = addr_hit[521] & reg_we & !reg_error; assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_5_we = addr_hit[516] & reg_we & !reg_error; + assign dio_pad_sleep_mode_5_we = addr_hit[522] & reg_we & !reg_error; assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_6_we = addr_hit[517] & reg_we & !reg_error; + assign dio_pad_sleep_mode_6_we = addr_hit[523] & reg_we & !reg_error; assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_7_we = addr_hit[518] & reg_we & !reg_error; + assign dio_pad_sleep_mode_7_we = addr_hit[524] & reg_we & !reg_error; assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_8_we = addr_hit[519] & reg_we & !reg_error; + assign dio_pad_sleep_mode_8_we = addr_hit[525] & reg_we & !reg_error; assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_9_we = addr_hit[520] & reg_we & !reg_error; + assign dio_pad_sleep_mode_9_we = addr_hit[526] & reg_we & !reg_error; assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_10_we = addr_hit[521] & reg_we & !reg_error; + assign dio_pad_sleep_mode_10_we = addr_hit[527] & reg_we & !reg_error; assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_11_we = addr_hit[522] & reg_we & !reg_error; + assign dio_pad_sleep_mode_11_we = addr_hit[528] & reg_we & !reg_error; assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_12_we = addr_hit[523] & reg_we & !reg_error; + assign dio_pad_sleep_mode_12_we = addr_hit[529] & reg_we & !reg_error; assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_13_we = addr_hit[524] & reg_we & !reg_error; + assign dio_pad_sleep_mode_13_we = addr_hit[530] & reg_we & !reg_error; assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_14_we = addr_hit[525] & reg_we & !reg_error; + assign dio_pad_sleep_mode_14_we = addr_hit[531] & reg_we & !reg_error; assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_15_we = addr_hit[526] & reg_we & !reg_error; + assign dio_pad_sleep_mode_15_we = addr_hit[532] & reg_we & !reg_error; assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[527] & reg_we & !reg_error; + assign wkup_detector_regwen_0_we = addr_hit[533] & reg_we & !reg_error; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[528] & reg_we & !reg_error; + assign wkup_detector_regwen_1_we = addr_hit[534] & reg_we & !reg_error; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[529] & reg_we & !reg_error; + assign wkup_detector_regwen_2_we = addr_hit[535] & reg_we & !reg_error; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[530] & reg_we & !reg_error; + assign wkup_detector_regwen_3_we = addr_hit[536] & reg_we & !reg_error; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[531] & reg_we & !reg_error; + assign wkup_detector_regwen_4_we = addr_hit[537] & reg_we & !reg_error; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[532] & reg_we & !reg_error; + assign wkup_detector_regwen_5_we = addr_hit[538] & reg_we & !reg_error; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[533] & reg_we & !reg_error; + assign wkup_detector_regwen_6_we = addr_hit[539] & reg_we & !reg_error; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[534] & reg_we & !reg_error; + assign wkup_detector_regwen_7_we = addr_hit[540] & reg_we & !reg_error; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[535] & reg_we & !reg_error; + assign wkup_detector_en_0_we = addr_hit[541] & reg_we & !reg_error; - assign wkup_detector_en_1_we = addr_hit[536] & reg_we & !reg_error; + assign wkup_detector_en_1_we = addr_hit[542] & reg_we & !reg_error; - assign wkup_detector_en_2_we = addr_hit[537] & reg_we & !reg_error; + assign wkup_detector_en_2_we = addr_hit[543] & reg_we & !reg_error; - assign wkup_detector_en_3_we = addr_hit[538] & reg_we & !reg_error; + assign wkup_detector_en_3_we = addr_hit[544] & reg_we & !reg_error; - assign wkup_detector_en_4_we = addr_hit[539] & reg_we & !reg_error; + assign wkup_detector_en_4_we = addr_hit[545] & reg_we & !reg_error; - assign wkup_detector_en_5_we = addr_hit[540] & reg_we & !reg_error; + assign wkup_detector_en_5_we = addr_hit[546] & reg_we & !reg_error; - assign wkup_detector_en_6_we = addr_hit[541] & reg_we & !reg_error; + assign wkup_detector_en_6_we = addr_hit[547] & reg_we & !reg_error; - assign wkup_detector_en_7_we = addr_hit[542] & reg_we & !reg_error; + assign wkup_detector_en_7_we = addr_hit[548] & reg_we & !reg_error; - assign wkup_detector_0_we = addr_hit[543] & reg_we & !reg_error; + assign wkup_detector_0_we = addr_hit[549] & reg_we & !reg_error; - assign wkup_detector_1_we = addr_hit[544] & reg_we & !reg_error; + assign wkup_detector_1_we = addr_hit[550] & reg_we & !reg_error; - assign wkup_detector_2_we = addr_hit[545] & reg_we & !reg_error; + assign wkup_detector_2_we = addr_hit[551] & reg_we & !reg_error; - assign wkup_detector_3_we = addr_hit[546] & reg_we & !reg_error; + assign wkup_detector_3_we = addr_hit[552] & reg_we & !reg_error; - assign wkup_detector_4_we = addr_hit[547] & reg_we & !reg_error; + assign wkup_detector_4_we = addr_hit[553] & reg_we & !reg_error; - assign wkup_detector_5_we = addr_hit[548] & reg_we & !reg_error; + assign wkup_detector_5_we = addr_hit[554] & reg_we & !reg_error; - assign wkup_detector_6_we = addr_hit[549] & reg_we & !reg_error; + assign wkup_detector_6_we = addr_hit[555] & reg_we & !reg_error; - assign wkup_detector_7_we = addr_hit[550] & reg_we & !reg_error; + assign wkup_detector_7_we = addr_hit[556] & reg_we & !reg_error; - assign wkup_detector_cnt_th_0_we = addr_hit[551] & reg_we & !reg_error; + assign wkup_detector_cnt_th_0_we = addr_hit[557] & reg_we & !reg_error; - assign wkup_detector_cnt_th_1_we = addr_hit[552] & reg_we & !reg_error; + assign wkup_detector_cnt_th_1_we = addr_hit[558] & reg_we & !reg_error; - assign wkup_detector_cnt_th_2_we = addr_hit[553] & reg_we & !reg_error; + assign wkup_detector_cnt_th_2_we = addr_hit[559] & reg_we & !reg_error; - assign wkup_detector_cnt_th_3_we = addr_hit[554] & reg_we & !reg_error; + assign wkup_detector_cnt_th_3_we = addr_hit[560] & reg_we & !reg_error; - assign wkup_detector_cnt_th_4_we = addr_hit[555] & reg_we & !reg_error; + assign wkup_detector_cnt_th_4_we = addr_hit[561] & reg_we & !reg_error; - assign wkup_detector_cnt_th_5_we = addr_hit[556] & reg_we & !reg_error; + assign wkup_detector_cnt_th_5_we = addr_hit[562] & reg_we & !reg_error; - assign wkup_detector_cnt_th_6_we = addr_hit[557] & reg_we & !reg_error; + assign wkup_detector_cnt_th_6_we = addr_hit[563] & reg_we & !reg_error; - assign wkup_detector_cnt_th_7_we = addr_hit[558] & reg_we & !reg_error; + assign wkup_detector_cnt_th_7_we = addr_hit[564] & reg_we & !reg_error; - assign wkup_detector_padsel_0_we = addr_hit[559] & reg_we & !reg_error; + assign wkup_detector_padsel_0_we = addr_hit[565] & reg_we & !reg_error; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[560] & reg_we & !reg_error; + assign wkup_detector_padsel_1_we = addr_hit[566] & reg_we & !reg_error; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[561] & reg_we & !reg_error; + assign wkup_detector_padsel_2_we = addr_hit[567] & reg_we & !reg_error; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[562] & reg_we & !reg_error; + assign wkup_detector_padsel_3_we = addr_hit[568] & reg_we & !reg_error; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[563] & reg_we & !reg_error; + assign wkup_detector_padsel_4_we = addr_hit[569] & reg_we & !reg_error; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[564] & reg_we & !reg_error; + assign wkup_detector_padsel_5_we = addr_hit[570] & reg_we & !reg_error; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[565] & reg_we & !reg_error; + assign wkup_detector_padsel_6_we = addr_hit[571] & reg_we & !reg_error; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[566] & reg_we & !reg_error; + assign wkup_detector_padsel_7_we = addr_hit[572] & reg_we & !reg_error; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_we = addr_hit[567] & reg_we & !reg_error; + assign wkup_cause_we = addr_hit[573] & reg_we & !reg_error; @@ -36755,516 +36986,522 @@ module pinmux_reg_top ( reg_we_check[55] = mio_periph_insel_regwen_54_we; reg_we_check[56] = mio_periph_insel_regwen_55_we; reg_we_check[57] = mio_periph_insel_regwen_56_we; - reg_we_check[58] = mio_periph_insel_0_gated_we; - reg_we_check[59] = mio_periph_insel_1_gated_we; - reg_we_check[60] = mio_periph_insel_2_gated_we; - reg_we_check[61] = mio_periph_insel_3_gated_we; - reg_we_check[62] = mio_periph_insel_4_gated_we; - reg_we_check[63] = mio_periph_insel_5_gated_we; - reg_we_check[64] = mio_periph_insel_6_gated_we; - reg_we_check[65] = mio_periph_insel_7_gated_we; - reg_we_check[66] = mio_periph_insel_8_gated_we; - reg_we_check[67] = mio_periph_insel_9_gated_we; - reg_we_check[68] = mio_periph_insel_10_gated_we; - reg_we_check[69] = mio_periph_insel_11_gated_we; - reg_we_check[70] = mio_periph_insel_12_gated_we; - reg_we_check[71] = mio_periph_insel_13_gated_we; - reg_we_check[72] = mio_periph_insel_14_gated_we; - reg_we_check[73] = mio_periph_insel_15_gated_we; - reg_we_check[74] = mio_periph_insel_16_gated_we; - reg_we_check[75] = mio_periph_insel_17_gated_we; - reg_we_check[76] = mio_periph_insel_18_gated_we; - reg_we_check[77] = mio_periph_insel_19_gated_we; - reg_we_check[78] = mio_periph_insel_20_gated_we; - reg_we_check[79] = mio_periph_insel_21_gated_we; - reg_we_check[80] = mio_periph_insel_22_gated_we; - reg_we_check[81] = mio_periph_insel_23_gated_we; - reg_we_check[82] = mio_periph_insel_24_gated_we; - reg_we_check[83] = mio_periph_insel_25_gated_we; - reg_we_check[84] = mio_periph_insel_26_gated_we; - reg_we_check[85] = mio_periph_insel_27_gated_we; - reg_we_check[86] = mio_periph_insel_28_gated_we; - reg_we_check[87] = mio_periph_insel_29_gated_we; - reg_we_check[88] = mio_periph_insel_30_gated_we; - reg_we_check[89] = mio_periph_insel_31_gated_we; - reg_we_check[90] = mio_periph_insel_32_gated_we; - reg_we_check[91] = mio_periph_insel_33_gated_we; - reg_we_check[92] = mio_periph_insel_34_gated_we; - reg_we_check[93] = mio_periph_insel_35_gated_we; - reg_we_check[94] = mio_periph_insel_36_gated_we; - reg_we_check[95] = mio_periph_insel_37_gated_we; - reg_we_check[96] = mio_periph_insel_38_gated_we; - reg_we_check[97] = mio_periph_insel_39_gated_we; - reg_we_check[98] = mio_periph_insel_40_gated_we; - reg_we_check[99] = mio_periph_insel_41_gated_we; - reg_we_check[100] = mio_periph_insel_42_gated_we; - reg_we_check[101] = mio_periph_insel_43_gated_we; - reg_we_check[102] = mio_periph_insel_44_gated_we; - reg_we_check[103] = mio_periph_insel_45_gated_we; - reg_we_check[104] = mio_periph_insel_46_gated_we; - reg_we_check[105] = mio_periph_insel_47_gated_we; - reg_we_check[106] = mio_periph_insel_48_gated_we; - reg_we_check[107] = mio_periph_insel_49_gated_we; - reg_we_check[108] = mio_periph_insel_50_gated_we; - reg_we_check[109] = mio_periph_insel_51_gated_we; - reg_we_check[110] = mio_periph_insel_52_gated_we; - reg_we_check[111] = mio_periph_insel_53_gated_we; - reg_we_check[112] = mio_periph_insel_54_gated_we; - reg_we_check[113] = mio_periph_insel_55_gated_we; - reg_we_check[114] = mio_periph_insel_56_gated_we; - reg_we_check[115] = mio_outsel_regwen_0_we; - reg_we_check[116] = mio_outsel_regwen_1_we; - reg_we_check[117] = mio_outsel_regwen_2_we; - reg_we_check[118] = mio_outsel_regwen_3_we; - reg_we_check[119] = mio_outsel_regwen_4_we; - reg_we_check[120] = mio_outsel_regwen_5_we; - reg_we_check[121] = mio_outsel_regwen_6_we; - reg_we_check[122] = mio_outsel_regwen_7_we; - reg_we_check[123] = mio_outsel_regwen_8_we; - reg_we_check[124] = mio_outsel_regwen_9_we; - reg_we_check[125] = mio_outsel_regwen_10_we; - reg_we_check[126] = mio_outsel_regwen_11_we; - reg_we_check[127] = mio_outsel_regwen_12_we; - reg_we_check[128] = mio_outsel_regwen_13_we; - reg_we_check[129] = mio_outsel_regwen_14_we; - reg_we_check[130] = mio_outsel_regwen_15_we; - reg_we_check[131] = mio_outsel_regwen_16_we; - reg_we_check[132] = mio_outsel_regwen_17_we; - reg_we_check[133] = mio_outsel_regwen_18_we; - reg_we_check[134] = mio_outsel_regwen_19_we; - reg_we_check[135] = mio_outsel_regwen_20_we; - reg_we_check[136] = mio_outsel_regwen_21_we; - reg_we_check[137] = mio_outsel_regwen_22_we; - reg_we_check[138] = mio_outsel_regwen_23_we; - reg_we_check[139] = mio_outsel_regwen_24_we; - reg_we_check[140] = mio_outsel_regwen_25_we; - reg_we_check[141] = mio_outsel_regwen_26_we; - reg_we_check[142] = mio_outsel_regwen_27_we; - reg_we_check[143] = mio_outsel_regwen_28_we; - reg_we_check[144] = mio_outsel_regwen_29_we; - reg_we_check[145] = mio_outsel_regwen_30_we; - reg_we_check[146] = mio_outsel_regwen_31_we; - reg_we_check[147] = mio_outsel_regwen_32_we; - reg_we_check[148] = mio_outsel_regwen_33_we; - reg_we_check[149] = mio_outsel_regwen_34_we; - reg_we_check[150] = mio_outsel_regwen_35_we; - reg_we_check[151] = mio_outsel_regwen_36_we; - reg_we_check[152] = mio_outsel_regwen_37_we; - reg_we_check[153] = mio_outsel_regwen_38_we; - reg_we_check[154] = mio_outsel_regwen_39_we; - reg_we_check[155] = mio_outsel_regwen_40_we; - reg_we_check[156] = mio_outsel_regwen_41_we; - reg_we_check[157] = mio_outsel_regwen_42_we; - reg_we_check[158] = mio_outsel_regwen_43_we; - reg_we_check[159] = mio_outsel_regwen_44_we; - reg_we_check[160] = mio_outsel_regwen_45_we; - reg_we_check[161] = mio_outsel_regwen_46_we; - reg_we_check[162] = mio_outsel_0_gated_we; - reg_we_check[163] = mio_outsel_1_gated_we; - reg_we_check[164] = mio_outsel_2_gated_we; - reg_we_check[165] = mio_outsel_3_gated_we; - reg_we_check[166] = mio_outsel_4_gated_we; - reg_we_check[167] = mio_outsel_5_gated_we; - reg_we_check[168] = mio_outsel_6_gated_we; - reg_we_check[169] = mio_outsel_7_gated_we; - reg_we_check[170] = mio_outsel_8_gated_we; - reg_we_check[171] = mio_outsel_9_gated_we; - reg_we_check[172] = mio_outsel_10_gated_we; - reg_we_check[173] = mio_outsel_11_gated_we; - reg_we_check[174] = mio_outsel_12_gated_we; - reg_we_check[175] = mio_outsel_13_gated_we; - reg_we_check[176] = mio_outsel_14_gated_we; - reg_we_check[177] = mio_outsel_15_gated_we; - reg_we_check[178] = mio_outsel_16_gated_we; - reg_we_check[179] = mio_outsel_17_gated_we; - reg_we_check[180] = mio_outsel_18_gated_we; - reg_we_check[181] = mio_outsel_19_gated_we; - reg_we_check[182] = mio_outsel_20_gated_we; - reg_we_check[183] = mio_outsel_21_gated_we; - reg_we_check[184] = mio_outsel_22_gated_we; - reg_we_check[185] = mio_outsel_23_gated_we; - reg_we_check[186] = mio_outsel_24_gated_we; - reg_we_check[187] = mio_outsel_25_gated_we; - reg_we_check[188] = mio_outsel_26_gated_we; - reg_we_check[189] = mio_outsel_27_gated_we; - reg_we_check[190] = mio_outsel_28_gated_we; - reg_we_check[191] = mio_outsel_29_gated_we; - reg_we_check[192] = mio_outsel_30_gated_we; - reg_we_check[193] = mio_outsel_31_gated_we; - reg_we_check[194] = mio_outsel_32_gated_we; - reg_we_check[195] = mio_outsel_33_gated_we; - reg_we_check[196] = mio_outsel_34_gated_we; - reg_we_check[197] = mio_outsel_35_gated_we; - reg_we_check[198] = mio_outsel_36_gated_we; - reg_we_check[199] = mio_outsel_37_gated_we; - reg_we_check[200] = mio_outsel_38_gated_we; - reg_we_check[201] = mio_outsel_39_gated_we; - reg_we_check[202] = mio_outsel_40_gated_we; - reg_we_check[203] = mio_outsel_41_gated_we; - reg_we_check[204] = mio_outsel_42_gated_we; - reg_we_check[205] = mio_outsel_43_gated_we; - reg_we_check[206] = mio_outsel_44_gated_we; - reg_we_check[207] = mio_outsel_45_gated_we; - reg_we_check[208] = mio_outsel_46_gated_we; - reg_we_check[209] = mio_pad_attr_regwen_0_we; - reg_we_check[210] = mio_pad_attr_regwen_1_we; - reg_we_check[211] = mio_pad_attr_regwen_2_we; - reg_we_check[212] = mio_pad_attr_regwen_3_we; - reg_we_check[213] = mio_pad_attr_regwen_4_we; - reg_we_check[214] = mio_pad_attr_regwen_5_we; - reg_we_check[215] = mio_pad_attr_regwen_6_we; - reg_we_check[216] = mio_pad_attr_regwen_7_we; - reg_we_check[217] = mio_pad_attr_regwen_8_we; - reg_we_check[218] = mio_pad_attr_regwen_9_we; - reg_we_check[219] = mio_pad_attr_regwen_10_we; - reg_we_check[220] = mio_pad_attr_regwen_11_we; - reg_we_check[221] = mio_pad_attr_regwen_12_we; - reg_we_check[222] = mio_pad_attr_regwen_13_we; - reg_we_check[223] = mio_pad_attr_regwen_14_we; - reg_we_check[224] = mio_pad_attr_regwen_15_we; - reg_we_check[225] = mio_pad_attr_regwen_16_we; - reg_we_check[226] = mio_pad_attr_regwen_17_we; - reg_we_check[227] = mio_pad_attr_regwen_18_we; - reg_we_check[228] = mio_pad_attr_regwen_19_we; - reg_we_check[229] = mio_pad_attr_regwen_20_we; - reg_we_check[230] = mio_pad_attr_regwen_21_we; - reg_we_check[231] = mio_pad_attr_regwen_22_we; - reg_we_check[232] = mio_pad_attr_regwen_23_we; - reg_we_check[233] = mio_pad_attr_regwen_24_we; - reg_we_check[234] = mio_pad_attr_regwen_25_we; - reg_we_check[235] = mio_pad_attr_regwen_26_we; - reg_we_check[236] = mio_pad_attr_regwen_27_we; - reg_we_check[237] = mio_pad_attr_regwen_28_we; - reg_we_check[238] = mio_pad_attr_regwen_29_we; - reg_we_check[239] = mio_pad_attr_regwen_30_we; - reg_we_check[240] = mio_pad_attr_regwen_31_we; - reg_we_check[241] = mio_pad_attr_regwen_32_we; - reg_we_check[242] = mio_pad_attr_regwen_33_we; - reg_we_check[243] = mio_pad_attr_regwen_34_we; - reg_we_check[244] = mio_pad_attr_regwen_35_we; - reg_we_check[245] = mio_pad_attr_regwen_36_we; - reg_we_check[246] = mio_pad_attr_regwen_37_we; - reg_we_check[247] = mio_pad_attr_regwen_38_we; - reg_we_check[248] = mio_pad_attr_regwen_39_we; - reg_we_check[249] = mio_pad_attr_regwen_40_we; - reg_we_check[250] = mio_pad_attr_regwen_41_we; - reg_we_check[251] = mio_pad_attr_regwen_42_we; - reg_we_check[252] = mio_pad_attr_regwen_43_we; - reg_we_check[253] = mio_pad_attr_regwen_44_we; - reg_we_check[254] = mio_pad_attr_regwen_45_we; - reg_we_check[255] = mio_pad_attr_regwen_46_we; - reg_we_check[256] = mio_pad_attr_0_gated_we; - reg_we_check[257] = mio_pad_attr_1_gated_we; - reg_we_check[258] = mio_pad_attr_2_gated_we; - reg_we_check[259] = mio_pad_attr_3_gated_we; - reg_we_check[260] = mio_pad_attr_4_gated_we; - reg_we_check[261] = mio_pad_attr_5_gated_we; - reg_we_check[262] = mio_pad_attr_6_gated_we; - reg_we_check[263] = mio_pad_attr_7_gated_we; - reg_we_check[264] = mio_pad_attr_8_gated_we; - reg_we_check[265] = mio_pad_attr_9_gated_we; - reg_we_check[266] = mio_pad_attr_10_gated_we; - reg_we_check[267] = mio_pad_attr_11_gated_we; - reg_we_check[268] = mio_pad_attr_12_gated_we; - reg_we_check[269] = mio_pad_attr_13_gated_we; - reg_we_check[270] = mio_pad_attr_14_gated_we; - reg_we_check[271] = mio_pad_attr_15_gated_we; - reg_we_check[272] = mio_pad_attr_16_gated_we; - reg_we_check[273] = mio_pad_attr_17_gated_we; - reg_we_check[274] = mio_pad_attr_18_gated_we; - reg_we_check[275] = mio_pad_attr_19_gated_we; - reg_we_check[276] = mio_pad_attr_20_gated_we; - reg_we_check[277] = mio_pad_attr_21_gated_we; - reg_we_check[278] = mio_pad_attr_22_gated_we; - reg_we_check[279] = mio_pad_attr_23_gated_we; - reg_we_check[280] = mio_pad_attr_24_gated_we; - reg_we_check[281] = mio_pad_attr_25_gated_we; - reg_we_check[282] = mio_pad_attr_26_gated_we; - reg_we_check[283] = mio_pad_attr_27_gated_we; - reg_we_check[284] = mio_pad_attr_28_gated_we; - reg_we_check[285] = mio_pad_attr_29_gated_we; - reg_we_check[286] = mio_pad_attr_30_gated_we; - reg_we_check[287] = mio_pad_attr_31_gated_we; - reg_we_check[288] = mio_pad_attr_32_gated_we; - reg_we_check[289] = mio_pad_attr_33_gated_we; - reg_we_check[290] = mio_pad_attr_34_gated_we; - reg_we_check[291] = mio_pad_attr_35_gated_we; - reg_we_check[292] = mio_pad_attr_36_gated_we; - reg_we_check[293] = mio_pad_attr_37_gated_we; - reg_we_check[294] = mio_pad_attr_38_gated_we; - reg_we_check[295] = mio_pad_attr_39_gated_we; - reg_we_check[296] = mio_pad_attr_40_gated_we; - reg_we_check[297] = mio_pad_attr_41_gated_we; - reg_we_check[298] = mio_pad_attr_42_gated_we; - reg_we_check[299] = mio_pad_attr_43_gated_we; - reg_we_check[300] = mio_pad_attr_44_gated_we; - reg_we_check[301] = mio_pad_attr_45_gated_we; - reg_we_check[302] = mio_pad_attr_46_gated_we; - reg_we_check[303] = dio_pad_attr_regwen_0_we; - reg_we_check[304] = dio_pad_attr_regwen_1_we; - reg_we_check[305] = dio_pad_attr_regwen_2_we; - reg_we_check[306] = dio_pad_attr_regwen_3_we; - reg_we_check[307] = dio_pad_attr_regwen_4_we; - reg_we_check[308] = dio_pad_attr_regwen_5_we; - reg_we_check[309] = dio_pad_attr_regwen_6_we; - reg_we_check[310] = dio_pad_attr_regwen_7_we; - reg_we_check[311] = dio_pad_attr_regwen_8_we; - reg_we_check[312] = dio_pad_attr_regwen_9_we; - reg_we_check[313] = dio_pad_attr_regwen_10_we; - reg_we_check[314] = dio_pad_attr_regwen_11_we; - reg_we_check[315] = dio_pad_attr_regwen_12_we; - reg_we_check[316] = dio_pad_attr_regwen_13_we; - reg_we_check[317] = dio_pad_attr_regwen_14_we; - reg_we_check[318] = dio_pad_attr_regwen_15_we; - reg_we_check[319] = dio_pad_attr_0_gated_we; - reg_we_check[320] = dio_pad_attr_1_gated_we; - reg_we_check[321] = dio_pad_attr_2_gated_we; - reg_we_check[322] = dio_pad_attr_3_gated_we; - reg_we_check[323] = dio_pad_attr_4_gated_we; - reg_we_check[324] = dio_pad_attr_5_gated_we; - reg_we_check[325] = dio_pad_attr_6_gated_we; - reg_we_check[326] = dio_pad_attr_7_gated_we; - reg_we_check[327] = dio_pad_attr_8_gated_we; - reg_we_check[328] = dio_pad_attr_9_gated_we; - reg_we_check[329] = dio_pad_attr_10_gated_we; - reg_we_check[330] = dio_pad_attr_11_gated_we; - reg_we_check[331] = dio_pad_attr_12_gated_we; - reg_we_check[332] = dio_pad_attr_13_gated_we; - reg_we_check[333] = dio_pad_attr_14_gated_we; - reg_we_check[334] = dio_pad_attr_15_gated_we; - reg_we_check[335] = mio_pad_sleep_status_0_we; - reg_we_check[336] = mio_pad_sleep_status_1_we; - reg_we_check[337] = mio_pad_sleep_regwen_0_we; - reg_we_check[338] = mio_pad_sleep_regwen_1_we; - reg_we_check[339] = mio_pad_sleep_regwen_2_we; - reg_we_check[340] = mio_pad_sleep_regwen_3_we; - reg_we_check[341] = mio_pad_sleep_regwen_4_we; - reg_we_check[342] = mio_pad_sleep_regwen_5_we; - reg_we_check[343] = mio_pad_sleep_regwen_6_we; - reg_we_check[344] = mio_pad_sleep_regwen_7_we; - reg_we_check[345] = mio_pad_sleep_regwen_8_we; - reg_we_check[346] = mio_pad_sleep_regwen_9_we; - reg_we_check[347] = mio_pad_sleep_regwen_10_we; - reg_we_check[348] = mio_pad_sleep_regwen_11_we; - reg_we_check[349] = mio_pad_sleep_regwen_12_we; - reg_we_check[350] = mio_pad_sleep_regwen_13_we; - reg_we_check[351] = mio_pad_sleep_regwen_14_we; - reg_we_check[352] = mio_pad_sleep_regwen_15_we; - reg_we_check[353] = mio_pad_sleep_regwen_16_we; - reg_we_check[354] = mio_pad_sleep_regwen_17_we; - reg_we_check[355] = mio_pad_sleep_regwen_18_we; - reg_we_check[356] = mio_pad_sleep_regwen_19_we; - reg_we_check[357] = mio_pad_sleep_regwen_20_we; - reg_we_check[358] = mio_pad_sleep_regwen_21_we; - reg_we_check[359] = mio_pad_sleep_regwen_22_we; - reg_we_check[360] = mio_pad_sleep_regwen_23_we; - reg_we_check[361] = mio_pad_sleep_regwen_24_we; - reg_we_check[362] = mio_pad_sleep_regwen_25_we; - reg_we_check[363] = mio_pad_sleep_regwen_26_we; - reg_we_check[364] = mio_pad_sleep_regwen_27_we; - reg_we_check[365] = mio_pad_sleep_regwen_28_we; - reg_we_check[366] = mio_pad_sleep_regwen_29_we; - reg_we_check[367] = mio_pad_sleep_regwen_30_we; - reg_we_check[368] = mio_pad_sleep_regwen_31_we; - reg_we_check[369] = mio_pad_sleep_regwen_32_we; - reg_we_check[370] = mio_pad_sleep_regwen_33_we; - reg_we_check[371] = mio_pad_sleep_regwen_34_we; - reg_we_check[372] = mio_pad_sleep_regwen_35_we; - reg_we_check[373] = mio_pad_sleep_regwen_36_we; - reg_we_check[374] = mio_pad_sleep_regwen_37_we; - reg_we_check[375] = mio_pad_sleep_regwen_38_we; - reg_we_check[376] = mio_pad_sleep_regwen_39_we; - reg_we_check[377] = mio_pad_sleep_regwen_40_we; - reg_we_check[378] = mio_pad_sleep_regwen_41_we; - reg_we_check[379] = mio_pad_sleep_regwen_42_we; - reg_we_check[380] = mio_pad_sleep_regwen_43_we; - reg_we_check[381] = mio_pad_sleep_regwen_44_we; - reg_we_check[382] = mio_pad_sleep_regwen_45_we; - reg_we_check[383] = mio_pad_sleep_regwen_46_we; - reg_we_check[384] = mio_pad_sleep_en_0_gated_we; - reg_we_check[385] = mio_pad_sleep_en_1_gated_we; - reg_we_check[386] = mio_pad_sleep_en_2_gated_we; - reg_we_check[387] = mio_pad_sleep_en_3_gated_we; - reg_we_check[388] = mio_pad_sleep_en_4_gated_we; - reg_we_check[389] = mio_pad_sleep_en_5_gated_we; - reg_we_check[390] = mio_pad_sleep_en_6_gated_we; - reg_we_check[391] = mio_pad_sleep_en_7_gated_we; - reg_we_check[392] = mio_pad_sleep_en_8_gated_we; - reg_we_check[393] = mio_pad_sleep_en_9_gated_we; - reg_we_check[394] = mio_pad_sleep_en_10_gated_we; - reg_we_check[395] = mio_pad_sleep_en_11_gated_we; - reg_we_check[396] = mio_pad_sleep_en_12_gated_we; - reg_we_check[397] = mio_pad_sleep_en_13_gated_we; - reg_we_check[398] = mio_pad_sleep_en_14_gated_we; - reg_we_check[399] = mio_pad_sleep_en_15_gated_we; - reg_we_check[400] = mio_pad_sleep_en_16_gated_we; - reg_we_check[401] = mio_pad_sleep_en_17_gated_we; - reg_we_check[402] = mio_pad_sleep_en_18_gated_we; - reg_we_check[403] = mio_pad_sleep_en_19_gated_we; - reg_we_check[404] = mio_pad_sleep_en_20_gated_we; - reg_we_check[405] = mio_pad_sleep_en_21_gated_we; - reg_we_check[406] = mio_pad_sleep_en_22_gated_we; - reg_we_check[407] = mio_pad_sleep_en_23_gated_we; - reg_we_check[408] = mio_pad_sleep_en_24_gated_we; - reg_we_check[409] = mio_pad_sleep_en_25_gated_we; - reg_we_check[410] = mio_pad_sleep_en_26_gated_we; - reg_we_check[411] = mio_pad_sleep_en_27_gated_we; - reg_we_check[412] = mio_pad_sleep_en_28_gated_we; - reg_we_check[413] = mio_pad_sleep_en_29_gated_we; - reg_we_check[414] = mio_pad_sleep_en_30_gated_we; - reg_we_check[415] = mio_pad_sleep_en_31_gated_we; - reg_we_check[416] = mio_pad_sleep_en_32_gated_we; - reg_we_check[417] = mio_pad_sleep_en_33_gated_we; - reg_we_check[418] = mio_pad_sleep_en_34_gated_we; - reg_we_check[419] = mio_pad_sleep_en_35_gated_we; - reg_we_check[420] = mio_pad_sleep_en_36_gated_we; - reg_we_check[421] = mio_pad_sleep_en_37_gated_we; - reg_we_check[422] = mio_pad_sleep_en_38_gated_we; - reg_we_check[423] = mio_pad_sleep_en_39_gated_we; - reg_we_check[424] = mio_pad_sleep_en_40_gated_we; - reg_we_check[425] = mio_pad_sleep_en_41_gated_we; - reg_we_check[426] = mio_pad_sleep_en_42_gated_we; - reg_we_check[427] = mio_pad_sleep_en_43_gated_we; - reg_we_check[428] = mio_pad_sleep_en_44_gated_we; - reg_we_check[429] = mio_pad_sleep_en_45_gated_we; - reg_we_check[430] = mio_pad_sleep_en_46_gated_we; - reg_we_check[431] = mio_pad_sleep_mode_0_gated_we; - reg_we_check[432] = mio_pad_sleep_mode_1_gated_we; - reg_we_check[433] = mio_pad_sleep_mode_2_gated_we; - reg_we_check[434] = mio_pad_sleep_mode_3_gated_we; - reg_we_check[435] = mio_pad_sleep_mode_4_gated_we; - reg_we_check[436] = mio_pad_sleep_mode_5_gated_we; - reg_we_check[437] = mio_pad_sleep_mode_6_gated_we; - reg_we_check[438] = mio_pad_sleep_mode_7_gated_we; - reg_we_check[439] = mio_pad_sleep_mode_8_gated_we; - reg_we_check[440] = mio_pad_sleep_mode_9_gated_we; - reg_we_check[441] = mio_pad_sleep_mode_10_gated_we; - reg_we_check[442] = mio_pad_sleep_mode_11_gated_we; - reg_we_check[443] = mio_pad_sleep_mode_12_gated_we; - reg_we_check[444] = mio_pad_sleep_mode_13_gated_we; - reg_we_check[445] = mio_pad_sleep_mode_14_gated_we; - reg_we_check[446] = mio_pad_sleep_mode_15_gated_we; - reg_we_check[447] = mio_pad_sleep_mode_16_gated_we; - reg_we_check[448] = mio_pad_sleep_mode_17_gated_we; - reg_we_check[449] = mio_pad_sleep_mode_18_gated_we; - reg_we_check[450] = mio_pad_sleep_mode_19_gated_we; - reg_we_check[451] = mio_pad_sleep_mode_20_gated_we; - reg_we_check[452] = mio_pad_sleep_mode_21_gated_we; - reg_we_check[453] = mio_pad_sleep_mode_22_gated_we; - reg_we_check[454] = mio_pad_sleep_mode_23_gated_we; - reg_we_check[455] = mio_pad_sleep_mode_24_gated_we; - reg_we_check[456] = mio_pad_sleep_mode_25_gated_we; - reg_we_check[457] = mio_pad_sleep_mode_26_gated_we; - reg_we_check[458] = mio_pad_sleep_mode_27_gated_we; - reg_we_check[459] = mio_pad_sleep_mode_28_gated_we; - reg_we_check[460] = mio_pad_sleep_mode_29_gated_we; - reg_we_check[461] = mio_pad_sleep_mode_30_gated_we; - reg_we_check[462] = mio_pad_sleep_mode_31_gated_we; - reg_we_check[463] = mio_pad_sleep_mode_32_gated_we; - reg_we_check[464] = mio_pad_sleep_mode_33_gated_we; - reg_we_check[465] = mio_pad_sleep_mode_34_gated_we; - reg_we_check[466] = mio_pad_sleep_mode_35_gated_we; - reg_we_check[467] = mio_pad_sleep_mode_36_gated_we; - reg_we_check[468] = mio_pad_sleep_mode_37_gated_we; - reg_we_check[469] = mio_pad_sleep_mode_38_gated_we; - reg_we_check[470] = mio_pad_sleep_mode_39_gated_we; - reg_we_check[471] = mio_pad_sleep_mode_40_gated_we; - reg_we_check[472] = mio_pad_sleep_mode_41_gated_we; - reg_we_check[473] = mio_pad_sleep_mode_42_gated_we; - reg_we_check[474] = mio_pad_sleep_mode_43_gated_we; - reg_we_check[475] = mio_pad_sleep_mode_44_gated_we; - reg_we_check[476] = mio_pad_sleep_mode_45_gated_we; - reg_we_check[477] = mio_pad_sleep_mode_46_gated_we; - reg_we_check[478] = dio_pad_sleep_status_we; - reg_we_check[479] = dio_pad_sleep_regwen_0_we; - reg_we_check[480] = dio_pad_sleep_regwen_1_we; - reg_we_check[481] = dio_pad_sleep_regwen_2_we; - reg_we_check[482] = dio_pad_sleep_regwen_3_we; - reg_we_check[483] = dio_pad_sleep_regwen_4_we; - reg_we_check[484] = dio_pad_sleep_regwen_5_we; - reg_we_check[485] = dio_pad_sleep_regwen_6_we; - reg_we_check[486] = dio_pad_sleep_regwen_7_we; - reg_we_check[487] = dio_pad_sleep_regwen_8_we; - reg_we_check[488] = dio_pad_sleep_regwen_9_we; - reg_we_check[489] = dio_pad_sleep_regwen_10_we; - reg_we_check[490] = dio_pad_sleep_regwen_11_we; - reg_we_check[491] = dio_pad_sleep_regwen_12_we; - reg_we_check[492] = dio_pad_sleep_regwen_13_we; - reg_we_check[493] = dio_pad_sleep_regwen_14_we; - reg_we_check[494] = dio_pad_sleep_regwen_15_we; - reg_we_check[495] = dio_pad_sleep_en_0_gated_we; - reg_we_check[496] = dio_pad_sleep_en_1_gated_we; - reg_we_check[497] = dio_pad_sleep_en_2_gated_we; - reg_we_check[498] = dio_pad_sleep_en_3_gated_we; - reg_we_check[499] = dio_pad_sleep_en_4_gated_we; - reg_we_check[500] = dio_pad_sleep_en_5_gated_we; - reg_we_check[501] = dio_pad_sleep_en_6_gated_we; - reg_we_check[502] = dio_pad_sleep_en_7_gated_we; - reg_we_check[503] = dio_pad_sleep_en_8_gated_we; - reg_we_check[504] = dio_pad_sleep_en_9_gated_we; - reg_we_check[505] = dio_pad_sleep_en_10_gated_we; - reg_we_check[506] = dio_pad_sleep_en_11_gated_we; - reg_we_check[507] = dio_pad_sleep_en_12_gated_we; - reg_we_check[508] = dio_pad_sleep_en_13_gated_we; - reg_we_check[509] = dio_pad_sleep_en_14_gated_we; - reg_we_check[510] = dio_pad_sleep_en_15_gated_we; - reg_we_check[511] = dio_pad_sleep_mode_0_gated_we; - reg_we_check[512] = dio_pad_sleep_mode_1_gated_we; - reg_we_check[513] = dio_pad_sleep_mode_2_gated_we; - reg_we_check[514] = dio_pad_sleep_mode_3_gated_we; - reg_we_check[515] = dio_pad_sleep_mode_4_gated_we; - reg_we_check[516] = dio_pad_sleep_mode_5_gated_we; - reg_we_check[517] = dio_pad_sleep_mode_6_gated_we; - reg_we_check[518] = dio_pad_sleep_mode_7_gated_we; - reg_we_check[519] = dio_pad_sleep_mode_8_gated_we; - reg_we_check[520] = dio_pad_sleep_mode_9_gated_we; - reg_we_check[521] = dio_pad_sleep_mode_10_gated_we; - reg_we_check[522] = dio_pad_sleep_mode_11_gated_we; - reg_we_check[523] = dio_pad_sleep_mode_12_gated_we; - reg_we_check[524] = dio_pad_sleep_mode_13_gated_we; - reg_we_check[525] = dio_pad_sleep_mode_14_gated_we; - reg_we_check[526] = dio_pad_sleep_mode_15_gated_we; - reg_we_check[527] = wkup_detector_regwen_0_we; - reg_we_check[528] = wkup_detector_regwen_1_we; - reg_we_check[529] = wkup_detector_regwen_2_we; - reg_we_check[530] = wkup_detector_regwen_3_we; - reg_we_check[531] = wkup_detector_regwen_4_we; - reg_we_check[532] = wkup_detector_regwen_5_we; - reg_we_check[533] = wkup_detector_regwen_6_we; - reg_we_check[534] = wkup_detector_regwen_7_we; - reg_we_check[535] = wkup_detector_en_0_we; - reg_we_check[536] = wkup_detector_en_1_we; - reg_we_check[537] = wkup_detector_en_2_we; - reg_we_check[538] = wkup_detector_en_3_we; - reg_we_check[539] = wkup_detector_en_4_we; - reg_we_check[540] = wkup_detector_en_5_we; - reg_we_check[541] = wkup_detector_en_6_we; - reg_we_check[542] = wkup_detector_en_7_we; - reg_we_check[543] = wkup_detector_0_we; - reg_we_check[544] = wkup_detector_1_we; - reg_we_check[545] = wkup_detector_2_we; - reg_we_check[546] = wkup_detector_3_we; - reg_we_check[547] = wkup_detector_4_we; - reg_we_check[548] = wkup_detector_5_we; - reg_we_check[549] = wkup_detector_6_we; - reg_we_check[550] = wkup_detector_7_we; - reg_we_check[551] = wkup_detector_cnt_th_0_we; - reg_we_check[552] = wkup_detector_cnt_th_1_we; - reg_we_check[553] = wkup_detector_cnt_th_2_we; - reg_we_check[554] = wkup_detector_cnt_th_3_we; - reg_we_check[555] = wkup_detector_cnt_th_4_we; - reg_we_check[556] = wkup_detector_cnt_th_5_we; - reg_we_check[557] = wkup_detector_cnt_th_6_we; - reg_we_check[558] = wkup_detector_cnt_th_7_we; - reg_we_check[559] = wkup_detector_padsel_0_gated_we; - reg_we_check[560] = wkup_detector_padsel_1_gated_we; - reg_we_check[561] = wkup_detector_padsel_2_gated_we; - reg_we_check[562] = wkup_detector_padsel_3_gated_we; - reg_we_check[563] = wkup_detector_padsel_4_gated_we; - reg_we_check[564] = wkup_detector_padsel_5_gated_we; - reg_we_check[565] = wkup_detector_padsel_6_gated_we; - reg_we_check[566] = wkup_detector_padsel_7_gated_we; - reg_we_check[567] = wkup_cause_we; + reg_we_check[58] = mio_periph_insel_regwen_57_we; + reg_we_check[59] = mio_periph_insel_regwen_58_we; + reg_we_check[60] = mio_periph_insel_regwen_59_we; + reg_we_check[61] = mio_periph_insel_0_gated_we; + reg_we_check[62] = mio_periph_insel_1_gated_we; + reg_we_check[63] = mio_periph_insel_2_gated_we; + reg_we_check[64] = mio_periph_insel_3_gated_we; + reg_we_check[65] = mio_periph_insel_4_gated_we; + reg_we_check[66] = mio_periph_insel_5_gated_we; + reg_we_check[67] = mio_periph_insel_6_gated_we; + reg_we_check[68] = mio_periph_insel_7_gated_we; + reg_we_check[69] = mio_periph_insel_8_gated_we; + reg_we_check[70] = mio_periph_insel_9_gated_we; + reg_we_check[71] = mio_periph_insel_10_gated_we; + reg_we_check[72] = mio_periph_insel_11_gated_we; + reg_we_check[73] = mio_periph_insel_12_gated_we; + reg_we_check[74] = mio_periph_insel_13_gated_we; + reg_we_check[75] = mio_periph_insel_14_gated_we; + reg_we_check[76] = mio_periph_insel_15_gated_we; + reg_we_check[77] = mio_periph_insel_16_gated_we; + reg_we_check[78] = mio_periph_insel_17_gated_we; + reg_we_check[79] = mio_periph_insel_18_gated_we; + reg_we_check[80] = mio_periph_insel_19_gated_we; + reg_we_check[81] = mio_periph_insel_20_gated_we; + reg_we_check[82] = mio_periph_insel_21_gated_we; + reg_we_check[83] = mio_periph_insel_22_gated_we; + reg_we_check[84] = mio_periph_insel_23_gated_we; + reg_we_check[85] = mio_periph_insel_24_gated_we; + reg_we_check[86] = mio_periph_insel_25_gated_we; + reg_we_check[87] = mio_periph_insel_26_gated_we; + reg_we_check[88] = mio_periph_insel_27_gated_we; + reg_we_check[89] = mio_periph_insel_28_gated_we; + reg_we_check[90] = mio_periph_insel_29_gated_we; + reg_we_check[91] = mio_periph_insel_30_gated_we; + reg_we_check[92] = mio_periph_insel_31_gated_we; + reg_we_check[93] = mio_periph_insel_32_gated_we; + reg_we_check[94] = mio_periph_insel_33_gated_we; + reg_we_check[95] = mio_periph_insel_34_gated_we; + reg_we_check[96] = mio_periph_insel_35_gated_we; + reg_we_check[97] = mio_periph_insel_36_gated_we; + reg_we_check[98] = mio_periph_insel_37_gated_we; + reg_we_check[99] = mio_periph_insel_38_gated_we; + reg_we_check[100] = mio_periph_insel_39_gated_we; + reg_we_check[101] = mio_periph_insel_40_gated_we; + reg_we_check[102] = mio_periph_insel_41_gated_we; + reg_we_check[103] = mio_periph_insel_42_gated_we; + reg_we_check[104] = mio_periph_insel_43_gated_we; + reg_we_check[105] = mio_periph_insel_44_gated_we; + reg_we_check[106] = mio_periph_insel_45_gated_we; + reg_we_check[107] = mio_periph_insel_46_gated_we; + reg_we_check[108] = mio_periph_insel_47_gated_we; + reg_we_check[109] = mio_periph_insel_48_gated_we; + reg_we_check[110] = mio_periph_insel_49_gated_we; + reg_we_check[111] = mio_periph_insel_50_gated_we; + reg_we_check[112] = mio_periph_insel_51_gated_we; + reg_we_check[113] = mio_periph_insel_52_gated_we; + reg_we_check[114] = mio_periph_insel_53_gated_we; + reg_we_check[115] = mio_periph_insel_54_gated_we; + reg_we_check[116] = mio_periph_insel_55_gated_we; + reg_we_check[117] = mio_periph_insel_56_gated_we; + reg_we_check[118] = mio_periph_insel_57_gated_we; + reg_we_check[119] = mio_periph_insel_58_gated_we; + reg_we_check[120] = mio_periph_insel_59_gated_we; + reg_we_check[121] = mio_outsel_regwen_0_we; + reg_we_check[122] = mio_outsel_regwen_1_we; + reg_we_check[123] = mio_outsel_regwen_2_we; + reg_we_check[124] = mio_outsel_regwen_3_we; + reg_we_check[125] = mio_outsel_regwen_4_we; + reg_we_check[126] = mio_outsel_regwen_5_we; + reg_we_check[127] = mio_outsel_regwen_6_we; + reg_we_check[128] = mio_outsel_regwen_7_we; + reg_we_check[129] = mio_outsel_regwen_8_we; + reg_we_check[130] = mio_outsel_regwen_9_we; + reg_we_check[131] = mio_outsel_regwen_10_we; + reg_we_check[132] = mio_outsel_regwen_11_we; + reg_we_check[133] = mio_outsel_regwen_12_we; + reg_we_check[134] = mio_outsel_regwen_13_we; + reg_we_check[135] = mio_outsel_regwen_14_we; + reg_we_check[136] = mio_outsel_regwen_15_we; + reg_we_check[137] = mio_outsel_regwen_16_we; + reg_we_check[138] = mio_outsel_regwen_17_we; + reg_we_check[139] = mio_outsel_regwen_18_we; + reg_we_check[140] = mio_outsel_regwen_19_we; + reg_we_check[141] = mio_outsel_regwen_20_we; + reg_we_check[142] = mio_outsel_regwen_21_we; + reg_we_check[143] = mio_outsel_regwen_22_we; + reg_we_check[144] = mio_outsel_regwen_23_we; + reg_we_check[145] = mio_outsel_regwen_24_we; + reg_we_check[146] = mio_outsel_regwen_25_we; + reg_we_check[147] = mio_outsel_regwen_26_we; + reg_we_check[148] = mio_outsel_regwen_27_we; + reg_we_check[149] = mio_outsel_regwen_28_we; + reg_we_check[150] = mio_outsel_regwen_29_we; + reg_we_check[151] = mio_outsel_regwen_30_we; + reg_we_check[152] = mio_outsel_regwen_31_we; + reg_we_check[153] = mio_outsel_regwen_32_we; + reg_we_check[154] = mio_outsel_regwen_33_we; + reg_we_check[155] = mio_outsel_regwen_34_we; + reg_we_check[156] = mio_outsel_regwen_35_we; + reg_we_check[157] = mio_outsel_regwen_36_we; + reg_we_check[158] = mio_outsel_regwen_37_we; + reg_we_check[159] = mio_outsel_regwen_38_we; + reg_we_check[160] = mio_outsel_regwen_39_we; + reg_we_check[161] = mio_outsel_regwen_40_we; + reg_we_check[162] = mio_outsel_regwen_41_we; + reg_we_check[163] = mio_outsel_regwen_42_we; + reg_we_check[164] = mio_outsel_regwen_43_we; + reg_we_check[165] = mio_outsel_regwen_44_we; + reg_we_check[166] = mio_outsel_regwen_45_we; + reg_we_check[167] = mio_outsel_regwen_46_we; + reg_we_check[168] = mio_outsel_0_gated_we; + reg_we_check[169] = mio_outsel_1_gated_we; + reg_we_check[170] = mio_outsel_2_gated_we; + reg_we_check[171] = mio_outsel_3_gated_we; + reg_we_check[172] = mio_outsel_4_gated_we; + reg_we_check[173] = mio_outsel_5_gated_we; + reg_we_check[174] = mio_outsel_6_gated_we; + reg_we_check[175] = mio_outsel_7_gated_we; + reg_we_check[176] = mio_outsel_8_gated_we; + reg_we_check[177] = mio_outsel_9_gated_we; + reg_we_check[178] = mio_outsel_10_gated_we; + reg_we_check[179] = mio_outsel_11_gated_we; + reg_we_check[180] = mio_outsel_12_gated_we; + reg_we_check[181] = mio_outsel_13_gated_we; + reg_we_check[182] = mio_outsel_14_gated_we; + reg_we_check[183] = mio_outsel_15_gated_we; + reg_we_check[184] = mio_outsel_16_gated_we; + reg_we_check[185] = mio_outsel_17_gated_we; + reg_we_check[186] = mio_outsel_18_gated_we; + reg_we_check[187] = mio_outsel_19_gated_we; + reg_we_check[188] = mio_outsel_20_gated_we; + reg_we_check[189] = mio_outsel_21_gated_we; + reg_we_check[190] = mio_outsel_22_gated_we; + reg_we_check[191] = mio_outsel_23_gated_we; + reg_we_check[192] = mio_outsel_24_gated_we; + reg_we_check[193] = mio_outsel_25_gated_we; + reg_we_check[194] = mio_outsel_26_gated_we; + reg_we_check[195] = mio_outsel_27_gated_we; + reg_we_check[196] = mio_outsel_28_gated_we; + reg_we_check[197] = mio_outsel_29_gated_we; + reg_we_check[198] = mio_outsel_30_gated_we; + reg_we_check[199] = mio_outsel_31_gated_we; + reg_we_check[200] = mio_outsel_32_gated_we; + reg_we_check[201] = mio_outsel_33_gated_we; + reg_we_check[202] = mio_outsel_34_gated_we; + reg_we_check[203] = mio_outsel_35_gated_we; + reg_we_check[204] = mio_outsel_36_gated_we; + reg_we_check[205] = mio_outsel_37_gated_we; + reg_we_check[206] = mio_outsel_38_gated_we; + reg_we_check[207] = mio_outsel_39_gated_we; + reg_we_check[208] = mio_outsel_40_gated_we; + reg_we_check[209] = mio_outsel_41_gated_we; + reg_we_check[210] = mio_outsel_42_gated_we; + reg_we_check[211] = mio_outsel_43_gated_we; + reg_we_check[212] = mio_outsel_44_gated_we; + reg_we_check[213] = mio_outsel_45_gated_we; + reg_we_check[214] = mio_outsel_46_gated_we; + reg_we_check[215] = mio_pad_attr_regwen_0_we; + reg_we_check[216] = mio_pad_attr_regwen_1_we; + reg_we_check[217] = mio_pad_attr_regwen_2_we; + reg_we_check[218] = mio_pad_attr_regwen_3_we; + reg_we_check[219] = mio_pad_attr_regwen_4_we; + reg_we_check[220] = mio_pad_attr_regwen_5_we; + reg_we_check[221] = mio_pad_attr_regwen_6_we; + reg_we_check[222] = mio_pad_attr_regwen_7_we; + reg_we_check[223] = mio_pad_attr_regwen_8_we; + reg_we_check[224] = mio_pad_attr_regwen_9_we; + reg_we_check[225] = mio_pad_attr_regwen_10_we; + reg_we_check[226] = mio_pad_attr_regwen_11_we; + reg_we_check[227] = mio_pad_attr_regwen_12_we; + reg_we_check[228] = mio_pad_attr_regwen_13_we; + reg_we_check[229] = mio_pad_attr_regwen_14_we; + reg_we_check[230] = mio_pad_attr_regwen_15_we; + reg_we_check[231] = mio_pad_attr_regwen_16_we; + reg_we_check[232] = mio_pad_attr_regwen_17_we; + reg_we_check[233] = mio_pad_attr_regwen_18_we; + reg_we_check[234] = mio_pad_attr_regwen_19_we; + reg_we_check[235] = mio_pad_attr_regwen_20_we; + reg_we_check[236] = mio_pad_attr_regwen_21_we; + reg_we_check[237] = mio_pad_attr_regwen_22_we; + reg_we_check[238] = mio_pad_attr_regwen_23_we; + reg_we_check[239] = mio_pad_attr_regwen_24_we; + reg_we_check[240] = mio_pad_attr_regwen_25_we; + reg_we_check[241] = mio_pad_attr_regwen_26_we; + reg_we_check[242] = mio_pad_attr_regwen_27_we; + reg_we_check[243] = mio_pad_attr_regwen_28_we; + reg_we_check[244] = mio_pad_attr_regwen_29_we; + reg_we_check[245] = mio_pad_attr_regwen_30_we; + reg_we_check[246] = mio_pad_attr_regwen_31_we; + reg_we_check[247] = mio_pad_attr_regwen_32_we; + reg_we_check[248] = mio_pad_attr_regwen_33_we; + reg_we_check[249] = mio_pad_attr_regwen_34_we; + reg_we_check[250] = mio_pad_attr_regwen_35_we; + reg_we_check[251] = mio_pad_attr_regwen_36_we; + reg_we_check[252] = mio_pad_attr_regwen_37_we; + reg_we_check[253] = mio_pad_attr_regwen_38_we; + reg_we_check[254] = mio_pad_attr_regwen_39_we; + reg_we_check[255] = mio_pad_attr_regwen_40_we; + reg_we_check[256] = mio_pad_attr_regwen_41_we; + reg_we_check[257] = mio_pad_attr_regwen_42_we; + reg_we_check[258] = mio_pad_attr_regwen_43_we; + reg_we_check[259] = mio_pad_attr_regwen_44_we; + reg_we_check[260] = mio_pad_attr_regwen_45_we; + reg_we_check[261] = mio_pad_attr_regwen_46_we; + reg_we_check[262] = mio_pad_attr_0_gated_we; + reg_we_check[263] = mio_pad_attr_1_gated_we; + reg_we_check[264] = mio_pad_attr_2_gated_we; + reg_we_check[265] = mio_pad_attr_3_gated_we; + reg_we_check[266] = mio_pad_attr_4_gated_we; + reg_we_check[267] = mio_pad_attr_5_gated_we; + reg_we_check[268] = mio_pad_attr_6_gated_we; + reg_we_check[269] = mio_pad_attr_7_gated_we; + reg_we_check[270] = mio_pad_attr_8_gated_we; + reg_we_check[271] = mio_pad_attr_9_gated_we; + reg_we_check[272] = mio_pad_attr_10_gated_we; + reg_we_check[273] = mio_pad_attr_11_gated_we; + reg_we_check[274] = mio_pad_attr_12_gated_we; + reg_we_check[275] = mio_pad_attr_13_gated_we; + reg_we_check[276] = mio_pad_attr_14_gated_we; + reg_we_check[277] = mio_pad_attr_15_gated_we; + reg_we_check[278] = mio_pad_attr_16_gated_we; + reg_we_check[279] = mio_pad_attr_17_gated_we; + reg_we_check[280] = mio_pad_attr_18_gated_we; + reg_we_check[281] = mio_pad_attr_19_gated_we; + reg_we_check[282] = mio_pad_attr_20_gated_we; + reg_we_check[283] = mio_pad_attr_21_gated_we; + reg_we_check[284] = mio_pad_attr_22_gated_we; + reg_we_check[285] = mio_pad_attr_23_gated_we; + reg_we_check[286] = mio_pad_attr_24_gated_we; + reg_we_check[287] = mio_pad_attr_25_gated_we; + reg_we_check[288] = mio_pad_attr_26_gated_we; + reg_we_check[289] = mio_pad_attr_27_gated_we; + reg_we_check[290] = mio_pad_attr_28_gated_we; + reg_we_check[291] = mio_pad_attr_29_gated_we; + reg_we_check[292] = mio_pad_attr_30_gated_we; + reg_we_check[293] = mio_pad_attr_31_gated_we; + reg_we_check[294] = mio_pad_attr_32_gated_we; + reg_we_check[295] = mio_pad_attr_33_gated_we; + reg_we_check[296] = mio_pad_attr_34_gated_we; + reg_we_check[297] = mio_pad_attr_35_gated_we; + reg_we_check[298] = mio_pad_attr_36_gated_we; + reg_we_check[299] = mio_pad_attr_37_gated_we; + reg_we_check[300] = mio_pad_attr_38_gated_we; + reg_we_check[301] = mio_pad_attr_39_gated_we; + reg_we_check[302] = mio_pad_attr_40_gated_we; + reg_we_check[303] = mio_pad_attr_41_gated_we; + reg_we_check[304] = mio_pad_attr_42_gated_we; + reg_we_check[305] = mio_pad_attr_43_gated_we; + reg_we_check[306] = mio_pad_attr_44_gated_we; + reg_we_check[307] = mio_pad_attr_45_gated_we; + reg_we_check[308] = mio_pad_attr_46_gated_we; + reg_we_check[309] = dio_pad_attr_regwen_0_we; + reg_we_check[310] = dio_pad_attr_regwen_1_we; + reg_we_check[311] = dio_pad_attr_regwen_2_we; + reg_we_check[312] = dio_pad_attr_regwen_3_we; + reg_we_check[313] = dio_pad_attr_regwen_4_we; + reg_we_check[314] = dio_pad_attr_regwen_5_we; + reg_we_check[315] = dio_pad_attr_regwen_6_we; + reg_we_check[316] = dio_pad_attr_regwen_7_we; + reg_we_check[317] = dio_pad_attr_regwen_8_we; + reg_we_check[318] = dio_pad_attr_regwen_9_we; + reg_we_check[319] = dio_pad_attr_regwen_10_we; + reg_we_check[320] = dio_pad_attr_regwen_11_we; + reg_we_check[321] = dio_pad_attr_regwen_12_we; + reg_we_check[322] = dio_pad_attr_regwen_13_we; + reg_we_check[323] = dio_pad_attr_regwen_14_we; + reg_we_check[324] = dio_pad_attr_regwen_15_we; + reg_we_check[325] = dio_pad_attr_0_gated_we; + reg_we_check[326] = dio_pad_attr_1_gated_we; + reg_we_check[327] = dio_pad_attr_2_gated_we; + reg_we_check[328] = dio_pad_attr_3_gated_we; + reg_we_check[329] = dio_pad_attr_4_gated_we; + reg_we_check[330] = dio_pad_attr_5_gated_we; + reg_we_check[331] = dio_pad_attr_6_gated_we; + reg_we_check[332] = dio_pad_attr_7_gated_we; + reg_we_check[333] = dio_pad_attr_8_gated_we; + reg_we_check[334] = dio_pad_attr_9_gated_we; + reg_we_check[335] = dio_pad_attr_10_gated_we; + reg_we_check[336] = dio_pad_attr_11_gated_we; + reg_we_check[337] = dio_pad_attr_12_gated_we; + reg_we_check[338] = dio_pad_attr_13_gated_we; + reg_we_check[339] = dio_pad_attr_14_gated_we; + reg_we_check[340] = dio_pad_attr_15_gated_we; + reg_we_check[341] = mio_pad_sleep_status_0_we; + reg_we_check[342] = mio_pad_sleep_status_1_we; + reg_we_check[343] = mio_pad_sleep_regwen_0_we; + reg_we_check[344] = mio_pad_sleep_regwen_1_we; + reg_we_check[345] = mio_pad_sleep_regwen_2_we; + reg_we_check[346] = mio_pad_sleep_regwen_3_we; + reg_we_check[347] = mio_pad_sleep_regwen_4_we; + reg_we_check[348] = mio_pad_sleep_regwen_5_we; + reg_we_check[349] = mio_pad_sleep_regwen_6_we; + reg_we_check[350] = mio_pad_sleep_regwen_7_we; + reg_we_check[351] = mio_pad_sleep_regwen_8_we; + reg_we_check[352] = mio_pad_sleep_regwen_9_we; + reg_we_check[353] = mio_pad_sleep_regwen_10_we; + reg_we_check[354] = mio_pad_sleep_regwen_11_we; + reg_we_check[355] = mio_pad_sleep_regwen_12_we; + reg_we_check[356] = mio_pad_sleep_regwen_13_we; + reg_we_check[357] = mio_pad_sleep_regwen_14_we; + reg_we_check[358] = mio_pad_sleep_regwen_15_we; + reg_we_check[359] = mio_pad_sleep_regwen_16_we; + reg_we_check[360] = mio_pad_sleep_regwen_17_we; + reg_we_check[361] = mio_pad_sleep_regwen_18_we; + reg_we_check[362] = mio_pad_sleep_regwen_19_we; + reg_we_check[363] = mio_pad_sleep_regwen_20_we; + reg_we_check[364] = mio_pad_sleep_regwen_21_we; + reg_we_check[365] = mio_pad_sleep_regwen_22_we; + reg_we_check[366] = mio_pad_sleep_regwen_23_we; + reg_we_check[367] = mio_pad_sleep_regwen_24_we; + reg_we_check[368] = mio_pad_sleep_regwen_25_we; + reg_we_check[369] = mio_pad_sleep_regwen_26_we; + reg_we_check[370] = mio_pad_sleep_regwen_27_we; + reg_we_check[371] = mio_pad_sleep_regwen_28_we; + reg_we_check[372] = mio_pad_sleep_regwen_29_we; + reg_we_check[373] = mio_pad_sleep_regwen_30_we; + reg_we_check[374] = mio_pad_sleep_regwen_31_we; + reg_we_check[375] = mio_pad_sleep_regwen_32_we; + reg_we_check[376] = mio_pad_sleep_regwen_33_we; + reg_we_check[377] = mio_pad_sleep_regwen_34_we; + reg_we_check[378] = mio_pad_sleep_regwen_35_we; + reg_we_check[379] = mio_pad_sleep_regwen_36_we; + reg_we_check[380] = mio_pad_sleep_regwen_37_we; + reg_we_check[381] = mio_pad_sleep_regwen_38_we; + reg_we_check[382] = mio_pad_sleep_regwen_39_we; + reg_we_check[383] = mio_pad_sleep_regwen_40_we; + reg_we_check[384] = mio_pad_sleep_regwen_41_we; + reg_we_check[385] = mio_pad_sleep_regwen_42_we; + reg_we_check[386] = mio_pad_sleep_regwen_43_we; + reg_we_check[387] = mio_pad_sleep_regwen_44_we; + reg_we_check[388] = mio_pad_sleep_regwen_45_we; + reg_we_check[389] = mio_pad_sleep_regwen_46_we; + reg_we_check[390] = mio_pad_sleep_en_0_gated_we; + reg_we_check[391] = mio_pad_sleep_en_1_gated_we; + reg_we_check[392] = mio_pad_sleep_en_2_gated_we; + reg_we_check[393] = mio_pad_sleep_en_3_gated_we; + reg_we_check[394] = mio_pad_sleep_en_4_gated_we; + reg_we_check[395] = mio_pad_sleep_en_5_gated_we; + reg_we_check[396] = mio_pad_sleep_en_6_gated_we; + reg_we_check[397] = mio_pad_sleep_en_7_gated_we; + reg_we_check[398] = mio_pad_sleep_en_8_gated_we; + reg_we_check[399] = mio_pad_sleep_en_9_gated_we; + reg_we_check[400] = mio_pad_sleep_en_10_gated_we; + reg_we_check[401] = mio_pad_sleep_en_11_gated_we; + reg_we_check[402] = mio_pad_sleep_en_12_gated_we; + reg_we_check[403] = mio_pad_sleep_en_13_gated_we; + reg_we_check[404] = mio_pad_sleep_en_14_gated_we; + reg_we_check[405] = mio_pad_sleep_en_15_gated_we; + reg_we_check[406] = mio_pad_sleep_en_16_gated_we; + reg_we_check[407] = mio_pad_sleep_en_17_gated_we; + reg_we_check[408] = mio_pad_sleep_en_18_gated_we; + reg_we_check[409] = mio_pad_sleep_en_19_gated_we; + reg_we_check[410] = mio_pad_sleep_en_20_gated_we; + reg_we_check[411] = mio_pad_sleep_en_21_gated_we; + reg_we_check[412] = mio_pad_sleep_en_22_gated_we; + reg_we_check[413] = mio_pad_sleep_en_23_gated_we; + reg_we_check[414] = mio_pad_sleep_en_24_gated_we; + reg_we_check[415] = mio_pad_sleep_en_25_gated_we; + reg_we_check[416] = mio_pad_sleep_en_26_gated_we; + reg_we_check[417] = mio_pad_sleep_en_27_gated_we; + reg_we_check[418] = mio_pad_sleep_en_28_gated_we; + reg_we_check[419] = mio_pad_sleep_en_29_gated_we; + reg_we_check[420] = mio_pad_sleep_en_30_gated_we; + reg_we_check[421] = mio_pad_sleep_en_31_gated_we; + reg_we_check[422] = mio_pad_sleep_en_32_gated_we; + reg_we_check[423] = mio_pad_sleep_en_33_gated_we; + reg_we_check[424] = mio_pad_sleep_en_34_gated_we; + reg_we_check[425] = mio_pad_sleep_en_35_gated_we; + reg_we_check[426] = mio_pad_sleep_en_36_gated_we; + reg_we_check[427] = mio_pad_sleep_en_37_gated_we; + reg_we_check[428] = mio_pad_sleep_en_38_gated_we; + reg_we_check[429] = mio_pad_sleep_en_39_gated_we; + reg_we_check[430] = mio_pad_sleep_en_40_gated_we; + reg_we_check[431] = mio_pad_sleep_en_41_gated_we; + reg_we_check[432] = mio_pad_sleep_en_42_gated_we; + reg_we_check[433] = mio_pad_sleep_en_43_gated_we; + reg_we_check[434] = mio_pad_sleep_en_44_gated_we; + reg_we_check[435] = mio_pad_sleep_en_45_gated_we; + reg_we_check[436] = mio_pad_sleep_en_46_gated_we; + reg_we_check[437] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[438] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[439] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[440] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[441] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[442] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[443] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[444] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[445] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[446] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[447] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[448] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[449] = mio_pad_sleep_mode_12_gated_we; + reg_we_check[450] = mio_pad_sleep_mode_13_gated_we; + reg_we_check[451] = mio_pad_sleep_mode_14_gated_we; + reg_we_check[452] = mio_pad_sleep_mode_15_gated_we; + reg_we_check[453] = mio_pad_sleep_mode_16_gated_we; + reg_we_check[454] = mio_pad_sleep_mode_17_gated_we; + reg_we_check[455] = mio_pad_sleep_mode_18_gated_we; + reg_we_check[456] = mio_pad_sleep_mode_19_gated_we; + reg_we_check[457] = mio_pad_sleep_mode_20_gated_we; + reg_we_check[458] = mio_pad_sleep_mode_21_gated_we; + reg_we_check[459] = mio_pad_sleep_mode_22_gated_we; + reg_we_check[460] = mio_pad_sleep_mode_23_gated_we; + reg_we_check[461] = mio_pad_sleep_mode_24_gated_we; + reg_we_check[462] = mio_pad_sleep_mode_25_gated_we; + reg_we_check[463] = mio_pad_sleep_mode_26_gated_we; + reg_we_check[464] = mio_pad_sleep_mode_27_gated_we; + reg_we_check[465] = mio_pad_sleep_mode_28_gated_we; + reg_we_check[466] = mio_pad_sleep_mode_29_gated_we; + reg_we_check[467] = mio_pad_sleep_mode_30_gated_we; + reg_we_check[468] = mio_pad_sleep_mode_31_gated_we; + reg_we_check[469] = mio_pad_sleep_mode_32_gated_we; + reg_we_check[470] = mio_pad_sleep_mode_33_gated_we; + reg_we_check[471] = mio_pad_sleep_mode_34_gated_we; + reg_we_check[472] = mio_pad_sleep_mode_35_gated_we; + reg_we_check[473] = mio_pad_sleep_mode_36_gated_we; + reg_we_check[474] = mio_pad_sleep_mode_37_gated_we; + reg_we_check[475] = mio_pad_sleep_mode_38_gated_we; + reg_we_check[476] = mio_pad_sleep_mode_39_gated_we; + reg_we_check[477] = mio_pad_sleep_mode_40_gated_we; + reg_we_check[478] = mio_pad_sleep_mode_41_gated_we; + reg_we_check[479] = mio_pad_sleep_mode_42_gated_we; + reg_we_check[480] = mio_pad_sleep_mode_43_gated_we; + reg_we_check[481] = mio_pad_sleep_mode_44_gated_we; + reg_we_check[482] = mio_pad_sleep_mode_45_gated_we; + reg_we_check[483] = mio_pad_sleep_mode_46_gated_we; + reg_we_check[484] = dio_pad_sleep_status_we; + reg_we_check[485] = dio_pad_sleep_regwen_0_we; + reg_we_check[486] = dio_pad_sleep_regwen_1_we; + reg_we_check[487] = dio_pad_sleep_regwen_2_we; + reg_we_check[488] = dio_pad_sleep_regwen_3_we; + reg_we_check[489] = dio_pad_sleep_regwen_4_we; + reg_we_check[490] = dio_pad_sleep_regwen_5_we; + reg_we_check[491] = dio_pad_sleep_regwen_6_we; + reg_we_check[492] = dio_pad_sleep_regwen_7_we; + reg_we_check[493] = dio_pad_sleep_regwen_8_we; + reg_we_check[494] = dio_pad_sleep_regwen_9_we; + reg_we_check[495] = dio_pad_sleep_regwen_10_we; + reg_we_check[496] = dio_pad_sleep_regwen_11_we; + reg_we_check[497] = dio_pad_sleep_regwen_12_we; + reg_we_check[498] = dio_pad_sleep_regwen_13_we; + reg_we_check[499] = dio_pad_sleep_regwen_14_we; + reg_we_check[500] = dio_pad_sleep_regwen_15_we; + reg_we_check[501] = dio_pad_sleep_en_0_gated_we; + reg_we_check[502] = dio_pad_sleep_en_1_gated_we; + reg_we_check[503] = dio_pad_sleep_en_2_gated_we; + reg_we_check[504] = dio_pad_sleep_en_3_gated_we; + reg_we_check[505] = dio_pad_sleep_en_4_gated_we; + reg_we_check[506] = dio_pad_sleep_en_5_gated_we; + reg_we_check[507] = dio_pad_sleep_en_6_gated_we; + reg_we_check[508] = dio_pad_sleep_en_7_gated_we; + reg_we_check[509] = dio_pad_sleep_en_8_gated_we; + reg_we_check[510] = dio_pad_sleep_en_9_gated_we; + reg_we_check[511] = dio_pad_sleep_en_10_gated_we; + reg_we_check[512] = dio_pad_sleep_en_11_gated_we; + reg_we_check[513] = dio_pad_sleep_en_12_gated_we; + reg_we_check[514] = dio_pad_sleep_en_13_gated_we; + reg_we_check[515] = dio_pad_sleep_en_14_gated_we; + reg_we_check[516] = dio_pad_sleep_en_15_gated_we; + reg_we_check[517] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[518] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[519] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[520] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[521] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[522] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[523] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[524] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[525] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[526] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[527] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[528] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[529] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[530] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[531] = dio_pad_sleep_mode_14_gated_we; + reg_we_check[532] = dio_pad_sleep_mode_15_gated_we; + reg_we_check[533] = wkup_detector_regwen_0_we; + reg_we_check[534] = wkup_detector_regwen_1_we; + reg_we_check[535] = wkup_detector_regwen_2_we; + reg_we_check[536] = wkup_detector_regwen_3_we; + reg_we_check[537] = wkup_detector_regwen_4_we; + reg_we_check[538] = wkup_detector_regwen_5_we; + reg_we_check[539] = wkup_detector_regwen_6_we; + reg_we_check[540] = wkup_detector_regwen_7_we; + reg_we_check[541] = wkup_detector_en_0_we; + reg_we_check[542] = wkup_detector_en_1_we; + reg_we_check[543] = wkup_detector_en_2_we; + reg_we_check[544] = wkup_detector_en_3_we; + reg_we_check[545] = wkup_detector_en_4_we; + reg_we_check[546] = wkup_detector_en_5_we; + reg_we_check[547] = wkup_detector_en_6_we; + reg_we_check[548] = wkup_detector_en_7_we; + reg_we_check[549] = wkup_detector_0_we; + reg_we_check[550] = wkup_detector_1_we; + reg_we_check[551] = wkup_detector_2_we; + reg_we_check[552] = wkup_detector_3_we; + reg_we_check[553] = wkup_detector_4_we; + reg_we_check[554] = wkup_detector_5_we; + reg_we_check[555] = wkup_detector_6_we; + reg_we_check[556] = wkup_detector_7_we; + reg_we_check[557] = wkup_detector_cnt_th_0_we; + reg_we_check[558] = wkup_detector_cnt_th_1_we; + reg_we_check[559] = wkup_detector_cnt_th_2_we; + reg_we_check[560] = wkup_detector_cnt_th_3_we; + reg_we_check[561] = wkup_detector_cnt_th_4_we; + reg_we_check[562] = wkup_detector_cnt_th_5_we; + reg_we_check[563] = wkup_detector_cnt_th_6_we; + reg_we_check[564] = wkup_detector_cnt_th_7_we; + reg_we_check[565] = wkup_detector_padsel_0_gated_we; + reg_we_check[566] = wkup_detector_padsel_1_gated_we; + reg_we_check[567] = wkup_detector_padsel_2_gated_we; + reg_we_check[568] = wkup_detector_padsel_3_gated_we; + reg_we_check[569] = wkup_detector_padsel_4_gated_we; + reg_we_check[570] = wkup_detector_padsel_5_gated_we; + reg_we_check[571] = wkup_detector_padsel_6_gated_we; + reg_we_check[572] = wkup_detector_padsel_7_gated_we; + reg_we_check[573] = wkup_cause_we; end // Read data return @@ -37504,798 +37741,822 @@ module pinmux_reg_top ( end addr_hit[58]: begin - reg_rdata_next[5:0] = mio_periph_insel_0_qs; + reg_rdata_next[0] = mio_periph_insel_regwen_57_qs; end addr_hit[59]: begin - reg_rdata_next[5:0] = mio_periph_insel_1_qs; + reg_rdata_next[0] = mio_periph_insel_regwen_58_qs; end addr_hit[60]: begin - reg_rdata_next[5:0] = mio_periph_insel_2_qs; + reg_rdata_next[0] = mio_periph_insel_regwen_59_qs; end addr_hit[61]: begin - reg_rdata_next[5:0] = mio_periph_insel_3_qs; + reg_rdata_next[5:0] = mio_periph_insel_0_qs; end addr_hit[62]: begin - reg_rdata_next[5:0] = mio_periph_insel_4_qs; + reg_rdata_next[5:0] = mio_periph_insel_1_qs; end addr_hit[63]: begin - reg_rdata_next[5:0] = mio_periph_insel_5_qs; + reg_rdata_next[5:0] = mio_periph_insel_2_qs; end addr_hit[64]: begin - reg_rdata_next[5:0] = mio_periph_insel_6_qs; + reg_rdata_next[5:0] = mio_periph_insel_3_qs; end addr_hit[65]: begin - reg_rdata_next[5:0] = mio_periph_insel_7_qs; + reg_rdata_next[5:0] = mio_periph_insel_4_qs; end addr_hit[66]: begin - reg_rdata_next[5:0] = mio_periph_insel_8_qs; + reg_rdata_next[5:0] = mio_periph_insel_5_qs; end addr_hit[67]: begin - reg_rdata_next[5:0] = mio_periph_insel_9_qs; + reg_rdata_next[5:0] = mio_periph_insel_6_qs; end addr_hit[68]: begin - reg_rdata_next[5:0] = mio_periph_insel_10_qs; + reg_rdata_next[5:0] = mio_periph_insel_7_qs; end addr_hit[69]: begin - reg_rdata_next[5:0] = mio_periph_insel_11_qs; + reg_rdata_next[5:0] = mio_periph_insel_8_qs; end addr_hit[70]: begin - reg_rdata_next[5:0] = mio_periph_insel_12_qs; + reg_rdata_next[5:0] = mio_periph_insel_9_qs; end addr_hit[71]: begin - reg_rdata_next[5:0] = mio_periph_insel_13_qs; + reg_rdata_next[5:0] = mio_periph_insel_10_qs; end addr_hit[72]: begin - reg_rdata_next[5:0] = mio_periph_insel_14_qs; + reg_rdata_next[5:0] = mio_periph_insel_11_qs; end addr_hit[73]: begin - reg_rdata_next[5:0] = mio_periph_insel_15_qs; + reg_rdata_next[5:0] = mio_periph_insel_12_qs; end addr_hit[74]: begin - reg_rdata_next[5:0] = mio_periph_insel_16_qs; + reg_rdata_next[5:0] = mio_periph_insel_13_qs; end addr_hit[75]: begin - reg_rdata_next[5:0] = mio_periph_insel_17_qs; + reg_rdata_next[5:0] = mio_periph_insel_14_qs; end addr_hit[76]: begin - reg_rdata_next[5:0] = mio_periph_insel_18_qs; + reg_rdata_next[5:0] = mio_periph_insel_15_qs; end addr_hit[77]: begin - reg_rdata_next[5:0] = mio_periph_insel_19_qs; + reg_rdata_next[5:0] = mio_periph_insel_16_qs; end addr_hit[78]: begin - reg_rdata_next[5:0] = mio_periph_insel_20_qs; + reg_rdata_next[5:0] = mio_periph_insel_17_qs; end addr_hit[79]: begin - reg_rdata_next[5:0] = mio_periph_insel_21_qs; + reg_rdata_next[5:0] = mio_periph_insel_18_qs; end addr_hit[80]: begin - reg_rdata_next[5:0] = mio_periph_insel_22_qs; + reg_rdata_next[5:0] = mio_periph_insel_19_qs; end addr_hit[81]: begin - reg_rdata_next[5:0] = mio_periph_insel_23_qs; + reg_rdata_next[5:0] = mio_periph_insel_20_qs; end addr_hit[82]: begin - reg_rdata_next[5:0] = mio_periph_insel_24_qs; + reg_rdata_next[5:0] = mio_periph_insel_21_qs; end addr_hit[83]: begin - reg_rdata_next[5:0] = mio_periph_insel_25_qs; + reg_rdata_next[5:0] = mio_periph_insel_22_qs; end addr_hit[84]: begin - reg_rdata_next[5:0] = mio_periph_insel_26_qs; + reg_rdata_next[5:0] = mio_periph_insel_23_qs; end addr_hit[85]: begin - reg_rdata_next[5:0] = mio_periph_insel_27_qs; + reg_rdata_next[5:0] = mio_periph_insel_24_qs; end addr_hit[86]: begin - reg_rdata_next[5:0] = mio_periph_insel_28_qs; + reg_rdata_next[5:0] = mio_periph_insel_25_qs; end addr_hit[87]: begin - reg_rdata_next[5:0] = mio_periph_insel_29_qs; + reg_rdata_next[5:0] = mio_periph_insel_26_qs; end addr_hit[88]: begin - reg_rdata_next[5:0] = mio_periph_insel_30_qs; + reg_rdata_next[5:0] = mio_periph_insel_27_qs; end addr_hit[89]: begin - reg_rdata_next[5:0] = mio_periph_insel_31_qs; + reg_rdata_next[5:0] = mio_periph_insel_28_qs; end addr_hit[90]: begin - reg_rdata_next[5:0] = mio_periph_insel_32_qs; + reg_rdata_next[5:0] = mio_periph_insel_29_qs; end addr_hit[91]: begin - reg_rdata_next[5:0] = mio_periph_insel_33_qs; + reg_rdata_next[5:0] = mio_periph_insel_30_qs; end addr_hit[92]: begin - reg_rdata_next[5:0] = mio_periph_insel_34_qs; + reg_rdata_next[5:0] = mio_periph_insel_31_qs; end addr_hit[93]: begin - reg_rdata_next[5:0] = mio_periph_insel_35_qs; + reg_rdata_next[5:0] = mio_periph_insel_32_qs; end addr_hit[94]: begin - reg_rdata_next[5:0] = mio_periph_insel_36_qs; + reg_rdata_next[5:0] = mio_periph_insel_33_qs; end addr_hit[95]: begin - reg_rdata_next[5:0] = mio_periph_insel_37_qs; + reg_rdata_next[5:0] = mio_periph_insel_34_qs; end addr_hit[96]: begin - reg_rdata_next[5:0] = mio_periph_insel_38_qs; + reg_rdata_next[5:0] = mio_periph_insel_35_qs; end addr_hit[97]: begin - reg_rdata_next[5:0] = mio_periph_insel_39_qs; + reg_rdata_next[5:0] = mio_periph_insel_36_qs; end addr_hit[98]: begin - reg_rdata_next[5:0] = mio_periph_insel_40_qs; + reg_rdata_next[5:0] = mio_periph_insel_37_qs; end addr_hit[99]: begin - reg_rdata_next[5:0] = mio_periph_insel_41_qs; + reg_rdata_next[5:0] = mio_periph_insel_38_qs; end addr_hit[100]: begin - reg_rdata_next[5:0] = mio_periph_insel_42_qs; + reg_rdata_next[5:0] = mio_periph_insel_39_qs; end addr_hit[101]: begin - reg_rdata_next[5:0] = mio_periph_insel_43_qs; + reg_rdata_next[5:0] = mio_periph_insel_40_qs; end addr_hit[102]: begin - reg_rdata_next[5:0] = mio_periph_insel_44_qs; + reg_rdata_next[5:0] = mio_periph_insel_41_qs; end addr_hit[103]: begin - reg_rdata_next[5:0] = mio_periph_insel_45_qs; + reg_rdata_next[5:0] = mio_periph_insel_42_qs; end addr_hit[104]: begin - reg_rdata_next[5:0] = mio_periph_insel_46_qs; + reg_rdata_next[5:0] = mio_periph_insel_43_qs; end addr_hit[105]: begin - reg_rdata_next[5:0] = mio_periph_insel_47_qs; + reg_rdata_next[5:0] = mio_periph_insel_44_qs; end addr_hit[106]: begin - reg_rdata_next[5:0] = mio_periph_insel_48_qs; + reg_rdata_next[5:0] = mio_periph_insel_45_qs; end addr_hit[107]: begin - reg_rdata_next[5:0] = mio_periph_insel_49_qs; + reg_rdata_next[5:0] = mio_periph_insel_46_qs; end addr_hit[108]: begin - reg_rdata_next[5:0] = mio_periph_insel_50_qs; + reg_rdata_next[5:0] = mio_periph_insel_47_qs; end addr_hit[109]: begin - reg_rdata_next[5:0] = mio_periph_insel_51_qs; + reg_rdata_next[5:0] = mio_periph_insel_48_qs; end addr_hit[110]: begin - reg_rdata_next[5:0] = mio_periph_insel_52_qs; + reg_rdata_next[5:0] = mio_periph_insel_49_qs; end addr_hit[111]: begin - reg_rdata_next[5:0] = mio_periph_insel_53_qs; + reg_rdata_next[5:0] = mio_periph_insel_50_qs; end addr_hit[112]: begin - reg_rdata_next[5:0] = mio_periph_insel_54_qs; + reg_rdata_next[5:0] = mio_periph_insel_51_qs; end addr_hit[113]: begin - reg_rdata_next[5:0] = mio_periph_insel_55_qs; + reg_rdata_next[5:0] = mio_periph_insel_52_qs; end addr_hit[114]: begin - reg_rdata_next[5:0] = mio_periph_insel_56_qs; + reg_rdata_next[5:0] = mio_periph_insel_53_qs; end addr_hit[115]: begin - reg_rdata_next[0] = mio_outsel_regwen_0_qs; + reg_rdata_next[5:0] = mio_periph_insel_54_qs; end addr_hit[116]: begin - reg_rdata_next[0] = mio_outsel_regwen_1_qs; + reg_rdata_next[5:0] = mio_periph_insel_55_qs; end addr_hit[117]: begin - reg_rdata_next[0] = mio_outsel_regwen_2_qs; + reg_rdata_next[5:0] = mio_periph_insel_56_qs; end addr_hit[118]: begin - reg_rdata_next[0] = mio_outsel_regwen_3_qs; + reg_rdata_next[5:0] = mio_periph_insel_57_qs; end addr_hit[119]: begin - reg_rdata_next[0] = mio_outsel_regwen_4_qs; + reg_rdata_next[5:0] = mio_periph_insel_58_qs; end addr_hit[120]: begin - reg_rdata_next[0] = mio_outsel_regwen_5_qs; + reg_rdata_next[5:0] = mio_periph_insel_59_qs; end addr_hit[121]: begin - reg_rdata_next[0] = mio_outsel_regwen_6_qs; + reg_rdata_next[0] = mio_outsel_regwen_0_qs; end addr_hit[122]: begin - reg_rdata_next[0] = mio_outsel_regwen_7_qs; + reg_rdata_next[0] = mio_outsel_regwen_1_qs; end addr_hit[123]: begin - reg_rdata_next[0] = mio_outsel_regwen_8_qs; + reg_rdata_next[0] = mio_outsel_regwen_2_qs; end addr_hit[124]: begin - reg_rdata_next[0] = mio_outsel_regwen_9_qs; + reg_rdata_next[0] = mio_outsel_regwen_3_qs; end addr_hit[125]: begin - reg_rdata_next[0] = mio_outsel_regwen_10_qs; + reg_rdata_next[0] = mio_outsel_regwen_4_qs; end addr_hit[126]: begin - reg_rdata_next[0] = mio_outsel_regwen_11_qs; + reg_rdata_next[0] = mio_outsel_regwen_5_qs; end addr_hit[127]: begin - reg_rdata_next[0] = mio_outsel_regwen_12_qs; + reg_rdata_next[0] = mio_outsel_regwen_6_qs; end addr_hit[128]: begin - reg_rdata_next[0] = mio_outsel_regwen_13_qs; + reg_rdata_next[0] = mio_outsel_regwen_7_qs; end addr_hit[129]: begin - reg_rdata_next[0] = mio_outsel_regwen_14_qs; + reg_rdata_next[0] = mio_outsel_regwen_8_qs; end addr_hit[130]: begin - reg_rdata_next[0] = mio_outsel_regwen_15_qs; + reg_rdata_next[0] = mio_outsel_regwen_9_qs; end addr_hit[131]: begin - reg_rdata_next[0] = mio_outsel_regwen_16_qs; + reg_rdata_next[0] = mio_outsel_regwen_10_qs; end addr_hit[132]: begin - reg_rdata_next[0] = mio_outsel_regwen_17_qs; + reg_rdata_next[0] = mio_outsel_regwen_11_qs; end addr_hit[133]: begin - reg_rdata_next[0] = mio_outsel_regwen_18_qs; + reg_rdata_next[0] = mio_outsel_regwen_12_qs; end addr_hit[134]: begin - reg_rdata_next[0] = mio_outsel_regwen_19_qs; + reg_rdata_next[0] = mio_outsel_regwen_13_qs; end addr_hit[135]: begin - reg_rdata_next[0] = mio_outsel_regwen_20_qs; + reg_rdata_next[0] = mio_outsel_regwen_14_qs; end addr_hit[136]: begin - reg_rdata_next[0] = mio_outsel_regwen_21_qs; + reg_rdata_next[0] = mio_outsel_regwen_15_qs; end addr_hit[137]: begin - reg_rdata_next[0] = mio_outsel_regwen_22_qs; + reg_rdata_next[0] = mio_outsel_regwen_16_qs; end addr_hit[138]: begin - reg_rdata_next[0] = mio_outsel_regwen_23_qs; + reg_rdata_next[0] = mio_outsel_regwen_17_qs; end addr_hit[139]: begin - reg_rdata_next[0] = mio_outsel_regwen_24_qs; + reg_rdata_next[0] = mio_outsel_regwen_18_qs; end addr_hit[140]: begin - reg_rdata_next[0] = mio_outsel_regwen_25_qs; + reg_rdata_next[0] = mio_outsel_regwen_19_qs; end addr_hit[141]: begin - reg_rdata_next[0] = mio_outsel_regwen_26_qs; + reg_rdata_next[0] = mio_outsel_regwen_20_qs; end addr_hit[142]: begin - reg_rdata_next[0] = mio_outsel_regwen_27_qs; + reg_rdata_next[0] = mio_outsel_regwen_21_qs; end addr_hit[143]: begin - reg_rdata_next[0] = mio_outsel_regwen_28_qs; + reg_rdata_next[0] = mio_outsel_regwen_22_qs; end addr_hit[144]: begin - reg_rdata_next[0] = mio_outsel_regwen_29_qs; + reg_rdata_next[0] = mio_outsel_regwen_23_qs; end addr_hit[145]: begin - reg_rdata_next[0] = mio_outsel_regwen_30_qs; + reg_rdata_next[0] = mio_outsel_regwen_24_qs; end addr_hit[146]: begin - reg_rdata_next[0] = mio_outsel_regwen_31_qs; + reg_rdata_next[0] = mio_outsel_regwen_25_qs; end addr_hit[147]: begin - reg_rdata_next[0] = mio_outsel_regwen_32_qs; + reg_rdata_next[0] = mio_outsel_regwen_26_qs; end addr_hit[148]: begin - reg_rdata_next[0] = mio_outsel_regwen_33_qs; + reg_rdata_next[0] = mio_outsel_regwen_27_qs; end addr_hit[149]: begin - reg_rdata_next[0] = mio_outsel_regwen_34_qs; + reg_rdata_next[0] = mio_outsel_regwen_28_qs; end addr_hit[150]: begin - reg_rdata_next[0] = mio_outsel_regwen_35_qs; + reg_rdata_next[0] = mio_outsel_regwen_29_qs; end addr_hit[151]: begin - reg_rdata_next[0] = mio_outsel_regwen_36_qs; + reg_rdata_next[0] = mio_outsel_regwen_30_qs; end addr_hit[152]: begin - reg_rdata_next[0] = mio_outsel_regwen_37_qs; + reg_rdata_next[0] = mio_outsel_regwen_31_qs; end addr_hit[153]: begin - reg_rdata_next[0] = mio_outsel_regwen_38_qs; + reg_rdata_next[0] = mio_outsel_regwen_32_qs; end addr_hit[154]: begin - reg_rdata_next[0] = mio_outsel_regwen_39_qs; + reg_rdata_next[0] = mio_outsel_regwen_33_qs; end addr_hit[155]: begin - reg_rdata_next[0] = mio_outsel_regwen_40_qs; + reg_rdata_next[0] = mio_outsel_regwen_34_qs; end addr_hit[156]: begin - reg_rdata_next[0] = mio_outsel_regwen_41_qs; + reg_rdata_next[0] = mio_outsel_regwen_35_qs; end addr_hit[157]: begin - reg_rdata_next[0] = mio_outsel_regwen_42_qs; + reg_rdata_next[0] = mio_outsel_regwen_36_qs; end addr_hit[158]: begin - reg_rdata_next[0] = mio_outsel_regwen_43_qs; + reg_rdata_next[0] = mio_outsel_regwen_37_qs; end addr_hit[159]: begin - reg_rdata_next[0] = mio_outsel_regwen_44_qs; + reg_rdata_next[0] = mio_outsel_regwen_38_qs; end addr_hit[160]: begin - reg_rdata_next[0] = mio_outsel_regwen_45_qs; + reg_rdata_next[0] = mio_outsel_regwen_39_qs; end addr_hit[161]: begin - reg_rdata_next[0] = mio_outsel_regwen_46_qs; + reg_rdata_next[0] = mio_outsel_regwen_40_qs; end addr_hit[162]: begin - reg_rdata_next[6:0] = mio_outsel_0_qs; + reg_rdata_next[0] = mio_outsel_regwen_41_qs; end addr_hit[163]: begin - reg_rdata_next[6:0] = mio_outsel_1_qs; + reg_rdata_next[0] = mio_outsel_regwen_42_qs; end addr_hit[164]: begin - reg_rdata_next[6:0] = mio_outsel_2_qs; + reg_rdata_next[0] = mio_outsel_regwen_43_qs; end addr_hit[165]: begin - reg_rdata_next[6:0] = mio_outsel_3_qs; + reg_rdata_next[0] = mio_outsel_regwen_44_qs; end addr_hit[166]: begin - reg_rdata_next[6:0] = mio_outsel_4_qs; + reg_rdata_next[0] = mio_outsel_regwen_45_qs; end addr_hit[167]: begin - reg_rdata_next[6:0] = mio_outsel_5_qs; + reg_rdata_next[0] = mio_outsel_regwen_46_qs; end addr_hit[168]: begin - reg_rdata_next[6:0] = mio_outsel_6_qs; + reg_rdata_next[6:0] = mio_outsel_0_qs; end addr_hit[169]: begin - reg_rdata_next[6:0] = mio_outsel_7_qs; + reg_rdata_next[6:0] = mio_outsel_1_qs; end addr_hit[170]: begin - reg_rdata_next[6:0] = mio_outsel_8_qs; + reg_rdata_next[6:0] = mio_outsel_2_qs; end addr_hit[171]: begin - reg_rdata_next[6:0] = mio_outsel_9_qs; + reg_rdata_next[6:0] = mio_outsel_3_qs; end addr_hit[172]: begin - reg_rdata_next[6:0] = mio_outsel_10_qs; + reg_rdata_next[6:0] = mio_outsel_4_qs; end addr_hit[173]: begin - reg_rdata_next[6:0] = mio_outsel_11_qs; + reg_rdata_next[6:0] = mio_outsel_5_qs; end addr_hit[174]: begin - reg_rdata_next[6:0] = mio_outsel_12_qs; + reg_rdata_next[6:0] = mio_outsel_6_qs; end addr_hit[175]: begin - reg_rdata_next[6:0] = mio_outsel_13_qs; + reg_rdata_next[6:0] = mio_outsel_7_qs; end addr_hit[176]: begin - reg_rdata_next[6:0] = mio_outsel_14_qs; + reg_rdata_next[6:0] = mio_outsel_8_qs; end addr_hit[177]: begin - reg_rdata_next[6:0] = mio_outsel_15_qs; + reg_rdata_next[6:0] = mio_outsel_9_qs; end addr_hit[178]: begin - reg_rdata_next[6:0] = mio_outsel_16_qs; + reg_rdata_next[6:0] = mio_outsel_10_qs; end addr_hit[179]: begin - reg_rdata_next[6:0] = mio_outsel_17_qs; + reg_rdata_next[6:0] = mio_outsel_11_qs; end addr_hit[180]: begin - reg_rdata_next[6:0] = mio_outsel_18_qs; + reg_rdata_next[6:0] = mio_outsel_12_qs; end addr_hit[181]: begin - reg_rdata_next[6:0] = mio_outsel_19_qs; + reg_rdata_next[6:0] = mio_outsel_13_qs; end addr_hit[182]: begin - reg_rdata_next[6:0] = mio_outsel_20_qs; + reg_rdata_next[6:0] = mio_outsel_14_qs; end addr_hit[183]: begin - reg_rdata_next[6:0] = mio_outsel_21_qs; + reg_rdata_next[6:0] = mio_outsel_15_qs; end addr_hit[184]: begin - reg_rdata_next[6:0] = mio_outsel_22_qs; + reg_rdata_next[6:0] = mio_outsel_16_qs; end addr_hit[185]: begin - reg_rdata_next[6:0] = mio_outsel_23_qs; + reg_rdata_next[6:0] = mio_outsel_17_qs; end addr_hit[186]: begin - reg_rdata_next[6:0] = mio_outsel_24_qs; + reg_rdata_next[6:0] = mio_outsel_18_qs; end addr_hit[187]: begin - reg_rdata_next[6:0] = mio_outsel_25_qs; + reg_rdata_next[6:0] = mio_outsel_19_qs; end addr_hit[188]: begin - reg_rdata_next[6:0] = mio_outsel_26_qs; + reg_rdata_next[6:0] = mio_outsel_20_qs; end addr_hit[189]: begin - reg_rdata_next[6:0] = mio_outsel_27_qs; + reg_rdata_next[6:0] = mio_outsel_21_qs; end addr_hit[190]: begin - reg_rdata_next[6:0] = mio_outsel_28_qs; + reg_rdata_next[6:0] = mio_outsel_22_qs; end addr_hit[191]: begin - reg_rdata_next[6:0] = mio_outsel_29_qs; + reg_rdata_next[6:0] = mio_outsel_23_qs; end addr_hit[192]: begin - reg_rdata_next[6:0] = mio_outsel_30_qs; + reg_rdata_next[6:0] = mio_outsel_24_qs; end addr_hit[193]: begin - reg_rdata_next[6:0] = mio_outsel_31_qs; + reg_rdata_next[6:0] = mio_outsel_25_qs; end addr_hit[194]: begin - reg_rdata_next[6:0] = mio_outsel_32_qs; + reg_rdata_next[6:0] = mio_outsel_26_qs; end addr_hit[195]: begin - reg_rdata_next[6:0] = mio_outsel_33_qs; + reg_rdata_next[6:0] = mio_outsel_27_qs; end addr_hit[196]: begin - reg_rdata_next[6:0] = mio_outsel_34_qs; + reg_rdata_next[6:0] = mio_outsel_28_qs; end addr_hit[197]: begin - reg_rdata_next[6:0] = mio_outsel_35_qs; + reg_rdata_next[6:0] = mio_outsel_29_qs; end addr_hit[198]: begin - reg_rdata_next[6:0] = mio_outsel_36_qs; + reg_rdata_next[6:0] = mio_outsel_30_qs; end addr_hit[199]: begin - reg_rdata_next[6:0] = mio_outsel_37_qs; + reg_rdata_next[6:0] = mio_outsel_31_qs; end addr_hit[200]: begin - reg_rdata_next[6:0] = mio_outsel_38_qs; + reg_rdata_next[6:0] = mio_outsel_32_qs; end addr_hit[201]: begin - reg_rdata_next[6:0] = mio_outsel_39_qs; + reg_rdata_next[6:0] = mio_outsel_33_qs; end addr_hit[202]: begin - reg_rdata_next[6:0] = mio_outsel_40_qs; + reg_rdata_next[6:0] = mio_outsel_34_qs; end addr_hit[203]: begin - reg_rdata_next[6:0] = mio_outsel_41_qs; + reg_rdata_next[6:0] = mio_outsel_35_qs; end addr_hit[204]: begin - reg_rdata_next[6:0] = mio_outsel_42_qs; + reg_rdata_next[6:0] = mio_outsel_36_qs; end addr_hit[205]: begin - reg_rdata_next[6:0] = mio_outsel_43_qs; + reg_rdata_next[6:0] = mio_outsel_37_qs; end addr_hit[206]: begin - reg_rdata_next[6:0] = mio_outsel_44_qs; + reg_rdata_next[6:0] = mio_outsel_38_qs; end addr_hit[207]: begin - reg_rdata_next[6:0] = mio_outsel_45_qs; + reg_rdata_next[6:0] = mio_outsel_39_qs; end addr_hit[208]: begin - reg_rdata_next[6:0] = mio_outsel_46_qs; + reg_rdata_next[6:0] = mio_outsel_40_qs; end addr_hit[209]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; + reg_rdata_next[6:0] = mio_outsel_41_qs; end addr_hit[210]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; + reg_rdata_next[6:0] = mio_outsel_42_qs; end addr_hit[211]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; + reg_rdata_next[6:0] = mio_outsel_43_qs; end addr_hit[212]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; + reg_rdata_next[6:0] = mio_outsel_44_qs; end addr_hit[213]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; + reg_rdata_next[6:0] = mio_outsel_45_qs; end addr_hit[214]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; + reg_rdata_next[6:0] = mio_outsel_46_qs; end addr_hit[215]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end addr_hit[216]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end addr_hit[217]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end addr_hit[218]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end addr_hit[219]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end addr_hit[220]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end addr_hit[221]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end addr_hit[222]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end addr_hit[223]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end addr_hit[224]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end addr_hit[225]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end addr_hit[226]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end addr_hit[227]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end addr_hit[228]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end addr_hit[229]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end addr_hit[230]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end addr_hit[231]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end addr_hit[232]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end addr_hit[233]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end addr_hit[234]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end addr_hit[235]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end addr_hit[236]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end addr_hit[237]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end addr_hit[238]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end addr_hit[239]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end addr_hit[240]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end addr_hit[241]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end addr_hit[242]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end addr_hit[243]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end addr_hit[244]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end addr_hit[245]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end addr_hit[246]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end addr_hit[247]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; end addr_hit[248]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; end addr_hit[249]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; end addr_hit[250]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; end addr_hit[251]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; end addr_hit[252]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; end addr_hit[253]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; end addr_hit[254]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; end addr_hit[255]: begin - reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; + reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; end addr_hit[256]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; + end + + addr_hit[260]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; + end + + addr_hit[261]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; + end + + addr_hit[262]: begin reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; @@ -38308,7 +38569,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; end - addr_hit[257]: begin + addr_hit[263]: begin reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; @@ -38321,7 +38582,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; end - addr_hit[258]: begin + addr_hit[264]: begin reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; @@ -38334,7 +38595,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; end - addr_hit[259]: begin + addr_hit[265]: begin reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; @@ -38347,7 +38608,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; end - addr_hit[260]: begin + addr_hit[266]: begin reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; @@ -38360,7 +38621,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; end - addr_hit[261]: begin + addr_hit[267]: begin reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; @@ -38373,7 +38634,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; end - addr_hit[262]: begin + addr_hit[268]: begin reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; @@ -38386,7 +38647,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; end - addr_hit[263]: begin + addr_hit[269]: begin reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; @@ -38399,7 +38660,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; end - addr_hit[264]: begin + addr_hit[270]: begin reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; @@ -38412,7 +38673,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; end - addr_hit[265]: begin + addr_hit[271]: begin reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; @@ -38425,7 +38686,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; end - addr_hit[266]: begin + addr_hit[272]: begin reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; @@ -38438,7 +38699,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; end - addr_hit[267]: begin + addr_hit[273]: begin reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; @@ -38451,7 +38712,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; end - addr_hit[268]: begin + addr_hit[274]: begin reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs; @@ -38464,7 +38725,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs; end - addr_hit[269]: begin + addr_hit[275]: begin reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs; @@ -38477,7 +38738,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs; end - addr_hit[270]: begin + addr_hit[276]: begin reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs; @@ -38490,7 +38751,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs; end - addr_hit[271]: begin + addr_hit[277]: begin reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs; @@ -38503,7 +38764,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs; end - addr_hit[272]: begin + addr_hit[278]: begin reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs; reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs; reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs; @@ -38516,7 +38777,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs; end - addr_hit[273]: begin + addr_hit[279]: begin reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs; reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs; reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs; @@ -38529,7 +38790,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs; end - addr_hit[274]: begin + addr_hit[280]: begin reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs; reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs; reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs; @@ -38542,7 +38803,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs; end - addr_hit[275]: begin + addr_hit[281]: begin reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs; reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs; reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs; @@ -38555,7 +38816,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs; end - addr_hit[276]: begin + addr_hit[282]: begin reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs; reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs; reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs; @@ -38568,7 +38829,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs; end - addr_hit[277]: begin + addr_hit[283]: begin reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs; reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs; reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs; @@ -38581,7 +38842,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs; end - addr_hit[278]: begin + addr_hit[284]: begin reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs; reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs; reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs; @@ -38594,7 +38855,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs; end - addr_hit[279]: begin + addr_hit[285]: begin reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs; reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs; reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs; @@ -38607,7 +38868,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs; end - addr_hit[280]: begin + addr_hit[286]: begin reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs; reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs; reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs; @@ -38620,7 +38881,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs; end - addr_hit[281]: begin + addr_hit[287]: begin reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs; reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs; reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs; @@ -38633,7 +38894,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs; end - addr_hit[282]: begin + addr_hit[288]: begin reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs; reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs; reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs; @@ -38646,7 +38907,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs; end - addr_hit[283]: begin + addr_hit[289]: begin reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs; reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs; reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs; @@ -38659,7 +38920,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs; end - addr_hit[284]: begin + addr_hit[290]: begin reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs; reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs; reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs; @@ -38672,7 +38933,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs; end - addr_hit[285]: begin + addr_hit[291]: begin reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs; reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs; reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs; @@ -38685,7 +38946,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs; end - addr_hit[286]: begin + addr_hit[292]: begin reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs; reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs; reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs; @@ -38698,7 +38959,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs; end - addr_hit[287]: begin + addr_hit[293]: begin reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs; reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs; reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs; @@ -38711,7 +38972,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs; end - addr_hit[288]: begin + addr_hit[294]: begin reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs; reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs; reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs; @@ -38724,7 +38985,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs; end - addr_hit[289]: begin + addr_hit[295]: begin reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs; reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs; reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs; @@ -38737,7 +38998,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs; end - addr_hit[290]: begin + addr_hit[296]: begin reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs; reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs; reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs; @@ -38750,7 +39011,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs; end - addr_hit[291]: begin + addr_hit[297]: begin reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs; reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs; reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs; @@ -38763,7 +39024,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs; end - addr_hit[292]: begin + addr_hit[298]: begin reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs; reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs; reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs; @@ -38776,7 +39037,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs; end - addr_hit[293]: begin + addr_hit[299]: begin reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs; reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs; reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs; @@ -38789,7 +39050,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs; end - addr_hit[294]: begin + addr_hit[300]: begin reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs; reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs; reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs; @@ -38802,7 +39063,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs; end - addr_hit[295]: begin + addr_hit[301]: begin reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs; reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs; reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs; @@ -38815,7 +39076,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs; end - addr_hit[296]: begin + addr_hit[302]: begin reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs; reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs; reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs; @@ -38828,7 +39089,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs; end - addr_hit[297]: begin + addr_hit[303]: begin reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs; reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs; reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs; @@ -38841,7 +39102,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs; end - addr_hit[298]: begin + addr_hit[304]: begin reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs; reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs; reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs; @@ -38854,7 +39115,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs; end - addr_hit[299]: begin + addr_hit[305]: begin reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs; reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs; reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs; @@ -38867,7 +39128,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs; end - addr_hit[300]: begin + addr_hit[306]: begin reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs; reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs; reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs; @@ -38880,7 +39141,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs; end - addr_hit[301]: begin + addr_hit[307]: begin reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs; reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs; reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs; @@ -38893,7 +39154,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs; end - addr_hit[302]: begin + addr_hit[308]: begin reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs; reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs; reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs; @@ -38906,71 +39167,71 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs; end - addr_hit[303]: begin + addr_hit[309]: begin reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end - addr_hit[304]: begin + addr_hit[310]: begin reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end - addr_hit[305]: begin + addr_hit[311]: begin reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end - addr_hit[306]: begin + addr_hit[312]: begin reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end - addr_hit[307]: begin + addr_hit[313]: begin reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end - addr_hit[308]: begin + addr_hit[314]: begin reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end - addr_hit[309]: begin + addr_hit[315]: begin reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end - addr_hit[310]: begin + addr_hit[316]: begin reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end - addr_hit[311]: begin + addr_hit[317]: begin reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end - addr_hit[312]: begin + addr_hit[318]: begin reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end - addr_hit[313]: begin + addr_hit[319]: begin reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end - addr_hit[314]: begin + addr_hit[320]: begin reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end - addr_hit[315]: begin + addr_hit[321]: begin reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end - addr_hit[316]: begin + addr_hit[322]: begin reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end - addr_hit[317]: begin + addr_hit[323]: begin reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; end - addr_hit[318]: begin + addr_hit[324]: begin reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; end - addr_hit[319]: begin + addr_hit[325]: begin reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; @@ -38983,7 +39244,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; end - addr_hit[320]: begin + addr_hit[326]: begin reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; @@ -38996,7 +39257,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; end - addr_hit[321]: begin + addr_hit[327]: begin reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; @@ -39009,7 +39270,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; end - addr_hit[322]: begin + addr_hit[328]: begin reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; @@ -39022,7 +39283,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; end - addr_hit[323]: begin + addr_hit[329]: begin reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; @@ -39035,7 +39296,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; end - addr_hit[324]: begin + addr_hit[330]: begin reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; @@ -39048,7 +39309,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; end - addr_hit[325]: begin + addr_hit[331]: begin reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; @@ -39061,7 +39322,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; end - addr_hit[326]: begin + addr_hit[332]: begin reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; @@ -39074,7 +39335,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; end - addr_hit[327]: begin + addr_hit[333]: begin reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; @@ -39087,7 +39348,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; end - addr_hit[328]: begin + addr_hit[334]: begin reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; @@ -39100,7 +39361,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; end - addr_hit[329]: begin + addr_hit[335]: begin reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; @@ -39113,7 +39374,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; end - addr_hit[330]: begin + addr_hit[336]: begin reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; @@ -39126,7 +39387,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; end - addr_hit[331]: begin + addr_hit[337]: begin reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; @@ -39139,7 +39400,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; end - addr_hit[332]: begin + addr_hit[338]: begin reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; @@ -39152,7 +39413,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; end - addr_hit[333]: begin + addr_hit[339]: begin reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs; @@ -39165,7 +39426,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs; end - addr_hit[334]: begin + addr_hit[340]: begin reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs; @@ -39178,7 +39439,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs; end - addr_hit[335]: begin + addr_hit[341]: begin reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs; reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs; reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs; @@ -39213,7 +39474,7 @@ module pinmux_reg_top ( reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs; end - addr_hit[336]: begin + addr_hit[342]: begin reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs; reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs; reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs; @@ -39231,571 +39492,571 @@ module pinmux_reg_top ( reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs; end - addr_hit[337]: begin + addr_hit[343]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end - addr_hit[338]: begin + addr_hit[344]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end - addr_hit[339]: begin + addr_hit[345]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end - addr_hit[340]: begin + addr_hit[346]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end - addr_hit[341]: begin + addr_hit[347]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end - addr_hit[342]: begin + addr_hit[348]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end - addr_hit[343]: begin + addr_hit[349]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end - addr_hit[344]: begin + addr_hit[350]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end - addr_hit[345]: begin + addr_hit[351]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end - addr_hit[346]: begin + addr_hit[352]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end - addr_hit[347]: begin + addr_hit[353]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end - addr_hit[348]: begin + addr_hit[354]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end - addr_hit[349]: begin + addr_hit[355]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end - addr_hit[350]: begin + addr_hit[356]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end - addr_hit[351]: begin + addr_hit[357]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end - addr_hit[352]: begin + addr_hit[358]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; end - addr_hit[353]: begin + addr_hit[359]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; end - addr_hit[354]: begin + addr_hit[360]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; end - addr_hit[355]: begin + addr_hit[361]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; end - addr_hit[356]: begin + addr_hit[362]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; end - addr_hit[357]: begin + addr_hit[363]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; end - addr_hit[358]: begin + addr_hit[364]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; end - addr_hit[359]: begin + addr_hit[365]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; end - addr_hit[360]: begin + addr_hit[366]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; end - addr_hit[361]: begin + addr_hit[367]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; end - addr_hit[362]: begin + addr_hit[368]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; end - addr_hit[363]: begin + addr_hit[369]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; end - addr_hit[364]: begin + addr_hit[370]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; end - addr_hit[365]: begin + addr_hit[371]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; end - addr_hit[366]: begin + addr_hit[372]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; end - addr_hit[367]: begin + addr_hit[373]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; end - addr_hit[368]: begin + addr_hit[374]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; end - addr_hit[369]: begin + addr_hit[375]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs; end - addr_hit[370]: begin + addr_hit[376]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs; end - addr_hit[371]: begin + addr_hit[377]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs; end - addr_hit[372]: begin + addr_hit[378]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs; end - addr_hit[373]: begin + addr_hit[379]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs; end - addr_hit[374]: begin + addr_hit[380]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs; end - addr_hit[375]: begin + addr_hit[381]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs; end - addr_hit[376]: begin + addr_hit[382]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs; end - addr_hit[377]: begin + addr_hit[383]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs; end - addr_hit[378]: begin + addr_hit[384]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs; end - addr_hit[379]: begin + addr_hit[385]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs; end - addr_hit[380]: begin + addr_hit[386]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs; end - addr_hit[381]: begin + addr_hit[387]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs; end - addr_hit[382]: begin + addr_hit[388]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs; end - addr_hit[383]: begin + addr_hit[389]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs; end - addr_hit[384]: begin + addr_hit[390]: begin reg_rdata_next[0] = mio_pad_sleep_en_0_qs; end - addr_hit[385]: begin + addr_hit[391]: begin reg_rdata_next[0] = mio_pad_sleep_en_1_qs; end - addr_hit[386]: begin + addr_hit[392]: begin reg_rdata_next[0] = mio_pad_sleep_en_2_qs; end - addr_hit[387]: begin + addr_hit[393]: begin reg_rdata_next[0] = mio_pad_sleep_en_3_qs; end - addr_hit[388]: begin + addr_hit[394]: begin reg_rdata_next[0] = mio_pad_sleep_en_4_qs; end - addr_hit[389]: begin + addr_hit[395]: begin reg_rdata_next[0] = mio_pad_sleep_en_5_qs; end - addr_hit[390]: begin + addr_hit[396]: begin reg_rdata_next[0] = mio_pad_sleep_en_6_qs; end - addr_hit[391]: begin + addr_hit[397]: begin reg_rdata_next[0] = mio_pad_sleep_en_7_qs; end - addr_hit[392]: begin + addr_hit[398]: begin reg_rdata_next[0] = mio_pad_sleep_en_8_qs; end - addr_hit[393]: begin + addr_hit[399]: begin reg_rdata_next[0] = mio_pad_sleep_en_9_qs; end - addr_hit[394]: begin + addr_hit[400]: begin reg_rdata_next[0] = mio_pad_sleep_en_10_qs; end - addr_hit[395]: begin + addr_hit[401]: begin reg_rdata_next[0] = mio_pad_sleep_en_11_qs; end - addr_hit[396]: begin + addr_hit[402]: begin reg_rdata_next[0] = mio_pad_sleep_en_12_qs; end - addr_hit[397]: begin + addr_hit[403]: begin reg_rdata_next[0] = mio_pad_sleep_en_13_qs; end - addr_hit[398]: begin + addr_hit[404]: begin reg_rdata_next[0] = mio_pad_sleep_en_14_qs; end - addr_hit[399]: begin + addr_hit[405]: begin reg_rdata_next[0] = mio_pad_sleep_en_15_qs; end - addr_hit[400]: begin + addr_hit[406]: begin reg_rdata_next[0] = mio_pad_sleep_en_16_qs; end - addr_hit[401]: begin + addr_hit[407]: begin reg_rdata_next[0] = mio_pad_sleep_en_17_qs; end - addr_hit[402]: begin + addr_hit[408]: begin reg_rdata_next[0] = mio_pad_sleep_en_18_qs; end - addr_hit[403]: begin + addr_hit[409]: begin reg_rdata_next[0] = mio_pad_sleep_en_19_qs; end - addr_hit[404]: begin + addr_hit[410]: begin reg_rdata_next[0] = mio_pad_sleep_en_20_qs; end - addr_hit[405]: begin + addr_hit[411]: begin reg_rdata_next[0] = mio_pad_sleep_en_21_qs; end - addr_hit[406]: begin + addr_hit[412]: begin reg_rdata_next[0] = mio_pad_sleep_en_22_qs; end - addr_hit[407]: begin + addr_hit[413]: begin reg_rdata_next[0] = mio_pad_sleep_en_23_qs; end - addr_hit[408]: begin + addr_hit[414]: begin reg_rdata_next[0] = mio_pad_sleep_en_24_qs; end - addr_hit[409]: begin + addr_hit[415]: begin reg_rdata_next[0] = mio_pad_sleep_en_25_qs; end - addr_hit[410]: begin + addr_hit[416]: begin reg_rdata_next[0] = mio_pad_sleep_en_26_qs; end - addr_hit[411]: begin + addr_hit[417]: begin reg_rdata_next[0] = mio_pad_sleep_en_27_qs; end - addr_hit[412]: begin + addr_hit[418]: begin reg_rdata_next[0] = mio_pad_sleep_en_28_qs; end - addr_hit[413]: begin + addr_hit[419]: begin reg_rdata_next[0] = mio_pad_sleep_en_29_qs; end - addr_hit[414]: begin + addr_hit[420]: begin reg_rdata_next[0] = mio_pad_sleep_en_30_qs; end - addr_hit[415]: begin + addr_hit[421]: begin reg_rdata_next[0] = mio_pad_sleep_en_31_qs; end - addr_hit[416]: begin + addr_hit[422]: begin reg_rdata_next[0] = mio_pad_sleep_en_32_qs; end - addr_hit[417]: begin + addr_hit[423]: begin reg_rdata_next[0] = mio_pad_sleep_en_33_qs; end - addr_hit[418]: begin + addr_hit[424]: begin reg_rdata_next[0] = mio_pad_sleep_en_34_qs; end - addr_hit[419]: begin + addr_hit[425]: begin reg_rdata_next[0] = mio_pad_sleep_en_35_qs; end - addr_hit[420]: begin + addr_hit[426]: begin reg_rdata_next[0] = mio_pad_sleep_en_36_qs; end - addr_hit[421]: begin + addr_hit[427]: begin reg_rdata_next[0] = mio_pad_sleep_en_37_qs; end - addr_hit[422]: begin + addr_hit[428]: begin reg_rdata_next[0] = mio_pad_sleep_en_38_qs; end - addr_hit[423]: begin + addr_hit[429]: begin reg_rdata_next[0] = mio_pad_sleep_en_39_qs; end - addr_hit[424]: begin + addr_hit[430]: begin reg_rdata_next[0] = mio_pad_sleep_en_40_qs; end - addr_hit[425]: begin + addr_hit[431]: begin reg_rdata_next[0] = mio_pad_sleep_en_41_qs; end - addr_hit[426]: begin + addr_hit[432]: begin reg_rdata_next[0] = mio_pad_sleep_en_42_qs; end - addr_hit[427]: begin + addr_hit[433]: begin reg_rdata_next[0] = mio_pad_sleep_en_43_qs; end - addr_hit[428]: begin + addr_hit[434]: begin reg_rdata_next[0] = mio_pad_sleep_en_44_qs; end - addr_hit[429]: begin + addr_hit[435]: begin reg_rdata_next[0] = mio_pad_sleep_en_45_qs; end - addr_hit[430]: begin + addr_hit[436]: begin reg_rdata_next[0] = mio_pad_sleep_en_46_qs; end - addr_hit[431]: begin + addr_hit[437]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; end - addr_hit[432]: begin + addr_hit[438]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; end - addr_hit[433]: begin + addr_hit[439]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; end - addr_hit[434]: begin + addr_hit[440]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; end - addr_hit[435]: begin + addr_hit[441]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; end - addr_hit[436]: begin + addr_hit[442]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; end - addr_hit[437]: begin + addr_hit[443]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; end - addr_hit[438]: begin + addr_hit[444]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; end - addr_hit[439]: begin + addr_hit[445]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; end - addr_hit[440]: begin + addr_hit[446]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; end - addr_hit[441]: begin + addr_hit[447]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; end - addr_hit[442]: begin + addr_hit[448]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; end - addr_hit[443]: begin + addr_hit[449]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; end - addr_hit[444]: begin + addr_hit[450]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; end - addr_hit[445]: begin + addr_hit[451]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; end - addr_hit[446]: begin + addr_hit[452]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; end - addr_hit[447]: begin + addr_hit[453]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; end - addr_hit[448]: begin + addr_hit[454]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; end - addr_hit[449]: begin + addr_hit[455]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; end - addr_hit[450]: begin + addr_hit[456]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; end - addr_hit[451]: begin + addr_hit[457]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; end - addr_hit[452]: begin + addr_hit[458]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; end - addr_hit[453]: begin + addr_hit[459]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; end - addr_hit[454]: begin + addr_hit[460]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; end - addr_hit[455]: begin + addr_hit[461]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; end - addr_hit[456]: begin + addr_hit[462]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; end - addr_hit[457]: begin + addr_hit[463]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; end - addr_hit[458]: begin + addr_hit[464]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; end - addr_hit[459]: begin + addr_hit[465]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; end - addr_hit[460]: begin + addr_hit[466]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; end - addr_hit[461]: begin + addr_hit[467]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; end - addr_hit[462]: begin + addr_hit[468]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; end - addr_hit[463]: begin + addr_hit[469]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs; end - addr_hit[464]: begin + addr_hit[470]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs; end - addr_hit[465]: begin + addr_hit[471]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs; end - addr_hit[466]: begin + addr_hit[472]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs; end - addr_hit[467]: begin + addr_hit[473]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs; end - addr_hit[468]: begin + addr_hit[474]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs; end - addr_hit[469]: begin + addr_hit[475]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs; end - addr_hit[470]: begin + addr_hit[476]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs; end - addr_hit[471]: begin + addr_hit[477]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs; end - addr_hit[472]: begin + addr_hit[478]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs; end - addr_hit[473]: begin + addr_hit[479]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs; end - addr_hit[474]: begin + addr_hit[480]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs; end - addr_hit[475]: begin + addr_hit[481]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs; end - addr_hit[476]: begin + addr_hit[482]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs; end - addr_hit[477]: begin + addr_hit[483]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs; end - addr_hit[478]: begin + addr_hit[484]: begin reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs; reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs; reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs; @@ -39814,335 +40075,335 @@ module pinmux_reg_top ( reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs; end - addr_hit[479]: begin + addr_hit[485]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; end - addr_hit[480]: begin + addr_hit[486]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; end - addr_hit[481]: begin + addr_hit[487]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; end - addr_hit[482]: begin + addr_hit[488]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; end - addr_hit[483]: begin + addr_hit[489]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; end - addr_hit[484]: begin + addr_hit[490]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; end - addr_hit[485]: begin + addr_hit[491]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; end - addr_hit[486]: begin + addr_hit[492]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; end - addr_hit[487]: begin + addr_hit[493]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; end - addr_hit[488]: begin + addr_hit[494]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; end - addr_hit[489]: begin + addr_hit[495]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; end - addr_hit[490]: begin + addr_hit[496]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; end - addr_hit[491]: begin + addr_hit[497]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; end - addr_hit[492]: begin + addr_hit[498]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; end - addr_hit[493]: begin + addr_hit[499]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; end - addr_hit[494]: begin + addr_hit[500]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; end - addr_hit[495]: begin + addr_hit[501]: begin reg_rdata_next[0] = dio_pad_sleep_en_0_qs; end - addr_hit[496]: begin + addr_hit[502]: begin reg_rdata_next[0] = dio_pad_sleep_en_1_qs; end - addr_hit[497]: begin + addr_hit[503]: begin reg_rdata_next[0] = dio_pad_sleep_en_2_qs; end - addr_hit[498]: begin + addr_hit[504]: begin reg_rdata_next[0] = dio_pad_sleep_en_3_qs; end - addr_hit[499]: begin + addr_hit[505]: begin reg_rdata_next[0] = dio_pad_sleep_en_4_qs; end - addr_hit[500]: begin + addr_hit[506]: begin reg_rdata_next[0] = dio_pad_sleep_en_5_qs; end - addr_hit[501]: begin + addr_hit[507]: begin reg_rdata_next[0] = dio_pad_sleep_en_6_qs; end - addr_hit[502]: begin + addr_hit[508]: begin reg_rdata_next[0] = dio_pad_sleep_en_7_qs; end - addr_hit[503]: begin + addr_hit[509]: begin reg_rdata_next[0] = dio_pad_sleep_en_8_qs; end - addr_hit[504]: begin + addr_hit[510]: begin reg_rdata_next[0] = dio_pad_sleep_en_9_qs; end - addr_hit[505]: begin + addr_hit[511]: begin reg_rdata_next[0] = dio_pad_sleep_en_10_qs; end - addr_hit[506]: begin + addr_hit[512]: begin reg_rdata_next[0] = dio_pad_sleep_en_11_qs; end - addr_hit[507]: begin + addr_hit[513]: begin reg_rdata_next[0] = dio_pad_sleep_en_12_qs; end - addr_hit[508]: begin + addr_hit[514]: begin reg_rdata_next[0] = dio_pad_sleep_en_13_qs; end - addr_hit[509]: begin + addr_hit[515]: begin reg_rdata_next[0] = dio_pad_sleep_en_14_qs; end - addr_hit[510]: begin + addr_hit[516]: begin reg_rdata_next[0] = dio_pad_sleep_en_15_qs; end - addr_hit[511]: begin + addr_hit[517]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; end - addr_hit[512]: begin + addr_hit[518]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; end - addr_hit[513]: begin + addr_hit[519]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; end - addr_hit[514]: begin + addr_hit[520]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; end - addr_hit[515]: begin + addr_hit[521]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; end - addr_hit[516]: begin + addr_hit[522]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; end - addr_hit[517]: begin + addr_hit[523]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; end - addr_hit[518]: begin + addr_hit[524]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; end - addr_hit[519]: begin + addr_hit[525]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; end - addr_hit[520]: begin + addr_hit[526]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; end - addr_hit[521]: begin + addr_hit[527]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; end - addr_hit[522]: begin + addr_hit[528]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; end - addr_hit[523]: begin + addr_hit[529]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; end - addr_hit[524]: begin + addr_hit[530]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; end - addr_hit[525]: begin + addr_hit[531]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; end - addr_hit[526]: begin + addr_hit[532]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; end - addr_hit[527]: begin + addr_hit[533]: begin reg_rdata_next[0] = wkup_detector_regwen_0_qs; end - addr_hit[528]: begin + addr_hit[534]: begin reg_rdata_next[0] = wkup_detector_regwen_1_qs; end - addr_hit[529]: begin + addr_hit[535]: begin reg_rdata_next[0] = wkup_detector_regwen_2_qs; end - addr_hit[530]: begin + addr_hit[536]: begin reg_rdata_next[0] = wkup_detector_regwen_3_qs; end - addr_hit[531]: begin + addr_hit[537]: begin reg_rdata_next[0] = wkup_detector_regwen_4_qs; end - addr_hit[532]: begin + addr_hit[538]: begin reg_rdata_next[0] = wkup_detector_regwen_5_qs; end - addr_hit[533]: begin + addr_hit[539]: begin reg_rdata_next[0] = wkup_detector_regwen_6_qs; end - addr_hit[534]: begin + addr_hit[540]: begin reg_rdata_next[0] = wkup_detector_regwen_7_qs; end - addr_hit[535]: begin + addr_hit[541]: begin reg_rdata_next = DW'(wkup_detector_en_0_qs); end - addr_hit[536]: begin + addr_hit[542]: begin reg_rdata_next = DW'(wkup_detector_en_1_qs); end - addr_hit[537]: begin + addr_hit[543]: begin reg_rdata_next = DW'(wkup_detector_en_2_qs); end - addr_hit[538]: begin + addr_hit[544]: begin reg_rdata_next = DW'(wkup_detector_en_3_qs); end - addr_hit[539]: begin + addr_hit[545]: begin reg_rdata_next = DW'(wkup_detector_en_4_qs); end - addr_hit[540]: begin + addr_hit[546]: begin reg_rdata_next = DW'(wkup_detector_en_5_qs); end - addr_hit[541]: begin + addr_hit[547]: begin reg_rdata_next = DW'(wkup_detector_en_6_qs); end - addr_hit[542]: begin + addr_hit[548]: begin reg_rdata_next = DW'(wkup_detector_en_7_qs); end - addr_hit[543]: begin + addr_hit[549]: begin reg_rdata_next = DW'(wkup_detector_0_qs); end - addr_hit[544]: begin + addr_hit[550]: begin reg_rdata_next = DW'(wkup_detector_1_qs); end - addr_hit[545]: begin + addr_hit[551]: begin reg_rdata_next = DW'(wkup_detector_2_qs); end - addr_hit[546]: begin + addr_hit[552]: begin reg_rdata_next = DW'(wkup_detector_3_qs); end - addr_hit[547]: begin + addr_hit[553]: begin reg_rdata_next = DW'(wkup_detector_4_qs); end - addr_hit[548]: begin + addr_hit[554]: begin reg_rdata_next = DW'(wkup_detector_5_qs); end - addr_hit[549]: begin + addr_hit[555]: begin reg_rdata_next = DW'(wkup_detector_6_qs); end - addr_hit[550]: begin + addr_hit[556]: begin reg_rdata_next = DW'(wkup_detector_7_qs); end - addr_hit[551]: begin + addr_hit[557]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); end - addr_hit[552]: begin + addr_hit[558]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); end - addr_hit[553]: begin + addr_hit[559]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); end - addr_hit[554]: begin + addr_hit[560]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); end - addr_hit[555]: begin + addr_hit[561]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); end - addr_hit[556]: begin + addr_hit[562]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); end - addr_hit[557]: begin + addr_hit[563]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); end - addr_hit[558]: begin + addr_hit[564]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); end - addr_hit[559]: begin + addr_hit[565]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[560]: begin + addr_hit[566]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[561]: begin + addr_hit[567]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[562]: begin + addr_hit[568]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[563]: begin + addr_hit[569]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[564]: begin + addr_hit[570]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[565]: begin + addr_hit[571]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[566]: begin + addr_hit[572]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[567]: begin + addr_hit[573]: begin reg_rdata_next = DW'(wkup_cause_qs); end default: begin @@ -40161,79 +40422,79 @@ module pinmux_reg_top ( always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[535]: begin + addr_hit[541]: begin reg_busy_sel = wkup_detector_en_0_busy; end - addr_hit[536]: begin + addr_hit[542]: begin reg_busy_sel = wkup_detector_en_1_busy; end - addr_hit[537]: begin + addr_hit[543]: begin reg_busy_sel = wkup_detector_en_2_busy; end - addr_hit[538]: begin + addr_hit[544]: begin reg_busy_sel = wkup_detector_en_3_busy; end - addr_hit[539]: begin + addr_hit[545]: begin reg_busy_sel = wkup_detector_en_4_busy; end - addr_hit[540]: begin + addr_hit[546]: begin reg_busy_sel = wkup_detector_en_5_busy; end - addr_hit[541]: begin + addr_hit[547]: begin reg_busy_sel = wkup_detector_en_6_busy; end - addr_hit[542]: begin + addr_hit[548]: begin reg_busy_sel = wkup_detector_en_7_busy; end - addr_hit[543]: begin + addr_hit[549]: begin reg_busy_sel = wkup_detector_0_busy; end - addr_hit[544]: begin + addr_hit[550]: begin reg_busy_sel = wkup_detector_1_busy; end - addr_hit[545]: begin + addr_hit[551]: begin reg_busy_sel = wkup_detector_2_busy; end - addr_hit[546]: begin + addr_hit[552]: begin reg_busy_sel = wkup_detector_3_busy; end - addr_hit[547]: begin + addr_hit[553]: begin reg_busy_sel = wkup_detector_4_busy; end - addr_hit[548]: begin + addr_hit[554]: begin reg_busy_sel = wkup_detector_5_busy; end - addr_hit[549]: begin + addr_hit[555]: begin reg_busy_sel = wkup_detector_6_busy; end - addr_hit[550]: begin + addr_hit[556]: begin reg_busy_sel = wkup_detector_7_busy; end - addr_hit[551]: begin + addr_hit[557]: begin reg_busy_sel = wkup_detector_cnt_th_0_busy; end - addr_hit[552]: begin + addr_hit[558]: begin reg_busy_sel = wkup_detector_cnt_th_1_busy; end - addr_hit[553]: begin + addr_hit[559]: begin reg_busy_sel = wkup_detector_cnt_th_2_busy; end - addr_hit[554]: begin + addr_hit[560]: begin reg_busy_sel = wkup_detector_cnt_th_3_busy; end - addr_hit[555]: begin + addr_hit[561]: begin reg_busy_sel = wkup_detector_cnt_th_4_busy; end - addr_hit[556]: begin + addr_hit[562]: begin reg_busy_sel = wkup_detector_cnt_th_5_busy; end - addr_hit[557]: begin + addr_hit[563]: begin reg_busy_sel = wkup_detector_cnt_th_6_busy; end - addr_hit[558]: begin + addr_hit[564]: begin reg_busy_sel = wkup_detector_cnt_th_7_busy; end - addr_hit[567]: begin + addr_hit[573]: begin reg_busy_sel = wkup_cause_busy; end default: begin diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson index 7fbf9757c3a0f..9184072914a0b 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson @@ -44,7 +44,7 @@ { name: "NumSrc", desc: "Number of interrupt sources", type: "int", - default: "184", + default: "190", local: "true" }, { name: "NumTarget", diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson index dfcda5dc1aed6..f5efed2cd40c4 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rv_plic/data/top_earlgrey_rv_plic.ipconfig.hjson @@ -6,7 +6,7 @@ param_values: { module_instance_name: rv_plic - src: 184 + src: 190 target: 1 prio: 3 topname: earlgrey diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv index a0e9c2192bd71..253d0b1850212 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -280,11 +280,17 @@ module rv_plic import rv_plic_reg_pkg::*; #( assign prio[181] = reg2hw.prio[181].q; assign prio[182] = reg2hw.prio[182].q; assign prio[183] = reg2hw.prio[183].q; + assign prio[184] = reg2hw.prio[184].q; + assign prio[185] = reg2hw.prio[185].q; + assign prio[186] = reg2hw.prio[186].q; + assign prio[187] = reg2hw.prio[187].q; + assign prio[188] = reg2hw.prio[188].q; + assign prio[189] = reg2hw.prio[189].q; ////////////////////// // Interrupt Enable // ////////////////////// - for (genvar s = 0; s < 184; s++) begin : gen_ie0 + for (genvar s = 0; s < 190; s++) begin : gen_ie0 assign ie[0][s] = reg2hw.ie0[s].q; end @@ -310,7 +316,7 @@ module rv_plic import rv_plic_reg_pkg::*; #( //////// // IP // //////// - for (genvar s = 0; s < 184; s++) begin : gen_ip + for (genvar s = 0; s < 190; s++) begin : gen_ip assign hw2reg.ip[s].de = 1'b1; // Always write assign hw2reg.ip[s].d = ip[s]; end diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv index e914a5517ce5e..71d52a259b151 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv @@ -7,7 +7,7 @@ package rv_plic_reg_pkg; // Param list - parameter int NumSrc = 184; + parameter int NumSrc = 190; parameter int NumTarget = 1; parameter int PrioWidth = 2; parameter int NumAlerts = 1; @@ -16,7 +16,7 @@ package rv_plic_reg_pkg; parameter int BlockAw = 27; // Number of registers for every interface - parameter int NumRegs = 200; + parameter int NumRegs = 206; // Alert indices typedef enum int { @@ -65,8 +65,8 @@ package rv_plic_reg_pkg; // Register -> HW type typedef struct packed { - rv_plic_reg2hw_prio_mreg_t [183:0] prio; // [566:199] - rv_plic_reg2hw_ie0_mreg_t [183:0] ie0; // [198:15] + rv_plic_reg2hw_prio_mreg_t [189:0] prio; // [584:205] + rv_plic_reg2hw_ie0_mreg_t [189:0] ie0; // [204:15] rv_plic_reg2hw_threshold0_reg_t threshold0; // [14:13] rv_plic_reg2hw_cc0_reg_t cc0; // [12:3] rv_plic_reg2hw_msip0_reg_t msip0; // [2:2] @@ -75,7 +75,7 @@ package rv_plic_reg_pkg; // HW -> register type typedef struct packed { - rv_plic_hw2reg_ip_mreg_t [183:0] ip; // [375:8] + rv_plic_hw2reg_ip_mreg_t [189:0] ip; // [387:8] rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] } rv_plic_hw2reg_t; @@ -264,6 +264,12 @@ package rv_plic_reg_pkg; parameter logic [BlockAw-1:0] RV_PLIC_PRIO_181_OFFSET = 27'h 2d4; parameter logic [BlockAw-1:0] RV_PLIC_PRIO_182_OFFSET = 27'h 2d8; parameter logic [BlockAw-1:0] RV_PLIC_PRIO_183_OFFSET = 27'h 2dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_184_OFFSET = 27'h 2e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_185_OFFSET = 27'h 2e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_186_OFFSET = 27'h 2e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_187_OFFSET = 27'h 2ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_188_OFFSET = 27'h 2f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_189_OFFSET = 27'h 2f4; parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000; parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004; parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008; @@ -471,6 +477,12 @@ package rv_plic_reg_pkg; RV_PLIC_PRIO_181, RV_PLIC_PRIO_182, RV_PLIC_PRIO_183, + RV_PLIC_PRIO_184, + RV_PLIC_PRIO_185, + RV_PLIC_PRIO_186, + RV_PLIC_PRIO_187, + RV_PLIC_PRIO_188, + RV_PLIC_PRIO_189, RV_PLIC_IP_0, RV_PLIC_IP_1, RV_PLIC_IP_2, @@ -490,7 +502,7 @@ package rv_plic_reg_pkg; } rv_plic_id_e; // Register width information to check illegal writes - parameter logic [3:0] RV_PLIC_PERMIT [200] = '{ + parameter logic [3:0] RV_PLIC_PERMIT [206] = '{ 4'b 0001, // index[ 0] RV_PLIC_PRIO_0 4'b 0001, // index[ 1] RV_PLIC_PRIO_1 4'b 0001, // index[ 2] RV_PLIC_PRIO_2 @@ -675,22 +687,28 @@ package rv_plic_reg_pkg; 4'b 0001, // index[181] RV_PLIC_PRIO_181 4'b 0001, // index[182] RV_PLIC_PRIO_182 4'b 0001, // index[183] RV_PLIC_PRIO_183 - 4'b 1111, // index[184] RV_PLIC_IP_0 - 4'b 1111, // index[185] RV_PLIC_IP_1 - 4'b 1111, // index[186] RV_PLIC_IP_2 - 4'b 1111, // index[187] RV_PLIC_IP_3 - 4'b 1111, // index[188] RV_PLIC_IP_4 - 4'b 0111, // index[189] RV_PLIC_IP_5 - 4'b 1111, // index[190] RV_PLIC_IE0_0 - 4'b 1111, // index[191] RV_PLIC_IE0_1 - 4'b 1111, // index[192] RV_PLIC_IE0_2 - 4'b 1111, // index[193] RV_PLIC_IE0_3 - 4'b 1111, // index[194] RV_PLIC_IE0_4 - 4'b 0111, // index[195] RV_PLIC_IE0_5 - 4'b 0001, // index[196] RV_PLIC_THRESHOLD0 - 4'b 0001, // index[197] RV_PLIC_CC0 - 4'b 0001, // index[198] RV_PLIC_MSIP0 - 4'b 0001 // index[199] RV_PLIC_ALERT_TEST + 4'b 0001, // index[184] RV_PLIC_PRIO_184 + 4'b 0001, // index[185] RV_PLIC_PRIO_185 + 4'b 0001, // index[186] RV_PLIC_PRIO_186 + 4'b 0001, // index[187] RV_PLIC_PRIO_187 + 4'b 0001, // index[188] RV_PLIC_PRIO_188 + 4'b 0001, // index[189] RV_PLIC_PRIO_189 + 4'b 1111, // index[190] RV_PLIC_IP_0 + 4'b 1111, // index[191] RV_PLIC_IP_1 + 4'b 1111, // index[192] RV_PLIC_IP_2 + 4'b 1111, // index[193] RV_PLIC_IP_3 + 4'b 1111, // index[194] RV_PLIC_IP_4 + 4'b 1111, // index[195] RV_PLIC_IP_5 + 4'b 1111, // index[196] RV_PLIC_IE0_0 + 4'b 1111, // index[197] RV_PLIC_IE0_1 + 4'b 1111, // index[198] RV_PLIC_IE0_2 + 4'b 1111, // index[199] RV_PLIC_IE0_3 + 4'b 1111, // index[200] RV_PLIC_IE0_4 + 4'b 1111, // index[201] RV_PLIC_IE0_5 + 4'b 0001, // index[202] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[203] RV_PLIC_CC0 + 4'b 0001, // index[204] RV_PLIC_MSIP0 + 4'b 0001 // index[205] RV_PLIC_ALERT_TEST }; endpackage diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv index fe267439e9eb7..f7e3aacdc0656 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv @@ -52,9 +52,9 @@ module rv_plic_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [199:0] reg_we_check; + logic [205:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(200) + .OneHotWidth(206) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -673,6 +673,24 @@ module rv_plic_reg_top ( logic prio_183_we; logic [1:0] prio_183_qs; logic [1:0] prio_183_wd; + logic prio_184_we; + logic [1:0] prio_184_qs; + logic [1:0] prio_184_wd; + logic prio_185_we; + logic [1:0] prio_185_qs; + logic [1:0] prio_185_wd; + logic prio_186_we; + logic [1:0] prio_186_qs; + logic [1:0] prio_186_wd; + logic prio_187_we; + logic [1:0] prio_187_qs; + logic [1:0] prio_187_wd; + logic prio_188_we; + logic [1:0] prio_188_qs; + logic [1:0] prio_188_wd; + logic prio_189_we; + logic [1:0] prio_189_qs; + logic [1:0] prio_189_wd; logic ip_0_p_0_qs; logic ip_0_p_1_qs; logic ip_0_p_2_qs; @@ -857,6 +875,12 @@ module rv_plic_reg_top ( logic ip_5_p_181_qs; logic ip_5_p_182_qs; logic ip_5_p_183_qs; + logic ip_5_p_184_qs; + logic ip_5_p_185_qs; + logic ip_5_p_186_qs; + logic ip_5_p_187_qs; + logic ip_5_p_188_qs; + logic ip_5_p_189_qs; logic ie0_0_we; logic ie0_0_e_0_qs; logic ie0_0_e_0_wd; @@ -1231,6 +1255,18 @@ module rv_plic_reg_top ( logic ie0_5_e_182_wd; logic ie0_5_e_183_qs; logic ie0_5_e_183_wd; + logic ie0_5_e_184_qs; + logic ie0_5_e_184_wd; + logic ie0_5_e_185_qs; + logic ie0_5_e_185_wd; + logic ie0_5_e_186_qs; + logic ie0_5_e_186_wd; + logic ie0_5_e_187_qs; + logic ie0_5_e_187_wd; + logic ie0_5_e_188_qs; + logic ie0_5_e_188_wd; + logic ie0_5_e_189_qs; + logic ie0_5_e_189_wd; logic threshold0_we; logic [1:0] threshold0_qs; logic [1:0] threshold0_wd; @@ -6581,6 +6617,180 @@ module rv_plic_reg_top ( ); + // Subregister 184 of Multireg prio + // R[prio_184]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_184 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_184_we), + .wd (prio_184_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[184].q), + .ds (), + + // to register interface (read) + .qs (prio_184_qs) + ); + + + // Subregister 185 of Multireg prio + // R[prio_185]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_185 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_185_we), + .wd (prio_185_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[185].q), + .ds (), + + // to register interface (read) + .qs (prio_185_qs) + ); + + + // Subregister 186 of Multireg prio + // R[prio_186]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_186 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_186_we), + .wd (prio_186_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[186].q), + .ds (), + + // to register interface (read) + .qs (prio_186_qs) + ); + + + // Subregister 187 of Multireg prio + // R[prio_187]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_187 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_187_we), + .wd (prio_187_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[187].q), + .ds (), + + // to register interface (read) + .qs (prio_187_qs) + ); + + + // Subregister 188 of Multireg prio + // R[prio_188]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_188 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_188_we), + .wd (prio_188_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[188].q), + .ds (), + + // to register interface (read) + .qs (prio_188_qs) + ); + + + // Subregister 189 of Multireg prio + // R[prio_189]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_189 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_189_we), + .wd (prio_189_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[189].q), + .ds (), + + // to register interface (read) + .qs (prio_189_qs) + ); + + // Subregister 0 of Multireg ip // R[ip_0]: V(False) // F[p_0]: 0:0 @@ -11566,6 +11776,168 @@ module rv_plic_reg_top ( .qs (ip_5_p_183_qs) ); + // F[p_184]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_184 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[184].de), + .d (hw2reg.ip[184].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_184_qs) + ); + + // F[p_185]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_185 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[185].de), + .d (hw2reg.ip[185].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_185_qs) + ); + + // F[p_186]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_186 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[186].de), + .d (hw2reg.ip[186].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_186_qs) + ); + + // F[p_187]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_187 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[187].de), + .d (hw2reg.ip[187].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_187_qs) + ); + + // F[p_188]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_188 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[188].de), + .d (hw2reg.ip[188].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_188_qs) + ); + + // F[p_189]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_189 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[189].de), + .d (hw2reg.ip[189].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_189_qs) + ); + // Subregister 0 of Multireg ie0 // R[ie0_0]: V(False) @@ -16552,6 +16924,168 @@ module rv_plic_reg_top ( .qs (ie0_5_e_183_qs) ); + // F[e_184]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_184 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_184_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[184].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_184_qs) + ); + + // F[e_185]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_185 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_185_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[185].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_185_qs) + ); + + // F[e_186]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_186 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_186_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[186].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_186_qs) + ); + + // F[e_187]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_187 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_187_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[187].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_187_qs) + ); + + // F[e_188]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_188 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_188_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[188].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_188_qs) + ); + + // F[e_189]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_189 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_189_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[189].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_189_qs) + ); + // R[threshold0]: V(False) prim_subreg #( @@ -16650,7 +17184,7 @@ module rv_plic_reg_top ( - logic [199:0] addr_hit; + logic [205:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO_0_OFFSET); addr_hit[ 1] = (reg_addr == RV_PLIC_PRIO_1_OFFSET); @@ -16836,22 +17370,28 @@ module rv_plic_reg_top ( addr_hit[181] = (reg_addr == RV_PLIC_PRIO_181_OFFSET); addr_hit[182] = (reg_addr == RV_PLIC_PRIO_182_OFFSET); addr_hit[183] = (reg_addr == RV_PLIC_PRIO_183_OFFSET); - addr_hit[184] = (reg_addr == RV_PLIC_IP_0_OFFSET); - addr_hit[185] = (reg_addr == RV_PLIC_IP_1_OFFSET); - addr_hit[186] = (reg_addr == RV_PLIC_IP_2_OFFSET); - addr_hit[187] = (reg_addr == RV_PLIC_IP_3_OFFSET); - addr_hit[188] = (reg_addr == RV_PLIC_IP_4_OFFSET); - addr_hit[189] = (reg_addr == RV_PLIC_IP_5_OFFSET); - addr_hit[190] = (reg_addr == RV_PLIC_IE0_0_OFFSET); - addr_hit[191] = (reg_addr == RV_PLIC_IE0_1_OFFSET); - addr_hit[192] = (reg_addr == RV_PLIC_IE0_2_OFFSET); - addr_hit[193] = (reg_addr == RV_PLIC_IE0_3_OFFSET); - addr_hit[194] = (reg_addr == RV_PLIC_IE0_4_OFFSET); - addr_hit[195] = (reg_addr == RV_PLIC_IE0_5_OFFSET); - addr_hit[196] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); - addr_hit[197] = (reg_addr == RV_PLIC_CC0_OFFSET); - addr_hit[198] = (reg_addr == RV_PLIC_MSIP0_OFFSET); - addr_hit[199] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); + addr_hit[184] = (reg_addr == RV_PLIC_PRIO_184_OFFSET); + addr_hit[185] = (reg_addr == RV_PLIC_PRIO_185_OFFSET); + addr_hit[186] = (reg_addr == RV_PLIC_PRIO_186_OFFSET); + addr_hit[187] = (reg_addr == RV_PLIC_PRIO_187_OFFSET); + addr_hit[188] = (reg_addr == RV_PLIC_PRIO_188_OFFSET); + addr_hit[189] = (reg_addr == RV_PLIC_PRIO_189_OFFSET); + addr_hit[190] = (reg_addr == RV_PLIC_IP_0_OFFSET); + addr_hit[191] = (reg_addr == RV_PLIC_IP_1_OFFSET); + addr_hit[192] = (reg_addr == RV_PLIC_IP_2_OFFSET); + addr_hit[193] = (reg_addr == RV_PLIC_IP_3_OFFSET); + addr_hit[194] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[195] = (reg_addr == RV_PLIC_IP_5_OFFSET); + addr_hit[196] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[197] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[198] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[199] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[200] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[201] = (reg_addr == RV_PLIC_IE0_5_OFFSET); + addr_hit[202] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[203] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[204] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[205] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -17058,7 +17598,13 @@ module rv_plic_reg_top ( (addr_hit[196] & (|(RV_PLIC_PERMIT[196] & ~reg_be))) | (addr_hit[197] & (|(RV_PLIC_PERMIT[197] & ~reg_be))) | (addr_hit[198] & (|(RV_PLIC_PERMIT[198] & ~reg_be))) | - (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))))); + (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))) | + (addr_hit[200] & (|(RV_PLIC_PERMIT[200] & ~reg_be))) | + (addr_hit[201] & (|(RV_PLIC_PERMIT[201] & ~reg_be))) | + (addr_hit[202] & (|(RV_PLIC_PERMIT[202] & ~reg_be))) | + (addr_hit[203] & (|(RV_PLIC_PERMIT[203] & ~reg_be))) | + (addr_hit[204] & (|(RV_PLIC_PERMIT[204] & ~reg_be))) | + (addr_hit[205] & (|(RV_PLIC_PERMIT[205] & ~reg_be))))); end // Generate write-enables @@ -17614,7 +18160,25 @@ module rv_plic_reg_top ( assign prio_183_we = addr_hit[183] & reg_we & !reg_error; assign prio_183_wd = reg_wdata[1:0]; - assign ie0_0_we = addr_hit[190] & reg_we & !reg_error; + assign prio_184_we = addr_hit[184] & reg_we & !reg_error; + + assign prio_184_wd = reg_wdata[1:0]; + assign prio_185_we = addr_hit[185] & reg_we & !reg_error; + + assign prio_185_wd = reg_wdata[1:0]; + assign prio_186_we = addr_hit[186] & reg_we & !reg_error; + + assign prio_186_wd = reg_wdata[1:0]; + assign prio_187_we = addr_hit[187] & reg_we & !reg_error; + + assign prio_187_wd = reg_wdata[1:0]; + assign prio_188_we = addr_hit[188] & reg_we & !reg_error; + + assign prio_188_wd = reg_wdata[1:0]; + assign prio_189_we = addr_hit[189] & reg_we & !reg_error; + + assign prio_189_wd = reg_wdata[1:0]; + assign ie0_0_we = addr_hit[196] & reg_we & !reg_error; assign ie0_0_e_0_wd = reg_wdata[0]; @@ -17679,7 +18243,7 @@ module rv_plic_reg_top ( assign ie0_0_e_30_wd = reg_wdata[30]; assign ie0_0_e_31_wd = reg_wdata[31]; - assign ie0_1_we = addr_hit[191] & reg_we & !reg_error; + assign ie0_1_we = addr_hit[197] & reg_we & !reg_error; assign ie0_1_e_32_wd = reg_wdata[0]; @@ -17744,7 +18308,7 @@ module rv_plic_reg_top ( assign ie0_1_e_62_wd = reg_wdata[30]; assign ie0_1_e_63_wd = reg_wdata[31]; - assign ie0_2_we = addr_hit[192] & reg_we & !reg_error; + assign ie0_2_we = addr_hit[198] & reg_we & !reg_error; assign ie0_2_e_64_wd = reg_wdata[0]; @@ -17809,7 +18373,7 @@ module rv_plic_reg_top ( assign ie0_2_e_94_wd = reg_wdata[30]; assign ie0_2_e_95_wd = reg_wdata[31]; - assign ie0_3_we = addr_hit[193] & reg_we & !reg_error; + assign ie0_3_we = addr_hit[199] & reg_we & !reg_error; assign ie0_3_e_96_wd = reg_wdata[0]; @@ -17874,7 +18438,7 @@ module rv_plic_reg_top ( assign ie0_3_e_126_wd = reg_wdata[30]; assign ie0_3_e_127_wd = reg_wdata[31]; - assign ie0_4_we = addr_hit[194] & reg_we & !reg_error; + assign ie0_4_we = addr_hit[200] & reg_we & !reg_error; assign ie0_4_e_128_wd = reg_wdata[0]; @@ -17939,7 +18503,7 @@ module rv_plic_reg_top ( assign ie0_4_e_158_wd = reg_wdata[30]; assign ie0_4_e_159_wd = reg_wdata[31]; - assign ie0_5_we = addr_hit[195] & reg_we & !reg_error; + assign ie0_5_we = addr_hit[201] & reg_we & !reg_error; assign ie0_5_e_160_wd = reg_wdata[0]; @@ -17988,17 +18552,29 @@ module rv_plic_reg_top ( assign ie0_5_e_182_wd = reg_wdata[22]; assign ie0_5_e_183_wd = reg_wdata[23]; - assign threshold0_we = addr_hit[196] & reg_we & !reg_error; + + assign ie0_5_e_184_wd = reg_wdata[24]; + + assign ie0_5_e_185_wd = reg_wdata[25]; + + assign ie0_5_e_186_wd = reg_wdata[26]; + + assign ie0_5_e_187_wd = reg_wdata[27]; + + assign ie0_5_e_188_wd = reg_wdata[28]; + + assign ie0_5_e_189_wd = reg_wdata[29]; + assign threshold0_we = addr_hit[202] & reg_we & !reg_error; assign threshold0_wd = reg_wdata[1:0]; - assign cc0_re = addr_hit[197] & reg_re & !reg_error; - assign cc0_we = addr_hit[197] & reg_we & !reg_error; + assign cc0_re = addr_hit[203] & reg_re & !reg_error; + assign cc0_we = addr_hit[203] & reg_we & !reg_error; assign cc0_wd = reg_wdata[7:0]; - assign msip0_we = addr_hit[198] & reg_we & !reg_error; + assign msip0_we = addr_hit[204] & reg_we & !reg_error; assign msip0_wd = reg_wdata[0]; - assign alert_test_we = addr_hit[199] & reg_we & !reg_error; + assign alert_test_we = addr_hit[205] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; @@ -18188,22 +18764,28 @@ module rv_plic_reg_top ( reg_we_check[181] = prio_181_we; reg_we_check[182] = prio_182_we; reg_we_check[183] = prio_183_we; - reg_we_check[184] = 1'b0; - reg_we_check[185] = 1'b0; - reg_we_check[186] = 1'b0; - reg_we_check[187] = 1'b0; - reg_we_check[188] = 1'b0; - reg_we_check[189] = 1'b0; - reg_we_check[190] = ie0_0_we; - reg_we_check[191] = ie0_1_we; - reg_we_check[192] = ie0_2_we; - reg_we_check[193] = ie0_3_we; - reg_we_check[194] = ie0_4_we; - reg_we_check[195] = ie0_5_we; - reg_we_check[196] = threshold0_we; - reg_we_check[197] = cc0_we; - reg_we_check[198] = msip0_we; - reg_we_check[199] = alert_test_we; + reg_we_check[184] = prio_184_we; + reg_we_check[185] = prio_185_we; + reg_we_check[186] = prio_186_we; + reg_we_check[187] = prio_187_we; + reg_we_check[188] = prio_188_we; + reg_we_check[189] = prio_189_we; + reg_we_check[190] = 1'b0; + reg_we_check[191] = 1'b0; + reg_we_check[192] = 1'b0; + reg_we_check[193] = 1'b0; + reg_we_check[194] = 1'b0; + reg_we_check[195] = 1'b0; + reg_we_check[196] = ie0_0_we; + reg_we_check[197] = ie0_1_we; + reg_we_check[198] = ie0_2_we; + reg_we_check[199] = ie0_3_we; + reg_we_check[200] = ie0_4_we; + reg_we_check[201] = ie0_5_we; + reg_we_check[202] = threshold0_we; + reg_we_check[203] = cc0_we; + reg_we_check[204] = msip0_we; + reg_we_check[205] = alert_test_we; end // Read data return @@ -18947,6 +19529,30 @@ module rv_plic_reg_top ( end addr_hit[184]: begin + reg_rdata_next[1:0] = prio_184_qs; + end + + addr_hit[185]: begin + reg_rdata_next[1:0] = prio_185_qs; + end + + addr_hit[186]: begin + reg_rdata_next[1:0] = prio_186_qs; + end + + addr_hit[187]: begin + reg_rdata_next[1:0] = prio_187_qs; + end + + addr_hit[188]: begin + reg_rdata_next[1:0] = prio_188_qs; + end + + addr_hit[189]: begin + reg_rdata_next[1:0] = prio_189_qs; + end + + addr_hit[190]: begin reg_rdata_next[0] = ip_0_p_0_qs; reg_rdata_next[1] = ip_0_p_1_qs; reg_rdata_next[2] = ip_0_p_2_qs; @@ -18981,7 +19587,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_0_p_31_qs; end - addr_hit[185]: begin + addr_hit[191]: begin reg_rdata_next[0] = ip_1_p_32_qs; reg_rdata_next[1] = ip_1_p_33_qs; reg_rdata_next[2] = ip_1_p_34_qs; @@ -19016,7 +19622,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_1_p_63_qs; end - addr_hit[186]: begin + addr_hit[192]: begin reg_rdata_next[0] = ip_2_p_64_qs; reg_rdata_next[1] = ip_2_p_65_qs; reg_rdata_next[2] = ip_2_p_66_qs; @@ -19051,7 +19657,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_2_p_95_qs; end - addr_hit[187]: begin + addr_hit[193]: begin reg_rdata_next[0] = ip_3_p_96_qs; reg_rdata_next[1] = ip_3_p_97_qs; reg_rdata_next[2] = ip_3_p_98_qs; @@ -19086,7 +19692,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_3_p_127_qs; end - addr_hit[188]: begin + addr_hit[194]: begin reg_rdata_next[0] = ip_4_p_128_qs; reg_rdata_next[1] = ip_4_p_129_qs; reg_rdata_next[2] = ip_4_p_130_qs; @@ -19121,7 +19727,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ip_4_p_159_qs; end - addr_hit[189]: begin + addr_hit[195]: begin reg_rdata_next[0] = ip_5_p_160_qs; reg_rdata_next[1] = ip_5_p_161_qs; reg_rdata_next[2] = ip_5_p_162_qs; @@ -19146,9 +19752,15 @@ module rv_plic_reg_top ( reg_rdata_next[21] = ip_5_p_181_qs; reg_rdata_next[22] = ip_5_p_182_qs; reg_rdata_next[23] = ip_5_p_183_qs; + reg_rdata_next[24] = ip_5_p_184_qs; + reg_rdata_next[25] = ip_5_p_185_qs; + reg_rdata_next[26] = ip_5_p_186_qs; + reg_rdata_next[27] = ip_5_p_187_qs; + reg_rdata_next[28] = ip_5_p_188_qs; + reg_rdata_next[29] = ip_5_p_189_qs; end - addr_hit[190]: begin + addr_hit[196]: begin reg_rdata_next[0] = ie0_0_e_0_qs; reg_rdata_next[1] = ie0_0_e_1_qs; reg_rdata_next[2] = ie0_0_e_2_qs; @@ -19183,7 +19795,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_0_e_31_qs; end - addr_hit[191]: begin + addr_hit[197]: begin reg_rdata_next[0] = ie0_1_e_32_qs; reg_rdata_next[1] = ie0_1_e_33_qs; reg_rdata_next[2] = ie0_1_e_34_qs; @@ -19218,7 +19830,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_1_e_63_qs; end - addr_hit[192]: begin + addr_hit[198]: begin reg_rdata_next[0] = ie0_2_e_64_qs; reg_rdata_next[1] = ie0_2_e_65_qs; reg_rdata_next[2] = ie0_2_e_66_qs; @@ -19253,7 +19865,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_2_e_95_qs; end - addr_hit[193]: begin + addr_hit[199]: begin reg_rdata_next[0] = ie0_3_e_96_qs; reg_rdata_next[1] = ie0_3_e_97_qs; reg_rdata_next[2] = ie0_3_e_98_qs; @@ -19288,7 +19900,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_3_e_127_qs; end - addr_hit[194]: begin + addr_hit[200]: begin reg_rdata_next[0] = ie0_4_e_128_qs; reg_rdata_next[1] = ie0_4_e_129_qs; reg_rdata_next[2] = ie0_4_e_130_qs; @@ -19323,7 +19935,7 @@ module rv_plic_reg_top ( reg_rdata_next[31] = ie0_4_e_159_qs; end - addr_hit[195]: begin + addr_hit[201]: begin reg_rdata_next[0] = ie0_5_e_160_qs; reg_rdata_next[1] = ie0_5_e_161_qs; reg_rdata_next[2] = ie0_5_e_162_qs; @@ -19348,21 +19960,27 @@ module rv_plic_reg_top ( reg_rdata_next[21] = ie0_5_e_181_qs; reg_rdata_next[22] = ie0_5_e_182_qs; reg_rdata_next[23] = ie0_5_e_183_qs; + reg_rdata_next[24] = ie0_5_e_184_qs; + reg_rdata_next[25] = ie0_5_e_185_qs; + reg_rdata_next[26] = ie0_5_e_186_qs; + reg_rdata_next[27] = ie0_5_e_187_qs; + reg_rdata_next[28] = ie0_5_e_188_qs; + reg_rdata_next[29] = ie0_5_e_189_qs; end - addr_hit[196]: begin + addr_hit[202]: begin reg_rdata_next[1:0] = threshold0_qs; end - addr_hit[197]: begin + addr_hit[203]: begin reg_rdata_next[7:0] = cc0_qs; end - addr_hit[198]: begin + addr_hit[204]: begin reg_rdata_next[0] = msip0_qs; end - addr_hit[199]: begin + addr_hit[205]: begin reg_rdata_next[0] = '0; end diff --git a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv index 4554ebe3e0d41..39c5785ba61e5 100644 --- a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv +++ b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv @@ -45,6 +45,10 @@ module earlgrey_pd_main #( parameter bit SecFlashCtrlScrambleEn = 1, parameter int FlashCtrlProgFifoDepth = 4, parameter int FlashCtrlRdFifoDepth = 16, + // parameters for rram_ctrl + parameter bit SecRramCtrlScrambleEn = 1, + parameter int RramCtrlWrFifoDepth = 4, + parameter int RramCtrlRdFifoDepth = 16, // parameters for rv_dm parameter logic [31:0] RvDmIdcodeValue = jtag_id_pkg::RV_DM_JTAG_IDCODE, parameter bit RvDmUseDmiInterface = 0, @@ -308,6 +312,12 @@ module earlgrey_pd_main #( localparam int SpiHost0NumCS = 1; // local parameters for spi_host1 localparam int SpiHost1NumCS = 1; + // local parameters for rram_macro + localparam int RramMacroTotalPages = rram_ctrl_pkg::TotalPages; + localparam int RramMacroDataWidth = rram_ctrl_pkg::DataWidth; + localparam int RramMacroWordsPerPage = rram_ctrl_pkg::WordsPerPage; + localparam int RramMacroTotalInfoPages = rram_ctrl_pkg::TotalInfoPages; + localparam int RramMacroMaxWrWords = rram_ctrl_pkg::MaxWrWords; // local parameters for entropy_src localparam int EntropySrcEsFifoDepth = 3; localparam int unsigned EntropySrcDistrFifoDepth = 3; @@ -325,9 +335,9 @@ module earlgrey_pd_main #( localparam bit RvCoreIbexInstructionPipeline = 1'b0; // Signals - logic [56:0] mio_p2d; - logic [64:0] mio_d2p; - logic [64:0] mio_en_d2p; + logic [59:0] mio_p2d; + logic [65:0] mio_d2p; + logic [65:0] mio_en_d2p; logic [15:0] dio_p2d; logic [15:0] dio_d2p; logic [15:0] dio_en_d2p; @@ -417,6 +427,13 @@ module earlgrey_pd_main #( logic cio_flash_ctrl_tdi_p2d; logic cio_flash_ctrl_tdo_d2p; logic cio_flash_ctrl_tdo_en_d2p; + // rram_ctrl + // rram_macro + logic cio_rram_macro_tck_p2d; + logic cio_rram_macro_tms_p2d; + logic cio_rram_macro_tdi_p2d; + logic cio_rram_macro_tdo_d2p; + logic cio_rram_macro_tdo_en_d2p; // rv_dm // rv_plic // aes @@ -434,7 +451,7 @@ module earlgrey_pd_main #( // rv_core_ibex - logic [183:0] intr_vector; + logic [189:0] intr_vector; // Interrupt source list logic intr_uart0_tx_watermark; logic intr_uart0_rx_watermark; @@ -561,6 +578,12 @@ module earlgrey_pd_main #( logic intr_flash_ctrl_rd_lvl; logic intr_flash_ctrl_op_done; logic intr_flash_ctrl_corr_err; + logic intr_rram_ctrl_wr_empty; + logic intr_rram_ctrl_wr_lvl; + logic intr_rram_ctrl_rd_full; + logic intr_rram_ctrl_rd_lvl; + logic intr_rram_ctrl_op_done; + logic intr_rram_ctrl_corr_err; logic intr_hmac_hmac_done; logic intr_hmac_fifo_empty; logic intr_hmac_hmac_err; @@ -681,6 +704,8 @@ module earlgrey_pd_main #( logic rv_dm_debug_req; spi_device_pkg::passthrough_req_t spi_device_passthrough_req; spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; + rram_ctrl_pkg::rram_macro_req_t rram_ctrl_rram_macro_req; + rram_ctrl_pkg::rram_macro_rsp_t rram_ctrl_rram_macro_rsp; tlul_pkg::tl_h2d_t main_tl_rv_core_ibex__corei_req; tlul_pkg::tl_d2h_t main_tl_rv_core_ibex__corei_rsp; tlul_pkg::tl_h2d_t main_tl_rv_core_ibex__cored_req; @@ -709,6 +734,12 @@ module earlgrey_pd_main #( tlul_pkg::tl_d2h_t flash_ctrl_prim_tl_rsp; tlul_pkg::tl_h2d_t flash_ctrl_mem_tl_req; tlul_pkg::tl_d2h_t flash_ctrl_mem_tl_rsp; + tlul_pkg::tl_h2d_t rram_ctrl_core_tl_req; + tlul_pkg::tl_d2h_t rram_ctrl_core_tl_rsp; + tlul_pkg::tl_h2d_t rram_macro_prim_tl_req; + tlul_pkg::tl_d2h_t rram_macro_prim_tl_rsp; + tlul_pkg::tl_h2d_t rram_ctrl_host_tl_req; + tlul_pkg::tl_d2h_t rram_ctrl_host_tl_rsp; tlul_pkg::tl_h2d_t hmac_tl_req; tlul_pkg::tl_d2h_t hmac_tl_rsp; tlul_pkg::tl_h2d_t kmac_tl_req; @@ -772,6 +803,8 @@ module earlgrey_pd_main #( logic rv_core_ibex_irq_timer; logic [31:0] rv_core_ibex_hart_id; logic [31:0] rv_core_ibex_boot_addr; + otp_ctrl_pkg::nvm_otp_key_req_t rram_ctrl_otp_key_req; + otp_ctrl_pkg::nvm_otp_key_rsp_t rram_ctrl_otp_key_rsp; jtag_pkg::jtag_req_t pinmux_dft_jtag_req; jtag_pkg::jtag_rsp_t pinmux_dft_jtag_rsp; otp_ctrl_part_pkg::otp_broadcast_t otp_ctrl_otp_broadcast; @@ -835,6 +868,12 @@ module earlgrey_pd_main #( otp_ctrl_keymgr_owner_seed }; + // TODO: remove once RRAM is connected to OTP + assign rram_ctrl_otp_key_rsp.data_ack = rram_ctrl_otp_key_req.data_req; + assign rram_ctrl_otp_key_rsp.addr_ack = rram_ctrl_otp_key_req.addr_req; + assign rram_ctrl_otp_key_rsp.key = '0; + assign rram_ctrl_otp_key_rsp.rand_key = '0; + assign rram_ctrl_otp_key_rsp.seed_valid = 1'b0; // Ibex-specific assignments // TODO: This should be further automated in the future. @@ -1976,8 +2015,102 @@ module earlgrey_pd_main #( .mem_tl_o(flash_ctrl_mem_tl_rsp) ); + rram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:38]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstAddrKey(RndCnstRramCtrlAddrKey), + .RndCnstDataKey(RndCnstRramCtrlDataKey), + .RndCnstAllSeeds(RndCnstRramCtrlAllSeeds), + .RndCnstLfsrSeed(RndCnstRramCtrlLfsrSeed), + .RndCnstLfsrPerm(RndCnstRramCtrlLfsrPerm), + .SecScrambleEn(SecRramCtrlScrambleEn), + .WrFifoDepth(RramCtrlWrFifoDepth), + .RdFifoDepth(RramCtrlRdFifoDepth) + ) u_rram_ctrl ( + // Clock and reset connections + .clk_i(clkmgr_clocks_i.clk_main_infra), + .clk_otp_i(clkmgr_clocks_i.clk_io_div4_infra), + .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), + .rst_otp_ni(rstmgr_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), + + // Interrupts + .intr_wr_empty_o(intr_rram_ctrl_wr_empty), + .intr_wr_lvl_o (intr_rram_ctrl_wr_lvl), + .intr_rd_full_o (intr_rram_ctrl_rd_full), + .intr_rd_lvl_o (intr_rram_ctrl_rd_lvl), + .intr_op_done_o (intr_rram_ctrl_op_done), + .intr_corr_err_o(intr_rram_ctrl_corr_err), + + // alert_handler[38]: recov_err + // alert_handler[39]: fatal_std_err + // alert_handler[40]: fatal_err + // alert_handler[41]: fatal_macro_err + // alert_handler[42]: recov_macro_err + .alert_tx_o(alert_tx[42:38]), + .alert_rx_i(alert_rx[42:38]), + + // Inter-module signals + .rram_macro_o(rram_ctrl_rram_macro_req), + .rram_macro_i(rram_ctrl_rram_macro_rsp), + .otp_key_o(rram_ctrl_otp_key_req), + .otp_key_i(rram_ctrl_otp_key_rsp), + .otp_macro_i('0), + .otp_macro_o(), + .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), + .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en), + .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en), + .lc_iso_part_sw_wr_en_i(lc_ctrl_lc_iso_part_sw_wr_en), + .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .rma_req_i(lc_ctrl_lc_nvm_rma_req), + .rma_ack_o(), + .rma_seed_i(lc_ctrl_lc_nvm_rma_seed), + .pwrmgr_o(), + .keymgr_o(), + .core_tl_i(rram_ctrl_core_tl_req), + .core_tl_o(rram_ctrl_core_tl_rsp), + .host_tl_i(rram_ctrl_host_tl_req), + .host_tl_o(rram_ctrl_host_tl_rsp) + ); + + rram_macro #( + .TotalPages(RramMacroTotalPages), + .DataWidth(RramMacroDataWidth), + .WordsPerPage(RramMacroWordsPerPage), + .TotalInfoPages(RramMacroTotalInfoPages), + .MaxWrWords(RramMacroMaxWrWords) + ) u_rram_macro ( + // Clock and reset connections + .clk_i(clkmgr_clocks_i.clk_main_infra), + .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), + + // DFT/scan connections + .scanmode_i, + .scan_rst_ni, + .scan_en_i, + + + // CIO inputs + .cio_tck_i (cio_rram_macro_tck_p2d), + .cio_tms_i (cio_rram_macro_tms_p2d), + .cio_tdi_i (cio_rram_macro_tdi_p2d), + + // CIO outputs + .cio_tdo_o (cio_rram_macro_tdo_d2p), + .cio_tdo_en_o(cio_rram_macro_tdo_en_d2p), + + // Inter-module signals + .rram_macro_i(rram_ctrl_rram_macro_req), + .rram_macro_o(rram_ctrl_rram_macro_rsp), + .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), + .obs_ctrl_i(ast_obs_ctrl), + .rram_obs_o(), + .prim_tl_i(rram_macro_prim_tl_req), + .prim_tl_o(rram_macro_prim_tl_rsp) + ); + rv_dm #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .IdcodeValue(RvDmIdcodeValue), .UseDmiInterface(RvDmUseDmiInterface), @@ -1994,9 +2127,9 @@ module earlgrey_pd_main #( .scanmode_i, .scan_rst_ni, - // alert_handler[38]: fatal_fault - .alert_tx_o(alert_tx[38]), - .alert_rx_i(alert_rx[38]), + // alert_handler[43]: fatal_fault + .alert_tx_o(alert_tx[43]), + .alert_rx_i(alert_rx[43]), // Inter-module signals .next_dm_addr_i('0), @@ -2029,16 +2162,16 @@ module earlgrey_pd_main #( ); rv_plic #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44]), .AlertSkewCycles(top_pkg::AlertSkewCycles) ) u_rv_plic ( // Clock and reset connections .clk_i(clkmgr_clocks_i.clk_main_secure), .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[39]: fatal_fault - .alert_tx_o(alert_tx[39]), - .alert_rx_i(alert_rx[39]), + // alert_handler[44]: fatal_fault + .alert_tx_o(alert_tx[44]), + .alert_rx_i(alert_rx[44]), // Inter-module signals .irq_o(rv_plic_irq), @@ -2053,7 +2186,7 @@ module earlgrey_pd_main #( ); aes #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .AES192Enable(1'b1), .AESGCMEnable(AesAESGCMEnable), @@ -2075,10 +2208,10 @@ module earlgrey_pd_main #( .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), .rst_edn_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[40]: recov_ctrl_update_err - // alert_handler[41]: fatal_fault - .alert_tx_o(alert_tx[41:40]), - .alert_rx_i(alert_rx[41:40]), + // alert_handler[45]: recov_ctrl_update_err + // alert_handler[46]: fatal_fault + .alert_tx_o(alert_tx[46:45]), + .alert_rx_i(alert_rx[46:45]), // Inter-module signals .idle_o(clkmgr_idle_o[0]), @@ -2093,7 +2226,7 @@ module earlgrey_pd_main #( ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47]), .AlertSkewCycles(top_pkg::AlertSkewCycles) ) u_hmac ( // Clock and reset connections @@ -2105,9 +2238,9 @@ module earlgrey_pd_main #( .intr_fifo_empty_o(intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // alert_handler[42]: fatal_fault - .alert_tx_o(alert_tx[42]), - .alert_rx_i(alert_rx[42]), + // alert_handler[47]: fatal_fault + .alert_tx_o(alert_tx[47]), + .alert_rx_i(alert_rx[47]), // Inter-module signals .idle_o(clkmgr_idle_o[1]), @@ -2116,7 +2249,7 @@ module earlgrey_pd_main #( ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .EnMasking(KmacEnMasking), .SwKeyMasked(KmacSwKeyMasked), @@ -2141,10 +2274,10 @@ module earlgrey_pd_main #( .intr_fifo_empty_o(intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // alert_handler[43]: recov_operation_err - // alert_handler[44]: fatal_fault_err - .alert_tx_o(alert_tx[44:43]), - .alert_rx_i(alert_rx[44:43]), + // alert_handler[48]: recov_operation_err + // alert_handler[49]: fatal_fault_err + .alert_tx_o(alert_tx[49:48]), + .alert_rx_i(alert_rx[49:48]), // Inter-module signals .keymgr_key_i(keymgr_kmac_key), @@ -2160,7 +2293,7 @@ module earlgrey_pd_main #( ); otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .Stub(OtbnStub), .RegFile(OtbnRegFile), @@ -2184,10 +2317,10 @@ module earlgrey_pd_main #( // Interrupts .intr_done_o(intr_otbn_done), - // alert_handler[45]: fatal - // alert_handler[46]: recov - .alert_tx_o(alert_tx[46:45]), - .alert_rx_i(alert_rx[46:45]), + // alert_handler[50]: fatal + // alert_handler[51]: recov + .alert_tx_o(alert_tx[51:50]), + .alert_rx_i(alert_rx[51:50]), // Inter-module signals .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), @@ -2212,7 +2345,7 @@ module earlgrey_pd_main #( ); keymgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:52]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .UseOtpSeedsInsteadOfFlash(KeymgrUseOtpSeedsInsteadOfFlash), .KmacEnMasking(KeymgrKmacEnMasking), @@ -2241,10 +2374,10 @@ module earlgrey_pd_main #( // Interrupts .intr_op_done_o(intr_keymgr_op_done), - // alert_handler[47]: recov_operation_err - // alert_handler[48]: fatal_fault_err - .alert_tx_o(alert_tx[48:47]), - .alert_rx_i(alert_rx[48:47]), + // alert_handler[52]: recov_operation_err + // alert_handler[53]: fatal_fault_err + .alert_tx_o(alert_tx[53:52]), + .alert_rx_i(alert_rx[53:52]), // Inter-module signals .edn_o(edn0_edn_req[0]), @@ -2266,7 +2399,7 @@ module earlgrey_pd_main #( ); csrng #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:54]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), @@ -2282,10 +2415,10 @@ module earlgrey_pd_main #( .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), - // alert_handler[49]: recov_alert - // alert_handler[50]: fatal_alert - .alert_tx_o(alert_tx[50:49]), - .alert_rx_i(alert_rx[50:49]), + // alert_handler[54]: recov_alert + // alert_handler[55]: fatal_alert + .alert_tx_o(alert_tx[55:54]), + .alert_rx_i(alert_rx[55:54]), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -2299,7 +2432,7 @@ module earlgrey_pd_main #( ); entropy_src #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:56]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RngBusWidth(EntropySrcRngBusWidth), .RngBusBitSelWidth(EntropySrcRngBusBitSelWidth), @@ -2318,10 +2451,10 @@ module earlgrey_pd_main #( .intr_es_observe_fifo_ready_o(intr_entropy_src_es_observe_fifo_ready), .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), - // alert_handler[51]: recov_alert - // alert_handler[52]: fatal_alert - .alert_tx_o(alert_tx[52:51]), - .alert_rx_i(alert_rx[52:51]), + // alert_handler[56]: recov_alert + // alert_handler[57]: fatal_alert + .alert_tx_o(alert_tx[57:56]), + .alert_rx_i(alert_rx[57:56]), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -2343,7 +2476,7 @@ module earlgrey_pd_main #( ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .NumEndPoints(Edn0NumEndPoints) ) u_edn0 ( @@ -2355,10 +2488,10 @@ module earlgrey_pd_main #( .intr_edn_cmd_req_done_o(intr_edn0_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), - // alert_handler[53]: recov_alert - // alert_handler[54]: fatal_alert - .alert_tx_o(alert_tx[54:53]), - .alert_rx_i(alert_rx[54:53]), + // alert_handler[58]: recov_alert + // alert_handler[59]: fatal_alert + .alert_tx_o(alert_tx[59:58]), + .alert_rx_i(alert_rx[59:58]), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[0]), @@ -2370,7 +2503,7 @@ module earlgrey_pd_main #( ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:60]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .NumEndPoints(Edn1NumEndPoints) ) u_edn1 ( @@ -2382,10 +2515,10 @@ module earlgrey_pd_main #( .intr_edn_cmd_req_done_o(intr_edn1_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), - // alert_handler[55]: recov_alert - // alert_handler[56]: fatal_alert - .alert_tx_o(alert_tx[56:55]), - .alert_rx_i(alert_rx[56:55]), + // alert_handler[60]: recov_alert + // alert_handler[61]: fatal_alert + .alert_tx_o(alert_tx[61:60]), + .alert_rx_i(alert_rx[61:60]), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[1]), @@ -2397,7 +2530,7 @@ module earlgrey_pd_main #( ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[62]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstSramKey(RndCnstSramCtrlMainSramKey), .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), @@ -2417,9 +2550,9 @@ module earlgrey_pd_main #( .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), .rst_otp_ni(rstmgr_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[57]: fatal_error - .alert_tx_o(alert_tx[57]), - .alert_rx_i(alert_rx[57]), + // alert_handler[62]: fatal_error + .alert_tx_o(alert_tx[62]), + .alert_rx_i(alert_rx[62]), // RACL policies .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), @@ -2442,7 +2575,7 @@ module earlgrey_pd_main #( ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstSramKey(RndCnstSramCtrlSecSramKey), .RndCnstSramNonce(RndCnstSramCtrlSecSramNonce), @@ -2462,9 +2595,9 @@ module earlgrey_pd_main #( .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), .rst_otp_ni(rstmgr_resets_i.rst_lc_io_div4_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[58]: fatal_error - .alert_tx_o(alert_tx[58]), - .alert_rx_i(alert_rx[58]), + // alert_handler[63]: fatal_error + .alert_tx_o(alert_tx[63]), + .alert_rx_i(alert_rx[63]), // RACL policies .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), @@ -2487,7 +2620,7 @@ module earlgrey_pd_main #( ); rom_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .BootRomInitFile(RomCtrlBootRomInitFile), .FlopToKmac(RomCtrlFlopToKmac), @@ -2500,9 +2633,9 @@ module earlgrey_pd_main #( .clk_i(clkmgr_clocks_i.clk_main_infra), .rst_ni(rstmgr_resets_i.rst_lc_n[rstmgr_pkg::DomainMainSel]), - // alert_handler[59]: fatal - .alert_tx_o(alert_tx[59]), - .alert_rx_i(alert_rx[59]), + // alert_handler[64]: fatal + .alert_tx_o(alert_tx[64]), + .alert_rx_i(alert_rx[64]), // Inter-module signals .rom_cfg_i(rom_ctrl_rom_cfg_req_i), @@ -2518,7 +2651,7 @@ module earlgrey_pd_main #( ); rv_core_ibex #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63:60]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[68:65]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed), .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm), @@ -2573,12 +2706,12 @@ module earlgrey_pd_main #( .scanmode_i, .scan_rst_ni, - // alert_handler[60]: fatal_sw_err - // alert_handler[61]: recov_sw_err - // alert_handler[62]: fatal_hw_err - // alert_handler[63]: recov_hw_err - .alert_tx_o(alert_tx[63:60]), - .alert_rx_i(alert_rx[63:60]), + // alert_handler[65]: fatal_sw_err + // alert_handler[66]: recov_sw_err + // alert_handler[67]: fatal_hw_err + // alert_handler[68]: recov_hw_err + .alert_tx_o(alert_tx[68:65]), + .alert_rx_i(alert_rx[68:65]), // Inter-module signals .rst_cpu_n_o(), @@ -2615,26 +2748,32 @@ module earlgrey_pd_main #( // Interrupt assignments assign intr_vector = { - intr_edn1_edn_fatal_err, // ID 183 - intr_edn1_edn_cmd_req_done, // ID 182 - intr_edn0_edn_fatal_err, // ID 181 - intr_edn0_edn_cmd_req_done, // ID 180 - intr_entropy_src_es_fatal_err, // ID 179 - intr_entropy_src_es_observe_fifo_ready, // ID 178 - intr_entropy_src_es_health_test_failed, // ID 177 - intr_entropy_src_es_entropy_valid, // ID 176 - intr_csrng_cs_fatal_err, // ID 175 - intr_csrng_cs_hw_inst_exc, // ID 174 - intr_csrng_cs_entropy_req, // ID 173 - intr_csrng_cs_cmd_req_done, // ID 172 - intr_keymgr_op_done, // ID 171 - intr_otbn_done, // ID 170 - intr_kmac_kmac_err, // ID 169 - intr_kmac_fifo_empty, // ID 168 - intr_kmac_kmac_done, // ID 167 - intr_hmac_hmac_err, // ID 166 - intr_hmac_fifo_empty, // ID 165 - intr_hmac_hmac_done, // ID 164 + intr_edn1_edn_fatal_err, // ID 189 + intr_edn1_edn_cmd_req_done, // ID 188 + intr_edn0_edn_fatal_err, // ID 187 + intr_edn0_edn_cmd_req_done, // ID 186 + intr_entropy_src_es_fatal_err, // ID 185 + intr_entropy_src_es_observe_fifo_ready, // ID 184 + intr_entropy_src_es_health_test_failed, // ID 183 + intr_entropy_src_es_entropy_valid, // ID 182 + intr_csrng_cs_fatal_err, // ID 181 + intr_csrng_cs_hw_inst_exc, // ID 180 + intr_csrng_cs_entropy_req, // ID 179 + intr_csrng_cs_cmd_req_done, // ID 178 + intr_keymgr_op_done, // ID 177 + intr_otbn_done, // ID 176 + intr_kmac_kmac_err, // ID 175 + intr_kmac_fifo_empty, // ID 174 + intr_kmac_kmac_done, // ID 173 + intr_hmac_hmac_err, // ID 172 + intr_hmac_fifo_empty, // ID 171 + intr_hmac_hmac_done, // ID 170 + intr_rram_ctrl_corr_err, // ID 169 + intr_rram_ctrl_op_done, // ID 168 + intr_rram_ctrl_rd_lvl, // ID 167 + intr_rram_ctrl_rd_full, // ID 166 + intr_rram_ctrl_wr_lvl, // ID 165 + intr_rram_ctrl_wr_empty, // ID 164 intr_flash_ctrl_corr_err, // ID 163 intr_flash_ctrl_op_done, // ID 162 intr_flash_ctrl_rd_lvl, // ID 161 @@ -2839,6 +2978,18 @@ module earlgrey_pd_main #( .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req), .tl_flash_ctrl__mem_i(flash_ctrl_mem_tl_rsp), + // port: tl_rram_ctrl__core + .tl_rram_ctrl__core_o(rram_ctrl_core_tl_req), + .tl_rram_ctrl__core_i(rram_ctrl_core_tl_rsp), + + // port: tl_rram_macro__prim + .tl_rram_macro__prim_o(rram_macro_prim_tl_req), + .tl_rram_macro__prim_i(rram_macro_prim_tl_rsp), + + // port: tl_rram_ctrl__host + .tl_rram_ctrl__host_o(rram_ctrl_host_tl_req), + .tl_rram_ctrl__host_i(rram_ctrl_host_tl_rsp), + // port: tl_hmac .tl_hmac_o(hmac_tl_req), .tl_hmac_i(hmac_tl_rsp), @@ -3066,6 +3217,9 @@ module earlgrey_pd_main #( assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck]; assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms]; assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi]; + assign cio_rram_macro_tck_p2d = mio_p2d[MioInRramMacroTck]; + assign cio_rram_macro_tms_p2d = mio_p2d[MioInRramMacroTms]; + assign cio_rram_macro_tdi_p2d = mio_p2d[MioInRramMacroTdi]; assign cio_sysrst_ctrl_ac_present_p2d_o = mio_p2d[MioInSysrstCtrlAcPresent]; assign cio_sysrst_ctrl_key0_in_p2d_o = mio_p2d[MioInSysrstCtrlKey0In]; assign cio_sysrst_ctrl_key1_in_p2d_o = mio_p2d[MioInSysrstCtrlKey1In]; @@ -3124,6 +3278,7 @@ module earlgrey_pd_main #( assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p; assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p; assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p; + assign mio_d2p[MioOutRramMacroTdo] = cio_rram_macro_tdo_d2p; assign mio_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_d2p_i[0]; assign mio_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_d2p_i[1]; assign mio_d2p[MioOutSensorCtrlAstDebugOut2] = cio_sensor_ctrl_ast_debug_out_d2p_i[2]; @@ -3191,6 +3346,7 @@ module earlgrey_pd_main #( assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p; assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p; assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p; + assign mio_en_d2p[MioOutRramMacroTdo] = cio_rram_macro_tdo_en_d2p; assign mio_en_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_en_d2p_i[0]; assign mio_en_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_en_d2p_i[1]; assign mio_en_d2p[MioOutSensorCtrlAstDebugOut2] = cio_sensor_ctrl_ast_debug_out_en_d2p_i[2]; diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv index aafa746834281..5dda5a90429d5 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv @@ -19,17 +19,17 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter otp_ctrl_top_specific_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { - 40'h08_F9EED04C + 40'hE6_596E87F9 }; // Compile-time random permutation for LFSR output parameter otp_ctrl_top_specific_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { - 240'h9577_622D2367_4E16822A_46C638C2_5664F143_44750422_379C01F6_10566801 + 240'h6E58_9D685860_3D61C92C_462744A5_D47C838C_04D0C279_04D26401_A356499C }; // Compile-time random permutation for scrambling key/nonce register reset value parameter otp_ctrl_top_specific_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { - 256'h956C7F90_4B9EDED0_9B89A754_33566F49_63D9DC27_F3ECB11C_E3B87AAA_7ABC8592 + 256'h4FB9D469_171B950E_364B0DAC_5469568E_661498FD_89197CCA_E8EA08FF_43EFC2BF }; // Compile-time scrambling key @@ -237,35 +237,35 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Diversification value used for all invalid life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { - 128'h0B188108_3AFF7BDE_18EACFF8_5679453D + 128'hB1C6AB5C_C63E6F47_41E80F77_7CB7FC05 }; // Diversification value used for the TEST_UNLOCKED* life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { - 128'hA77D92A1_76B87118_AF11CDBE_78D67060 + 128'h041A1B89_6350C963_6D6814D2_3E2F5FF1 }; // Diversification value used for the DEV life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { - 128'h615A20B9_C0740F07_969CCD2D_10A1A6E7 + 128'h275EF199_59AAA8B6_A004D557_4984DED1 }; // Diversification value used for the PROD/PROD_END life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { - 128'h988FA528_AC032E0A_6138CB83_16FF95C6 + 128'hCC79BD67_87D6663A_A5E62268_2A6525E0 }; // Diversification value used for the RMA life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { - 128'h5CD7A1A7_68B06E01_06D60EDA_0F1BC67A + 128'h83CCDDBD_2A1B0080_57C22C88_4ED49D87 }; // Compile-time random bits used for invalid tokens in the token mux parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { - 256'hDF85BD9A_56EA088D_33FFAA6A_1155AFB0_169AB2DE_3973D027_EE30B8F9_01F644EC, - 256'h7CD3E56C_8ED1EC38_739F1D0D_EB7C7741_99CF6DD0_57F44C13_E25C7A58_77BC5242, - 256'hE6EE63EC_DF458AE6_596E87F9_F973DB98_AAA29356_8FD1F31A_0165939D_819D1518, - 256'h690E6473_CDB24793_91635057_CA1045B9_E1917E1F_F0189B04_A4F7FBA9_60FE098A + 256'hA5B56BA7_353C5321_42F50667_E220C5B7_24C3FDB6_D060653B_42A96F88_B574E4D3, + 256'h814F5116_B3E6F3E3_31DA1182_DBC29C89_4F1800ED_ECF7B176_82D2CE3D_B9B12E1A, + 256'hF4339E1F_45164A41_8EBC5221_0D58DC65_508E869A_F565C1B8_7D687EE8_37FC119F, + 256'h5BBE7395_CAC38919_C27006C2_3E142591_0840042A_75ECC25D_4E2267E3_BFF26E00 }; //////////////////////////////////////////// @@ -273,12 +273,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter alert_handler_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { - 32'h4FB9D469 + 32'h3AACBF7D }; // Compile-time random permutation for LFSR output parameter alert_handler_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { - 160'h769F9B6F_A88170B2_0267F53E_C8DDAAAF_1260C862 + 160'h13CC9759_93DE297D_46B0CC88_51F1BEFA_C28074EA }; //////////////////////////////////////////// @@ -286,23 +286,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetSramKey = { - 128'hFC05041A_1B896350_C9636D68_14D23E2F + 128'hCD6CD2CE_715E7CCE_B1BC1C61_B3D27BB8 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetSramNonce = { - 128'h5FF1275E_F19959AA_A8B6A004_D5574984 + 128'hE8398E88_0ECD2529_56BA8161_6362B27E }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetLfsrSeed = { - 64'hDED1CC79_BD6787D6 + 64'hAFB903EC_79BDDF0A }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetLfsrPerm = { - 128'h76599773_2C42D6C6_D20EEB45_DE3F91AF, - 256'h4C07A8CA_1E7C4598_938050ED_43CDEBD8_674E22D5_D801BCBF_3809FCA6_88E69399 + 128'h7AAAECC2_51DD554E_63EF872F_34838ACF, + 256'hE31142E0_9287CD29_6D65DA64_6CB53C49_ED9A0E89_8852C0C6_8FC3918D_FDD817D3 }; //////////////////////////////////////////// @@ -310,29 +310,59 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for default address key parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlAddrKey = { - 128'hB12E1AF4_339E1F45_164A418E_BC52210D + 128'h5C0CAE7E_D7FE6C45_D1534FD3_90C7B068 }; // Compile-time random bits for default data key parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlDataKey = { - 128'h58DC6550_8E869AF5_65C1B87D_687EE837 + 128'hCFE89687_94DE88E8_FF4ADC3D_02EBFA0A }; // Compile-time random bits for default seeds parameter flash_ctrl_top_specific_pkg::all_seeds_t RndCnstFlashCtrlAllSeeds = { - 256'hFC119F5B_BE7395CA_C38919C2_7006C23E_14259108_40042A75_ECC25D4E_2267E3BF, - 256'hF26E003A_ACBF7D51_3AEA01E9_EE420D5B_523F6B00_C81BDED7_282425B1_BB59B801 + 256'h1D5FAA5E_E00CA534_911723E1_EA068740_2A816510_C535A816_4939D97D_F7421AD4, + 256'hD2C18B27_0D422EC3_9C41F727_D130ED9B_18B90E42_E4287F60_AD57D6A5_51E78F94 }; // Compile-time random bits for initial LFSR seed parameter flash_ctrl_top_specific_pkg::lfsr_seed_t RndCnstFlashCtrlLfsrSeed = { - 64'h481ED579_3ACCFB3A + 64'h0B8AE9F2_BB40621F }; // Compile-time random permutation for LFSR output parameter flash_ctrl_top_specific_pkg::lfsr_perm_t RndCnstFlashCtrlLfsrPerm = { - 128'hB869F014_42D0211E_544E5F2A_66948C77, - 256'h46A6EB8F_40C643D6_EE8B60DC_A2438A33_9EBD81EC_7D77356F_3095CB60_7F36B87E + 128'h56869361_988CC8F1_EB9B97E5_537227B6, + 256'hE5DE0FE4_BAB1B756_87DC4A11_1BC9CC0E_3B3A409C_C01A6018_5FE32F43_75DAAF10 + }; + + //////////////////////////////////////////// + // rram_ctrl + //////////////////////////////////////////// + // Compile-time random bits for default address key + parameter rram_ctrl_pkg::rram_key_t RndCnstRramCtrlAddrKey = { + 128'h40CA72CE_50C55920_BA14E126_DCD0A3F6 + }; + + // Compile-time random bits for default data key + parameter rram_ctrl_pkg::rram_key_t RndCnstRramCtrlDataKey = { + 128'hC9B71D03_E571BEE0_E47E5B49_E80E3DA3 + }; + + // Compile-time random bits for default seeds + parameter rram_ctrl_pkg::all_seeds_t RndCnstRramCtrlAllSeeds = { + 256'h9A52777D_BCFD9E38_D4D189EC_4B433E53_14F88C89_3A6CB3FD_30A87C38_225A1510, + 256'h8E992D14_BF1225D4_B19B23F4_0E358F1B_F4FE1D5A_50B10232_A8B3C33A_6017B970 + }; + + // Compile-time random bits for initial LFSR seed + parameter rram_ctrl_pkg::lfsr_seed_t RndCnstRramCtrlLfsrSeed = { + 64'h36561AA2_62310424 + }; + + // Compile-time random permutation for LFSR output + parameter rram_ctrl_pkg::lfsr_perm_t RndCnstRramCtrlLfsrPerm = { + 128'h08F2BE5E_F95BAC55_48A33487_42170E9C, + 256'h647700D6_133099AC_ABCC72E9_A2E4520D_1E8E27C4_FF5C2EDB_DB690F85_9977BE41 }; //////////////////////////////////////////// @@ -340,34 +370,34 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for register clearing. parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { - 64'h3EAE3C2F_18B4666B + 64'hD66B5813_54CBCB9A }; // Permutation applied to the LFSR of the PRNG used for clearing. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { - 128'h7DC306FB_5D82893B_03A5445E_87FC8A20, - 256'hDDEEF660_4EAABCD9_6B8C52BE_8E843F9F_1091D540_ED8C2380_7165B672_C96F4597 + 128'h7BE94F37_F4088F9C_141F8743_4554E6CD, + 256'hA61B4AD9_3428915F_F5CF2BB8_4B0B5C08_B71B282A_A3AA4286_FD8C056E_E7D59C4E }; // Permutation applied to the clearing PRNG output for clearing the second share of registers. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { - 128'h967BFC5C_0D074F65_B5742CEE_8DBADEF9, - 256'h8EF045C5_1ADD590F_F66A6C33_2A0BB432_621B97CE_4BFA8DC4_46602908_41EB8205 + 128'h7FA5F85B_1AFF0915_4166EB3E_D4AA3D60, + 256'hF404A6FA_BCD06D9E_372E5D0D_41478A03_128DB6A4_97B9F320_B3ADDC04_DC866270 }; // Default seed of the PRNG used for masking. parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { - 32'hEF142E02, - 256'h83257145_13BFDC2A_062C2EB4_ECDC716A_92861FF7_C06C6910_E727CBED_4EE2B19E + 32'hD8582552, + 256'h6737C611_FA0E7D75_4AE64A35_4CC7C16F_A06AE28E_208C1D5A_FC5F0D9D_E8D61CC3 }; // Permutation applied to the output of the PRNG used for masking. parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { - 256'h64058194_3F434535_8388890F_78626692_4B904E13_2A5D1060_0C57399B_2E063B5C, - 256'h37002F4A_48179151_82538B27_6C2C635A_348F2455_748C8D3C_6F1E2380_22417504, - 256'h9C423386_56323A85_61976D31_7F2B1B38_0B307019_01287A84_0D651A07_694D9A12, - 256'h095F6716_4C9F0898_2D117C3E_54188E36_8A79460A_961F9D25_9944686A_1C4F875E, - 256'h93779E3D_0E495B7E_71031D26_14205950_7240157D_7B952902_7376586B_6E215247 + 256'h5B671E8F_6A9A7218_5A85382F_120B4992_1C069811_7B91909F_4E524C36_43762C94, + 256'h47587732_196B1D35_2A0A5481_15995053_1B443982_8A7A782D_93591334_8B7D5131, + 256'h37230C30_4B273B9E_898C6100_1F41634F_757F4846_6C9B0109_034A2604_3C627197, + 256'h253D079C_05695C7E_248E732E_107C2B57_6F42885D_5614705E_744D5508_0F96283A, + 256'h2186953F_683E0E33_22178D80_5F647960_836D1602_0D846E45_1A874029_9D666520 }; //////////////////////////////////////////// @@ -375,58 +405,58 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random data for PRNG default seed parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { - 32'h9D9F58F7, - 256'h0432D8BF_8509A79C_A1D3AB83_A61AF330_C5CFD188_035E2F18_108133B3_8A7167F8 + 32'hB4592FF1, + 256'h9842D516_06FE22B8_ED0E3F50_759650EF_701A4E6E_4916EEE5_6EF868E4_092F9516 }; // Compile-time random permutation for PRNG output parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { - 64'h1730472D_BE79E723, - 256'h5E533D13_5B585590_45F55C9D_1D021955_3C5B2708_85C0B3CD_35C62D1E_CF7260D8, - 256'h7AEB26A5_DA341F11_C5F694A4_300D6B76_EDB13E3D_252F9632_A8A34D50_C01C4B84, - 256'hB502E7AC_70151A6A_C6C3130C_771BE1A9_DDB84B1C_E9FE0531_95B74C84_B4A6C284, - 256'h89096785_4A5653D9_645C676F_2BE71805_B7A71B3B_05761E28_A50C84ED_042A5B47, - 256'h168728BC_66E25531_116F5795_E1F7414E_7596F0C0_2AEA387E_7ED104F4_CAA1CD44, - 256'h9E35436F_23360E73_E2A42588_A268FC55_A836A28B_DF113C58_3A0F0A65_E648EA11, - 256'h5BDADC42_C14761F9_D1075160_AA88F30B_2A37867E_0FCFE8C1_CC6BB073_585224ED, - 256'h51CA6885_65D22F03_54EFB810_9F0057D2_D9C3480E_E3499211_1DD996EA_C201B5EA, - 256'hE66AB189_3AB3AE23_4B0E88A9_88545313_11C64880_0E704170_A43C1980_61BAC87A, - 256'h4DEAC2A9_3BD1F268_FA29D737_206BB028_46FD0F55_624A5960_306BB83E_61082ACC, - 256'h75823C9E_4408DD52_E198729F_7E9F25FC_A3B9131C_0A2733AC_5749FC38_8149B407, - 256'hB500285C_68010F00_26750BDF_9B28E8A6_AED821B7_A41EE910_B4534AE9_7E7A25A1, - 256'h4A90562E_17275986_36E930A2_01A64E68_027B808E_A78EF477_D9F099FD_A1AE3046, - 256'h12512FC2_65C9C191_25D70D6C_D9090943_C6712489_DC37C0DA_76C46500_B38CF823, - 256'h08D8E69E_2AA493A6_513B47D9_14B710AB_A526F875_44347AD7_4ED4E0E9_85C25B43, - 256'h72467E12_604D80A5_55A4D1B6_0B70C200_5A5A95DA_ADDE5880_C462185C_15E10717, - 256'hB75C24FE_E1BD4D10_6104B4D0_12446D5D_D9A0C937_AF1849DA_FF30AF15_D20C69A5, - 256'h051EE8A9_C9B7827D_68AA5666_3195EBF1_40C47C18_1BA64B62_52A88C35_2B4B07F9, - 256'hFFC3AAF6_78B39CEF_D5B47C0B_8B97A2DA_751C425E_DF8FD916_3A33541E_C661A73F, - 256'hCB108D87_B80B2C69_7C585258_DA3C3F4E_5C7816A2_E07B45F4_242CC0F8_4C302639, - 256'h30A61884_D0697B99_8D948C8F_C3E828F8_EC455B58_426BA51D_97B4BA59_DA304108, - 256'h63500981_6699E62B_72A0B62E_B07AF327_9CD889A5_93CCCBBC_A44E878B_0A482AD1, - 256'hA3D4FBA6_0835581D_324A057D_933208AB_BA8018C5_D1B2C92B_2B70DCEB_96A8A270, - 256'h27B66371_3A2E7CEB_505476A6_E1621A26_BEAF6419_EF690701_FE5CAD13_9B1C1F18, - 256'h1B058C45_001591AB_14C7E034_A569509B_163D030A_98A44CA9_B1A47798_0A8E0A8B, - 256'h8A7C46C4_9928CF71_52D8B291_C585B6E4_69966AA0_E05842D6_49611962_EB656024, - 256'h6CAAD064_796EAA13_86928BCE_4505D72B_D0E5514A_15C5E048_224FA1B6_EC614E20, - 256'h92FDEA3F_20B9E5D0_8C948121_360E62B4_BC3D0AD2_12055C28_A6F119D1_A71A0C70, - 256'hF90EC889_52BD5F9E_5834590D_26945A8C_878A5A15_95B2C730_D87520A8_14CD284A, - 256'hDF5BF895_5D8C714C_BD9B84A6_AD6EAE40_F6B2E523_9AF670C5_022CD0CC_511EA064, - 256'h923B6865_E71C8738_13087492_C2D322EE_971519D2_F8653DAE_C32C4090_24D544B5 + 64'h30A2887D_19A2CB9A, + 256'h171B18CB_3951EA60_EDCB28D0_31A948B1_626E2A58_6C97C193_EA12F357_C4EC5E9A, + 256'h69186A0C_D66F8E76_55E4A881_D5D1D11C_9E13A6D3_9F22311D_6E5983E5_349C0615, + 256'h77081319_1E5408DA_5443B01E_9189CF65_0AF28A44_21E5D799_6EA6EEF1_29C50B7A, + 256'hBAC38171_85AF260C_520DFA4C_C903FE88_0665C306_D9B60CA7_6DD2002F_F41A2A9E, + 256'hED41B681_5C2141CF_1E641EB8_0D368922_D9481E2A_A1523173_AF5B5A09_DE86604C, + 256'h55108792_5AB8328C_A7021149_BBA3A0C6_866A8E81_ACA3018B_5B6C8F6B_4020BD8B, + 256'h7398430E_5799A451_DEC21803_78982A66_E1046DD5_55915AA1_FF52DEDB_6961006D, + 256'hD47ED04E_99C6B2D5_1E8541A6_0D77D6B7_B08A07D4_3AD46FB2_2C04F678_90DB2B5C, + 256'h5DB383A4_1302582A_76685E2C_4053F213_C3D0D06D_D8AFCAF8_3CD57CA6_F9C60059, + 256'h169A7455_3B8A891F_0421A9B1_B8229FC4_38F00D3D_EE1020D9_7650E605_8C4B5356, + 256'h08F5AC55_84A4A142_1E27F00F_8C2554AE_B2344922_0589A7DC_60963FAA_716A3051, + 256'h7D8F02D8_EF012672_FD75AD19_95E00B2B_5CD3F5C7_9922B21C_8B6B988B_A0BD85C9, + 256'h3A5C65A7_A682ECEA_8D98A895_45928CC2_E96F5486_62F2AD4E_4CF255EF_2445C5FA, + 256'hC6339CF4_2A779E60_951A1A43_1B663E21_C3099299_7A7703D6_7DC143C0_EBD0527D, + 256'h4CBB34E1_1F6F81D5_DD72A052_90709184_8BFB1F95_A1C4CA74_6C476371_725A211B, + 256'h14214B06_89048E3E_82E70DA0_C61B7804_204AA2EA_EE924BB0_1781189F_AE5BDACC, + 256'hB2DA6BBD_3CB1C356_4D0511A4_95226938_24E071C5_392B783A_98AE42C6_52ED96C1, + 256'h62E11DC2_25A7317C_8CF13B90_7893D23C_64C85DA5_F0CC2834_D97B8E8A_56DC8702, + 256'h6B6EAE07_E22F85A4_D8D5161A_8344C1CB_C2E73554_453D295B_F44A4868_03AEF59D, + 256'h52F3CF10_450F2B5B_05930D8A_907438D9_8295D069_65031D27_6594E4E2_317DC582, + 256'h804B5505_B15D1E76_AA37EDA2_6FC36AF0_AC0FE391_89F436EA_67C53788_2993989F, + 256'h45E63132_EB614880_C0E279E5_9C70DFB9_D53C502D_BEAAA4C5_00468BEC_285A2504, + 256'h1A3CC07E_687798D7_2C8C9098_AB59E408_2A8E7A55_07585325_9A75959D_AB1115DD, + 256'h24862909_4C2B13DA_B8890756_6071C5E8_6F5137F8_DD3C60B8_197FAF9A_182237C1, + 256'hC148E2B8_C68677CE_9600DC98_F8399616_3482F9B0_4FE9B28D_C341168C_5F3EF037, + 256'h501A6442_38313F0E_0D2A70CD_288B097B_118497D2_6DBC5E50_B1349E4E_CEC9E9B4, + 256'h504893E5_6D9A87BB_458D2142_93B55E5E_EDF602C3_52A72874_49A25409_831DA859, + 256'hE3111C63_AFCAC059_1F262236_4B78C6CA_8171C02E_261C0C4A_009B9922_B483CAAE, + 256'hCF4989A3_7A34568D_457202A4_EB674CA9_6C1446CC_24ABEF07_C09D921E_E0490391, + 256'h1349F63B_2B80A974_E5056FB2_D26EACDB_9405C404_044945FD_1014C8F4_8053D929, + 256'hB512BA50_9B26F7BB_3095A947_9DA613E0_B709C7E1_FDA815B1_2576C490_96C6A482 }; // Compile-time random data for PRNG buffer default seed parameter kmac_pkg::buffer_lfsr_seed_t RndCnstKmacBufferLfsrSeed = { - 32'h3238DCDF, - 256'h7DE88B56_B405E02B_BFD73849_C511F7F0_B79F91DC_D1D589B4_CAC4372C_385F89D9, - 256'h02019DAB_B6DD5702_2C77EDE8_609C409D_905B3C78_19B26A67_43288199_28C5D79B, - 256'hF1DB63D1_1E1C31BB_C9A8C73F_C4CC3D14_CA6BC0B9_6812DE7C_775A54FF_19343CB3 + 32'h740A7CE7, + 256'hC92A49F7_1747D5A7_E3B7E444_732A39A6_9F03F5A8_8525A587_CEDEA909_13BBCE81, + 256'h4E6794DF_2BDD99E6_6D07801B_027BD4E9_BF578B14_6F616B60_82465E44_680CE936, + 256'h49A84575_B465479F_31A97523_4377E00D_28EC32FA_5850E8A7_F607A49B_2CADE12A }; // Compile-time random permutation for LFSR Message output parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = { - 128'hFE376B54_463DE2A7_87383305_2CDC7C7E, - 256'hDE8F6F6C_0ACD6FA4_475A405E_51B27268_02528674_DEFED3E6_1B899E26_814AC408 + 128'h375A21BC_7D010BBC_D4CA2458_D8900A6C, + 256'hC4159ACF_43FC490F_E7EC5CAD_31465AD8_E767039F_778A5768_BABA8257_88B92DFC }; //////////////////////////////////////////// @@ -434,30 +464,30 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for URND. parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { - 32'hE856F1D9, - 256'h08E3F70D_E343D222_6E9E8644_65A8EE55_EC0E6A29_6789DED5_C0AF59EE_62F1FD1B + 32'hB2D1DC64, + 256'h55D87F13_C9A46714_46BEA856_D5FBB54B_B5B253A7_0BC372CF_C9BB0AB3_8A5EDABE }; // Compile-time random permutation for URND permutation in BN MAC. parameter otbn_pkg::bn_mac_urnd_perm_t RndCnstOtbnBnMacUrndPerm = { - 256'hB9330DB8_45B48936_B039A170_F15F724E_E2A65A14_1EEF3F7D_AE11C54D_FB2113D4, - 256'hB218D85C_83EE4A16_970E296C_9BAA79BF_D553C364_3EB34943_759881CD_EA730923, - 256'h479EF28B_27FA4B86_DA3B07A3_461B7F41_F99C2042_C7F7CF88_BA381234_0A625067, - 256'hDC1517BB_55A8DDB5_56D663ED_F5F61C19_5BECC4D0_E3FDC17B_8C0078DE_769DA226, - 256'h2DA5F891_DFCE1D6D_80AD6182_6E68102C_E8E93C74_7E3590D7_03C032BD_57F48466, - 256'h08E631CC_87FC6BB6_06D3AF96_8F3D02A4_9F2F8E24_0FDB2BA0_A7C6778D_6037302A, - 256'hC804F359_93928558_A9E09599_01CBCA4C_510C44C9_0BFE9A7A_C25469E4_28526A8A, - 256'h1FE5F048_6F407CE1_D2BC4FAB_D965255D_D13A711A_EBB72EE7_945EB105_22ACFFBE + 256'h0F265907_E8B6C14F_5711C345_E3BAA8CC_74FA5E71_218DAD7E_AEF10020_8F0DE56B, + 256'hBED4D95B_3B4387F5_CBC52D78_96E229F4_FB90ED95_2AA4C2E4_1B66A9F6_481963B8, + 256'hBC4E3D15_72B75635_3E503867_39B5177F_9B580903_012F4C6E_CD47F8DA_494225C4, + 256'h761C1E91_36FEBDB2_533C80F2_5161A097_C6BB70B1_41523A77_0BAF757C_DE4B12FC, + 256'h5D9DC09F_9E86040E_92D39AA3_CF995FB9_B4461F8A_88186CEA_05A528D5_DCD61D02, + 256'h93082E54_D732DB8B_FF83D0F3_44ACC827_E994C7DF_A74A7313_857DE6D8_F02334B0, + 256'hEE9CB30C_5C31CA6F_F77AA122_2C821089_AAE06DE1_55166914_8E4DEB40_5A3F65EF, + 256'hBFCE6264_33AB3081_6AC998A2_EC1A0A8C_062B607B_79FDDDF9_843768A6_D124D2E7 }; // Compile-time random reset value for IMem/DMem scrambling key. parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { - 128'hD5A7E3B7_E444732A_39A69F03_F5A88525 + 128'hA6F2B35C_99FB71E1_AAAB3C20_8383ADF5 }; // Compile-time random reset value for IMem/DMem scrambling nonce. parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { - 64'hA587CEDE_A90913BB + 64'h0311FF71_FD469219 }; //////////////////////////////////////////// @@ -465,73 +495,73 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrLfsrSeed = { - 64'hCE814E67_94DF2BDD + 64'h23A8CD8C_6FF98F9B }; // Compile-time random permutation for LFSR output parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrLfsrPerm = { - 128'h938856D2_94289EA0_B63DF8C7_109DF24E, - 256'hCF9428BE_B3F1C3AE_22533F65_DAD2343C_2D5D1EF1_698F4589_5BF57801_A005BE66 + 128'h20A733FE_35C48BE4_587532C5_ACF642E6, + 256'h7B5EC722_7CAA639F_414EFDBE_4A0C5929_786FA860_1F536E1A_9015D036_B606CC37 }; // Compile-time random permutation for entropy used in share overriding parameter keymgr_pkg::rand_perm_t RndCnstKeymgrRandPerm = { - 160'hD13CC6A8_A03237D0_9FF8959F_0E6522A8_D7474677 + 160'h1F75401D_1BCC54C2_CCCBADED_8FC1C26F_83223F89 }; // Compile-time random bits for revision seed parameter keymgr_pkg::seed_t RndCnstKeymgrRevisionSeed = { - 256'h9DA8413D_DA43FECD_D6C1A586_93232D1C_3E361D85_6AB2D1DC_6455D87F_13C9A467 + 256'h57A6A15F_AA577395_193CDE4A_6705BD11_203330A9_27A8CE1A_C88224A4_41C4192A }; // Compile-time random bits for creator identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrCreatorIdentitySeed = { - 256'h1446BEA8_56D5FBB5_4BB5B253_A70BC372_CFC9BB0A_B38A5EDA_BEE7D224_D1A66837 + 256'hBE1DC426_FEEE2C9B_1C8B34B1_A821AFE5_22E11C40_49D9B85F_9DC3C99A_37868579 }; // Compile-time random bits for owner intermediate identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIntIdentitySeed = { - 256'h8437DD24_797B602B_068C0A1A_ECA298C9_6A8130AB_336462CE_E1BF8C65_3FDE5A40 + 256'hB46A8409_5EA98114_0FF7F0C4_AD73D597_26774A37_E3356026_6D52A2D9_C4901261 }; // Compile-time random bits for owner identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIdentitySeed = { - 256'hA24DF78E_146916DC_55F8CE6D_BFAAD089_10FBE182_2C22A17A_376FA131_5C0CB3C2 + 256'hC19F4802_38C0197C_FA2C9010_EEFDD66D_4B91725B_5E1A95A1_411451C3_DA5967F2 }; // Compile-time random bits for software generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrSoftOutputSeed = { - 256'h9CF4D10A_E5C8F0C7_B034BF23_C9068E30_7D8513B7_734AA78C_C36F947A_2737BBC0 + 256'hCC89F1B0_ECA3388F_277FFAE4_319B4144_B76B7C90_2A9C89F6_F8F8856D_8B76B9B8 }; // Compile-time random bits for hardware generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrHardOutputSeed = { - 256'hACD1447B_AA83C3FC_818BB3B4_A840AD32_14CEB3F3_54CA2E08_9302C3EE_1D695AA6 + 256'hEC2F4F0E_AE6D9D26_C47E2790_80DD58BC_F5AA54A3_F54824B5_C6538F8A_AE68EC24 }; // Compile-time random bits for generation seed when aes destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrAesSeed = { - 256'h16283205_DB05CD6C_18888AD0_1FE046EA_FD8BF298_DB7D5FE0_FD32A296_89A0C154 + 256'hDF2D9B07_0658CB5B_072BB74E_79DEA47A_41863ADA_ED04A043_653AFA57_48AEFE46 }; // Compile-time random bits for generation seed when kmac destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrKmacSeed = { - 256'h9C28C210_C01FF7E6_E6D20E04_04E7B51D_020AA369_5DF42597_CACAEA4E_16EF75A4 + 256'hB7A51953_22D57D74_AF0790F5_050E1343_B18DDA68_27D47465_7B77F7ED_A1A07047 }; // Compile-time random bits for generation seed when otbn destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrOtbnSeed = { - 256'h823EE1BF_100B50C3_A2C1BA79_A60BD0D9_47C26D8D_3C3874C6_B8E34A85_925CE73B + 256'hF937051A_05746141_4B8B3587_C6DE71B9_22084EC4_EA31A97E_0ACB1ACB_48CBA01D }; // Compile-time random bits for generation seed when no CDI is selected parameter keymgr_pkg::seed_t RndCnstKeymgrCdi = { - 256'h8F155098_5EB503E8_E4071315_2D132E9E_94DA720A_712D7D6B_7326F310_2BA57AB1 + 256'hEA88816D_C0357C3D_419213EE_BD8FED49_C167447D_0A22FBFD_5230D29F_B8E5B65E }; // Compile-time random bits for generation seed when no destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrNoneSeed = { - 256'h2F0C11E4_64E61308_8D6DF2CC_4352AA62_DF6B0719_9EA6C678_2AD9BB2E_78FA04C6 + 256'h7C4102C3_7BC6A838_63A98A9A_7F84EA7C_2377F98C_F20CCAAA_3BD0E4E0_2590E09C }; //////////////////////////////////////////// @@ -539,14 +569,14 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { - 128'h8991DE3B_57A9B612_06E6C0A2_AFA6A3C5, - 256'h6D97128C_7811E36A_2829DB02_5EC69547_062345C4_00F5EF1B_06A11965_0A85C302 + 128'h975C71CA_965F7B31_6D6C12EA_819870D4, + 256'h51DC29EE_296DA185_0BE6BED0_73F6EE87_0F58B89F_ABFE08C8_27837C78_67EEC58F }; // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { - 128'h37536DC3_E35040DE_9AC1A6F2_B35C99FB, - 256'h71E1AAAB_3C208383_ADF50311_FF71FD46_921923A8_CD8C6FF9_8F9BDFC2_B205D869 + 128'hF573DB5A_AF6E9564_4DFAD426_2A7ADB7F, + 256'h05D963E4_282AE9DD_B8FBE7A1_38D956AC_336341A5_36F70C3E_E90CAEAE_11CB84B6 }; //////////////////////////////////////////// @@ -554,23 +584,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { - 128'h0DD35500_E5A51BBA_34A71D81_E9EB876B + 128'h5FDC5C70_2578F9F8_93C20A28_65EF55E0 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { - 128'h6F1996B2_BE4B58DF_CFB830B9_E25BDAA3 + 128'hA6E7A0BA_0B1C2967_31C59D86_1E3633E7 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { - 64'hE1AFFA91_806D01A8 + 64'h5586C29B_02CB9DE8 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { - 128'h0E4D3302_F22CE229_EA15318B_A7B5D9A3, - 256'hA5BE8CDC_8182E3DC_C4E4767B_D2BF2553_2B7DA107_635E656D_20BCB5D4_30854DE6 + 128'hEF969056_42C5E12B_25C9F6FD_9D65E82A, + 256'h912252A8_4347380F_FC70B7C2_E63ED0E7_094D9F2D_D71EB676_3BCC9801_AB20178D }; //////////////////////////////////////////// @@ -578,23 +608,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlSecSramKey = { - 128'h57A6A15F_AA577395_193CDE4A_6705BD11 + 128'hC752A9C4_607CEC7D_CA3EB5F3_D09295A3 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlSecSramNonce = { - 128'h203330A9_27A8CE1A_C88224A4_41C4192A + 128'h2C9CBAFE_5EFF3CF3_5156B781_5F112BB8 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlSecLfsrSeed = { - 64'hBE1DC426_FEEE2C9B + 64'hBDC22909_AD6A99CF }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlSecLfsrPerm = { - 128'hDB154BE6_8E0E3DB7_FC059591_9770234F, - 256'hEA7B6142_B210C1A4_BF574970_3160CC2B_5A7B487D_9B09D7B9_243FEAB2_2AB0D887 + 128'h7126AE21_3C3C463A_2FDAC6C4_34518BD4, + 256'hCCF1CA29_960277C1_5255691D_8FB47612_B7FFDB79_ED0ABA39_9E0F5EB7_A00C2264 }; //////////////////////////////////////////// @@ -602,12 +632,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Fixed nonce used for address / data scrambling parameter bit [63:0] RndCnstRomCtrlScrNonce = { - 64'h51C3DA59_67F2CC89 + 64'h9E648FB1_0EE6F51A }; // Randomised constant used as a scrambling key for ROM data parameter bit [127:0] RndCnstRomCtrlScrKey = { - 128'hF1B0ECA3_388F277F_FAE4319B_4144B76B + 128'hC4FCDB4B_8F96F977_53B0A824_7424B489 }; //////////////////////////////////////////// @@ -615,22 +645,22 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for random instructions. parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexLfsrSeed = { - 32'h7C902A9C + 32'h90156C71 }; // Permutation applied to the LFSR of the PRNG used for random instructions. parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexLfsrPerm = { - 160'h38066D0B_75EB14BC_511693C9_3E0525CD_DDF6C3D1 + 160'h3D59FD39_6DDF262F_01E81961_D50629BD_2D8C9246 }; // Default icache scrambling key parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexIbexKeyDefault = { - 128'hEC24DF2D_9B070658_CB5B072B_B74E79DE + 128'h8CD14C0F_2E129D94_3ABF68DA_18DBF422 }; // Default icache scrambling nonce parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexIbexNonceDefault = { - 64'hA47A4186_3ADAED04 + 64'hA9EBB7EB_AF19BE85 }; endpackage : top_earlgrey_rnd_cnst_pkg diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core index b04b159d554f0..d8f283206d729 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core @@ -22,6 +22,7 @@ filesets: - lowrisc:ip:lc_ctrl_pkg - lowrisc:ip:otbn_pkg - lowrisc:ip:otp_ctrl_pkg + - lowrisc:ip:rram_ctrl_pkg - lowrisc:ip:sram_ctrl_pkg files: - top_earlgrey_rnd_cnst_pkg.sv diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 1616b6950bbcf..4eafff95ed068 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -54,6 +54,10 @@ module top_earlgrey #( parameter bit SecFlashCtrlScrambleEn = 1, parameter int FlashCtrlProgFifoDepth = 4, parameter int FlashCtrlRdFifoDepth = 16, + // parameters for rram_ctrl + parameter bit SecRramCtrlScrambleEn = 1, + parameter int RramCtrlWrFifoDepth = 4, + parameter int RramCtrlRdFifoDepth = 16, // parameters for rv_dm parameter logic [31:0] RvDmIdcodeValue = jtag_id_pkg::RV_DM_JTAG_IDCODE, parameter bit RvDmUseDmiInterface = 0, @@ -356,6 +360,9 @@ module top_earlgrey #( .SecFlashCtrlScrambleEn(SecFlashCtrlScrambleEn), .FlashCtrlProgFifoDepth(FlashCtrlProgFifoDepth), .FlashCtrlRdFifoDepth(FlashCtrlRdFifoDepth), + .SecRramCtrlScrambleEn(SecRramCtrlScrambleEn), + .RramCtrlWrFifoDepth(RramCtrlWrFifoDepth), + .RramCtrlRdFifoDepth(RramCtrlRdFifoDepth), .RvDmIdcodeValue(RvDmIdcodeValue), .RvDmUseDmiInterface(RvDmUseDmiInterface), .SecRvDmVolatileRawUnlockEn(SecRvDmVolatileRawUnlockEn), diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 21edd865e4268..f210cc6dfc736 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -299,6 +299,26 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h80; + /** + * Peripheral base address for core device on rram_ctrl in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR = 32'h41010000; + + /** + * Peripheral size in bytes for core device on rram_ctrl in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES = 32'h200; + + /** + * Peripheral base address for prim device on rram_macro in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR = 32'h41018000; + + /** + * Peripheral size in bytes for prim device on rram_macro in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES = 32'h10; + /** * Peripheral base address for regs device on rv_dm in top earlgrey. */ @@ -479,6 +499,16 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES = 32'h100000; + /** + * Memory base address for host memory on rram_ctrl in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR = 32'h30000000; + + /** + * Memory size for host memory on rram_ctrl in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES = 32'h200000; + /** * Memory base address for ram memory on sram_ctrl_main in top earlgrey. */ @@ -537,21 +567,22 @@ package top_earlgrey_pkg; TopEarlgreyAlertPeripheralSensorCtrl = 22, TopEarlgreyAlertPeripheralSramCtrlRet = 23, TopEarlgreyAlertPeripheralFlashCtrl = 24, - TopEarlgreyAlertPeripheralRvDm = 25, - TopEarlgreyAlertPeripheralRvPlic = 26, - TopEarlgreyAlertPeripheralAes = 27, - TopEarlgreyAlertPeripheralHmac = 28, - TopEarlgreyAlertPeripheralKmac = 29, - TopEarlgreyAlertPeripheralOtbn = 30, - TopEarlgreyAlertPeripheralKeymgr = 31, - TopEarlgreyAlertPeripheralCsrng = 32, - TopEarlgreyAlertPeripheralEntropySrc = 33, - TopEarlgreyAlertPeripheralEdn0 = 34, - TopEarlgreyAlertPeripheralEdn1 = 35, - TopEarlgreyAlertPeripheralSramCtrlMain = 36, - TopEarlgreyAlertPeripheralSramCtrlSec = 37, - TopEarlgreyAlertPeripheralRomCtrl = 38, - TopEarlgreyAlertPeripheralRvCoreIbex = 39, + TopEarlgreyAlertPeripheralRramCtrl = 25, + TopEarlgreyAlertPeripheralRvDm = 26, + TopEarlgreyAlertPeripheralRvPlic = 27, + TopEarlgreyAlertPeripheralAes = 28, + TopEarlgreyAlertPeripheralHmac = 29, + TopEarlgreyAlertPeripheralKmac = 30, + TopEarlgreyAlertPeripheralOtbn = 31, + TopEarlgreyAlertPeripheralKeymgr = 32, + TopEarlgreyAlertPeripheralCsrng = 33, + TopEarlgreyAlertPeripheralEntropySrc = 34, + TopEarlgreyAlertPeripheralEdn0 = 35, + TopEarlgreyAlertPeripheralEdn1 = 36, + TopEarlgreyAlertPeripheralSramCtrlMain = 37, + TopEarlgreyAlertPeripheralSramCtrlSec = 38, + TopEarlgreyAlertPeripheralRomCtrl = 39, + TopEarlgreyAlertPeripheralRvCoreIbex = 40, TopEarlgreyAlertPeripheralCount } alert_peripheral_e; @@ -595,32 +626,37 @@ package top_earlgrey_pkg; TopEarlgreyAlertIdFlashCtrlFatalErr = 35, TopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 36, TopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 37, - TopEarlgreyAlertIdRvDmFatalFault = 38, - TopEarlgreyAlertIdRvPlicFatalFault = 39, - TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 40, - TopEarlgreyAlertIdAesFatalFault = 41, - TopEarlgreyAlertIdHmacFatalFault = 42, - TopEarlgreyAlertIdKmacRecovOperationErr = 43, - TopEarlgreyAlertIdKmacFatalFaultErr = 44, - TopEarlgreyAlertIdOtbnFatal = 45, - TopEarlgreyAlertIdOtbnRecov = 46, - TopEarlgreyAlertIdKeymgrRecovOperationErr = 47, - TopEarlgreyAlertIdKeymgrFatalFaultErr = 48, - TopEarlgreyAlertIdCsrngRecovAlert = 49, - TopEarlgreyAlertIdCsrngFatalAlert = 50, - TopEarlgreyAlertIdEntropySrcRecovAlert = 51, - TopEarlgreyAlertIdEntropySrcFatalAlert = 52, - TopEarlgreyAlertIdEdn0RecovAlert = 53, - TopEarlgreyAlertIdEdn0FatalAlert = 54, - TopEarlgreyAlertIdEdn1RecovAlert = 55, - TopEarlgreyAlertIdEdn1FatalAlert = 56, - TopEarlgreyAlertIdSramCtrlMainFatalError = 57, - TopEarlgreyAlertIdSramCtrlSecFatalError = 58, - TopEarlgreyAlertIdRomCtrlFatal = 59, - TopEarlgreyAlertIdRvCoreIbexFatalSwErr = 60, - TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 61, - TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 62, - TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 63, + TopEarlgreyAlertIdRramCtrlRecovErr = 38, + TopEarlgreyAlertIdRramCtrlFatalStdErr = 39, + TopEarlgreyAlertIdRramCtrlFatalErr = 40, + TopEarlgreyAlertIdRramCtrlFatalMacroErr = 41, + TopEarlgreyAlertIdRramCtrlRecovMacroErr = 42, + TopEarlgreyAlertIdRvDmFatalFault = 43, + TopEarlgreyAlertIdRvPlicFatalFault = 44, + TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 45, + TopEarlgreyAlertIdAesFatalFault = 46, + TopEarlgreyAlertIdHmacFatalFault = 47, + TopEarlgreyAlertIdKmacRecovOperationErr = 48, + TopEarlgreyAlertIdKmacFatalFaultErr = 49, + TopEarlgreyAlertIdOtbnFatal = 50, + TopEarlgreyAlertIdOtbnRecov = 51, + TopEarlgreyAlertIdKeymgrRecovOperationErr = 52, + TopEarlgreyAlertIdKeymgrFatalFaultErr = 53, + TopEarlgreyAlertIdCsrngRecovAlert = 54, + TopEarlgreyAlertIdCsrngFatalAlert = 55, + TopEarlgreyAlertIdEntropySrcRecovAlert = 56, + TopEarlgreyAlertIdEntropySrcFatalAlert = 57, + TopEarlgreyAlertIdEdn0RecovAlert = 58, + TopEarlgreyAlertIdEdn0FatalAlert = 59, + TopEarlgreyAlertIdEdn1RecovAlert = 60, + TopEarlgreyAlertIdEdn1FatalAlert = 61, + TopEarlgreyAlertIdSramCtrlMainFatalError = 62, + TopEarlgreyAlertIdSramCtrlSecFatalError = 63, + TopEarlgreyAlertIdRomCtrlFatal = 64, + TopEarlgreyAlertIdRvCoreIbexFatalSwErr = 65, + TopEarlgreyAlertIdRvCoreIbexRecovSwErr = 66, + TopEarlgreyAlertIdRvCoreIbexFatalHwErr = 67, + TopEarlgreyAlertIdRvCoreIbexRecovHwErr = 68, TopEarlgreyAlertIdCount } alert_id_e; @@ -790,26 +826,32 @@ package top_earlgrey_pkg; TopEarlgreyPlicIrqIdFlashCtrlRdLvl = 161, TopEarlgreyPlicIrqIdFlashCtrlOpDone = 162, TopEarlgreyPlicIrqIdFlashCtrlCorrErr = 163, - TopEarlgreyPlicIrqIdHmacHmacDone = 164, - TopEarlgreyPlicIrqIdHmacFifoEmpty = 165, - TopEarlgreyPlicIrqIdHmacHmacErr = 166, - TopEarlgreyPlicIrqIdKmacKmacDone = 167, - TopEarlgreyPlicIrqIdKmacFifoEmpty = 168, - TopEarlgreyPlicIrqIdKmacKmacErr = 169, - TopEarlgreyPlicIrqIdOtbnDone = 170, - TopEarlgreyPlicIrqIdKeymgrOpDone = 171, - TopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 172, - TopEarlgreyPlicIrqIdCsrngCsEntropyReq = 173, - TopEarlgreyPlicIrqIdCsrngCsHwInstExc = 174, - TopEarlgreyPlicIrqIdCsrngCsFatalErr = 175, - TopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 176, - TopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 177, - TopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 178, - TopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 179, - TopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 180, - TopEarlgreyPlicIrqIdEdn0EdnFatalErr = 181, - TopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 182, - TopEarlgreyPlicIrqIdEdn1EdnFatalErr = 183, + TopEarlgreyPlicIrqIdRramCtrlWrEmpty = 164, + TopEarlgreyPlicIrqIdRramCtrlWrLvl = 165, + TopEarlgreyPlicIrqIdRramCtrlRdFull = 166, + TopEarlgreyPlicIrqIdRramCtrlRdLvl = 167, + TopEarlgreyPlicIrqIdRramCtrlOpDone = 168, + TopEarlgreyPlicIrqIdRramCtrlCorrErr = 169, + TopEarlgreyPlicIrqIdHmacHmacDone = 170, + TopEarlgreyPlicIrqIdHmacFifoEmpty = 171, + TopEarlgreyPlicIrqIdHmacHmacErr = 172, + TopEarlgreyPlicIrqIdKmacKmacDone = 173, + TopEarlgreyPlicIrqIdKmacFifoEmpty = 174, + TopEarlgreyPlicIrqIdKmacKmacErr = 175, + TopEarlgreyPlicIrqIdOtbnDone = 176, + TopEarlgreyPlicIrqIdKeymgrOpDone = 177, + TopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 178, + TopEarlgreyPlicIrqIdCsrngCsEntropyReq = 179, + TopEarlgreyPlicIrqIdCsrngCsHwInstExc = 180, + TopEarlgreyPlicIrqIdCsrngCsFatalErr = 181, + TopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 182, + TopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 183, + TopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 184, + TopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 185, + TopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 186, + TopEarlgreyPlicIrqIdEdn0EdnFatalErr = 187, + TopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 188, + TopEarlgreyPlicIrqIdEdn1EdnFatalErr = 189, TopEarlgreyPlicIrqIdCount } interrupt_rv_plic_id_e; @@ -876,14 +918,17 @@ package top_earlgrey_pkg; MioInFlashCtrlTck = 47, MioInFlashCtrlTms = 48, MioInFlashCtrlTdi = 49, - MioInSysrstCtrlAcPresent = 50, - MioInSysrstCtrlKey0In = 51, - MioInSysrstCtrlKey1In = 52, - MioInSysrstCtrlKey2In = 53, - MioInSysrstCtrlPwrbIn = 54, - MioInSysrstCtrlLidOpen = 55, - MioInUsbdevSense = 56, - MioInCount = 57 + MioInRramMacroTck = 50, + MioInRramMacroTms = 51, + MioInRramMacroTdi = 52, + MioInSysrstCtrlAcPresent = 53, + MioInSysrstCtrlKey0In = 54, + MioInSysrstCtrlKey1In = 55, + MioInSysrstCtrlKey2In = 56, + MioInSysrstCtrlPwrbIn = 57, + MioInSysrstCtrlLidOpen = 58, + MioInUsbdevSense = 59, + MioInCount = 60 } mio_in_e; typedef enum { @@ -936,23 +981,24 @@ package top_earlgrey_pkg; MioOutSpiHost1Sck = 46, MioOutSpiHost1Csb = 47, MioOutFlashCtrlTdo = 48, - MioOutSensorCtrlAstDebugOut0 = 49, - MioOutSensorCtrlAstDebugOut1 = 50, - MioOutSensorCtrlAstDebugOut2 = 51, - MioOutSensorCtrlAstDebugOut3 = 52, - MioOutSensorCtrlAstDebugOut4 = 53, - MioOutSensorCtrlAstDebugOut5 = 54, - MioOutSensorCtrlAstDebugOut6 = 55, - MioOutSensorCtrlAstDebugOut7 = 56, - MioOutSensorCtrlAstDebugOut8 = 57, - MioOutOtpMacroTest0 = 58, - MioOutSysrstCtrlBatDisable = 59, - MioOutSysrstCtrlKey0Out = 60, - MioOutSysrstCtrlKey1Out = 61, - MioOutSysrstCtrlKey2Out = 62, - MioOutSysrstCtrlPwrbOut = 63, - MioOutSysrstCtrlZ3Wakeup = 64, - MioOutCount = 65 + MioOutRramMacroTdo = 49, + MioOutSensorCtrlAstDebugOut0 = 50, + MioOutSensorCtrlAstDebugOut1 = 51, + MioOutSensorCtrlAstDebugOut2 = 52, + MioOutSensorCtrlAstDebugOut3 = 53, + MioOutSensorCtrlAstDebugOut4 = 54, + MioOutSensorCtrlAstDebugOut5 = 55, + MioOutSensorCtrlAstDebugOut6 = 56, + MioOutSensorCtrlAstDebugOut7 = 57, + MioOutSensorCtrlAstDebugOut8 = 58, + MioOutOtpMacroTest0 = 59, + MioOutSysrstCtrlBatDisable = 60, + MioOutSysrstCtrlKey0Out = 61, + MioOutSysrstCtrlKey1Out = 62, + MioOutSysrstCtrlKey2Out = 63, + MioOutSysrstCtrlPwrbOut = 64, + MioOutSysrstCtrlZ3Wakeup = 65, + MioOutCount = 66 } mio_out_e; // Enumeration for DIO signals, used on both the top and chip-levels. @@ -1090,6 +1136,8 @@ package top_earlgrey_pkg; PeripheralPinmux, PeripheralPwrmgr, PeripheralRomCtrl, + PeripheralRramCtrl, + PeripheralRramMacro, PeripheralRstmgr, PeripheralRvCoreIbex, PeripheralRvDm, diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index 90252857d6431..7a41cf3c892a2 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -427,6 +427,34 @@ pub const FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000; /// `FLASH_CTRL_PRIM_BASE_ADDR + FLASH_CTRL_PRIM_SIZE_BYTES`. pub const FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80; +/// Peripheral base address for core device on rram_ctrl in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RRAM_CTRL_CORE_BASE_ADDR: usize = 0x41010000; + +/// Peripheral size for core device on rram_ctrl in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RRAM_CTRL_CORE_BASE_ADDR and +/// `RRAM_CTRL_CORE_BASE_ADDR + RRAM_CTRL_CORE_SIZE_BYTES`. +pub const RRAM_CTRL_CORE_SIZE_BYTES: usize = 0x200; + +/// Peripheral base address for prim device on rram_macro in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RRAM_MACRO_PRIM_BASE_ADDR: usize = 0x41018000; + +/// Peripheral size for prim device on rram_macro in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RRAM_MACRO_PRIM_BASE_ADDR and +/// `RRAM_MACRO_PRIM_BASE_ADDR + RRAM_MACRO_PRIM_SIZE_BYTES`. +pub const RRAM_MACRO_PRIM_SIZE_BYTES: usize = 0x10; + /// Peripheral base address for regs device on rv_dm in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -663,6 +691,12 @@ pub const FLASH_CTRL_MEM_BASE_ADDR: usize = 0x20000000; /// Memory size for mem memory on flash_ctrl in top earlgrey. pub const FLASH_CTRL_MEM_SIZE_BYTES: usize = 0x100000; +/// Memory base address for host memory on rram_ctrl in top earlgrey. +pub const RRAM_CTRL_HOST_BASE_ADDR: usize = 0x30000000; + +/// Memory size for host memory on rram_ctrl in top earlgrey. +pub const RRAM_CTRL_HOST_SIZE_BYTES: usize = 0x200000; + /// Memory base address for ram memory on sram_ctrl_main in top earlgrey. pub const SRAM_CTRL_MAIN_RAM_BASE_ADDR: usize = 0x10000000; @@ -732,22 +766,24 @@ pub enum PlicPeripheral { SensorCtrl = 20, /// flash_ctrl FlashCtrl = 21, + /// rram_ctrl + RramCtrl = 22, /// hmac - Hmac = 22, + Hmac = 23, /// kmac - Kmac = 23, + Kmac = 24, /// otbn - Otbn = 24, + Otbn = 25, /// keymgr - Keymgr = 25, + Keymgr = 26, /// csrng - Csrng = 26, + Csrng = 27, /// entropy_src - EntropySrc = 27, + EntropySrc = 28, /// edn0 - Edn0 = 28, + Edn0 = 29, /// edn1 - Edn1 = 29, + Edn1 = 30, } impl TryFrom for PlicPeripheral { @@ -776,14 +812,15 @@ impl TryFrom for PlicPeripheral { 19 => Ok(Self::AonTimer), 20 => Ok(Self::SensorCtrl), 21 => Ok(Self::FlashCtrl), - 22 => Ok(Self::Hmac), - 23 => Ok(Self::Kmac), - 24 => Ok(Self::Otbn), - 25 => Ok(Self::Keymgr), - 26 => Ok(Self::Csrng), - 27 => Ok(Self::EntropySrc), - 28 => Ok(Self::Edn0), - 29 => Ok(Self::Edn1), + 22 => Ok(Self::RramCtrl), + 23 => Ok(Self::Hmac), + 24 => Ok(Self::Kmac), + 25 => Ok(Self::Otbn), + 26 => Ok(Self::Keymgr), + 27 => Ok(Self::Csrng), + 28 => Ok(Self::EntropySrc), + 29 => Ok(Self::Edn0), + 30 => Ok(Self::Edn1), _ => Err(val), } } @@ -1124,46 +1161,58 @@ pub enum PlicIrqId { FlashCtrlOpDone = 162, /// flash_ctrl_corr_err FlashCtrlCorrErr = 163, + /// rram_ctrl_wr_empty + RramCtrlWrEmpty = 164, + /// rram_ctrl_wr_lvl + RramCtrlWrLvl = 165, + /// rram_ctrl_rd_full + RramCtrlRdFull = 166, + /// rram_ctrl_rd_lvl + RramCtrlRdLvl = 167, + /// rram_ctrl_op_done + RramCtrlOpDone = 168, + /// rram_ctrl_corr_err + RramCtrlCorrErr = 169, /// hmac_hmac_done - HmacHmacDone = 164, + HmacHmacDone = 170, /// hmac_fifo_empty - HmacFifoEmpty = 165, + HmacFifoEmpty = 171, /// hmac_hmac_err - HmacHmacErr = 166, + HmacHmacErr = 172, /// kmac_kmac_done - KmacKmacDone = 167, + KmacKmacDone = 173, /// kmac_fifo_empty - KmacFifoEmpty = 168, + KmacFifoEmpty = 174, /// kmac_kmac_err - KmacKmacErr = 169, + KmacKmacErr = 175, /// otbn_done - OtbnDone = 170, + OtbnDone = 176, /// keymgr_op_done - KeymgrOpDone = 171, + KeymgrOpDone = 177, /// csrng_cs_cmd_req_done - CsrngCsCmdReqDone = 172, + CsrngCsCmdReqDone = 178, /// csrng_cs_entropy_req - CsrngCsEntropyReq = 173, + CsrngCsEntropyReq = 179, /// csrng_cs_hw_inst_exc - CsrngCsHwInstExc = 174, + CsrngCsHwInstExc = 180, /// csrng_cs_fatal_err - CsrngCsFatalErr = 175, + CsrngCsFatalErr = 181, /// entropy_src_es_entropy_valid - EntropySrcEsEntropyValid = 176, + EntropySrcEsEntropyValid = 182, /// entropy_src_es_health_test_failed - EntropySrcEsHealthTestFailed = 177, + EntropySrcEsHealthTestFailed = 183, /// entropy_src_es_observe_fifo_ready - EntropySrcEsObserveFifoReady = 178, + EntropySrcEsObserveFifoReady = 184, /// entropy_src_es_fatal_err - EntropySrcEsFatalErr = 179, + EntropySrcEsFatalErr = 185, /// edn0_edn_cmd_req_done - Edn0EdnCmdReqDone = 180, + Edn0EdnCmdReqDone = 186, /// edn0_edn_fatal_err - Edn0EdnFatalErr = 181, + Edn0EdnFatalErr = 187, /// edn1_edn_cmd_req_done - Edn1EdnCmdReqDone = 182, + Edn1EdnCmdReqDone = 188, /// edn1_edn_fatal_err - Edn1EdnFatalErr = 183, + Edn1EdnFatalErr = 189, } impl TryFrom for PlicIrqId { @@ -1334,26 +1383,32 @@ impl TryFrom for PlicIrqId { 161 => Ok(Self::FlashCtrlRdLvl), 162 => Ok(Self::FlashCtrlOpDone), 163 => Ok(Self::FlashCtrlCorrErr), - 164 => Ok(Self::HmacHmacDone), - 165 => Ok(Self::HmacFifoEmpty), - 166 => Ok(Self::HmacHmacErr), - 167 => Ok(Self::KmacKmacDone), - 168 => Ok(Self::KmacFifoEmpty), - 169 => Ok(Self::KmacKmacErr), - 170 => Ok(Self::OtbnDone), - 171 => Ok(Self::KeymgrOpDone), - 172 => Ok(Self::CsrngCsCmdReqDone), - 173 => Ok(Self::CsrngCsEntropyReq), - 174 => Ok(Self::CsrngCsHwInstExc), - 175 => Ok(Self::CsrngCsFatalErr), - 176 => Ok(Self::EntropySrcEsEntropyValid), - 177 => Ok(Self::EntropySrcEsHealthTestFailed), - 178 => Ok(Self::EntropySrcEsObserveFifoReady), - 179 => Ok(Self::EntropySrcEsFatalErr), - 180 => Ok(Self::Edn0EdnCmdReqDone), - 181 => Ok(Self::Edn0EdnFatalErr), - 182 => Ok(Self::Edn1EdnCmdReqDone), - 183 => Ok(Self::Edn1EdnFatalErr), + 164 => Ok(Self::RramCtrlWrEmpty), + 165 => Ok(Self::RramCtrlWrLvl), + 166 => Ok(Self::RramCtrlRdFull), + 167 => Ok(Self::RramCtrlRdLvl), + 168 => Ok(Self::RramCtrlOpDone), + 169 => Ok(Self::RramCtrlCorrErr), + 170 => Ok(Self::HmacHmacDone), + 171 => Ok(Self::HmacFifoEmpty), + 172 => Ok(Self::HmacHmacErr), + 173 => Ok(Self::KmacKmacDone), + 174 => Ok(Self::KmacFifoEmpty), + 175 => Ok(Self::KmacKmacErr), + 176 => Ok(Self::OtbnDone), + 177 => Ok(Self::KeymgrOpDone), + 178 => Ok(Self::CsrngCsCmdReqDone), + 179 => Ok(Self::CsrngCsEntropyReq), + 180 => Ok(Self::CsrngCsHwInstExc), + 181 => Ok(Self::CsrngCsFatalErr), + 182 => Ok(Self::EntropySrcEsEntropyValid), + 183 => Ok(Self::EntropySrcEsHealthTestFailed), + 184 => Ok(Self::EntropySrcEsObserveFifoReady), + 185 => Ok(Self::EntropySrcEsFatalErr), + 186 => Ok(Self::Edn0EdnCmdReqDone), + 187 => Ok(Self::Edn0EdnFatalErr), + 188 => Ok(Self::Edn1EdnCmdReqDone), + 189 => Ok(Self::Edn1EdnFatalErr), _ => Err(val), } } @@ -1374,7 +1429,7 @@ pub enum PlicTarget { /// /// This array is a mapping from `PlicIrqId` to /// `PlicPeripheral`. -pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 184] = [ +pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 190] = [ // None -> PlicPeripheral::Unknown PlicPeripheral::Unknown, // Uart0TxWatermark -> PlicPeripheral::Uart0 @@ -1703,6 +1758,18 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 184] = [ PlicPeripheral::FlashCtrl, // FlashCtrlCorrErr -> PlicPeripheral::FlashCtrl PlicPeripheral::FlashCtrl, + // RramCtrlWrEmpty -> PlicPeripheral::RramCtrl + PlicPeripheral::RramCtrl, + // RramCtrlWrLvl -> PlicPeripheral::RramCtrl + PlicPeripheral::RramCtrl, + // RramCtrlRdFull -> PlicPeripheral::RramCtrl + PlicPeripheral::RramCtrl, + // RramCtrlRdLvl -> PlicPeripheral::RramCtrl + PlicPeripheral::RramCtrl, + // RramCtrlOpDone -> PlicPeripheral::RramCtrl + PlicPeripheral::RramCtrl, + // RramCtrlCorrErr -> PlicPeripheral::RramCtrl + PlicPeripheral::RramCtrl, // HmacHmacDone -> PlicPeripheral::Hmac PlicPeripheral::Hmac, // HmacFifoEmpty -> PlicPeripheral::Hmac @@ -1804,36 +1871,38 @@ pub enum AlertPeripheral { SramCtrlRet = 24, /// flash_ctrl FlashCtrl = 25, + /// rram_ctrl + RramCtrl = 26, /// rv_dm - RvDm = 26, + RvDm = 27, /// rv_plic - RvPlic = 27, + RvPlic = 28, /// aes - Aes = 28, + Aes = 29, /// hmac - Hmac = 29, + Hmac = 30, /// kmac - Kmac = 30, + Kmac = 31, /// otbn - Otbn = 31, + Otbn = 32, /// keymgr - Keymgr = 32, + Keymgr = 33, /// csrng - Csrng = 33, + Csrng = 34, /// entropy_src - EntropySrc = 34, + EntropySrc = 35, /// edn0 - Edn0 = 35, + Edn0 = 36, /// edn1 - Edn1 = 36, + Edn1 = 37, /// sram_ctrl_main - SramCtrlMain = 37, + SramCtrlMain = 38, /// sram_ctrl_sec - SramCtrlSec = 38, + SramCtrlSec = 39, /// rom_ctrl - RomCtrl = 39, + RomCtrl = 40, /// rv_core_ibex - RvCoreIbex = 40, + RvCoreIbex = 41, } /// Alert Handler Alert Source. @@ -1919,58 +1988,68 @@ pub enum AlertId { FlashCtrlFatalPrimFlashAlert = 36, /// flash_ctrl_recov_prim_flash_alert FlashCtrlRecovPrimFlashAlert = 37, + /// rram_ctrl_recov_err + RramCtrlRecovErr = 38, + /// rram_ctrl_fatal_std_err + RramCtrlFatalStdErr = 39, + /// rram_ctrl_fatal_err + RramCtrlFatalErr = 40, + /// rram_ctrl_fatal_macro_err + RramCtrlFatalMacroErr = 41, + /// rram_ctrl_recov_macro_err + RramCtrlRecovMacroErr = 42, /// rv_dm_fatal_fault - RvDmFatalFault = 38, + RvDmFatalFault = 43, /// rv_plic_fatal_fault - RvPlicFatalFault = 39, + RvPlicFatalFault = 44, /// aes_recov_ctrl_update_err - AesRecovCtrlUpdateErr = 40, + AesRecovCtrlUpdateErr = 45, /// aes_fatal_fault - AesFatalFault = 41, + AesFatalFault = 46, /// hmac_fatal_fault - HmacFatalFault = 42, + HmacFatalFault = 47, /// kmac_recov_operation_err - KmacRecovOperationErr = 43, + KmacRecovOperationErr = 48, /// kmac_fatal_fault_err - KmacFatalFaultErr = 44, + KmacFatalFaultErr = 49, /// otbn_fatal - OtbnFatal = 45, + OtbnFatal = 50, /// otbn_recov - OtbnRecov = 46, + OtbnRecov = 51, /// keymgr_recov_operation_err - KeymgrRecovOperationErr = 47, + KeymgrRecovOperationErr = 52, /// keymgr_fatal_fault_err - KeymgrFatalFaultErr = 48, + KeymgrFatalFaultErr = 53, /// csrng_recov_alert - CsrngRecovAlert = 49, + CsrngRecovAlert = 54, /// csrng_fatal_alert - CsrngFatalAlert = 50, + CsrngFatalAlert = 55, /// entropy_src_recov_alert - EntropySrcRecovAlert = 51, + EntropySrcRecovAlert = 56, /// entropy_src_fatal_alert - EntropySrcFatalAlert = 52, + EntropySrcFatalAlert = 57, /// edn0_recov_alert - Edn0RecovAlert = 53, + Edn0RecovAlert = 58, /// edn0_fatal_alert - Edn0FatalAlert = 54, + Edn0FatalAlert = 59, /// edn1_recov_alert - Edn1RecovAlert = 55, + Edn1RecovAlert = 60, /// edn1_fatal_alert - Edn1FatalAlert = 56, + Edn1FatalAlert = 61, /// sram_ctrl_main_fatal_error - SramCtrlMainFatalError = 57, + SramCtrlMainFatalError = 62, /// sram_ctrl_sec_fatal_error - SramCtrlSecFatalError = 58, + SramCtrlSecFatalError = 63, /// rom_ctrl_fatal - RomCtrlFatal = 59, + RomCtrlFatal = 64, /// rv_core_ibex_fatal_sw_err - RvCoreIbexFatalSwErr = 60, + RvCoreIbexFatalSwErr = 65, /// rv_core_ibex_recov_sw_err - RvCoreIbexRecovSwErr = 61, + RvCoreIbexRecovSwErr = 66, /// rv_core_ibex_fatal_hw_err - RvCoreIbexFatalHwErr = 62, + RvCoreIbexFatalHwErr = 67, /// rv_core_ibex_recov_hw_err - RvCoreIbexRecovHwErr = 63, + RvCoreIbexRecovHwErr = 68, } impl TryFrom for AlertId { @@ -2015,32 +2094,37 @@ impl TryFrom for AlertId { 35 => Ok(Self::FlashCtrlFatalErr), 36 => Ok(Self::FlashCtrlFatalPrimFlashAlert), 37 => Ok(Self::FlashCtrlRecovPrimFlashAlert), - 38 => Ok(Self::RvDmFatalFault), - 39 => Ok(Self::RvPlicFatalFault), - 40 => Ok(Self::AesRecovCtrlUpdateErr), - 41 => Ok(Self::AesFatalFault), - 42 => Ok(Self::HmacFatalFault), - 43 => Ok(Self::KmacRecovOperationErr), - 44 => Ok(Self::KmacFatalFaultErr), - 45 => Ok(Self::OtbnFatal), - 46 => Ok(Self::OtbnRecov), - 47 => Ok(Self::KeymgrRecovOperationErr), - 48 => Ok(Self::KeymgrFatalFaultErr), - 49 => Ok(Self::CsrngRecovAlert), - 50 => Ok(Self::CsrngFatalAlert), - 51 => Ok(Self::EntropySrcRecovAlert), - 52 => Ok(Self::EntropySrcFatalAlert), - 53 => Ok(Self::Edn0RecovAlert), - 54 => Ok(Self::Edn0FatalAlert), - 55 => Ok(Self::Edn1RecovAlert), - 56 => Ok(Self::Edn1FatalAlert), - 57 => Ok(Self::SramCtrlMainFatalError), - 58 => Ok(Self::SramCtrlSecFatalError), - 59 => Ok(Self::RomCtrlFatal), - 60 => Ok(Self::RvCoreIbexFatalSwErr), - 61 => Ok(Self::RvCoreIbexRecovSwErr), - 62 => Ok(Self::RvCoreIbexFatalHwErr), - 63 => Ok(Self::RvCoreIbexRecovHwErr), + 38 => Ok(Self::RramCtrlRecovErr), + 39 => Ok(Self::RramCtrlFatalStdErr), + 40 => Ok(Self::RramCtrlFatalErr), + 41 => Ok(Self::RramCtrlFatalMacroErr), + 42 => Ok(Self::RramCtrlRecovMacroErr), + 43 => Ok(Self::RvDmFatalFault), + 44 => Ok(Self::RvPlicFatalFault), + 45 => Ok(Self::AesRecovCtrlUpdateErr), + 46 => Ok(Self::AesFatalFault), + 47 => Ok(Self::HmacFatalFault), + 48 => Ok(Self::KmacRecovOperationErr), + 49 => Ok(Self::KmacFatalFaultErr), + 50 => Ok(Self::OtbnFatal), + 51 => Ok(Self::OtbnRecov), + 52 => Ok(Self::KeymgrRecovOperationErr), + 53 => Ok(Self::KeymgrFatalFaultErr), + 54 => Ok(Self::CsrngRecovAlert), + 55 => Ok(Self::CsrngFatalAlert), + 56 => Ok(Self::EntropySrcRecovAlert), + 57 => Ok(Self::EntropySrcFatalAlert), + 58 => Ok(Self::Edn0RecovAlert), + 59 => Ok(Self::Edn0FatalAlert), + 60 => Ok(Self::Edn1RecovAlert), + 61 => Ok(Self::Edn1FatalAlert), + 62 => Ok(Self::SramCtrlMainFatalError), + 63 => Ok(Self::SramCtrlSecFatalError), + 64 => Ok(Self::RomCtrlFatal), + 65 => Ok(Self::RvCoreIbexFatalSwErr), + 66 => Ok(Self::RvCoreIbexRecovSwErr), + 67 => Ok(Self::RvCoreIbexFatalHwErr), + 68 => Ok(Self::RvCoreIbexRecovHwErr), _ => Err(val), } } @@ -2050,7 +2134,7 @@ impl TryFrom for AlertId { /// /// This array is a mapping from `AlertId` to /// `AlertPeripheral`. -pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 64] = [ +pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 69] = [ // Uart0FatalFault -> AlertPeripheral::Uart0 AlertPeripheral::Uart0, // Uart1FatalFault -> AlertPeripheral::Uart1 @@ -2127,6 +2211,16 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 64] = [ AlertPeripheral::FlashCtrl, // FlashCtrlRecovPrimFlashAlert -> AlertPeripheral::FlashCtrl AlertPeripheral::FlashCtrl, + // RramCtrlRecovErr -> AlertPeripheral::RramCtrl + AlertPeripheral::RramCtrl, + // RramCtrlFatalStdErr -> AlertPeripheral::RramCtrl + AlertPeripheral::RramCtrl, + // RramCtrlFatalErr -> AlertPeripheral::RramCtrl + AlertPeripheral::RramCtrl, + // RramCtrlFatalMacroErr -> AlertPeripheral::RramCtrl + AlertPeripheral::RramCtrl, + // RramCtrlRecovMacroErr -> AlertPeripheral::RramCtrl + AlertPeripheral::RramCtrl, // RvDmFatalFault -> AlertPeripheral::RvDm AlertPeripheral::RvDm, // RvPlicFatalFault -> AlertPeripheral::RvPlic @@ -2294,19 +2388,25 @@ pub enum PinmuxPeripheralIn { /// Peripheral Input 49 FlashCtrlTdi = 49, /// Peripheral Input 50 - SysrstCtrlAcPresent = 50, + RramMacroTck = 50, /// Peripheral Input 51 - SysrstCtrlKey0In = 51, + RramMacroTms = 51, /// Peripheral Input 52 - SysrstCtrlKey1In = 52, + RramMacroTdi = 52, /// Peripheral Input 53 - SysrstCtrlKey2In = 53, + SysrstCtrlAcPresent = 53, /// Peripheral Input 54 - SysrstCtrlPwrbIn = 54, + SysrstCtrlKey0In = 54, /// Peripheral Input 55 - SysrstCtrlLidOpen = 55, + SysrstCtrlKey1In = 55, /// Peripheral Input 56 - UsbdevSense = 56, + SysrstCtrlKey2In = 56, + /// Peripheral Input 57 + SysrstCtrlPwrbIn = 57, + /// Peripheral Input 58 + SysrstCtrlLidOpen = 58, + /// Peripheral Input 59 + UsbdevSense = 59, } impl TryFrom for PinmuxPeripheralIn { @@ -2363,13 +2463,16 @@ impl TryFrom for PinmuxPeripheralIn { 47 => Ok(Self::FlashCtrlTck), 48 => Ok(Self::FlashCtrlTms), 49 => Ok(Self::FlashCtrlTdi), - 50 => Ok(Self::SysrstCtrlAcPresent), - 51 => Ok(Self::SysrstCtrlKey0In), - 52 => Ok(Self::SysrstCtrlKey1In), - 53 => Ok(Self::SysrstCtrlKey2In), - 54 => Ok(Self::SysrstCtrlPwrbIn), - 55 => Ok(Self::SysrstCtrlLidOpen), - 56 => Ok(Self::UsbdevSense), + 50 => Ok(Self::RramMacroTck), + 51 => Ok(Self::RramMacroTms), + 52 => Ok(Self::RramMacroTdi), + 53 => Ok(Self::SysrstCtrlAcPresent), + 54 => Ok(Self::SysrstCtrlKey0In), + 55 => Ok(Self::SysrstCtrlKey1In), + 56 => Ok(Self::SysrstCtrlKey2In), + 57 => Ok(Self::SysrstCtrlPwrbIn), + 58 => Ok(Self::SysrstCtrlLidOpen), + 59 => Ok(Self::UsbdevSense), _ => Err(val), } } @@ -2802,37 +2905,39 @@ pub enum PinmuxOutsel { /// Peripheral Output 48 FlashCtrlTdo = 51, /// Peripheral Output 49 - SensorCtrlAstDebugOut0 = 52, + RramMacroTdo = 52, /// Peripheral Output 50 - SensorCtrlAstDebugOut1 = 53, + SensorCtrlAstDebugOut0 = 53, /// Peripheral Output 51 - SensorCtrlAstDebugOut2 = 54, + SensorCtrlAstDebugOut1 = 54, /// Peripheral Output 52 - SensorCtrlAstDebugOut3 = 55, + SensorCtrlAstDebugOut2 = 55, /// Peripheral Output 53 - SensorCtrlAstDebugOut4 = 56, + SensorCtrlAstDebugOut3 = 56, /// Peripheral Output 54 - SensorCtrlAstDebugOut5 = 57, + SensorCtrlAstDebugOut4 = 57, /// Peripheral Output 55 - SensorCtrlAstDebugOut6 = 58, + SensorCtrlAstDebugOut5 = 58, /// Peripheral Output 56 - SensorCtrlAstDebugOut7 = 59, + SensorCtrlAstDebugOut6 = 59, /// Peripheral Output 57 - SensorCtrlAstDebugOut8 = 60, + SensorCtrlAstDebugOut7 = 60, /// Peripheral Output 58 - OtpMacroTest0 = 61, + SensorCtrlAstDebugOut8 = 61, /// Peripheral Output 59 - SysrstCtrlBatDisable = 62, + OtpMacroTest0 = 62, /// Peripheral Output 60 - SysrstCtrlKey0Out = 63, + SysrstCtrlBatDisable = 63, /// Peripheral Output 61 - SysrstCtrlKey1Out = 64, + SysrstCtrlKey0Out = 64, /// Peripheral Output 62 - SysrstCtrlKey2Out = 65, + SysrstCtrlKey1Out = 65, /// Peripheral Output 63 - SysrstCtrlPwrbOut = 66, + SysrstCtrlKey2Out = 66, /// Peripheral Output 64 - SysrstCtrlZ3Wakeup = 67, + SysrstCtrlPwrbOut = 67, + /// Peripheral Output 65 + SysrstCtrlZ3Wakeup = 68, } impl TryFrom for PinmuxOutsel { @@ -2891,22 +2996,23 @@ impl TryFrom for PinmuxOutsel { 49 => Ok(Self::SpiHost1Sck), 50 => Ok(Self::SpiHost1Csb), 51 => Ok(Self::FlashCtrlTdo), - 52 => Ok(Self::SensorCtrlAstDebugOut0), - 53 => Ok(Self::SensorCtrlAstDebugOut1), - 54 => Ok(Self::SensorCtrlAstDebugOut2), - 55 => Ok(Self::SensorCtrlAstDebugOut3), - 56 => Ok(Self::SensorCtrlAstDebugOut4), - 57 => Ok(Self::SensorCtrlAstDebugOut5), - 58 => Ok(Self::SensorCtrlAstDebugOut6), - 59 => Ok(Self::SensorCtrlAstDebugOut7), - 60 => Ok(Self::SensorCtrlAstDebugOut8), - 61 => Ok(Self::OtpMacroTest0), - 62 => Ok(Self::SysrstCtrlBatDisable), - 63 => Ok(Self::SysrstCtrlKey0Out), - 64 => Ok(Self::SysrstCtrlKey1Out), - 65 => Ok(Self::SysrstCtrlKey2Out), - 66 => Ok(Self::SysrstCtrlPwrbOut), - 67 => Ok(Self::SysrstCtrlZ3Wakeup), + 52 => Ok(Self::RramMacroTdo), + 53 => Ok(Self::SensorCtrlAstDebugOut0), + 54 => Ok(Self::SensorCtrlAstDebugOut1), + 55 => Ok(Self::SensorCtrlAstDebugOut2), + 56 => Ok(Self::SensorCtrlAstDebugOut3), + 57 => Ok(Self::SensorCtrlAstDebugOut4), + 58 => Ok(Self::SensorCtrlAstDebugOut5), + 59 => Ok(Self::SensorCtrlAstDebugOut6), + 60 => Ok(Self::SensorCtrlAstDebugOut7), + 61 => Ok(Self::SensorCtrlAstDebugOut8), + 62 => Ok(Self::OtpMacroTest0), + 63 => Ok(Self::SysrstCtrlBatDisable), + 64 => Ok(Self::SysrstCtrlKey0Out), + 65 => Ok(Self::SysrstCtrlKey1Out), + 66 => Ok(Self::SysrstCtrlKey2Out), + 67 => Ok(Self::SysrstCtrlPwrbOut), + 68 => Ok(Self::SysrstCtrlZ3Wakeup), _ => Err(val), } } diff --git a/hw/top_earlgrey/sw/autogen/tests/BUILD b/hw/top_earlgrey/sw/autogen/tests/BUILD index baabb0e59aa66..f335fbbcdb212 100644 --- a/hw/top_earlgrey/sw/autogen/tests/BUILD +++ b/hw/top_earlgrey/sw/autogen/tests/BUILD @@ -75,6 +75,7 @@ NR_IRQ_PERIPH_TESTS = 3 "//sw/device/lib/dif/autogen:otbn", "//sw/device/lib/dif/autogen:otp_ctrl", "//sw/device/lib/dif/autogen:pwrmgr", + "//sw/device/lib/dif/autogen:rram_ctrl", "//sw/device/lib/dif/autogen:rv_plic", "//sw/device/lib/dif/autogen:rv_timer", "//sw/device/lib/dif/autogen:sensor_ctrl", @@ -137,6 +138,7 @@ opentitan_test( "//sw/device/lib/dif/autogen:pinmux", "//sw/device/lib/dif/autogen:pwrmgr", "//sw/device/lib/dif/autogen:rom_ctrl", + "//sw/device/lib/dif/autogen:rram_ctrl", "//sw/device/lib/dif/autogen:rstmgr", "//sw/device/lib/dif/autogen:rv_core_ibex", "//sw/device/lib/dif/autogen:rv_plic", diff --git a/hw/top_earlgrey/sw/autogen/tests/alert_test.c b/hw/top_earlgrey/sw/autogen/tests/alert_test.c index 1ccae5bfb343b..bc09dccf3b552 100644 --- a/hw/top_earlgrey/sw/autogen/tests/alert_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/alert_test.c @@ -30,6 +30,7 @@ #include "sw/device/lib/dif/autogen/dif_pinmux_autogen.h" #include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" #include "sw/device/lib/dif/autogen/dif_rom_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_rram_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_rstmgr_autogen.h" #include "sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h" #include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h" @@ -74,6 +75,7 @@ static dif_otp_ctrl_t otp_ctrl; static dif_pinmux_t pinmux; static dif_pwrmgr_t pwrmgr; static dif_rom_ctrl_t rom_ctrl; +static dif_rram_ctrl_t rram_ctrl; static dif_rstmgr_t rstmgr; static dif_rv_core_ibex_t rv_core_ibex; static dif_rv_plic_t rv_plic; @@ -166,6 +168,9 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR); CHECK_DIF_OK(dif_rom_ctrl_init(base_addr, &rom_ctrl)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_rram_ctrl_init(base_addr, &rram_ctrl)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_RSTMGR_BASE_ADDR); CHECK_DIF_OK(dif_rstmgr_init(base_addr, &rstmgr)); @@ -608,6 +613,21 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } + // Write rram_ctrl's alert_test reg and check alert_cause. + for (dif_rram_ctrl_alert_t i = 0; i < 5; ++i) { + CHECK_DIF_OK(dif_rram_ctrl_alert_force(&rram_ctrl, kDifRramCtrlAlertRecovErr + i)); + + // Verify that alert handler received it. + exp_alert = (int)kTopEarlgreyAlertIdRramCtrlRecovErr + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + // Write rstmgr's alert_test reg and check alert_cause. for (dif_rstmgr_alert_t i = 0; i < 2; ++i) { CHECK_DIF_OK(dif_rstmgr_alert_force(&rstmgr, kDifRstmgrAlertFatalFault + i)); diff --git a/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c b/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c index cdc5dce88ef81..a9309b1e35d31 100644 --- a/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c @@ -22,7 +22,7 @@ #endif #ifndef TEST_MAX_IRQ_PERIPHERAL -#define TEST_MAX_IRQ_PERIPHERAL 22 +#define TEST_MAX_IRQ_PERIPHERAL 23 #endif #include "sw/device/lib/arch/boot_stage.h" @@ -43,6 +43,7 @@ #include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" +#include "sw/device/lib/dif/autogen/dif_rram_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h" #include "sw/device/lib/dif/autogen/dif_rv_timer_autogen.h" #include "sw/device/lib/dif/autogen/dif_sensor_ctrl_autogen.h" @@ -134,46 +135,50 @@ static dif_pwrmgr_t pwrmgr; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL -static dif_rv_timer_t rv_timer; +static dif_rram_ctrl_t rram_ctrl; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL -static dif_sensor_ctrl_t sensor_ctrl; +static dif_rv_timer_t rv_timer; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL -static dif_spi_device_t spi_device; +static dif_sensor_ctrl_t sensor_ctrl; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +static dif_spi_device_t spi_device; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_host_t spi_host0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL static dif_spi_host_t spi_host1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static dif_sysrst_ctrl_t sysrst_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart2; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static dif_uart_t uart3; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL static dif_usbdev_t usbdev; #endif @@ -272,36 +277,41 @@ static volatile dif_pwrmgr_irq_t pwrmgr_irq_serviced; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_rram_ctrl_irq_t rram_ctrl_irq_expected; +static volatile dif_rram_ctrl_irq_t rram_ctrl_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_rv_timer_irq_t rv_timer_irq_expected; static volatile dif_rv_timer_irq_t rv_timer_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_expected; static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_spi_device_irq_t spi_device_irq_expected; static volatile dif_spi_device_irq_t spi_device_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_spi_host_irq_t spi_host_irq_expected; static volatile dif_spi_host_irq_t spi_host_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_expected; static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_uart_irq_t uart_irq_expected; static volatile dif_uart_irq_t uart_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_usbdev_irq_t usbdev_irq_expected; static volatile dif_usbdev_irq_t usbdev_irq_serviced; #endif @@ -836,6 +846,42 @@ void ottf_external_isr(uint32_t *exc_info) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + case kTopEarlgreyPlicPeripheralRramCtrl: { + dif_rram_ctrl_irq_t irq = + (dif_rram_ctrl_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopEarlgreyPlicIrqIdRramCtrlWrEmpty); + CHECK(irq == rram_ctrl_irq_expected, + "Incorrect rram_ctrl IRQ triggered: exp = %d, obs = %d", + rram_ctrl_irq_expected, irq); + rram_ctrl_irq_serviced = irq; + + dif_rram_ctrl_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_rram_ctrl_irq_get_state(&rram_ctrl, &snapshot)); + CHECK(snapshot == (dif_rram_ctrl_irq_state_snapshot_t)((1 << irq) | 0x3), + "Expected rram_ctrl interrupt status %x. Actual interrupt " + "status = %x", + (1 << irq) | 0x3, snapshot); + + if (0xf & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_rram_ctrl_irq_force(&rram_ctrl, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x3 & (1 << irq))) { + CHECK_DIF_OK(dif_rram_ctrl_irq_set_enabled(&rram_ctrl, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_rram_ctrl_irq_acknowledge(&rram_ctrl, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralRvTimer: { dif_rv_timer_irq_t irq = (dif_rv_timer_irq_t)(plic_irq_id - @@ -858,7 +904,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSensorCtrl: { dif_sensor_ctrl_irq_t irq = (dif_sensor_ctrl_irq_t)(plic_irq_id - @@ -881,7 +927,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSpiDevice: { dif_spi_device_irq_t irq = (dif_spi_device_irq_t)(plic_irq_id - @@ -917,7 +963,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSpiHost0: { dif_spi_host_irq_t irq = (dif_spi_host_irq_t)(plic_irq_id - @@ -953,7 +999,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSpiHost1: { dif_spi_host_irq_t irq = (dif_spi_host_irq_t)(plic_irq_id - @@ -989,7 +1035,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralSysrstCtrl: { dif_sysrst_ctrl_irq_t irq = (dif_sysrst_ctrl_irq_t)(plic_irq_id - @@ -1025,7 +1071,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart0: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1061,7 +1107,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart1: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1097,7 +1143,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart2: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1133,7 +1179,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUart3: { dif_uart_irq_t irq = (dif_uart_irq_t)(plic_irq_id - @@ -1169,7 +1215,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralUsbdev: { dif_usbdev_irq_t irq = (dif_usbdev_irq_t)(plic_irq_id - @@ -1310,56 +1356,61 @@ static void peripherals_init(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_rram_ctrl_init(base_addr, &rram_ctrl)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR); CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR); CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_DEVICE_BASE_ADDR); CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST0_BASE_ADDR); CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR); CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR); CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART1_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART2_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_UART3_BASE_ADDR); CHECK_DIF_OK(dif_uart_init(base_addr, &uart3)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_USBDEV_BASE_ADDR); CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev)); #endif @@ -1447,46 +1498,50 @@ static void peripheral_irqs_clear(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_rv_timer_irq_acknowledge_all(&rv_timer, kHart)); + CHECK_DIF_OK(dif_rram_ctrl_irq_acknowledge_all(&rram_ctrl)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge_all(&sensor_ctrl)); + CHECK_DIF_OK(dif_rv_timer_irq_acknowledge_all(&rv_timer, kHart)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device)); + CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge_all(&sensor_ctrl)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_sysrst_ctrl_irq_acknowledge_all(&sysrst_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart3)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_usbdev_irq_acknowledge_all(&usbdev)); #endif } @@ -1570,31 +1625,40 @@ static void peripheral_irqs_enable(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + // Note: this peripheral contains status interrupts that are asserted by + // default. Therefore, not all interrupts are enabled here, since that + // would interfere with this test. Instead, these interrupts are enabled on + // demand once they are being tested. + dif_rram_ctrl_irq_state_snapshot_t rram_ctrl_irqs = + (dif_rram_ctrl_irq_state_snapshot_t)0xfffffffc; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL dif_rv_timer_irq_state_snapshot_t rv_timer_irqs = (dif_rv_timer_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL dif_sensor_ctrl_irq_state_snapshot_t sensor_ctrl_irqs = (dif_sensor_ctrl_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL dif_spi_device_irq_state_snapshot_t spi_device_irqs = (dif_spi_device_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL dif_spi_host_irq_state_snapshot_t spi_host_irqs = (dif_spi_host_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL dif_sysrst_ctrl_irq_state_snapshot_t sysrst_ctrl_irqs = (dif_sysrst_ctrl_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL // Note: this peripheral contains status interrupts that are asserted by // default. Therefore, not all interrupts are enabled here, since that // would interfere with this test. Instead, these interrupts are enabled on @@ -1603,7 +1667,7 @@ static void peripheral_irqs_enable(void) { (dif_uart_irq_state_snapshot_t)0xfffffefe; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL dif_usbdev_irq_state_snapshot_t usbdev_irqs = (dif_usbdev_irq_state_snapshot_t)0xffffffff; #endif @@ -1679,30 +1743,34 @@ static void peripheral_irqs_enable(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_rv_timer_irq_restore_all(&rv_timer, kHart, &rv_timer_irqs)); + CHECK_DIF_OK(dif_rram_ctrl_irq_restore_all(&rram_ctrl, &rram_ctrl_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_sensor_ctrl_irq_restore_all(&sensor_ctrl, &sensor_ctrl_irqs)); + CHECK_DIF_OK(dif_rv_timer_irq_restore_all(&rv_timer, kHart, &rv_timer_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_spi_device_irq_restore_all(&spi_device, &spi_device_irqs)); + CHECK_DIF_OK(dif_sensor_ctrl_irq_restore_all(&sensor_ctrl, &sensor_ctrl_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_spi_device_irq_restore_all(&spi_device, &spi_device_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_restore_all(&spi_host0, &spi_host_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_spi_host_irq_restore_all(&spi_host1, &spi_host_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl, &sysrst_ctrl_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. if (kDeviceType == kDeviceSimDV) { @@ -1710,19 +1778,19 @@ static void peripheral_irqs_enable(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_restore_all(&uart1, &uart_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_restore_all(&uart2, &uart_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_uart_irq_restore_all(&uart3, &uart_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_usbdev_irq_restore_all(&usbdev, &usbdev_irqs)); #endif } @@ -2087,6 +2155,30 @@ static void peripheral_irqs_trigger(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEarlgreyPlicPeripheralRramCtrl; + status_default_mask = 0x3; + for (dif_rram_ctrl_irq_t irq = kDifRramCtrlIrqWrEmpty; irq <= kDifRramCtrlIrqCorrErr; + ++irq) { + rram_ctrl_irq_expected = irq; + LOG_INFO("Triggering rram_ctrl IRQ %d.", irq); + CHECK_DIF_OK(dif_rram_ctrl_irq_force(&rram_ctrl, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_rram_ctrl_irq_set_enabled(&rram_ctrl, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(rram_ctrl_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from rram_ctrl is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralRvTimer; for (dif_rv_timer_irq_t irq = kDifRvTimerIrqTimerExpiredHart0Timer0; irq <= kDifRvTimerIrqTimerExpiredHart0Timer0; ++irq) { @@ -2101,7 +2193,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSensorCtrl; for (dif_sensor_ctrl_irq_t irq = kDifSensorCtrlIrqIoStatusChange; irq <= kDifSensorCtrlIrqInitStatusChange; ++irq) { @@ -2116,7 +2208,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSpiDevice; status_default_mask = 0x0; for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqUploadCmdfifoNotEmpty; irq <= kDifSpiDeviceIrqTpmRdfifoDrop; @@ -2140,7 +2232,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSpiHost0; status_default_mask = 0x0; for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; irq <= kDifSpiHostIrqSpiEvent; @@ -2164,7 +2256,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSpiHost1; status_default_mask = 0x0; for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; irq <= kDifSpiHostIrqSpiEvent; @@ -2188,7 +2280,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralSysrstCtrl; status_default_mask = 0x0; for (dif_sysrst_ctrl_irq_t irq = kDifSysrstCtrlIrqEventDetected; irq <= kDifSysrstCtrlIrqEventDetected; @@ -2212,7 +2304,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. @@ -2243,7 +2335,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUart1; status_default_mask = 0x101; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; @@ -2267,7 +2359,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUart2; status_default_mask = 0x101; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; @@ -2291,7 +2383,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUart3; status_default_mask = 0x101; for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; @@ -2315,7 +2407,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 21 && 21 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 22 && 22 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralUsbdev; status_default_mask = 0x0; for (dif_usbdev_irq_t irq = kDifUsbdevIrqPktReceived; irq <= kDifUsbdevIrqAvSetupEmpty; diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index 7c34ea3b2de4c..7b7125d3cfab5 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c @@ -16,7 +16,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[64] = { + top_earlgrey_alert_for_peripheral[69] = { [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0, [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1, [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2, @@ -55,6 +55,11 @@ const top_earlgrey_alert_peripheral_t [kTopEarlgreyAlertIdFlashCtrlFatalErr] = kTopEarlgreyAlertPeripheralFlashCtrl, [kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl, [kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl, + [kTopEarlgreyAlertIdRramCtrlRecovErr] = kTopEarlgreyAlertPeripheralRramCtrl, + [kTopEarlgreyAlertIdRramCtrlFatalStdErr] = kTopEarlgreyAlertPeripheralRramCtrl, + [kTopEarlgreyAlertIdRramCtrlFatalErr] = kTopEarlgreyAlertPeripheralRramCtrl, + [kTopEarlgreyAlertIdRramCtrlFatalMacroErr] = kTopEarlgreyAlertPeripheralRramCtrl, + [kTopEarlgreyAlertIdRramCtrlRecovMacroErr] = kTopEarlgreyAlertPeripheralRramCtrl, [kTopEarlgreyAlertIdRvDmFatalFault] = kTopEarlgreyAlertPeripheralRvDm, [kTopEarlgreyAlertIdRvPlicFatalFault] = kTopEarlgreyAlertPeripheralRvPlic, [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes, @@ -90,7 +95,7 @@ const top_earlgrey_alert_peripheral_t * `top_earlgrey_plic_peripheral_t`. */ const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[184] = { + top_earlgrey_plic_interrupt_for_peripheral[190] = { [kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown, [kTopEarlgreyPlicIrqIdUart0TxWatermark] = kTopEarlgreyPlicPeripheralUart0, [kTopEarlgreyPlicIrqIdUart0RxWatermark] = kTopEarlgreyPlicPeripheralUart0, @@ -255,6 +260,12 @@ const top_earlgrey_plic_peripheral_t [kTopEarlgreyPlicIrqIdFlashCtrlRdLvl] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdFlashCtrlOpDone] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdFlashCtrlCorrErr] = kTopEarlgreyPlicPeripheralFlashCtrl, + [kTopEarlgreyPlicIrqIdRramCtrlWrEmpty] = kTopEarlgreyPlicPeripheralRramCtrl, + [kTopEarlgreyPlicIrqIdRramCtrlWrLvl] = kTopEarlgreyPlicPeripheralRramCtrl, + [kTopEarlgreyPlicIrqIdRramCtrlRdFull] = kTopEarlgreyPlicPeripheralRramCtrl, + [kTopEarlgreyPlicIrqIdRramCtrlRdLvl] = kTopEarlgreyPlicPeripheralRramCtrl, + [kTopEarlgreyPlicIrqIdRramCtrlOpDone] = kTopEarlgreyPlicPeripheralRramCtrl, + [kTopEarlgreyPlicIrqIdRramCtrlCorrErr] = kTopEarlgreyPlicPeripheralRramCtrl, [kTopEarlgreyPlicIrqIdHmacHmacDone] = kTopEarlgreyPlicPeripheralHmac, [kTopEarlgreyPlicIrqIdHmacFifoEmpty] = kTopEarlgreyPlicPeripheralHmac, [kTopEarlgreyPlicIrqIdHmacHmacErr] = kTopEarlgreyPlicPeripheralHmac, diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 1439119f46431..345bbfae45f60 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -552,6 +552,42 @@ extern "C" { */ #define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u +/** + * Peripheral base address for core device on rram_ctrl in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR 0x41010000u + +/** + * Peripheral size for core device on rram_ctrl in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR and + * `TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES 0x200u + +/** + * Peripheral base address for prim device on rram_macro in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR 0x41018000u + +/** + * Peripheral size for prim device on rram_macro in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR and + * `TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR + TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES 0x10u + /** * Peripheral base address for regs device on rv_dm in top earlgrey. * @@ -861,6 +897,16 @@ extern "C" { */ #define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u +/** + * Memory base address for host memory on rram_ctrl in top earlgrey. + */ +#define TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR 0x30000000u + +/** + * Memory size for host memory on rram_ctrl in top earlgrey. + */ +#define TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES 0x200000u + /** * Memory base address for ram memory on sram_ctrl_main in top earlgrey. */ @@ -921,15 +967,16 @@ typedef enum top_earlgrey_plic_peripheral { kTopEarlgreyPlicPeripheralAonTimer = 19, /**< aon_timer */ kTopEarlgreyPlicPeripheralSensorCtrl = 20, /**< sensor_ctrl */ kTopEarlgreyPlicPeripheralFlashCtrl = 21, /**< flash_ctrl */ - kTopEarlgreyPlicPeripheralHmac = 22, /**< hmac */ - kTopEarlgreyPlicPeripheralKmac = 23, /**< kmac */ - kTopEarlgreyPlicPeripheralOtbn = 24, /**< otbn */ - kTopEarlgreyPlicPeripheralKeymgr = 25, /**< keymgr */ - kTopEarlgreyPlicPeripheralCsrng = 26, /**< csrng */ - kTopEarlgreyPlicPeripheralEntropySrc = 27, /**< entropy_src */ - kTopEarlgreyPlicPeripheralEdn0 = 28, /**< edn0 */ - kTopEarlgreyPlicPeripheralEdn1 = 29, /**< edn1 */ - kTopEarlgreyPlicPeripheralLast = 29, /**< \internal Final PLIC peripheral */ + kTopEarlgreyPlicPeripheralRramCtrl = 22, /**< rram_ctrl */ + kTopEarlgreyPlicPeripheralHmac = 23, /**< hmac */ + kTopEarlgreyPlicPeripheralKmac = 24, /**< kmac */ + kTopEarlgreyPlicPeripheralOtbn = 25, /**< otbn */ + kTopEarlgreyPlicPeripheralKeymgr = 26, /**< keymgr */ + kTopEarlgreyPlicPeripheralCsrng = 27, /**< csrng */ + kTopEarlgreyPlicPeripheralEntropySrc = 28, /**< entropy_src */ + kTopEarlgreyPlicPeripheralEdn0 = 29, /**< edn0 */ + kTopEarlgreyPlicPeripheralEdn1 = 30, /**< edn1 */ + kTopEarlgreyPlicPeripheralLast = 30, /**< \internal Final PLIC peripheral */ } top_earlgrey_plic_peripheral_t; /** @@ -1103,27 +1150,33 @@ typedef enum top_earlgrey_plic_irq_id { kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 161, /**< flash_ctrl_rd_lvl */ kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 162, /**< flash_ctrl_op_done */ kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 163, /**< flash_ctrl_corr_err */ - kTopEarlgreyPlicIrqIdHmacHmacDone = 164, /**< hmac_hmac_done */ - kTopEarlgreyPlicIrqIdHmacFifoEmpty = 165, /**< hmac_fifo_empty */ - kTopEarlgreyPlicIrqIdHmacHmacErr = 166, /**< hmac_hmac_err */ - kTopEarlgreyPlicIrqIdKmacKmacDone = 167, /**< kmac_kmac_done */ - kTopEarlgreyPlicIrqIdKmacFifoEmpty = 168, /**< kmac_fifo_empty */ - kTopEarlgreyPlicIrqIdKmacKmacErr = 169, /**< kmac_kmac_err */ - kTopEarlgreyPlicIrqIdOtbnDone = 170, /**< otbn_done */ - kTopEarlgreyPlicIrqIdKeymgrOpDone = 171, /**< keymgr_op_done */ - kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 172, /**< csrng_cs_cmd_req_done */ - kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 173, /**< csrng_cs_entropy_req */ - kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 174, /**< csrng_cs_hw_inst_exc */ - kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 175, /**< csrng_cs_fatal_err */ - kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 176, /**< entropy_src_es_entropy_valid */ - kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 177, /**< entropy_src_es_health_test_failed */ - kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 178, /**< entropy_src_es_observe_fifo_ready */ - kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 179, /**< entropy_src_es_fatal_err */ - kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 180, /**< edn0_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 181, /**< edn0_edn_fatal_err */ - kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 182, /**< edn1_edn_cmd_req_done */ - kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 183, /**< edn1_edn_fatal_err */ - kTopEarlgreyPlicIrqIdLast = 183, /**< \internal The Last Valid Interrupt ID. */ + kTopEarlgreyPlicIrqIdRramCtrlWrEmpty = 164, /**< rram_ctrl_wr_empty */ + kTopEarlgreyPlicIrqIdRramCtrlWrLvl = 165, /**< rram_ctrl_wr_lvl */ + kTopEarlgreyPlicIrqIdRramCtrlRdFull = 166, /**< rram_ctrl_rd_full */ + kTopEarlgreyPlicIrqIdRramCtrlRdLvl = 167, /**< rram_ctrl_rd_lvl */ + kTopEarlgreyPlicIrqIdRramCtrlOpDone = 168, /**< rram_ctrl_op_done */ + kTopEarlgreyPlicIrqIdRramCtrlCorrErr = 169, /**< rram_ctrl_corr_err */ + kTopEarlgreyPlicIrqIdHmacHmacDone = 170, /**< hmac_hmac_done */ + kTopEarlgreyPlicIrqIdHmacFifoEmpty = 171, /**< hmac_fifo_empty */ + kTopEarlgreyPlicIrqIdHmacHmacErr = 172, /**< hmac_hmac_err */ + kTopEarlgreyPlicIrqIdKmacKmacDone = 173, /**< kmac_kmac_done */ + kTopEarlgreyPlicIrqIdKmacFifoEmpty = 174, /**< kmac_fifo_empty */ + kTopEarlgreyPlicIrqIdKmacKmacErr = 175, /**< kmac_kmac_err */ + kTopEarlgreyPlicIrqIdOtbnDone = 176, /**< otbn_done */ + kTopEarlgreyPlicIrqIdKeymgrOpDone = 177, /**< keymgr_op_done */ + kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 178, /**< csrng_cs_cmd_req_done */ + kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 179, /**< csrng_cs_entropy_req */ + kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 180, /**< csrng_cs_hw_inst_exc */ + kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 181, /**< csrng_cs_fatal_err */ + kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 182, /**< entropy_src_es_entropy_valid */ + kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 183, /**< entropy_src_es_health_test_failed */ + kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 184, /**< entropy_src_es_observe_fifo_ready */ + kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 185, /**< entropy_src_es_fatal_err */ + kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 186, /**< edn0_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 187, /**< edn0_edn_fatal_err */ + kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 188, /**< edn1_edn_cmd_req_done */ + kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 189, /**< edn1_edn_fatal_err */ + kTopEarlgreyPlicIrqIdLast = 189, /**< \internal The Last Valid Interrupt ID. */ } top_earlgrey_plic_irq_id_t; /** @@ -1133,7 +1186,7 @@ typedef enum top_earlgrey_plic_irq_id { * `top_earlgrey_plic_peripheral_t`. */ extern const top_earlgrey_plic_peripheral_t - top_earlgrey_plic_interrupt_for_peripheral[184]; + top_earlgrey_plic_interrupt_for_peripheral[190]; /** * PLIC Interrupt Target. @@ -1180,22 +1233,23 @@ typedef enum top_earlgrey_alert_peripheral { kTopEarlgreyAlertPeripheralSensorCtrl = 23, /**< sensor_ctrl */ kTopEarlgreyAlertPeripheralSramCtrlRet = 24, /**< sram_ctrl_ret */ kTopEarlgreyAlertPeripheralFlashCtrl = 25, /**< flash_ctrl */ - kTopEarlgreyAlertPeripheralRvDm = 26, /**< rv_dm */ - kTopEarlgreyAlertPeripheralRvPlic = 27, /**< rv_plic */ - kTopEarlgreyAlertPeripheralAes = 28, /**< aes */ - kTopEarlgreyAlertPeripheralHmac = 29, /**< hmac */ - kTopEarlgreyAlertPeripheralKmac = 30, /**< kmac */ - kTopEarlgreyAlertPeripheralOtbn = 31, /**< otbn */ - kTopEarlgreyAlertPeripheralKeymgr = 32, /**< keymgr */ - kTopEarlgreyAlertPeripheralCsrng = 33, /**< csrng */ - kTopEarlgreyAlertPeripheralEntropySrc = 34, /**< entropy_src */ - kTopEarlgreyAlertPeripheralEdn0 = 35, /**< edn0 */ - kTopEarlgreyAlertPeripheralEdn1 = 36, /**< edn1 */ - kTopEarlgreyAlertPeripheralSramCtrlMain = 37, /**< sram_ctrl_main */ - kTopEarlgreyAlertPeripheralSramCtrlSec = 38, /**< sram_ctrl_sec */ - kTopEarlgreyAlertPeripheralRomCtrl = 39, /**< rom_ctrl */ - kTopEarlgreyAlertPeripheralRvCoreIbex = 40, /**< rv_core_ibex */ - kTopEarlgreyAlertPeripheralLast = 40, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralRramCtrl = 26, /**< rram_ctrl */ + kTopEarlgreyAlertPeripheralRvDm = 27, /**< rv_dm */ + kTopEarlgreyAlertPeripheralRvPlic = 28, /**< rv_plic */ + kTopEarlgreyAlertPeripheralAes = 29, /**< aes */ + kTopEarlgreyAlertPeripheralHmac = 30, /**< hmac */ + kTopEarlgreyAlertPeripheralKmac = 31, /**< kmac */ + kTopEarlgreyAlertPeripheralOtbn = 32, /**< otbn */ + kTopEarlgreyAlertPeripheralKeymgr = 33, /**< keymgr */ + kTopEarlgreyAlertPeripheralCsrng = 34, /**< csrng */ + kTopEarlgreyAlertPeripheralEntropySrc = 35, /**< entropy_src */ + kTopEarlgreyAlertPeripheralEdn0 = 36, /**< edn0 */ + kTopEarlgreyAlertPeripheralEdn1 = 37, /**< edn1 */ + kTopEarlgreyAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */ + kTopEarlgreyAlertPeripheralSramCtrlSec = 39, /**< sram_ctrl_sec */ + kTopEarlgreyAlertPeripheralRomCtrl = 40, /**< rom_ctrl */ + kTopEarlgreyAlertPeripheralRvCoreIbex = 41, /**< rv_core_ibex */ + kTopEarlgreyAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -1243,33 +1297,38 @@ typedef enum top_earlgrey_alert_id { kTopEarlgreyAlertIdFlashCtrlFatalErr = 35, /**< flash_ctrl_fatal_err */ kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 36, /**< flash_ctrl_fatal_prim_flash_alert */ kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 37, /**< flash_ctrl_recov_prim_flash_alert */ - kTopEarlgreyAlertIdRvDmFatalFault = 38, /**< rv_dm_fatal_fault */ - kTopEarlgreyAlertIdRvPlicFatalFault = 39, /**< rv_plic_fatal_fault */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 40, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 41, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdHmacFatalFault = 42, /**< hmac_fatal_fault */ - kTopEarlgreyAlertIdKmacRecovOperationErr = 43, /**< kmac_recov_operation_err */ - kTopEarlgreyAlertIdKmacFatalFaultErr = 44, /**< kmac_fatal_fault_err */ - kTopEarlgreyAlertIdOtbnFatal = 45, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 46, /**< otbn_recov */ - kTopEarlgreyAlertIdKeymgrRecovOperationErr = 47, /**< keymgr_recov_operation_err */ - kTopEarlgreyAlertIdKeymgrFatalFaultErr = 48, /**< keymgr_fatal_fault_err */ - kTopEarlgreyAlertIdCsrngRecovAlert = 49, /**< csrng_recov_alert */ - kTopEarlgreyAlertIdCsrngFatalAlert = 50, /**< csrng_fatal_alert */ - kTopEarlgreyAlertIdEntropySrcRecovAlert = 51, /**< entropy_src_recov_alert */ - kTopEarlgreyAlertIdEntropySrcFatalAlert = 52, /**< entropy_src_fatal_alert */ - kTopEarlgreyAlertIdEdn0RecovAlert = 53, /**< edn0_recov_alert */ - kTopEarlgreyAlertIdEdn0FatalAlert = 54, /**< edn0_fatal_alert */ - kTopEarlgreyAlertIdEdn1RecovAlert = 55, /**< edn1_recov_alert */ - kTopEarlgreyAlertIdEdn1FatalAlert = 56, /**< edn1_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlMainFatalError = 57, /**< sram_ctrl_main_fatal_error */ - kTopEarlgreyAlertIdSramCtrlSecFatalError = 58, /**< sram_ctrl_sec_fatal_error */ - kTopEarlgreyAlertIdRomCtrlFatal = 59, /**< rom_ctrl_fatal */ - kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 60, /**< rv_core_ibex_fatal_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 61, /**< rv_core_ibex_recov_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 62, /**< rv_core_ibex_fatal_hw_err */ - kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 63, /**< rv_core_ibex_recov_hw_err */ - kTopEarlgreyAlertIdLast = 63, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdRramCtrlRecovErr = 38, /**< rram_ctrl_recov_err */ + kTopEarlgreyAlertIdRramCtrlFatalStdErr = 39, /**< rram_ctrl_fatal_std_err */ + kTopEarlgreyAlertIdRramCtrlFatalErr = 40, /**< rram_ctrl_fatal_err */ + kTopEarlgreyAlertIdRramCtrlFatalMacroErr = 41, /**< rram_ctrl_fatal_macro_err */ + kTopEarlgreyAlertIdRramCtrlRecovMacroErr = 42, /**< rram_ctrl_recov_macro_err */ + kTopEarlgreyAlertIdRvDmFatalFault = 43, /**< rv_dm_fatal_fault */ + kTopEarlgreyAlertIdRvPlicFatalFault = 44, /**< rv_plic_fatal_fault */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 45, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 46, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdHmacFatalFault = 47, /**< hmac_fatal_fault */ + kTopEarlgreyAlertIdKmacRecovOperationErr = 48, /**< kmac_recov_operation_err */ + kTopEarlgreyAlertIdKmacFatalFaultErr = 49, /**< kmac_fatal_fault_err */ + kTopEarlgreyAlertIdOtbnFatal = 50, /**< otbn_fatal */ + kTopEarlgreyAlertIdOtbnRecov = 51, /**< otbn_recov */ + kTopEarlgreyAlertIdKeymgrRecovOperationErr = 52, /**< keymgr_recov_operation_err */ + kTopEarlgreyAlertIdKeymgrFatalFaultErr = 53, /**< keymgr_fatal_fault_err */ + kTopEarlgreyAlertIdCsrngRecovAlert = 54, /**< csrng_recov_alert */ + kTopEarlgreyAlertIdCsrngFatalAlert = 55, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdEntropySrcRecovAlert = 56, /**< entropy_src_recov_alert */ + kTopEarlgreyAlertIdEntropySrcFatalAlert = 57, /**< entropy_src_fatal_alert */ + kTopEarlgreyAlertIdEdn0RecovAlert = 58, /**< edn0_recov_alert */ + kTopEarlgreyAlertIdEdn0FatalAlert = 59, /**< edn0_fatal_alert */ + kTopEarlgreyAlertIdEdn1RecovAlert = 60, /**< edn1_recov_alert */ + kTopEarlgreyAlertIdEdn1FatalAlert = 61, /**< edn1_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalError = 62, /**< sram_ctrl_main_fatal_error */ + kTopEarlgreyAlertIdSramCtrlSecFatalError = 63, /**< sram_ctrl_sec_fatal_error */ + kTopEarlgreyAlertIdRomCtrlFatal = 64, /**< rom_ctrl_fatal */ + kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 65, /**< rv_core_ibex_fatal_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 66, /**< rv_core_ibex_recov_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 67, /**< rv_core_ibex_fatal_hw_err */ + kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 68, /**< rv_core_ibex_recov_hw_err */ + kTopEarlgreyAlertIdLast = 68, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1279,7 +1338,7 @@ typedef enum top_earlgrey_alert_id { * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[64]; + top_earlgrey_alert_for_peripheral[69]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 @@ -1344,14 +1403,17 @@ typedef enum top_earlgrey_pinmux_peripheral_in { kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 47, /**< Peripheral Input 47 */ kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 48, /**< Peripheral Input 48 */ kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 49, /**< Peripheral Input 49 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent = 50, /**< Peripheral Input 50 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In = 51, /**< Peripheral Input 51 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In = 52, /**< Peripheral Input 52 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In = 53, /**< Peripheral Input 53 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn = 54, /**< Peripheral Input 54 */ - kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen = 55, /**< Peripheral Input 55 */ - kTopEarlgreyPinmuxPeripheralInUsbdevSense = 56, /**< Peripheral Input 56 */ - kTopEarlgreyPinmuxPeripheralInLast = 56, /**< \internal Last valid peripheral input */ + kTopEarlgreyPinmuxPeripheralInRramMacroTck = 50, /**< Peripheral Input 50 */ + kTopEarlgreyPinmuxPeripheralInRramMacroTms = 51, /**< Peripheral Input 51 */ + kTopEarlgreyPinmuxPeripheralInRramMacroTdi = 52, /**< Peripheral Input 52 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent = 53, /**< Peripheral Input 53 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In = 54, /**< Peripheral Input 54 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In = 55, /**< Peripheral Input 55 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In = 56, /**< Peripheral Input 56 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn = 57, /**< Peripheral Input 57 */ + kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen = 58, /**< Peripheral Input 58 */ + kTopEarlgreyPinmuxPeripheralInUsbdevSense = 59, /**< Peripheral Input 59 */ + kTopEarlgreyPinmuxPeripheralInLast = 59, /**< \internal Last valid peripheral input */ } top_earlgrey_pinmux_peripheral_in_t; /** @@ -1520,23 +1582,24 @@ typedef enum top_earlgrey_pinmux_outsel { kTopEarlgreyPinmuxOutselSpiHost1Sck = 49, /**< Peripheral Output 46 */ kTopEarlgreyPinmuxOutselSpiHost1Csb = 50, /**< Peripheral Output 47 */ kTopEarlgreyPinmuxOutselFlashCtrlTdo = 51, /**< Peripheral Output 48 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 = 52, /**< Peripheral Output 49 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 = 53, /**< Peripheral Output 50 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 = 54, /**< Peripheral Output 51 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3 = 55, /**< Peripheral Output 52 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4 = 56, /**< Peripheral Output 53 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5 = 57, /**< Peripheral Output 54 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6 = 58, /**< Peripheral Output 55 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7 = 59, /**< Peripheral Output 56 */ - kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8 = 60, /**< Peripheral Output 57 */ - kTopEarlgreyPinmuxOutselOtpMacroTest0 = 61, /**< Peripheral Output 58 */ - kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable = 62, /**< Peripheral Output 59 */ - kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out = 63, /**< Peripheral Output 60 */ - kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out = 64, /**< Peripheral Output 61 */ - kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out = 65, /**< Peripheral Output 62 */ - kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut = 66, /**< Peripheral Output 63 */ - kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup = 67, /**< Peripheral Output 64 */ - kTopEarlgreyPinmuxOutselLast = 67, /**< \internal Last valid outsel value */ + kTopEarlgreyPinmuxOutselRramMacroTdo = 52, /**< Peripheral Output 49 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 = 53, /**< Peripheral Output 50 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 = 54, /**< Peripheral Output 51 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 = 55, /**< Peripheral Output 52 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3 = 56, /**< Peripheral Output 53 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4 = 57, /**< Peripheral Output 54 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5 = 58, /**< Peripheral Output 55 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6 = 59, /**< Peripheral Output 56 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7 = 60, /**< Peripheral Output 57 */ + kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8 = 61, /**< Peripheral Output 58 */ + kTopEarlgreyPinmuxOutselOtpMacroTest0 = 62, /**< Peripheral Output 59 */ + kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable = 63, /**< Peripheral Output 60 */ + kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out = 64, /**< Peripheral Output 61 */ + kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out = 65, /**< Peripheral Output 62 */ + kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out = 66, /**< Peripheral Output 63 */ + kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut = 67, /**< Peripheral Output 64 */ + kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup = 68, /**< Peripheral Output 65 */ + kTopEarlgreyPinmuxOutselLast = 68, /**< \internal Last valid outsel value */ } top_earlgrey_pinmux_outsel_t; /** diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index d24fbce359c0b..ef2b475cc8911 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -45,6 +45,16 @@ */ #define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000 +/** + * Memory base for host memory on rram_ctrl in top earlgrey. + */ +#define TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR 0x30000000 + +/** + * Memory size for host memory on rram_ctrl in top earlgrey. + */ +#define TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES 0x200000 + /** * Memory base for ram memory on sram_ctrl_main in top earlgrey. */ @@ -569,6 +579,40 @@ * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`. */ #define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on rram_ctrl in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR 0x41010000 + +/** + * Peripheral size for core device on rram_ctrl in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR and + * `TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES 0x200 +/** + * Peripheral base address for prim device on rram_macro in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR 0x41018000 + +/** + * Peripheral size for prim device on rram_macro in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR and + * `TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR + TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES 0x10 /** * Peripheral base address for regs device on rv_dm in top earlgrey. * diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld index 246872efdd27d..cc9ab452c10ce 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld @@ -16,6 +16,7 @@ MEMORY { ram_ret_aon(rwx) : ORIGIN = 0x40600000, LENGTH = 0x1000 eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 + rram(rx) : ORIGIN = 0x30000000, LENGTH = 0x200000 ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 ram_secondary(rwx) : ORIGIN = 0x10020000, LENGTH = 0x10000 rom(rx) : ORIGIN = 0x00040000, LENGTH = 0xc000 diff --git a/sw/host/opentitanlib/src/otp/alert_handler.rs b/sw/host/opentitanlib/src/otp/alert_handler.rs index a0b66d725fbed..17b7074454a42 100644 --- a/sw/host/opentitanlib/src/otp/alert_handler.rs +++ b/sw/host/opentitanlib/src/otp/alert_handler.rs @@ -373,7 +373,7 @@ mod test { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, - 0x00000001, + 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, ], en: [ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -385,7 +385,7 @@ mod test { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, ], class: [ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -397,7 +397,7 @@ mod test { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, ], loc_regwen: [ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, @@ -512,7 +512,7 @@ mod test { #[test] fn test_crc_from_regs() { - assert_eq!(TEST_REGS.crc32(), 0x1391a65e); + assert_eq!(TEST_REGS.crc32(), 0x3d61fdac); } #[test] @@ -529,7 +529,7 @@ mod test { AlertRegs::try_new(LcStateVal::Dev, &TestOtpAlertsDisabled {}) .unwrap() .crc32(), - 0x1391a65e + 0x3d61fdac ); } @@ -539,7 +539,7 @@ mod test { AlertRegs::try_new(LcStateVal::Dev, &TestOtpAlertsEnabled {}) .unwrap() .crc32(), - 0xbceb0c68 + 0x921b579a ); } } diff --git a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs index 9bfe8faac718a..a7cd8797aac90 100644 --- a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs +++ b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs @@ -7,7 +7,7 @@ /* automatically generated by rust-bindgen 0.72.1 */ -pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 64; +pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 69; pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 24; pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5; pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32; @@ -61,7 +61,7 @@ pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: u32 = 20; pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 64; +pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 69; pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: u32 = 24; pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; @@ -251,200 +251,236 @@ pub const ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET: u32 = 272; pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET: u32 = 276; +pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: u32 = 280; +pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET: u32 = 284; +pub const ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_66_REG_OFFSET: u32 = 288; +pub const ALERT_HANDLER_ALERT_REGWEN_66_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_66_EN_66_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_67_REG_OFFSET: u32 = 292; +pub const ALERT_HANDLER_ALERT_REGWEN_67_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_67_EN_67_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_REGWEN_68_REG_OFFSET: u32 = 296; +pub const ALERT_HANDLER_ALERT_REGWEN_68_REG_RESVAL: u32 = 1; +pub const ALERT_HANDLER_ALERT_REGWEN_68_EN_68_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 64; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 276; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 69; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 300; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 280; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 304; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 284; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 308; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 288; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 312; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 292; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 316; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 296; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 320; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 300; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 324; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 304; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 328; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 308; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 332; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 312; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 336; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 316; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 340; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 320; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 344; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 324; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 348; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 328; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 352; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 332; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 356; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 336; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 360; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 340; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 364; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 344; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 368; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 348; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 372; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 352; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 376; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 356; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 380; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 360; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 384; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 364; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 388; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 368; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 392; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 372; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 396; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 376; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 400; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 380; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 404; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 384; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 408; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 388; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 412; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 392; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 416; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 396; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 420; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 400; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 424; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 404; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 428; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 408; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 432; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 412; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 436; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 416; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 440; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 420; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 444; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 424; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 448; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 428; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 452; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 432; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 456; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 436; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 460; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 440; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 464; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 444; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 468; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 448; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 472; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 452; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 476; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 456; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 480; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 460; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 484; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 464; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 488; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 468; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 492; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 472; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 496; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 476; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 500; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 480; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 504; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 484; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 508; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 488; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 512; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 492; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 516; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 496; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 520; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 500; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 524; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 504; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 528; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 508; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 532; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 512; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 536; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 516; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 540; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 520; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 544; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 524; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 548; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 552; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 556; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET: u32 = 560; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_OFFSET: u32 = 564; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_66_EN_A_66_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_OFFSET: u32 = 568; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_67_EN_A_67_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_OFFSET: u32 = 572; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_EN_SHADOWED_68_EN_A_68_BIT: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 64; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 528; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 69; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 576; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: u32 = 0; @@ -452,494 +488,536 @@ pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 1; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 2; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 3; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 532; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 580; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 536; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 584; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 540; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 588; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 544; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 592; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 548; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 596; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 552; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 600; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 556; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 604; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 560; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 608; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 564; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 612; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 568; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 616; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 572; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 620; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 576; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 624; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 580; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 628; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 584; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 632; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 588; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 636; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 592; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 640; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 596; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 644; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 600; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 648; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 604; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 652; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 608; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 656; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 612; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 660; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 616; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 664; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 620; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 668; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 624; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 672; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 628; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 676; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 632; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 680; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 636; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 684; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 640; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 688; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 644; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 692; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 648; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 696; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 652; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 700; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 656; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 704; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 660; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 708; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 664; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 712; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 668; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 716; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 672; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 720; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 676; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 724; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 680; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 728; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 684; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 732; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 688; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 736; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 692; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 740; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 696; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 744; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 700; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 748; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 704; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 752; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 708; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 756; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 712; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 760; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 716; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 764; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 720; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 768; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 724; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 772; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 728; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 776; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 732; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 780; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 736; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 784; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 740; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 788; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 744; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 792; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 748; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 796; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 752; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 800; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 756; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 804; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 760; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 808; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 764; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 812; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 768; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 816; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 772; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 820; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: u32 = 0; -pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 776; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 824; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 3; pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 828; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 832; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET: u32 = 836; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_OFFSET: u32 = 840; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_OFFSET: u32 = 844; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_OFFSET: u32 = 848; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK: u32 = 3; +pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1; -pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 64; -pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 780; +pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 69; +pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 852; pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 784; +pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 856; pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 788; +pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 860; pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 792; +pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 864; pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 796; +pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 868; pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 800; +pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 872; pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 804; +pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 876; pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 808; +pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 880; pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 812; +pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 884; pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 816; +pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 888; pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 820; +pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 892; pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 824; +pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 896; pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 828; +pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 900; pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 832; +pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 904; pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 836; +pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 908; pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 840; +pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 912; pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 844; +pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 916; pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 848; +pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 920; pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 852; +pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 924; pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 856; +pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 928; pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 860; +pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 932; pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 864; +pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 936; pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 868; +pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 940; pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 872; +pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 944; pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 876; +pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 948; pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 880; +pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 952; pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 884; +pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 956; pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 888; +pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 960; pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 892; +pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 964; pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 896; +pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 968; pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 900; +pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 972; pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 904; +pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 976; pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 908; +pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 980; pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 912; +pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 984; pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 916; +pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 988; pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 920; +pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 992; pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 924; +pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 996; pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 928; +pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 1000; pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 932; +pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 1004; pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 936; +pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 1008; pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 940; +pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 1012; pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 944; +pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 1016; pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 948; +pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 1020; pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 952; +pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 1024; pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 956; +pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 1028; pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 960; +pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 1032; pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 964; +pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 1036; pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 968; +pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 1040; pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 972; +pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 1044; pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 976; +pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1048; pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 980; +pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1052; pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 984; +pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1056; pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 988; +pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1060; pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 992; +pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1064; pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 996; +pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1068; pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1000; +pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1072; pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1004; +pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1076; pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1008; +pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1080; pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1012; +pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1084; pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1016; +pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1088; pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1020; +pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1092; pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1024; +pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1096; pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0; -pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1028; +pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1100; pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1104; +pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1108; +pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET: u32 = 1112; +pub const ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_66_REG_OFFSET: u32 = 1116; +pub const ALERT_HANDLER_ALERT_CAUSE_66_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_66_A_66_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_67_REG_OFFSET: u32 = 1120; +pub const ALERT_HANDLER_ALERT_CAUSE_67_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_67_A_67_BIT: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_68_REG_OFFSET: u32 = 1124; +pub const ALERT_HANDLER_ALERT_CAUSE_68_REG_RESVAL: u32 = 0; +pub const ALERT_HANDLER_ALERT_CAUSE_68_A_68_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1032; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1128; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1036; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1132; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1040; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1136; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1044; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1140; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1048; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1144; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1052; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1148; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1056; +pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1152; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1060; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1156; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1064; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1160; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1068; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1164; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1072; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1168; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1076; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1172; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1080; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1176; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1084; +pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1180; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1088; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1184; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: u32 = 0; @@ -947,57 +1025,57 @@ pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 2; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 3; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1092; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1188; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1096; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1192; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1100; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1196; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1104; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1200; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1108; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1204; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1112; +pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1208; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 3; pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1116; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1212; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1120; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1216; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1124; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1220; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1128; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1224; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1132; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1228; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1136; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1232; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0; -pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1140; +pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1236; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1144; +pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1240; pub const ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1148; +pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1244; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1013,38 +1091,38 @@ pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1152; +pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1248; pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1156; +pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1252; pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1160; +pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1256; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1164; +pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1260; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1168; +pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1264; pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1172; +pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1268; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1176; +pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1272; pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1180; +pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1276; pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1184; +pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1280; pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1188; +pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1284; pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1192; +pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1288; pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1196; +pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1292; pub const ALERT_HANDLER_CLASSA_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: u32 = 0; @@ -1056,10 +1134,10 @@ pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1200; +pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1296; pub const ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1204; +pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1300; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1075,38 +1153,38 @@ pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1208; +pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1304; pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1212; +pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1308; pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1216; +pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1312; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1220; +pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1316; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1224; +pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1320; pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1228; +pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1324; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1232; +pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1328; pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1236; +pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1332; pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1240; +pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1336; pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1244; +pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1340; pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1248; +pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1344; pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1252; +pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1348; pub const ALERT_HANDLER_CLASSB_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: u32 = 0; @@ -1118,10 +1196,10 @@ pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1256; +pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1352; pub const ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1260; +pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1356; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1137,38 +1215,38 @@ pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1264; +pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1360; pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1268; +pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1364; pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1272; +pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1368; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1276; +pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1372; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1280; +pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1376; pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1284; +pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1380; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1288; +pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1384; pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1292; +pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1388; pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1296; +pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1392; pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1300; +pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1396; pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1304; +pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1400; pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1308; +pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1404; pub const ALERT_HANDLER_CLASSC_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: u32 = 0; @@ -1180,10 +1258,10 @@ pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 4; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 5; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 6; pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 7; -pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1312; +pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1408; pub const ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1316; +pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1412; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1; @@ -1199,38 +1277,38 @@ pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; -pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1320; +pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1416; pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL: u32 = 1; pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1324; +pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1420; pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1328; +pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1424; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1332; +pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1428; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; -pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1336; +pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1432; pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1340; +pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1436; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK: u32 = 3; pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; -pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1344; +pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1440; pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1348; +pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1444; pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1352; +pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1448; pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1356; +pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1452; pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1360; +pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1456; pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL: u32 = 0; -pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1364; +pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1460; pub const ALERT_HANDLER_CLASSD_STATE_REG_RESVAL: u32 = 0; pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 7; pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: u32 = 0; diff --git a/sw/host/ot_hal/src/top/autogen/earlgrey.rs b/sw/host/ot_hal/src/top/autogen/earlgrey.rs index d069106b33d9e..519b9cef181bf 100644 --- a/sw/host/ot_hal/src/top/autogen/earlgrey.rs +++ b/sw/host/ot_hal/src/top/autogen/earlgrey.rs @@ -63,14 +63,17 @@ with_unknown! { FlashCtrlTck = 47, FlashCtrlTms = 48, FlashCtrlTdi = 49, - SysrstCtrlAcPresent = 50, - SysrstCtrlKey0In = 51, - SysrstCtrlKey1In = 52, - SysrstCtrlKey2In = 53, - SysrstCtrlPwrbIn = 54, - SysrstCtrlLidOpen = 55, - UsbdevSense = 56, - End = 57, + RramMacroTck = 50, + RramMacroTms = 51, + RramMacroTdi = 52, + SysrstCtrlAcPresent = 53, + SysrstCtrlKey0In = 54, + SysrstCtrlKey1In = 55, + SysrstCtrlKey2In = 56, + SysrstCtrlPwrbIn = 57, + SysrstCtrlLidOpen = 58, + UsbdevSense = 59, + End = 60, } pub enum PinmuxInsel: u32 [default = Self::End] { @@ -230,23 +233,24 @@ with_unknown! { SpiHost1Sck = 49, SpiHost1Csb = 50, FlashCtrlTdo = 51, - SensorCtrlAstDebugOut0 = 52, - SensorCtrlAstDebugOut1 = 53, - SensorCtrlAstDebugOut2 = 54, - SensorCtrlAstDebugOut3 = 55, - SensorCtrlAstDebugOut4 = 56, - SensorCtrlAstDebugOut5 = 57, - SensorCtrlAstDebugOut6 = 58, - SensorCtrlAstDebugOut7 = 59, - SensorCtrlAstDebugOut8 = 60, - OtpMacroTest0 = 61, - SysrstCtrlBatDisable = 62, - SysrstCtrlKey0Out = 63, - SysrstCtrlKey1Out = 64, - SysrstCtrlKey2Out = 65, - SysrstCtrlPwrbOut = 66, - SysrstCtrlZ3Wakeup = 67, - End = 68, + RramMacroTdo = 52, + SensorCtrlAstDebugOut0 = 53, + SensorCtrlAstDebugOut1 = 54, + SensorCtrlAstDebugOut2 = 55, + SensorCtrlAstDebugOut3 = 56, + SensorCtrlAstDebugOut4 = 57, + SensorCtrlAstDebugOut5 = 58, + SensorCtrlAstDebugOut6 = 59, + SensorCtrlAstDebugOut7 = 60, + SensorCtrlAstDebugOut8 = 61, + OtpMacroTest0 = 62, + SysrstCtrlBatDisable = 63, + SysrstCtrlKey0Out = 64, + SysrstCtrlKey1Out = 65, + SysrstCtrlKey2Out = 66, + SysrstCtrlPwrbOut = 67, + SysrstCtrlZ3Wakeup = 68, + End = 69, } pub enum DirectPads: u32 [default = Self::End] { From 111a0608d8a8260429c36392e3e573e3a34bb7df Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Fri, 8 May 2026 18:04:05 +0200 Subject: [PATCH 03/41] [rram_ctrl,sec] Align countermeasures Align all security countermeasures in sec_cm_testplan, hjson and RTL Signed-off-by: Michael Gautschi --- hw/ip/rram_ctrl/rtl/rram_ctrl_rd.sv | 2 ++ hw/ip/rram_ctrl/rtl/rram_ctrl_wr.sv | 2 ++ hw/ip/rram_ctrl/rtl/rram_phy.sv | 3 +++ hw/ip/rram_ctrl/rtl/rram_phy_rd.sv | 3 +++ hw/ip/rram_ctrl/rtl/rram_phy_wr.sv | 5 +++-- 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/ip/rram_ctrl/rtl/rram_ctrl_rd.sv b/hw/ip/rram_ctrl/rtl/rram_ctrl_rd.sv index b0dde2849b6e4..880d9deff28d9 100644 --- a/hw/ip/rram_ctrl/rtl/rram_ctrl_rd.sv +++ b/hw/ip/rram_ctrl/rtl/rram_ctrl_rd.sv @@ -84,6 +84,7 @@ module rram_ctrl_rd import rram_ctrl_pkg::*; ( end end + // SEC_CM: CTR.REDUN prim_count #( .Width(CtrlMaxWordsW), .PossibleActions(prim_count_pkg::Clr | @@ -175,6 +176,7 @@ module rram_ctrl_rd import rram_ctrl_pkg::*; ( // if error, return "empty" data assign err_sel = rd_wr & |op_err_o; + // SEC_CM: MEM.ADDR_INFECTION // When there is no error, return the rram data and remove the addr-xor // When there is an error, return invalid data with the correct bus integrity logic [BusWidth-1:0] addr_xor; diff --git a/hw/ip/rram_ctrl/rtl/rram_ctrl_wr.sv b/hw/ip/rram_ctrl/rtl/rram_ctrl_wr.sv index 6886911854d8a..8444abae1d1d6 100644 --- a/hw/ip/rram_ctrl/rtl/rram_ctrl_wr.sv +++ b/hw/ip/rram_ctrl/rtl/rram_ctrl_wr.sv @@ -37,6 +37,7 @@ module rram_ctrl_wr import rram_ctrl_pkg::*; ( input logic rram_wr_intg_err_i ); + // SEC_CM: PHY_WR.FSM.SPARSE // Encoding generated at commit 61d4d1cd9e using Python 3.10.19 with: // $ ./util/design/sparse-fsm-encode.py --language=sv \ // --seed 718361455 --distance 4 --states 2 --bits 5 @@ -72,6 +73,7 @@ module rram_ctrl_wr import rram_ctrl_pkg::*; ( rram_ctrl_err_t op_err_q, op_err_d; + // SEC_CM: CTR.REDUN prim_count #( .Width(CtrlMaxWordsW), .PossibleActions(prim_count_pkg::Clr | diff --git a/hw/ip/rram_ctrl/rtl/rram_phy.sv b/hw/ip/rram_ctrl/rtl/rram_phy.sv index f84ce00ab4909..f95dc00dd71e4 100644 --- a/hw/ip/rram_ctrl/rtl/rram_phy.sv +++ b/hw/ip/rram_ctrl/rtl/rram_phy.sv @@ -393,6 +393,7 @@ module rram_phy ////////////////////////////// // Shared scrambling module // ////////////////////////////// + // SEC_CM: MEM.SCRAMBLE rram_scramble #( .RndCnstAddrKey(RndCnstAddrKey), .RndCnstDataKey(RndCnstDataKey), @@ -427,7 +428,9 @@ module rram_phy assign spurious_rd_done = ctrl_rd_done_o & host_rsp; assign spurious_rd_host_done = host_rd_done_o & ctrl_rsp; + // SEC_CM: PHY_RSP.CTRL.CONSISTENCY assign spurious_done_o = spurious_rd_done | spurious_rd_host_done; + // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY assign host_gnt_err_o = host_gnt & ((muxed_part_buf != RramPartData) | ~host_req_i); ///////////////////////////////////////////////// diff --git a/hw/ip/rram_ctrl/rtl/rram_phy_rd.sv b/hw/ip/rram_ctrl/rtl/rram_phy_rd.sv index 19e0e7a9e5f62..2b878f5a0a145 100644 --- a/hw/ip/rram_ctrl/rtl/rram_phy_rd.sv +++ b/hw/ip/rram_ctrl/rtl/rram_phy_rd.sv @@ -615,6 +615,7 @@ module rram_phy_rd // Output response selection // /////////////////////////////// logic [BusFullWidth-1:0] inv_data; + // SEC_CM: MEM.BUS.INTEGRITY tlul_data_integ_enc u_bus_intg ( .data_i ({BusWidth{1'b1}}), .data_intg_o(inv_data) @@ -674,12 +675,14 @@ module rram_phy_rd assign cmd_intg_err = data_valid_o ? (cmd_rsp_intg != meta_q_buf.cmd_intg) : 1'b0; + // SEC_CM: PHY_RD_RSP.CTRL.INTEGRITY // Control flow error if any of the above errors is set assign ctrl_err_o = valid_err | req_err | cmd_intg_err; // If any fifo shows an integrity error assign fifo_err_o = |{meta_fifo_err, rd_fifo_err, mask_fifo_err}; + // SEC_CM: PHY_RD_BUF.CTRL.INTEGRITY // Integrity error if a verify operation found a mismatch assign intg_err_o = |buf_intg_err; diff --git a/hw/ip/rram_ctrl/rtl/rram_phy_wr.sv b/hw/ip/rram_ctrl/rtl/rram_phy_wr.sv index c1c3c25c8df38..16e738e6732f1 100644 --- a/hw/ip/rram_ctrl/rtl/rram_phy_wr.sv +++ b/hw/ip/rram_ctrl/rtl/rram_phy_wr.sv @@ -55,10 +55,10 @@ module rram_phy_wr import rram_ctrl_pkg::*; ( output logic intg_err_o ); - // SEC_CM: CTR.REDUN logic word_cnt_en, word_cnt_clr; logic [WordW-1:0] word_cnt_q; + // SEC_CM: CTR.REDUN prim_count #( .Width(WordW), .PossibleActions(prim_count_pkg::Clr | @@ -156,11 +156,12 @@ module rram_phy_wr import rram_ctrl_pkg::*; ( logic last_q; - // SEC_CM: PHY_PROG.FSM.SPARSE + // SEC_CM: PHY_WR.FSM.SPARSE `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle) assign word_sel = addr_i[WordSelW-1:0]; + // SEC_CM: MEM.ADDR_INFECTION // address infection. It will be removed during read in u_tl_adapter_host or u_rram_ctrl_rd assign addr_xor = addr_xor_en_i ? {{(BusWidth-BusAddrW){1'b0}}, addr_i[BusAddrW-1:0]} : '0; // in case of data integrity issues, simply fill with 0 From 4c862ee2934914d002a7e5ba0d78b57f5aa6739a Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 29 Jul 2026 12:27:44 +0200 Subject: [PATCH 04/41] [earlgrey,rtl] route rram_test_analog to top This is an analog signal that is required for testing/trimming the RRAM. It has to be routed directly to the top without any buffers similar to otp_ext_volt or flash_test_volt. Signed-off-by: Michael Gautschi --- hw/ip/rram_macro/data/rram_macro.hjson | 8 ++ .../data/autogen/top_earlgrey.gen.hjson | 102 +++++++++++++++--- hw/top_earlgrey/data/top_earlgrey.hjson | 7 +- hw/top_earlgrey/doc/design/README.md | 29 ++--- .../ip_autogen/pinmux/doc/pinout_asic.md | 1 + .../ip_autogen/pinmux/doc/pinout_verilator.md | 1 + .../ip_autogen/pinmux/doc/targets.md | 4 +- .../rtl/autogen/chip_earlgrey_asic.sv | 23 +++- .../rtl/autogen/chip_earlgrey_cw340.sv | 3 +- .../rtl/autogen/chip_earlgrey_verilator.sv | 1 + .../rtl/autogen/earlgrey_pd_main.sv | 2 + hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 2 + .../rtl/autogen/top_earlgrey_pkg.sv | 29 ++--- hw/top_earlgrey/rtl/pad_orient_pkg.sv | 1 + hw/top_earlgrey/rtl/scan_role_pkg.sv | 1 + hw/top_earlgrey/templates/chiplevel.sv.tpl | 6 +- 16 files changed, 169 insertions(+), 51 deletions(-) diff --git a/hw/ip/rram_macro/data/rram_macro.hjson b/hw/ip/rram_macro/data/rram_macro.hjson index 617fc7c2db232..605025c10cc92 100644 --- a/hw/ip/rram_macro/data/rram_macro.hjson +++ b/hw/ip/rram_macro/data/rram_macro.hjson @@ -113,6 +113,14 @@ package: "" desc: "AST observability bus." } + // RRAM analog port - directly wired to top pad + { struct: "" + type: "io" + name: "rram_test_analog" + act: "none" + default: "'0" + package: "", + } ] regwidth: "32", diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index b642c9a054bf9..231a9412a660c 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -6847,6 +6847,20 @@ inst_name: rram_macro index: -1 } + { + name: rram_test_analog + struct: "" + type: io + act: none + width: 1 + default: "'0" + inst_name: rram_macro + package: "" + external: true + conn_type: false + index: -1 + top_signame: rram_test_analog + } { name: prim_tl struct: tl @@ -11274,6 +11288,7 @@ otp_macro.pwr_seq_h: "" otp_macro.ext_voltage_h: otp_ext_voltage_h otp_macro.otp_obs: otp_obs + rram_macro.rram_test_analog: rram_test_analog rstmgr.por_n: por_n rstmgr.resets: "" rstmgr.rst_en: "" @@ -13588,13 +13603,22 @@ idx: 8 port_type: inout } + { + name: RRAM_ANALOG + type: AnalogIn0 + bank: VCC + connection: manual + desc: RRAM analog test signal + idx: 9 + port_type: inout + } { name: SPI_HOST_D0 type: BidirStd bank: VIOA connection: direct desc: SPI host data - idx: 9 + idx: 10 port_type: inout } { @@ -13603,7 +13627,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 10 + idx: 11 port_type: inout } { @@ -13612,7 +13636,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 11 + idx: 12 port_type: inout } { @@ -13621,7 +13645,7 @@ bank: VIOA connection: direct desc: SPI host data - idx: 12 + idx: 13 port_type: inout } { @@ -13630,7 +13654,7 @@ bank: VIOA connection: direct desc: SPI host clock - idx: 13 + idx: 14 port_type: inout } { @@ -13639,7 +13663,7 @@ bank: VIOA connection: direct desc: SPI host chip select - idx: 14 + idx: 15 port_type: inout } { @@ -13648,7 +13672,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 15 + idx: 16 port_type: inout } { @@ -13657,7 +13681,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 16 + idx: 17 port_type: inout } { @@ -13666,7 +13690,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 17 + idx: 18 port_type: inout } { @@ -13675,7 +13699,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 18 + idx: 19 port_type: inout } { @@ -13684,7 +13708,7 @@ bank: VIOA connection: direct desc: SPI device clock - idx: 19 + idx: 20 port_type: inout } { @@ -13693,7 +13717,7 @@ bank: VIOA connection: direct desc: SPI device chip select - idx: 20 + idx: 21 port_type: inout } { @@ -14089,7 +14113,7 @@ bank: VCC connection: direct desc: Dedicated sysrst_ctrl output (ec_rst_l) - idx: 21 + idx: 22 port_type: inout } { @@ -14098,7 +14122,7 @@ bank: VCC connection: direct desc: Dedicated sysrst_ctrl output (flash_wp_l)) - idx: 22 + idx: 23 port_type: inout } { @@ -15702,7 +15726,7 @@ inouts: 12 inputs: 2 outputs: 2 - pads: 23 + pads: 24 } muxed: { @@ -15749,6 +15773,10 @@ { signal: OTP_EXT_VOLT } + rram_macro.rram_test_analog: + { + signal: RRAM_ANALOG + } sensor_ctrl.ast_alert: { signal: ast_alert @@ -15907,6 +15935,11 @@ unused: true tie_value: "" } + rram_macro.rram_test_analog: + { + unused: true + tie_value: "" + } sensor_ctrl.ast_alert: { signal: ast_alert @@ -16118,6 +16151,10 @@ { unused: true } + rram_macro.rram_test_analog: + { + unused: true + } flash_ctrl.flash_test_mode_a: { unused: true @@ -16146,6 +16183,7 @@ CC2 FLASH_TEST_VOLT OTP_EXT_VOLT + RRAM_ANALOG FLASH_TEST_MODE0 FLASH_TEST_MODE1 USB_P @@ -25476,6 +25514,20 @@ inst_name: rram_macro index: -1 } + { + name: rram_test_analog + struct: "" + type: io + act: none + width: 1 + default: "'0" + inst_name: rram_macro + package: "" + external: true + conn_type: false + index: -1 + top_signame: rram_test_analog + } { name: prim_tl struct: tl @@ -31501,6 +31553,26 @@ index: -1 netname: otp_obs } + { + package: "" + struct: "" + domain: Main + inter_pd: false + signame: rram_test_analog_io + signame_chip: + { + asic: RRAM_ANALOG + verilator: "" + cw340: "'0" + } + width: 1 + type: io + default: "'0" + direction: inout + conn_type: false + index: -1 + netname: rram_test_analog + } { package: "" struct: logic diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index a22a40b65ecd1..67d8908d8b56e 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1438,6 +1438,7 @@ 'otp_macro.pwr_seq_h' : '', 'otp_macro.ext_voltage_h' : 'otp_ext_voltage_h', 'otp_macro.otp_obs' : 'otp_obs', + 'rram_macro.rram_test_analog' : 'rram_test_analog', 'rstmgr.por_n' : 'por_n', 'rstmgr.resets' : '', 'rstmgr.rst_en' : '', @@ -1523,6 +1524,7 @@ { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, { name: 'OTP_EXT_VOLT' , type: 'AnalogIn1', bank: 'VCC' , connection: 'manual', desc: 'OTP external voltage input'}, + { name: 'RRAM_ANALOG' , type: 'AnalogIn0', bank: 'VCC' , connection: 'manual', desc: 'RRAM analog test signal'}, // Dedicated IOs { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, @@ -1712,6 +1714,7 @@ 'flash_ctrl.flash_test_mode_a' : { signal: "{FLASH_TEST_MODE1, FLASH_TEST_MODE0}"}, 'flash_ctrl.flash_test_voltage_h' : { signal: 'FLASH_TEST_VOLT' }, 'otp_macro.ext_voltage_h' : { signal: 'OTP_EXT_VOLT' }, + 'rram_macro.rram_test_analog' : { signal: 'RRAM_ANALOG' }, 'sensor_ctrl.ast_alert' : { signal: 'ast_alert' }, 'sensor_ctrl.ast_status' : { signal: 'ast_pwst.io_pok' }, 'usbdev.usb_rx_d' : { signal: 'usb_rx_d' }, @@ -1806,6 +1809,7 @@ 'flash_ctrl.flash_test_mode_a' : { unused: true, tie_value: "" }, 'flash_ctrl.flash_test_voltage_h' : { unused: true, tie_value: "" }, 'otp_macro.ext_voltage_h' : { unused: true, tie_value: "" }, + 'rram_macro.rram_test_analog' : { unused: true, tie_value: "" }, 'sensor_ctrl.ast_alert' : { signal: 'ast_alert' }, 'sensor_ctrl.ast_status' : { signal: 'ast_pwst.io_pok' }, 'sensor_ctrl.manual_pad_attr' : { unused: true }, @@ -1875,6 +1879,7 @@ 'sensor_ctrl.ast_status' : { signal: 'ast_pwst.io_pok' }, 'entropy_src.rng_fips' : { unused: true }, 'otp_macro.ext_voltage_h' : { unused: true }, + 'rram_macro.rram_test_analog' : { unused: true }, 'flash_ctrl.flash_test_mode_a' : { unused: true }, 'flash_ctrl.flash_test_voltage_h' : { unused: true }, 'flash_ctrl.flash_power_down_h' : { unused: true }, @@ -1886,7 +1891,7 @@ remove_ports: [], remove_pads: [ 'CC1', 'CC2', - 'FLASH_TEST_VOLT', 'OTP_EXT_VOLT' + 'FLASH_TEST_VOLT', 'OTP_EXT_VOLT', 'RRAM_ANALOG', 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', 'USB_P', 'USB_N' ], diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index 796c8cbecaf50..b2e4f0f8151c1 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -416,18 +416,19 @@ The first EDN instance, `u_edn0` is intended to be configured to deliver entropy | 6 | FLASH_TEST_MODE0 | VCC | InputStd | manual | Flash test mode signal | | 7 | FLASH_TEST_MODE1 | VCC | InputStd | manual | Flash test mode signal | | 8 | OTP_EXT_VOLT | VCC | AnalogIn1 | manual | OTP external voltage input | -| 9 | SPI_HOST_D0 | VIOA | BidirStd | direct | SPI host data | -| 10 | SPI_HOST_D1 | VIOA | BidirStd | direct | SPI host data | -| 11 | SPI_HOST_D2 | VIOA | BidirStd | direct | SPI host data | -| 12 | SPI_HOST_D3 | VIOA | BidirStd | direct | SPI host data | -| 13 | SPI_HOST_CLK | VIOA | BidirStd | direct | SPI host clock | -| 14 | SPI_HOST_CS_L | VIOA | BidirStd | direct | SPI host chip select | -| 15 | SPI_DEV_D0 | VIOA | BidirStd | direct | SPI device data | -| 16 | SPI_DEV_D1 | VIOA | BidirStd | direct | SPI device data | -| 17 | SPI_DEV_D2 | VIOA | BidirStd | direct | SPI device data | -| 18 | SPI_DEV_D3 | VIOA | BidirStd | direct | SPI device data | -| 19 | SPI_DEV_CLK | VIOA | InputStd | direct | SPI device clock | -| 20 | SPI_DEV_CS_L | VIOA | InputStd | direct | SPI device chip select | +| 9 | RRAM_ANALOG | VCC | AnalogIn0 | manual | RRAM analog test signal | +| 10 | SPI_HOST_D0 | VIOA | BidirStd | direct | SPI host data | +| 11 | SPI_HOST_D1 | VIOA | BidirStd | direct | SPI host data | +| 12 | SPI_HOST_D2 | VIOA | BidirStd | direct | SPI host data | +| 13 | SPI_HOST_D3 | VIOA | BidirStd | direct | SPI host data | +| 14 | SPI_HOST_CLK | VIOA | BidirStd | direct | SPI host clock | +| 15 | SPI_HOST_CS_L | VIOA | BidirStd | direct | SPI host chip select | +| 16 | SPI_DEV_D0 | VIOA | BidirStd | direct | SPI device data | +| 17 | SPI_DEV_D1 | VIOA | BidirStd | direct | SPI device data | +| 18 | SPI_DEV_D2 | VIOA | BidirStd | direct | SPI device data | +| 19 | SPI_DEV_D3 | VIOA | BidirStd | direct | SPI device data | +| 20 | SPI_DEV_CLK | VIOA | InputStd | direct | SPI device clock | +| 21 | SPI_DEV_CS_L | VIOA | InputStd | direct | SPI device chip select | | 0 | IOA0 | VIOA | BidirStd | muxed | Muxed IO pad | | 1 | IOA1 | VIOA | BidirStd | muxed | Muxed IO pad | | 2 | IOA2 | VIOA | BidirStd | muxed | Muxed IO pad | @@ -471,8 +472,8 @@ The first EDN instance, `u_edn0` is intended to be configured to deliver entropy | 40 | IOR5 | VCC | BidirStd | muxed | Muxed IO pad | | 41 | IOR6 | VCC | BidirStd | muxed | Muxed IO pad | | 42 | IOR7 | VCC | BidirStd | muxed | Muxed IO pad | -| 21 | IOR8 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (ec_rst_l) | -| 22 | IOR9 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (flash_wp_l)) | +| 22 | IOR8 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (ec_rst_l) | +| 23 | IOR9 | VCC | BidirOd | direct | Dedicated sysrst_ctrl output (flash_wp_l)) | | 43 | IOR10 | VCC | BidirOd | muxed | Muxed IO pad | | 44 | IOR11 | VCC | BidirOd | muxed | Muxed IO pad | | 45 | IOR12 | VCC | BidirOd | muxed | Muxed IO pad | diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md index fed97f11c22a4..d8af892cc3a24 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md @@ -17,6 +17,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

FLASH_TEST_MODE0

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| |

FLASH_TEST_MODE1

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| |

OTP_EXT_VOLT

|

AnalogIn1

|

VCC

|

manual

|

-

|

- / -

|

OTP external voltage input

| +|

RRAM_ANALOG

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

RRAM analog test signal

| |

SPI_HOST_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| |

SPI_HOST_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| |

SPI_HOST_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md index 1c3a77c33fb5c..57aa673d6ea34 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_verilator.md @@ -17,6 +17,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

FLASH_TEST_MODE0

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| |

FLASH_TEST_MODE1

|

InputStd

|

VCC

|

manual

|

-

|

- / -

|

Flash test mode signal

| |

OTP_EXT_VOLT

|

AnalogIn1

|

VCC

|

manual

|

-

|

- / -

|

OTP external voltage input

| +|

RRAM_ANALOG

|

AnalogIn0

|

VCC

|

manual

|

-

|

- / -

|

RRAM analog test signal

| |

SPI_HOST_D0

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| |

SPI_HOST_D1

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| |

SPI_HOST_D2

|

BidirStd

|

VIOA

|

direct

|

-

|

- / -

|

SPI host data

| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md index eabe947d5a321..72b146b86fca5 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/targets.md @@ -6,6 +6,6 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ --> | Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables | |:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:-------------------------------------:| -| ASIC | 4 | 47 | 14 | 9 | 70 | [Pinout Table](./pinout_asic.md) | -| VERILATOR | 4 | 47 | 14 | 9 | 70 | [Pinout Table](./pinout_verilator.md) | +| ASIC | 4 | 47 | 14 | 10 | 71 | [Pinout Table](./pinout_asic.md) | +| VERILATOR | 4 | 47 | 14 | 10 | 71 | [Pinout Table](./pinout_verilator.md) | | CW340 | 4 | 47 | 14 | 13 | 74 | [Pinout Table](./pinout_cw340.md) | diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index f514cb6884aaf..c5f7ac9000bf0 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -23,6 +23,7 @@ module chip_earlgrey_asic #( inout FLASH_TEST_MODE0, // Manual Pad inout FLASH_TEST_MODE1, // Manual Pad inout OTP_EXT_VOLT, // Manual Pad + inout RRAM_ANALOG, // Manual Pad inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd @@ -275,7 +276,7 @@ module chip_earlgrey_asic #( logic [3:0] mux_iob_sel; logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; - logic [22:0] dio_in_raw; + logic [23:0] dio_in_raw; logic unused_mio_in_raw; logic unused_dio_in_raw; @@ -292,6 +293,7 @@ module chip_earlgrey_asic #( logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0; logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1; logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt; + logic manual_in_rram_analog, manual_out_rram_analog, manual_oe_rram_analog; pad_attr_t manual_attr_por_n; pad_attr_t manual_attr_usb_p; @@ -302,6 +304,7 @@ module chip_earlgrey_asic #( pad_attr_t manual_attr_flash_test_mode0; pad_attr_t manual_attr_flash_test_mode1; pad_attr_t manual_attr_otp_ext_volt; + pad_attr_t manual_attr_rram_analog; ////////////////////// // Padring Instance // @@ -314,7 +317,7 @@ module chip_earlgrey_asic #( padring #( // Padring specific counts may differ from pinmux config due // to custom, stubbed or added pads. - .NDioPads(23), + .NDioPads(24), .NMioPads(47), .PhysicalPads(1), .NIoBanks(int'(IoBankCount)), @@ -333,6 +336,7 @@ module chip_earlgrey_asic #( scan_role_pkg::DioPadSpiHostD2ScanRole, scan_role_pkg::DioPadSpiHostD1ScanRole, scan_role_pkg::DioPadSpiHostD0ScanRole, + scan_role_pkg::DioPadRramAnalogScanRole, scan_role_pkg::DioPadOtpExtVoltScanRole, scan_role_pkg::DioPadFlashTestMode1ScanRole, scan_role_pkg::DioPadFlashTestMode0ScanRole, @@ -407,6 +411,7 @@ module chip_earlgrey_asic #( pad_orient_pkg::DioPadSpiHostD2PadOrient, pad_orient_pkg::DioPadSpiHostD1PadOrient, pad_orient_pkg::DioPadSpiHostD0PadOrient, + pad_orient_pkg::DioPadRramAnalogPadOrient, pad_orient_pkg::DioPadOtpExtVoltPadOrient, pad_orient_pkg::DioPadFlashTestMode1PadOrient, pad_orient_pkg::DioPadFlashTestMode0PadOrient, @@ -481,6 +486,7 @@ module chip_earlgrey_asic #( IoBankVioa, // SPI_HOST_D2 IoBankVioa, // SPI_HOST_D1 IoBankVioa, // SPI_HOST_D0 + IoBankVcc, // RRAM_ANALOG IoBankVcc, // OTP_EXT_VOLT IoBankVcc, // FLASH_TEST_MODE1 IoBankVcc, // FLASH_TEST_MODE0 @@ -555,6 +561,7 @@ module chip_earlgrey_asic #( BidirStd, // SPI_HOST_D2 BidirStd, // SPI_HOST_D1 BidirStd, // SPI_HOST_D0 + AnalogIn0, // RRAM_ANALOG AnalogIn1, // OTP_EXT_VOLT InputStd, // FLASH_TEST_MODE1 InputStd, // FLASH_TEST_MODE0 @@ -638,6 +645,7 @@ module chip_earlgrey_asic #( SPI_HOST_D2, SPI_HOST_D1, SPI_HOST_D0, + RRAM_ANALOG, OTP_EXT_VOLT, FLASH_TEST_MODE1, FLASH_TEST_MODE0, @@ -731,6 +739,7 @@ module chip_earlgrey_asic #( dio_in[DioSpiHost0Sd2], dio_in[DioSpiHost0Sd1], dio_in[DioSpiHost0Sd0], + manual_in_rram_analog, manual_in_otp_ext_volt, manual_in_flash_test_mode1, manual_in_flash_test_mode0, @@ -756,6 +765,7 @@ module chip_earlgrey_asic #( dio_out[DioSpiHost0Sd2], dio_out[DioSpiHost0Sd1], dio_out[DioSpiHost0Sd0], + manual_out_rram_analog, manual_out_otp_ext_volt, manual_out_flash_test_mode1, manual_out_flash_test_mode0, @@ -781,6 +791,7 @@ module chip_earlgrey_asic #( dio_oe[DioSpiHost0Sd2], dio_oe[DioSpiHost0Sd1], dio_oe[DioSpiHost0Sd0], + manual_oe_rram_analog, manual_oe_otp_ext_volt, manual_oe_flash_test_mode1, manual_oe_flash_test_mode0, @@ -806,6 +817,7 @@ module chip_earlgrey_asic #( dio_attr[DioSpiHost0Sd2], dio_attr[DioSpiHost0Sd1], dio_attr[DioSpiHost0Sd0], + manual_attr_rram_analog, manual_attr_otp_ext_volt, manual_attr_flash_test_mode1, manual_attr_flash_test_mode0, @@ -1148,6 +1160,8 @@ module chip_earlgrey_asic #( assign manual_oe_flash_test_volt = 1'b0; assign manual_out_otp_ext_volt = 1'b0; assign manual_oe_otp_ext_volt = 1'b0; + assign manual_out_rram_analog = 1'b0; + assign manual_oe_rram_analog = 1'b0; // Enable schmitt trigger on POR for better signal integrity. assign manual_attr_por_n = '{schmitt_en: 1'b1, pull_en: 1'b1, pull_select: 1'b1, default: '0}; @@ -1163,6 +1177,7 @@ module chip_earlgrey_asic #( // These pad attributes are currently tied off permanently (these are supply pads). assign manual_attr_flash_test_volt = '0; assign manual_attr_otp_ext_volt = '0; + assign manual_attr_rram_analog = '0; logic unused_manual_sigs; assign unused_manual_sigs = ^{ @@ -1171,7 +1186,8 @@ module chip_earlgrey_asic #( manual_in_flash_test_volt, manual_in_flash_test_mode0, manual_in_flash_test_mode1, - manual_in_otp_ext_volt + manual_in_otp_ext_volt, + manual_in_rram_analog }; /////////////////////////////// @@ -1315,6 +1331,7 @@ module chip_earlgrey_asic #( .otp_macro_pwr_seq_h_i (otp_macro_pwr_seq_h ), .otp_ext_voltage_h_io (OTP_EXT_VOLT ), .otp_obs_o (otp_obs ), + .rram_test_analog_io (RRAM_ANALOG ), .por_n_i (por_n ), .rstmgr_resets_o (rstmgr_resets ), .rstmgr_rst_en_o ( ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv index 41f28054a32fa..69cbb8b321564 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv @@ -327,7 +327,7 @@ module chip_earlgrey_cw340 #( ///////////////////////// // Only signals going to non-custom pads need to be tied off. - logic [69:0] unused_sig; + logic [70:0] unused_sig; ////////////////////// // Padring Instance // ////////////////////// @@ -1233,6 +1233,7 @@ module chip_earlgrey_cw340 #( .otp_macro_pwr_seq_h_i (otp_macro_pwr_seq_h ), .otp_ext_voltage_h_io ('0 ), .otp_obs_o (otp_obs ), + .rram_test_analog_io ('0 ), .por_n_i (por_n ), .rstmgr_resets_o (rstmgr_resets ), .rstmgr_rst_en_o ( ), diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv index 6069cd8f8028e..2d7c9b887003a 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_verilator.sv @@ -683,6 +683,7 @@ module chip_earlgrey_verilator ( .otp_macro_pwr_seq_h_i (otp_macro_pwr_seq_h ), .otp_ext_voltage_h_io ( ), .otp_obs_o (otp_obs ), + .rram_test_analog_io ( ), .por_n_i (por_n ), .rstmgr_resets_o (rstmgr_resets ), .rstmgr_rst_en_o ( ), diff --git a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv index 39c5785ba61e5..0b327fd22aa3f 100644 --- a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv +++ b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv @@ -230,6 +230,7 @@ module earlgrey_pd_main #( input otp_macro_pkg::pwr_seq_t otp_macro_pwr_seq_h_i, inout otp_ext_voltage_h_io, output logic [7:0] otp_obs_o, + inout rram_test_analog_io, input logic [31:0] fpga_info_i, output logic sck_monitor_o, input logic usbdev_usb_rx_d_i, @@ -2105,6 +2106,7 @@ module earlgrey_pd_main #( .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), .obs_ctrl_i(ast_obs_ctrl), .rram_obs_o(), + .rram_test_analog_io(rram_test_analog_io), .prim_tl_i(rram_macro_prim_tl_req), .prim_tl_o(rram_macro_prim_tl_rsp) ); diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 4eafff95ed068..fdf78734ef5a9 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -234,6 +234,7 @@ module top_earlgrey #( input otp_macro_pkg::pwr_seq_t otp_macro_pwr_seq_h_i, inout otp_ext_voltage_h_io, output logic [7:0] otp_obs_o, + inout rram_test_analog_io, input logic [1:0] por_n_i, output rstmgr_pkg::rstmgr_out_t rstmgr_resets_o, output rstmgr_pkg::rstmgr_rst_en_t rstmgr_rst_en_o, @@ -591,6 +592,7 @@ module top_earlgrey #( .otp_macro_pwr_seq_h_i, .otp_ext_voltage_h_io, .otp_obs_o, + .rram_test_analog_io, .fpga_info_i, .sck_monitor_o, .usbdev_usb_rx_d_i, diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index f210cc6dfc736..5e0e4d1e8e18e 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -1092,20 +1092,21 @@ package top_earlgrey_pkg; DioPadFlashTestMode0 = 6, DioPadFlashTestMode1 = 7, DioPadOtpExtVolt = 8, - DioPadSpiHostD0 = 9, - DioPadSpiHostD1 = 10, - DioPadSpiHostD2 = 11, - DioPadSpiHostD3 = 12, - DioPadSpiHostClk = 13, - DioPadSpiHostCsL = 14, - DioPadSpiDevD0 = 15, - DioPadSpiDevD1 = 16, - DioPadSpiDevD2 = 17, - DioPadSpiDevD3 = 18, - DioPadSpiDevClk = 19, - DioPadSpiDevCsL = 20, - DioPadIor8 = 21, - DioPadIor9 = 22, + DioPadRramAnalog = 9, + DioPadSpiHostD0 = 10, + DioPadSpiHostD1 = 11, + DioPadSpiHostD2 = 12, + DioPadSpiHostD3 = 13, + DioPadSpiHostClk = 14, + DioPadSpiHostCsL = 15, + DioPadSpiDevD0 = 16, + DioPadSpiDevD1 = 17, + DioPadSpiDevD2 = 18, + DioPadSpiDevD3 = 19, + DioPadSpiDevClk = 20, + DioPadSpiDevCsL = 21, + DioPadIor8 = 22, + DioPadIor9 = 23, DioPadCount } dio_pad_e; diff --git a/hw/top_earlgrey/rtl/pad_orient_pkg.sv b/hw/top_earlgrey/rtl/pad_orient_pkg.sv index aba9efed0dd11..eb77b46bc4358 100644 --- a/hw/top_earlgrey/rtl/pad_orient_pkg.sv +++ b/hw/top_earlgrey/rtl/pad_orient_pkg.sv @@ -31,6 +31,7 @@ package pad_orient_pkg; parameter pad_orient_e DioPadFlashTestMode0PadOrient = OrientH; parameter pad_orient_e DioPadFlashTestMode1PadOrient = OrientH; parameter pad_orient_e DioPadOtpExtVoltPadOrient = OrientH; + parameter pad_orient_e DioPadRramAnalogPadOrient = OrientH; parameter pad_orient_e DioPadIor8PadOrient = OrientV; parameter pad_orient_e DioPadIor9PadOrient = OrientV; parameter pad_orient_e MioPadIoa0PadOrient = OrientH; diff --git a/hw/top_earlgrey/rtl/scan_role_pkg.sv b/hw/top_earlgrey/rtl/scan_role_pkg.sv index 0e54583580c2c..dc1e2d646cc4f 100644 --- a/hw/top_earlgrey/rtl/scan_role_pkg.sv +++ b/hw/top_earlgrey/rtl/scan_role_pkg.sv @@ -31,6 +31,7 @@ package scan_role_pkg; parameter scan_role_e DioPadFlashTestMode0ScanRole = NoScan; parameter scan_role_e DioPadFlashTestMode1ScanRole = NoScan; parameter scan_role_e DioPadOtpExtVoltScanRole = NoScan; + parameter scan_role_e DioPadRramAnalogScanRole = NoScan; parameter scan_role_e DioPadIor8ScanRole = NoScan; parameter scan_role_e DioPadIor9ScanRole = NoScan; parameter scan_role_e MioPadIoa0ScanRole = NoScan; diff --git a/hw/top_earlgrey/templates/chiplevel.sv.tpl b/hw/top_earlgrey/templates/chiplevel.sv.tpl index 65dd67c5d002a..e14e683071918 100644 --- a/hw/top_earlgrey/templates/chiplevel.sv.tpl +++ b/hw/top_earlgrey/templates/chiplevel.sv.tpl @@ -1027,6 +1027,8 @@ module chip_${top["name"]}_${target["name"]} #( assign manual_oe_flash_test_volt = 1'b0; assign manual_out_otp_ext_volt = 1'b0; assign manual_oe_otp_ext_volt = 1'b0; + assign manual_out_rram_analog = 1'b0; + assign manual_oe_rram_analog = 1'b0; // Enable schmitt trigger on POR for better signal integrity. assign manual_attr_por_n = '{schmitt_en: 1'b1, pull_en: 1'b1, pull_select: 1'b1, default: '0}; @@ -1042,6 +1044,7 @@ module chip_${top["name"]}_${target["name"]} #( // These pad attributes are currently tied off permanently (these are supply pads). assign manual_attr_flash_test_volt = '0; assign manual_attr_otp_ext_volt = '0; + assign manual_attr_rram_analog = '0; logic unused_manual_sigs; assign unused_manual_sigs = ^{ @@ -1050,7 +1053,8 @@ module chip_${top["name"]}_${target["name"]} #( manual_in_flash_test_volt, manual_in_flash_test_mode0, manual_in_flash_test_mode1, - manual_in_otp_ext_volt + manual_in_otp_ext_volt, + manual_in_rram_analog }; /////////////////////////////// From a0dafca9df37f43cfcba75027a812ca075d411c0 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 23 Jul 2026 17:18:45 +0200 Subject: [PATCH 05/41] [bkdr_loader,rram] support RRAM in backdoor loader This allows to preload RRAM images and write selected pages through the backdoor. Signed-off-by: Michael Gautschi --- hw/ip/bkdr_loader/data/bkdr_loader.hjson | 2 +- hw/ip/bkdr_loader/doc/registers.md | 16 + hw/ip/bkdr_loader/rtl/bkdr_loader.svh | 4 + hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv | 6 + hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv | 184 ++--- .../rtl/bkdr_loader_regs_reg_top.sv | 646 ++++++++++++------ rules/opentitan/fpga.bzl | 1 + .../python/util/hyperdebug.py | 3 +- 8 files changed, 578 insertions(+), 284 deletions(-) diff --git a/hw/ip/bkdr_loader/data/bkdr_loader.hjson b/hw/ip/bkdr_loader/data/bkdr_loader.hjson index 5044db48d7269..ddb67cac225c3 100644 --- a/hw/ip/bkdr_loader/data/bkdr_loader.hjson +++ b/hw/ip/bkdr_loader/data/bkdr_loader.hjson @@ -41,7 +41,7 @@ { name: "NumBkdrTgts", desc: "Number of RAM Targets", type: "int unsigned", - default: "13", + default: "15", } { name: "MaxWordWidthDiv32", desc: "Max bit width of a word / 32", diff --git a/hw/ip/bkdr_loader/doc/registers.md b/hw/ip/bkdr_loader/doc/registers.md index 14a8f6a310c76..8774067b21885 100644 --- a/hw/ip/bkdr_loader/doc/registers.md +++ b/hw/ip/bkdr_loader/doc/registers.md @@ -23,6 +23,8 @@ | bkdr_loader.[`TARGET_INFO_10`](#target_info) | 0x128 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | | bkdr_loader.[`TARGET_INFO_11`](#target_info) | 0x12c | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | | bkdr_loader.[`TARGET_INFO_12`](#target_info) | 0x130 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | +| bkdr_loader.[`TARGET_INFO_13`](#target_info) | 0x134 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | +| bkdr_loader.[`TARGET_INFO_14`](#target_info) | 0x138 | 4 | ASCII 4-character string values (big endian) identifying each bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_0`](#width_info) | 0x200 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_1`](#width_info) | 0x204 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_2`](#width_info) | 0x208 | 4 | The SRAM word width of a given bkdr target memory. | @@ -36,6 +38,8 @@ | bkdr_loader.[`WIDTH_INFO_10`](#width_info) | 0x228 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_11`](#width_info) | 0x22c | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`WIDTH_INFO_12`](#width_info) | 0x230 | 4 | The SRAM word width of a given bkdr target memory. | +| bkdr_loader.[`WIDTH_INFO_13`](#width_info) | 0x234 | 4 | The SRAM word width of a given bkdr target memory. | +| bkdr_loader.[`WIDTH_INFO_14`](#width_info) | 0x238 | 4 | The SRAM word width of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_0`](#depth_info) | 0x300 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_1`](#depth_info) | 0x304 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_2`](#depth_info) | 0x308 | 4 | The number of SRAM words of a given bkdr target memory. | @@ -49,6 +53,8 @@ | bkdr_loader.[`DEPTH_INFO_10`](#depth_info) | 0x328 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_11`](#depth_info) | 0x32c | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`DEPTH_INFO_12`](#depth_info) | 0x330 | 4 | The number of SRAM words of a given bkdr target memory. | +| bkdr_loader.[`DEPTH_INFO_13`](#depth_info) | 0x334 | 4 | The number of SRAM words of a given bkdr target memory. | +| bkdr_loader.[`DEPTH_INFO_14`](#depth_info) | 0x338 | 4 | The number of SRAM words of a given bkdr target memory. | | bkdr_loader.[`READ_DATA_0`](#read_data) | 0x400 | 4 | Value to be read from the target memory at the current `INDEX`. If | | bkdr_loader.[`READ_DATA_1`](#read_data) | 0x404 | 4 | Value to be read from the target memory at the current `INDEX`. If | | bkdr_loader.[`READ_DATA_2`](#read_data) | 0x408 | 4 | Value to be read from the target memory at the current `INDEX`. If | @@ -79,6 +85,8 @@ | bkdr_loader.[`HASH_LAST_LOADED_10`](#hash_last_loaded) | 0x728 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | | bkdr_loader.[`HASH_LAST_LOADED_11`](#hash_last_loaded) | 0x72c | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | | bkdr_loader.[`HASH_LAST_LOADED_12`](#hash_last_loaded) | 0x730 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | +| bkdr_loader.[`HASH_LAST_LOADED_13`](#hash_last_loaded) | 0x734 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | +| bkdr_loader.[`HASH_LAST_LOADED_14`](#hash_last_loaded) | 0x738 | 4 | Non-reset register to store a hash digest of the memory file loaded most recently. | ## STATUS Status register @@ -228,6 +236,8 @@ ASCII 4-character string values (big endian) identifying each bkdr target memory | TARGET_INFO_10 | 0x128 | | TARGET_INFO_11 | 0x12c | | TARGET_INFO_12 | 0x130 | +| TARGET_INFO_13 | 0x134 | +| TARGET_INFO_14 | 0x138 | ### Fields @@ -262,6 +272,8 @@ The SRAM word width of a given bkdr target memory. | WIDTH_INFO_10 | 0x228 | | WIDTH_INFO_11 | 0x22c | | WIDTH_INFO_12 | 0x230 | +| WIDTH_INFO_13 | 0x234 | +| WIDTH_INFO_14 | 0x238 | ### Fields @@ -296,6 +308,8 @@ The number of SRAM words of a given bkdr target memory. | DEPTH_INFO_10 | 0x328 | | DEPTH_INFO_11 | 0x32c | | DEPTH_INFO_12 | 0x330 | +| DEPTH_INFO_13 | 0x334 | +| DEPTH_INFO_14 | 0x338 | ### Fields @@ -418,6 +432,8 @@ the same memory file is already loaded and a preload can be skipped. | HASH_LAST_LOADED_10 | 0x728 | | HASH_LAST_LOADED_11 | 0x72c | | HASH_LAST_LOADED_12 | 0x730 | +| HASH_LAST_LOADED_13 | 0x734 | +| HASH_LAST_LOADED_14 | 0x738 | ### Fields diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader.svh b/hw/ip/bkdr_loader/rtl/bkdr_loader.svh index c4b9ceb755a30..47dc1853ddec7 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader.svh +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader.svh @@ -7,6 +7,8 @@ `define BKDR_LOADER_CONNECT_REQS \ assign top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrAon]; \ + assign top_earlgrey.earlgrey_pd_main.u_rram_macro.u_info_array.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRramInfo]; \ + assign top_earlgrey.earlgrey_pd_main.u_rram_macro.u_data_array.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRramData]; \ assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I2]; \ assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I1]; \ assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I0]; \ @@ -22,6 +24,8 @@ `define BKDR_LOADER_CONNECT_RSPS \ assign bkdr_rsp[bkdr_loader_pkg::BkdrAon] = top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrRramInfo] = top_earlgrey.earlgrey_pd_main.u_rram_macro.u_info_array.bkdr_rsp; \ + assign bkdr_rsp[bkdr_loader_pkg::BkdrRramData] = top_earlgrey.earlgrey_pd_main.u_rram_macro.u_data_array.bkdr_rsp; \ assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I2] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \ assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \ assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \ diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv b/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv index 5fe98ae24f35b..c65e8c689e3a3 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader_pkg.sv @@ -33,6 +33,8 @@ package bkdr_loader_pkg; // Target indices typedef enum logic [TargetIdxWidth-1:0] { + BkdrRramInfo = 'd14, + BkdrRramData = 'd13, BkdrAon = 'd12, BkdrFlashB1I2 = 'd11, BkdrFlashB1I1 = 'd10, @@ -50,6 +52,8 @@ package bkdr_loader_pkg; // Valid targets localparam bkdr_idx_e BkdrValidTgts [NumBkdrTgts] = { + BkdrRramInfo, + BkdrRramData, BkdrAon, BkdrFlashB1I2, BkdrFlashB1I1, @@ -67,6 +71,8 @@ package bkdr_loader_pkg; // Strings describing the targets (max, 4 chars) localparam reg_t [NumBkdrTgts-1:0] BkdrTargets = { + "RRIN", + "RRDA", "AON ", "FI12", "FI11", diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv b/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv index 6bed6fc501f70..22e432f5c2f57 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader_reg_pkg.sv @@ -7,7 +7,7 @@ package bkdr_loader_reg_pkg; // Param list - parameter int unsigned NumBkdrTgts = 13; + parameter int unsigned NumBkdrTgts = 15; parameter int unsigned MaxWordWidthDiv32 = 8; parameter int unsigned TargetIdxWidth = 8; @@ -15,7 +15,7 @@ package bkdr_loader_reg_pkg; parameter int RegsAw = 11; // Number of registers for every interface - parameter int NumRegsRegs = 74; + parameter int NumRegsRegs = 82; /////////////////////////////////////////////// // Typedefs for registers for regs interface // @@ -119,26 +119,26 @@ package bkdr_loader_reg_pkg; // Register -> HW type for regs interface typedef struct packed { - bkdr_loader_reg2hw_control_reg_t control; // [1038:1022] - bkdr_loader_reg2hw_mission_mode_switch_delay_reg_t mission_mode_switch_delay; // [1021:990] - bkdr_loader_reg2hw_read_data_mreg_t [7:0] read_data; // [989:726] - bkdr_loader_reg2hw_write_data_mreg_t [7:0] write_data; // [725:462] - bkdr_loader_reg2hw_index_reg_t index; // [461:429] - bkdr_loader_reg2hw_hash_last_loaded_mreg_t [12:0] hash_last_loaded; // [428:0] + bkdr_loader_reg2hw_control_reg_t control; // [1104:1088] + bkdr_loader_reg2hw_mission_mode_switch_delay_reg_t mission_mode_switch_delay; // [1087:1056] + bkdr_loader_reg2hw_read_data_mreg_t [7:0] read_data; // [1055:792] + bkdr_loader_reg2hw_write_data_mreg_t [7:0] write_data; // [791:528] + bkdr_loader_reg2hw_index_reg_t index; // [527:495] + bkdr_loader_reg2hw_hash_last_loaded_mreg_t [14:0] hash_last_loaded; // [494:0] } bkdr_loader_regs_reg2hw_t; // HW -> register type for regs interface typedef struct packed { - bkdr_loader_hw2reg_status_reg_t status; // [2020:2019] - bkdr_loader_hw2reg_control_reg_t control; // [2018:2017] - bkdr_loader_hw2reg_num_bkdr_targets_reg_t num_bkdr_targets; // [2016:1985] - bkdr_loader_hw2reg_usr_access_timestamp_reg_t usr_access_timestamp; // [1984:1953] - bkdr_loader_hw2reg_target_info_mreg_t [12:0] target_info; // [1952:1537] - bkdr_loader_hw2reg_width_info_mreg_t [12:0] width_info; // [1536:1121] - bkdr_loader_hw2reg_depth_info_mreg_t [12:0] depth_info; // [1120:705] - bkdr_loader_hw2reg_read_data_mreg_t [7:0] read_data; // [704:449] - bkdr_loader_hw2reg_index_reg_t index; // [448:416] - bkdr_loader_hw2reg_hash_last_loaded_mreg_t [12:0] hash_last_loaded; // [415:0] + bkdr_loader_hw2reg_status_reg_t status; // [2276:2275] + bkdr_loader_hw2reg_control_reg_t control; // [2274:2273] + bkdr_loader_hw2reg_num_bkdr_targets_reg_t num_bkdr_targets; // [2272:2241] + bkdr_loader_hw2reg_usr_access_timestamp_reg_t usr_access_timestamp; // [2240:2209] + bkdr_loader_hw2reg_target_info_mreg_t [14:0] target_info; // [2208:1729] + bkdr_loader_hw2reg_width_info_mreg_t [14:0] width_info; // [1728:1249] + bkdr_loader_hw2reg_depth_info_mreg_t [14:0] depth_info; // [1248:769] + bkdr_loader_hw2reg_read_data_mreg_t [7:0] read_data; // [768:513] + bkdr_loader_hw2reg_index_reg_t index; // [512:480] + bkdr_loader_hw2reg_hash_last_loaded_mreg_t [14:0] hash_last_loaded; // [479:0] } bkdr_loader_regs_hw2reg_t; // Register offsets for regs interface @@ -160,6 +160,8 @@ package bkdr_loader_reg_pkg; parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_10_OFFSET = 11'h 128; parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_11_OFFSET = 11'h 12c; parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_12_OFFSET = 11'h 130; + parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_13_OFFSET = 11'h 134; + parameter logic [RegsAw-1:0] BKDR_LOADER_TARGET_INFO_14_OFFSET = 11'h 138; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_0_OFFSET = 11'h 200; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_1_OFFSET = 11'h 204; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_2_OFFSET = 11'h 208; @@ -173,6 +175,8 @@ package bkdr_loader_reg_pkg; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_10_OFFSET = 11'h 228; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_11_OFFSET = 11'h 22c; parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_12_OFFSET = 11'h 230; + parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_13_OFFSET = 11'h 234; + parameter logic [RegsAw-1:0] BKDR_LOADER_WIDTH_INFO_14_OFFSET = 11'h 238; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_0_OFFSET = 11'h 300; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_1_OFFSET = 11'h 304; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_2_OFFSET = 11'h 308; @@ -186,6 +190,8 @@ package bkdr_loader_reg_pkg; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_10_OFFSET = 11'h 328; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_11_OFFSET = 11'h 32c; parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_12_OFFSET = 11'h 330; + parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_13_OFFSET = 11'h 334; + parameter logic [RegsAw-1:0] BKDR_LOADER_DEPTH_INFO_14_OFFSET = 11'h 338; parameter logic [RegsAw-1:0] BKDR_LOADER_READ_DATA_0_OFFSET = 11'h 400; parameter logic [RegsAw-1:0] BKDR_LOADER_READ_DATA_1_OFFSET = 11'h 404; parameter logic [RegsAw-1:0] BKDR_LOADER_READ_DATA_2_OFFSET = 11'h 408; @@ -216,6 +222,8 @@ package bkdr_loader_reg_pkg; parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_10_OFFSET = 11'h 728; parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_11_OFFSET = 11'h 72c; parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_12_OFFSET = 11'h 730; + parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_13_OFFSET = 11'h 734; + parameter logic [RegsAw-1:0] BKDR_LOADER_HASH_LAST_LOADED_14_OFFSET = 11'h 738; // Reset values for hwext registers and their fields for regs interface parameter logic [1:0] BKDR_LOADER_STATUS_RESVAL = 2'h 0; @@ -234,6 +242,8 @@ package bkdr_loader_reg_pkg; parameter logic [31:0] BKDR_LOADER_TARGET_INFO_10_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_TARGET_INFO_11_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_TARGET_INFO_12_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_TARGET_INFO_13_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_TARGET_INFO_14_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_1_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_2_RESVAL = 32'h 0; @@ -247,6 +257,8 @@ package bkdr_loader_reg_pkg; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_10_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_11_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_12_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_13_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_WIDTH_INFO_14_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_1_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_2_RESVAL = 32'h 0; @@ -260,6 +272,8 @@ package bkdr_loader_reg_pkg; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_10_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_11_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_12_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_13_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_DEPTH_INFO_14_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_READ_DATA_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_READ_DATA_0_VAL_0_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_READ_DATA_1_RESVAL = 32'h 0; @@ -289,6 +303,8 @@ package bkdr_loader_reg_pkg; parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_10_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_11_RESVAL = 32'h 0; parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_12_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_13_RESVAL = 32'h 0; + parameter logic [31:0] BKDR_LOADER_HASH_LAST_LOADED_14_RESVAL = 32'h 0; // Register index for regs interface typedef enum int { @@ -310,6 +326,8 @@ package bkdr_loader_reg_pkg; BKDR_LOADER_TARGET_INFO_10, BKDR_LOADER_TARGET_INFO_11, BKDR_LOADER_TARGET_INFO_12, + BKDR_LOADER_TARGET_INFO_13, + BKDR_LOADER_TARGET_INFO_14, BKDR_LOADER_WIDTH_INFO_0, BKDR_LOADER_WIDTH_INFO_1, BKDR_LOADER_WIDTH_INFO_2, @@ -323,6 +341,8 @@ package bkdr_loader_reg_pkg; BKDR_LOADER_WIDTH_INFO_10, BKDR_LOADER_WIDTH_INFO_11, BKDR_LOADER_WIDTH_INFO_12, + BKDR_LOADER_WIDTH_INFO_13, + BKDR_LOADER_WIDTH_INFO_14, BKDR_LOADER_DEPTH_INFO_0, BKDR_LOADER_DEPTH_INFO_1, BKDR_LOADER_DEPTH_INFO_2, @@ -336,6 +356,8 @@ package bkdr_loader_reg_pkg; BKDR_LOADER_DEPTH_INFO_10, BKDR_LOADER_DEPTH_INFO_11, BKDR_LOADER_DEPTH_INFO_12, + BKDR_LOADER_DEPTH_INFO_13, + BKDR_LOADER_DEPTH_INFO_14, BKDR_LOADER_READ_DATA_0, BKDR_LOADER_READ_DATA_1, BKDR_LOADER_READ_DATA_2, @@ -365,11 +387,13 @@ package bkdr_loader_reg_pkg; BKDR_LOADER_HASH_LAST_LOADED_9, BKDR_LOADER_HASH_LAST_LOADED_10, BKDR_LOADER_HASH_LAST_LOADED_11, - BKDR_LOADER_HASH_LAST_LOADED_12 + BKDR_LOADER_HASH_LAST_LOADED_12, + BKDR_LOADER_HASH_LAST_LOADED_13, + BKDR_LOADER_HASH_LAST_LOADED_14 } bkdr_loader_regs_id_e; // Register width information to check illegal writes for regs interface - parameter logic [3:0] BKDR_LOADER_REGS_PERMIT [74] = '{ + parameter logic [3:0] BKDR_LOADER_REGS_PERMIT [82] = '{ 4'b 0001, // index[ 0] BKDR_LOADER_STATUS 4'b 0011, // index[ 1] BKDR_LOADER_CONTROL 4'b 1111, // index[ 2] BKDR_LOADER_NUM_BKDR_TARGETS @@ -388,62 +412,70 @@ package bkdr_loader_reg_pkg; 4'b 1111, // index[15] BKDR_LOADER_TARGET_INFO_10 4'b 1111, // index[16] BKDR_LOADER_TARGET_INFO_11 4'b 1111, // index[17] BKDR_LOADER_TARGET_INFO_12 - 4'b 1111, // index[18] BKDR_LOADER_WIDTH_INFO_0 - 4'b 1111, // index[19] BKDR_LOADER_WIDTH_INFO_1 - 4'b 1111, // index[20] BKDR_LOADER_WIDTH_INFO_2 - 4'b 1111, // index[21] BKDR_LOADER_WIDTH_INFO_3 - 4'b 1111, // index[22] BKDR_LOADER_WIDTH_INFO_4 - 4'b 1111, // index[23] BKDR_LOADER_WIDTH_INFO_5 - 4'b 1111, // index[24] BKDR_LOADER_WIDTH_INFO_6 - 4'b 1111, // index[25] BKDR_LOADER_WIDTH_INFO_7 - 4'b 1111, // index[26] BKDR_LOADER_WIDTH_INFO_8 - 4'b 1111, // index[27] BKDR_LOADER_WIDTH_INFO_9 - 4'b 1111, // index[28] BKDR_LOADER_WIDTH_INFO_10 - 4'b 1111, // index[29] BKDR_LOADER_WIDTH_INFO_11 - 4'b 1111, // index[30] BKDR_LOADER_WIDTH_INFO_12 - 4'b 1111, // index[31] BKDR_LOADER_DEPTH_INFO_0 - 4'b 1111, // index[32] BKDR_LOADER_DEPTH_INFO_1 - 4'b 1111, // index[33] BKDR_LOADER_DEPTH_INFO_2 - 4'b 1111, // index[34] BKDR_LOADER_DEPTH_INFO_3 - 4'b 1111, // index[35] BKDR_LOADER_DEPTH_INFO_4 - 4'b 1111, // index[36] BKDR_LOADER_DEPTH_INFO_5 - 4'b 1111, // index[37] BKDR_LOADER_DEPTH_INFO_6 - 4'b 1111, // index[38] BKDR_LOADER_DEPTH_INFO_7 - 4'b 1111, // index[39] BKDR_LOADER_DEPTH_INFO_8 - 4'b 1111, // index[40] BKDR_LOADER_DEPTH_INFO_9 - 4'b 1111, // index[41] BKDR_LOADER_DEPTH_INFO_10 - 4'b 1111, // index[42] BKDR_LOADER_DEPTH_INFO_11 - 4'b 1111, // index[43] BKDR_LOADER_DEPTH_INFO_12 - 4'b 1111, // index[44] BKDR_LOADER_READ_DATA_0 - 4'b 1111, // index[45] BKDR_LOADER_READ_DATA_1 - 4'b 1111, // index[46] BKDR_LOADER_READ_DATA_2 - 4'b 1111, // index[47] BKDR_LOADER_READ_DATA_3 - 4'b 1111, // index[48] BKDR_LOADER_READ_DATA_4 - 4'b 1111, // index[49] BKDR_LOADER_READ_DATA_5 - 4'b 1111, // index[50] BKDR_LOADER_READ_DATA_6 - 4'b 1111, // index[51] BKDR_LOADER_READ_DATA_7 - 4'b 1111, // index[52] BKDR_LOADER_WRITE_DATA_0 - 4'b 1111, // index[53] BKDR_LOADER_WRITE_DATA_1 - 4'b 1111, // index[54] BKDR_LOADER_WRITE_DATA_2 - 4'b 1111, // index[55] BKDR_LOADER_WRITE_DATA_3 - 4'b 1111, // index[56] BKDR_LOADER_WRITE_DATA_4 - 4'b 1111, // index[57] BKDR_LOADER_WRITE_DATA_5 - 4'b 1111, // index[58] BKDR_LOADER_WRITE_DATA_6 - 4'b 1111, // index[59] BKDR_LOADER_WRITE_DATA_7 - 4'b 1111, // index[60] BKDR_LOADER_INDEX - 4'b 1111, // index[61] BKDR_LOADER_HASH_LAST_LOADED_0 - 4'b 1111, // index[62] BKDR_LOADER_HASH_LAST_LOADED_1 - 4'b 1111, // index[63] BKDR_LOADER_HASH_LAST_LOADED_2 - 4'b 1111, // index[64] BKDR_LOADER_HASH_LAST_LOADED_3 - 4'b 1111, // index[65] BKDR_LOADER_HASH_LAST_LOADED_4 - 4'b 1111, // index[66] BKDR_LOADER_HASH_LAST_LOADED_5 - 4'b 1111, // index[67] BKDR_LOADER_HASH_LAST_LOADED_6 - 4'b 1111, // index[68] BKDR_LOADER_HASH_LAST_LOADED_7 - 4'b 1111, // index[69] BKDR_LOADER_HASH_LAST_LOADED_8 - 4'b 1111, // index[70] BKDR_LOADER_HASH_LAST_LOADED_9 - 4'b 1111, // index[71] BKDR_LOADER_HASH_LAST_LOADED_10 - 4'b 1111, // index[72] BKDR_LOADER_HASH_LAST_LOADED_11 - 4'b 1111 // index[73] BKDR_LOADER_HASH_LAST_LOADED_12 + 4'b 1111, // index[18] BKDR_LOADER_TARGET_INFO_13 + 4'b 1111, // index[19] BKDR_LOADER_TARGET_INFO_14 + 4'b 1111, // index[20] BKDR_LOADER_WIDTH_INFO_0 + 4'b 1111, // index[21] BKDR_LOADER_WIDTH_INFO_1 + 4'b 1111, // index[22] BKDR_LOADER_WIDTH_INFO_2 + 4'b 1111, // index[23] BKDR_LOADER_WIDTH_INFO_3 + 4'b 1111, // index[24] BKDR_LOADER_WIDTH_INFO_4 + 4'b 1111, // index[25] BKDR_LOADER_WIDTH_INFO_5 + 4'b 1111, // index[26] BKDR_LOADER_WIDTH_INFO_6 + 4'b 1111, // index[27] BKDR_LOADER_WIDTH_INFO_7 + 4'b 1111, // index[28] BKDR_LOADER_WIDTH_INFO_8 + 4'b 1111, // index[29] BKDR_LOADER_WIDTH_INFO_9 + 4'b 1111, // index[30] BKDR_LOADER_WIDTH_INFO_10 + 4'b 1111, // index[31] BKDR_LOADER_WIDTH_INFO_11 + 4'b 1111, // index[32] BKDR_LOADER_WIDTH_INFO_12 + 4'b 1111, // index[33] BKDR_LOADER_WIDTH_INFO_13 + 4'b 1111, // index[34] BKDR_LOADER_WIDTH_INFO_14 + 4'b 1111, // index[35] BKDR_LOADER_DEPTH_INFO_0 + 4'b 1111, // index[36] BKDR_LOADER_DEPTH_INFO_1 + 4'b 1111, // index[37] BKDR_LOADER_DEPTH_INFO_2 + 4'b 1111, // index[38] BKDR_LOADER_DEPTH_INFO_3 + 4'b 1111, // index[39] BKDR_LOADER_DEPTH_INFO_4 + 4'b 1111, // index[40] BKDR_LOADER_DEPTH_INFO_5 + 4'b 1111, // index[41] BKDR_LOADER_DEPTH_INFO_6 + 4'b 1111, // index[42] BKDR_LOADER_DEPTH_INFO_7 + 4'b 1111, // index[43] BKDR_LOADER_DEPTH_INFO_8 + 4'b 1111, // index[44] BKDR_LOADER_DEPTH_INFO_9 + 4'b 1111, // index[45] BKDR_LOADER_DEPTH_INFO_10 + 4'b 1111, // index[46] BKDR_LOADER_DEPTH_INFO_11 + 4'b 1111, // index[47] BKDR_LOADER_DEPTH_INFO_12 + 4'b 1111, // index[48] BKDR_LOADER_DEPTH_INFO_13 + 4'b 1111, // index[49] BKDR_LOADER_DEPTH_INFO_14 + 4'b 1111, // index[50] BKDR_LOADER_READ_DATA_0 + 4'b 1111, // index[51] BKDR_LOADER_READ_DATA_1 + 4'b 1111, // index[52] BKDR_LOADER_READ_DATA_2 + 4'b 1111, // index[53] BKDR_LOADER_READ_DATA_3 + 4'b 1111, // index[54] BKDR_LOADER_READ_DATA_4 + 4'b 1111, // index[55] BKDR_LOADER_READ_DATA_5 + 4'b 1111, // index[56] BKDR_LOADER_READ_DATA_6 + 4'b 1111, // index[57] BKDR_LOADER_READ_DATA_7 + 4'b 1111, // index[58] BKDR_LOADER_WRITE_DATA_0 + 4'b 1111, // index[59] BKDR_LOADER_WRITE_DATA_1 + 4'b 1111, // index[60] BKDR_LOADER_WRITE_DATA_2 + 4'b 1111, // index[61] BKDR_LOADER_WRITE_DATA_3 + 4'b 1111, // index[62] BKDR_LOADER_WRITE_DATA_4 + 4'b 1111, // index[63] BKDR_LOADER_WRITE_DATA_5 + 4'b 1111, // index[64] BKDR_LOADER_WRITE_DATA_6 + 4'b 1111, // index[65] BKDR_LOADER_WRITE_DATA_7 + 4'b 1111, // index[66] BKDR_LOADER_INDEX + 4'b 1111, // index[67] BKDR_LOADER_HASH_LAST_LOADED_0 + 4'b 1111, // index[68] BKDR_LOADER_HASH_LAST_LOADED_1 + 4'b 1111, // index[69] BKDR_LOADER_HASH_LAST_LOADED_2 + 4'b 1111, // index[70] BKDR_LOADER_HASH_LAST_LOADED_3 + 4'b 1111, // index[71] BKDR_LOADER_HASH_LAST_LOADED_4 + 4'b 1111, // index[72] BKDR_LOADER_HASH_LAST_LOADED_5 + 4'b 1111, // index[73] BKDR_LOADER_HASH_LAST_LOADED_6 + 4'b 1111, // index[74] BKDR_LOADER_HASH_LAST_LOADED_7 + 4'b 1111, // index[75] BKDR_LOADER_HASH_LAST_LOADED_8 + 4'b 1111, // index[76] BKDR_LOADER_HASH_LAST_LOADED_9 + 4'b 1111, // index[77] BKDR_LOADER_HASH_LAST_LOADED_10 + 4'b 1111, // index[78] BKDR_LOADER_HASH_LAST_LOADED_11 + 4'b 1111, // index[79] BKDR_LOADER_HASH_LAST_LOADED_12 + 4'b 1111, // index[80] BKDR_LOADER_HASH_LAST_LOADED_13 + 4'b 1111 // index[81] BKDR_LOADER_HASH_LAST_LOADED_14 }; endpackage diff --git a/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv b/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv index fb4455905eb87..529ae2326217e 100644 --- a/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv +++ b/hw/ip/bkdr_loader/rtl/bkdr_loader_regs_reg_top.sv @@ -52,9 +52,9 @@ module bkdr_loader_regs_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [73:0] reg_we_check; + logic [81:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(74) + .OneHotWidth(82) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -168,6 +168,10 @@ module bkdr_loader_regs_reg_top ( logic [31:0] target_info_11_qs; logic target_info_12_re; logic [31:0] target_info_12_qs; + logic target_info_13_re; + logic [31:0] target_info_13_qs; + logic target_info_14_re; + logic [31:0] target_info_14_qs; logic width_info_0_re; logic [31:0] width_info_0_qs; logic width_info_1_re; @@ -194,6 +198,10 @@ module bkdr_loader_regs_reg_top ( logic [31:0] width_info_11_qs; logic width_info_12_re; logic [31:0] width_info_12_qs; + logic width_info_13_re; + logic [31:0] width_info_13_qs; + logic width_info_14_re; + logic [31:0] width_info_14_qs; logic depth_info_0_re; logic [31:0] depth_info_0_qs; logic depth_info_1_re; @@ -220,6 +228,10 @@ module bkdr_loader_regs_reg_top ( logic [31:0] depth_info_11_qs; logic depth_info_12_re; logic [31:0] depth_info_12_qs; + logic depth_info_13_re; + logic [31:0] depth_info_13_qs; + logic depth_info_14_re; + logic [31:0] depth_info_14_qs; logic read_data_0_re; logic [31:0] read_data_0_qs; logic read_data_1_re; @@ -315,6 +327,14 @@ module bkdr_loader_regs_reg_top ( logic hash_last_loaded_12_we; logic [31:0] hash_last_loaded_12_qs; logic [31:0] hash_last_loaded_12_wd; + logic hash_last_loaded_13_re; + logic hash_last_loaded_13_we; + logic [31:0] hash_last_loaded_13_qs; + logic [31:0] hash_last_loaded_13_wd; + logic hash_last_loaded_14_re; + logic hash_last_loaded_14_we; + logic [31:0] hash_last_loaded_14_qs; + logic [31:0] hash_last_loaded_14_wd; // Register instances // R[status]: V(True) @@ -787,6 +807,40 @@ module bkdr_loader_regs_reg_top ( ); + // Subregister 13 of Multireg target_info + // R[target_info_13]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_target_info_13 ( + .re (target_info_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.target_info[13].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (target_info_13_qs) + ); + + + // Subregister 14 of Multireg target_info + // R[target_info_14]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_target_info_14 ( + .re (target_info_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.target_info[14].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (target_info_14_qs) + ); + + // Subregister 0 of Multireg width_info // R[width_info_0]: V(True) prim_subreg_ext #( @@ -1008,6 +1062,40 @@ module bkdr_loader_regs_reg_top ( ); + // Subregister 13 of Multireg width_info + // R[width_info_13]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_width_info_13 ( + .re (width_info_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.width_info[13].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (width_info_13_qs) + ); + + + // Subregister 14 of Multireg width_info + // R[width_info_14]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_width_info_14 ( + .re (width_info_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.width_info[14].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (width_info_14_qs) + ); + + // Subregister 0 of Multireg depth_info // R[depth_info_0]: V(True) prim_subreg_ext #( @@ -1229,6 +1317,40 @@ module bkdr_loader_regs_reg_top ( ); + // Subregister 13 of Multireg depth_info + // R[depth_info_13]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_depth_info_13 ( + .re (depth_info_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.depth_info[13].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (depth_info_13_qs) + ); + + + // Subregister 14 of Multireg depth_info + // R[depth_info_14]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_depth_info_14 ( + .re (depth_info_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.depth_info[14].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (depth_info_14_qs) + ); + + // Subregister 0 of Multireg read_data // R[read_data_0]: V(True) prim_subreg_ext #( @@ -2006,8 +2128,50 @@ module bkdr_loader_regs_reg_top ( assign reg2hw.hash_last_loaded[12].qe = hash_last_loaded_12_qe; + // Subregister 13 of Multireg hash_last_loaded + // R[hash_last_loaded_13]: V(True) + logic hash_last_loaded_13_qe; + logic [0:0] hash_last_loaded_13_flds_we; + assign hash_last_loaded_13_qe = &hash_last_loaded_13_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_hash_last_loaded_13 ( + .re (hash_last_loaded_13_re), + .we (hash_last_loaded_13_we), + .wd (hash_last_loaded_13_wd), + .d (hw2reg.hash_last_loaded[13].d), + .qre (), + .qe (hash_last_loaded_13_flds_we[0]), + .q (reg2hw.hash_last_loaded[13].q), + .ds (), + .qs (hash_last_loaded_13_qs) + ); + assign reg2hw.hash_last_loaded[13].qe = hash_last_loaded_13_qe; + + + // Subregister 14 of Multireg hash_last_loaded + // R[hash_last_loaded_14]: V(True) + logic hash_last_loaded_14_qe; + logic [0:0] hash_last_loaded_14_flds_we; + assign hash_last_loaded_14_qe = &hash_last_loaded_14_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_hash_last_loaded_14 ( + .re (hash_last_loaded_14_re), + .we (hash_last_loaded_14_we), + .wd (hash_last_loaded_14_wd), + .d (hw2reg.hash_last_loaded[14].d), + .qre (), + .qe (hash_last_loaded_14_flds_we[0]), + .q (reg2hw.hash_last_loaded[14].q), + .ds (), + .qs (hash_last_loaded_14_qs) + ); + assign reg2hw.hash_last_loaded[14].qe = hash_last_loaded_14_qe; + + - logic [73:0] addr_hit; + logic [81:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == BKDR_LOADER_STATUS_OFFSET); addr_hit[ 1] = (reg_addr == BKDR_LOADER_CONTROL_OFFSET); @@ -2027,62 +2191,70 @@ module bkdr_loader_regs_reg_top ( addr_hit[15] = (reg_addr == BKDR_LOADER_TARGET_INFO_10_OFFSET); addr_hit[16] = (reg_addr == BKDR_LOADER_TARGET_INFO_11_OFFSET); addr_hit[17] = (reg_addr == BKDR_LOADER_TARGET_INFO_12_OFFSET); - addr_hit[18] = (reg_addr == BKDR_LOADER_WIDTH_INFO_0_OFFSET); - addr_hit[19] = (reg_addr == BKDR_LOADER_WIDTH_INFO_1_OFFSET); - addr_hit[20] = (reg_addr == BKDR_LOADER_WIDTH_INFO_2_OFFSET); - addr_hit[21] = (reg_addr == BKDR_LOADER_WIDTH_INFO_3_OFFSET); - addr_hit[22] = (reg_addr == BKDR_LOADER_WIDTH_INFO_4_OFFSET); - addr_hit[23] = (reg_addr == BKDR_LOADER_WIDTH_INFO_5_OFFSET); - addr_hit[24] = (reg_addr == BKDR_LOADER_WIDTH_INFO_6_OFFSET); - addr_hit[25] = (reg_addr == BKDR_LOADER_WIDTH_INFO_7_OFFSET); - addr_hit[26] = (reg_addr == BKDR_LOADER_WIDTH_INFO_8_OFFSET); - addr_hit[27] = (reg_addr == BKDR_LOADER_WIDTH_INFO_9_OFFSET); - addr_hit[28] = (reg_addr == BKDR_LOADER_WIDTH_INFO_10_OFFSET); - addr_hit[29] = (reg_addr == BKDR_LOADER_WIDTH_INFO_11_OFFSET); - addr_hit[30] = (reg_addr == BKDR_LOADER_WIDTH_INFO_12_OFFSET); - addr_hit[31] = (reg_addr == BKDR_LOADER_DEPTH_INFO_0_OFFSET); - addr_hit[32] = (reg_addr == BKDR_LOADER_DEPTH_INFO_1_OFFSET); - addr_hit[33] = (reg_addr == BKDR_LOADER_DEPTH_INFO_2_OFFSET); - addr_hit[34] = (reg_addr == BKDR_LOADER_DEPTH_INFO_3_OFFSET); - addr_hit[35] = (reg_addr == BKDR_LOADER_DEPTH_INFO_4_OFFSET); - addr_hit[36] = (reg_addr == BKDR_LOADER_DEPTH_INFO_5_OFFSET); - addr_hit[37] = (reg_addr == BKDR_LOADER_DEPTH_INFO_6_OFFSET); - addr_hit[38] = (reg_addr == BKDR_LOADER_DEPTH_INFO_7_OFFSET); - addr_hit[39] = (reg_addr == BKDR_LOADER_DEPTH_INFO_8_OFFSET); - addr_hit[40] = (reg_addr == BKDR_LOADER_DEPTH_INFO_9_OFFSET); - addr_hit[41] = (reg_addr == BKDR_LOADER_DEPTH_INFO_10_OFFSET); - addr_hit[42] = (reg_addr == BKDR_LOADER_DEPTH_INFO_11_OFFSET); - addr_hit[43] = (reg_addr == BKDR_LOADER_DEPTH_INFO_12_OFFSET); - addr_hit[44] = (reg_addr == BKDR_LOADER_READ_DATA_0_OFFSET); - addr_hit[45] = (reg_addr == BKDR_LOADER_READ_DATA_1_OFFSET); - addr_hit[46] = (reg_addr == BKDR_LOADER_READ_DATA_2_OFFSET); - addr_hit[47] = (reg_addr == BKDR_LOADER_READ_DATA_3_OFFSET); - addr_hit[48] = (reg_addr == BKDR_LOADER_READ_DATA_4_OFFSET); - addr_hit[49] = (reg_addr == BKDR_LOADER_READ_DATA_5_OFFSET); - addr_hit[50] = (reg_addr == BKDR_LOADER_READ_DATA_6_OFFSET); - addr_hit[51] = (reg_addr == BKDR_LOADER_READ_DATA_7_OFFSET); - addr_hit[52] = (reg_addr == BKDR_LOADER_WRITE_DATA_0_OFFSET); - addr_hit[53] = (reg_addr == BKDR_LOADER_WRITE_DATA_1_OFFSET); - addr_hit[54] = (reg_addr == BKDR_LOADER_WRITE_DATA_2_OFFSET); - addr_hit[55] = (reg_addr == BKDR_LOADER_WRITE_DATA_3_OFFSET); - addr_hit[56] = (reg_addr == BKDR_LOADER_WRITE_DATA_4_OFFSET); - addr_hit[57] = (reg_addr == BKDR_LOADER_WRITE_DATA_5_OFFSET); - addr_hit[58] = (reg_addr == BKDR_LOADER_WRITE_DATA_6_OFFSET); - addr_hit[59] = (reg_addr == BKDR_LOADER_WRITE_DATA_7_OFFSET); - addr_hit[60] = (reg_addr == BKDR_LOADER_INDEX_OFFSET); - addr_hit[61] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_0_OFFSET); - addr_hit[62] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_1_OFFSET); - addr_hit[63] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_2_OFFSET); - addr_hit[64] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_3_OFFSET); - addr_hit[65] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_4_OFFSET); - addr_hit[66] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_5_OFFSET); - addr_hit[67] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_6_OFFSET); - addr_hit[68] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_7_OFFSET); - addr_hit[69] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_8_OFFSET); - addr_hit[70] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_9_OFFSET); - addr_hit[71] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_10_OFFSET); - addr_hit[72] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_11_OFFSET); - addr_hit[73] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_12_OFFSET); + addr_hit[18] = (reg_addr == BKDR_LOADER_TARGET_INFO_13_OFFSET); + addr_hit[19] = (reg_addr == BKDR_LOADER_TARGET_INFO_14_OFFSET); + addr_hit[20] = (reg_addr == BKDR_LOADER_WIDTH_INFO_0_OFFSET); + addr_hit[21] = (reg_addr == BKDR_LOADER_WIDTH_INFO_1_OFFSET); + addr_hit[22] = (reg_addr == BKDR_LOADER_WIDTH_INFO_2_OFFSET); + addr_hit[23] = (reg_addr == BKDR_LOADER_WIDTH_INFO_3_OFFSET); + addr_hit[24] = (reg_addr == BKDR_LOADER_WIDTH_INFO_4_OFFSET); + addr_hit[25] = (reg_addr == BKDR_LOADER_WIDTH_INFO_5_OFFSET); + addr_hit[26] = (reg_addr == BKDR_LOADER_WIDTH_INFO_6_OFFSET); + addr_hit[27] = (reg_addr == BKDR_LOADER_WIDTH_INFO_7_OFFSET); + addr_hit[28] = (reg_addr == BKDR_LOADER_WIDTH_INFO_8_OFFSET); + addr_hit[29] = (reg_addr == BKDR_LOADER_WIDTH_INFO_9_OFFSET); + addr_hit[30] = (reg_addr == BKDR_LOADER_WIDTH_INFO_10_OFFSET); + addr_hit[31] = (reg_addr == BKDR_LOADER_WIDTH_INFO_11_OFFSET); + addr_hit[32] = (reg_addr == BKDR_LOADER_WIDTH_INFO_12_OFFSET); + addr_hit[33] = (reg_addr == BKDR_LOADER_WIDTH_INFO_13_OFFSET); + addr_hit[34] = (reg_addr == BKDR_LOADER_WIDTH_INFO_14_OFFSET); + addr_hit[35] = (reg_addr == BKDR_LOADER_DEPTH_INFO_0_OFFSET); + addr_hit[36] = (reg_addr == BKDR_LOADER_DEPTH_INFO_1_OFFSET); + addr_hit[37] = (reg_addr == BKDR_LOADER_DEPTH_INFO_2_OFFSET); + addr_hit[38] = (reg_addr == BKDR_LOADER_DEPTH_INFO_3_OFFSET); + addr_hit[39] = (reg_addr == BKDR_LOADER_DEPTH_INFO_4_OFFSET); + addr_hit[40] = (reg_addr == BKDR_LOADER_DEPTH_INFO_5_OFFSET); + addr_hit[41] = (reg_addr == BKDR_LOADER_DEPTH_INFO_6_OFFSET); + addr_hit[42] = (reg_addr == BKDR_LOADER_DEPTH_INFO_7_OFFSET); + addr_hit[43] = (reg_addr == BKDR_LOADER_DEPTH_INFO_8_OFFSET); + addr_hit[44] = (reg_addr == BKDR_LOADER_DEPTH_INFO_9_OFFSET); + addr_hit[45] = (reg_addr == BKDR_LOADER_DEPTH_INFO_10_OFFSET); + addr_hit[46] = (reg_addr == BKDR_LOADER_DEPTH_INFO_11_OFFSET); + addr_hit[47] = (reg_addr == BKDR_LOADER_DEPTH_INFO_12_OFFSET); + addr_hit[48] = (reg_addr == BKDR_LOADER_DEPTH_INFO_13_OFFSET); + addr_hit[49] = (reg_addr == BKDR_LOADER_DEPTH_INFO_14_OFFSET); + addr_hit[50] = (reg_addr == BKDR_LOADER_READ_DATA_0_OFFSET); + addr_hit[51] = (reg_addr == BKDR_LOADER_READ_DATA_1_OFFSET); + addr_hit[52] = (reg_addr == BKDR_LOADER_READ_DATA_2_OFFSET); + addr_hit[53] = (reg_addr == BKDR_LOADER_READ_DATA_3_OFFSET); + addr_hit[54] = (reg_addr == BKDR_LOADER_READ_DATA_4_OFFSET); + addr_hit[55] = (reg_addr == BKDR_LOADER_READ_DATA_5_OFFSET); + addr_hit[56] = (reg_addr == BKDR_LOADER_READ_DATA_6_OFFSET); + addr_hit[57] = (reg_addr == BKDR_LOADER_READ_DATA_7_OFFSET); + addr_hit[58] = (reg_addr == BKDR_LOADER_WRITE_DATA_0_OFFSET); + addr_hit[59] = (reg_addr == BKDR_LOADER_WRITE_DATA_1_OFFSET); + addr_hit[60] = (reg_addr == BKDR_LOADER_WRITE_DATA_2_OFFSET); + addr_hit[61] = (reg_addr == BKDR_LOADER_WRITE_DATA_3_OFFSET); + addr_hit[62] = (reg_addr == BKDR_LOADER_WRITE_DATA_4_OFFSET); + addr_hit[63] = (reg_addr == BKDR_LOADER_WRITE_DATA_5_OFFSET); + addr_hit[64] = (reg_addr == BKDR_LOADER_WRITE_DATA_6_OFFSET); + addr_hit[65] = (reg_addr == BKDR_LOADER_WRITE_DATA_7_OFFSET); + addr_hit[66] = (reg_addr == BKDR_LOADER_INDEX_OFFSET); + addr_hit[67] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_0_OFFSET); + addr_hit[68] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_1_OFFSET); + addr_hit[69] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_2_OFFSET); + addr_hit[70] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_3_OFFSET); + addr_hit[71] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_4_OFFSET); + addr_hit[72] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_5_OFFSET); + addr_hit[73] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_6_OFFSET); + addr_hit[74] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_7_OFFSET); + addr_hit[75] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_8_OFFSET); + addr_hit[76] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_9_OFFSET); + addr_hit[77] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_10_OFFSET); + addr_hit[78] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_11_OFFSET); + addr_hit[79] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_12_OFFSET); + addr_hit[80] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_13_OFFSET); + addr_hit[81] = (reg_addr == BKDR_LOADER_HASH_LAST_LOADED_14_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2163,7 +2335,15 @@ module bkdr_loader_regs_reg_top ( (addr_hit[70] & (|(BKDR_LOADER_REGS_PERMIT[70] & ~reg_be))) | (addr_hit[71] & (|(BKDR_LOADER_REGS_PERMIT[71] & ~reg_be))) | (addr_hit[72] & (|(BKDR_LOADER_REGS_PERMIT[72] & ~reg_be))) | - (addr_hit[73] & (|(BKDR_LOADER_REGS_PERMIT[73] & ~reg_be))))); + (addr_hit[73] & (|(BKDR_LOADER_REGS_PERMIT[73] & ~reg_be))) | + (addr_hit[74] & (|(BKDR_LOADER_REGS_PERMIT[74] & ~reg_be))) | + (addr_hit[75] & (|(BKDR_LOADER_REGS_PERMIT[75] & ~reg_be))) | + (addr_hit[76] & (|(BKDR_LOADER_REGS_PERMIT[76] & ~reg_be))) | + (addr_hit[77] & (|(BKDR_LOADER_REGS_PERMIT[77] & ~reg_be))) | + (addr_hit[78] & (|(BKDR_LOADER_REGS_PERMIT[78] & ~reg_be))) | + (addr_hit[79] & (|(BKDR_LOADER_REGS_PERMIT[79] & ~reg_be))) | + (addr_hit[80] & (|(BKDR_LOADER_REGS_PERMIT[80] & ~reg_be))) | + (addr_hit[81] & (|(BKDR_LOADER_REGS_PERMIT[81] & ~reg_be))))); end // Generate write-enables @@ -2197,119 +2377,133 @@ module bkdr_loader_regs_reg_top ( assign target_info_10_re = addr_hit[15] & reg_re & !reg_error; assign target_info_11_re = addr_hit[16] & reg_re & !reg_error; assign target_info_12_re = addr_hit[17] & reg_re & !reg_error; - assign width_info_0_re = addr_hit[18] & reg_re & !reg_error; - assign width_info_1_re = addr_hit[19] & reg_re & !reg_error; - assign width_info_2_re = addr_hit[20] & reg_re & !reg_error; - assign width_info_3_re = addr_hit[21] & reg_re & !reg_error; - assign width_info_4_re = addr_hit[22] & reg_re & !reg_error; - assign width_info_5_re = addr_hit[23] & reg_re & !reg_error; - assign width_info_6_re = addr_hit[24] & reg_re & !reg_error; - assign width_info_7_re = addr_hit[25] & reg_re & !reg_error; - assign width_info_8_re = addr_hit[26] & reg_re & !reg_error; - assign width_info_9_re = addr_hit[27] & reg_re & !reg_error; - assign width_info_10_re = addr_hit[28] & reg_re & !reg_error; - assign width_info_11_re = addr_hit[29] & reg_re & !reg_error; - assign width_info_12_re = addr_hit[30] & reg_re & !reg_error; - assign depth_info_0_re = addr_hit[31] & reg_re & !reg_error; - assign depth_info_1_re = addr_hit[32] & reg_re & !reg_error; - assign depth_info_2_re = addr_hit[33] & reg_re & !reg_error; - assign depth_info_3_re = addr_hit[34] & reg_re & !reg_error; - assign depth_info_4_re = addr_hit[35] & reg_re & !reg_error; - assign depth_info_5_re = addr_hit[36] & reg_re & !reg_error; - assign depth_info_6_re = addr_hit[37] & reg_re & !reg_error; - assign depth_info_7_re = addr_hit[38] & reg_re & !reg_error; - assign depth_info_8_re = addr_hit[39] & reg_re & !reg_error; - assign depth_info_9_re = addr_hit[40] & reg_re & !reg_error; - assign depth_info_10_re = addr_hit[41] & reg_re & !reg_error; - assign depth_info_11_re = addr_hit[42] & reg_re & !reg_error; - assign depth_info_12_re = addr_hit[43] & reg_re & !reg_error; - assign read_data_0_re = addr_hit[44] & reg_re & !reg_error; - assign read_data_1_re = addr_hit[45] & reg_re & !reg_error; - assign read_data_2_re = addr_hit[46] & reg_re & !reg_error; - assign read_data_3_re = addr_hit[47] & reg_re & !reg_error; - assign read_data_4_re = addr_hit[48] & reg_re & !reg_error; - assign read_data_5_re = addr_hit[49] & reg_re & !reg_error; - assign read_data_6_re = addr_hit[50] & reg_re & !reg_error; - assign read_data_7_re = addr_hit[51] & reg_re & !reg_error; - assign write_data_0_we = addr_hit[52] & reg_we & !reg_error; + assign target_info_13_re = addr_hit[18] & reg_re & !reg_error; + assign target_info_14_re = addr_hit[19] & reg_re & !reg_error; + assign width_info_0_re = addr_hit[20] & reg_re & !reg_error; + assign width_info_1_re = addr_hit[21] & reg_re & !reg_error; + assign width_info_2_re = addr_hit[22] & reg_re & !reg_error; + assign width_info_3_re = addr_hit[23] & reg_re & !reg_error; + assign width_info_4_re = addr_hit[24] & reg_re & !reg_error; + assign width_info_5_re = addr_hit[25] & reg_re & !reg_error; + assign width_info_6_re = addr_hit[26] & reg_re & !reg_error; + assign width_info_7_re = addr_hit[27] & reg_re & !reg_error; + assign width_info_8_re = addr_hit[28] & reg_re & !reg_error; + assign width_info_9_re = addr_hit[29] & reg_re & !reg_error; + assign width_info_10_re = addr_hit[30] & reg_re & !reg_error; + assign width_info_11_re = addr_hit[31] & reg_re & !reg_error; + assign width_info_12_re = addr_hit[32] & reg_re & !reg_error; + assign width_info_13_re = addr_hit[33] & reg_re & !reg_error; + assign width_info_14_re = addr_hit[34] & reg_re & !reg_error; + assign depth_info_0_re = addr_hit[35] & reg_re & !reg_error; + assign depth_info_1_re = addr_hit[36] & reg_re & !reg_error; + assign depth_info_2_re = addr_hit[37] & reg_re & !reg_error; + assign depth_info_3_re = addr_hit[38] & reg_re & !reg_error; + assign depth_info_4_re = addr_hit[39] & reg_re & !reg_error; + assign depth_info_5_re = addr_hit[40] & reg_re & !reg_error; + assign depth_info_6_re = addr_hit[41] & reg_re & !reg_error; + assign depth_info_7_re = addr_hit[42] & reg_re & !reg_error; + assign depth_info_8_re = addr_hit[43] & reg_re & !reg_error; + assign depth_info_9_re = addr_hit[44] & reg_re & !reg_error; + assign depth_info_10_re = addr_hit[45] & reg_re & !reg_error; + assign depth_info_11_re = addr_hit[46] & reg_re & !reg_error; + assign depth_info_12_re = addr_hit[47] & reg_re & !reg_error; + assign depth_info_13_re = addr_hit[48] & reg_re & !reg_error; + assign depth_info_14_re = addr_hit[49] & reg_re & !reg_error; + assign read_data_0_re = addr_hit[50] & reg_re & !reg_error; + assign read_data_1_re = addr_hit[51] & reg_re & !reg_error; + assign read_data_2_re = addr_hit[52] & reg_re & !reg_error; + assign read_data_3_re = addr_hit[53] & reg_re & !reg_error; + assign read_data_4_re = addr_hit[54] & reg_re & !reg_error; + assign read_data_5_re = addr_hit[55] & reg_re & !reg_error; + assign read_data_6_re = addr_hit[56] & reg_re & !reg_error; + assign read_data_7_re = addr_hit[57] & reg_re & !reg_error; + assign write_data_0_we = addr_hit[58] & reg_we & !reg_error; assign write_data_0_wd = reg_wdata[31:0]; - assign write_data_1_we = addr_hit[53] & reg_we & !reg_error; + assign write_data_1_we = addr_hit[59] & reg_we & !reg_error; assign write_data_1_wd = reg_wdata[31:0]; - assign write_data_2_we = addr_hit[54] & reg_we & !reg_error; + assign write_data_2_we = addr_hit[60] & reg_we & !reg_error; assign write_data_2_wd = reg_wdata[31:0]; - assign write_data_3_we = addr_hit[55] & reg_we & !reg_error; + assign write_data_3_we = addr_hit[61] & reg_we & !reg_error; assign write_data_3_wd = reg_wdata[31:0]; - assign write_data_4_we = addr_hit[56] & reg_we & !reg_error; + assign write_data_4_we = addr_hit[62] & reg_we & !reg_error; assign write_data_4_wd = reg_wdata[31:0]; - assign write_data_5_we = addr_hit[57] & reg_we & !reg_error; + assign write_data_5_we = addr_hit[63] & reg_we & !reg_error; assign write_data_5_wd = reg_wdata[31:0]; - assign write_data_6_we = addr_hit[58] & reg_we & !reg_error; + assign write_data_6_we = addr_hit[64] & reg_we & !reg_error; assign write_data_6_wd = reg_wdata[31:0]; - assign write_data_7_we = addr_hit[59] & reg_we & !reg_error; + assign write_data_7_we = addr_hit[65] & reg_we & !reg_error; assign write_data_7_wd = reg_wdata[31:0]; - assign index_we = addr_hit[60] & reg_we & !reg_error; + assign index_we = addr_hit[66] & reg_we & !reg_error; assign index_wd = reg_wdata[31:0]; - assign hash_last_loaded_0_re = addr_hit[61] & reg_re & !reg_error; - assign hash_last_loaded_0_we = addr_hit[61] & reg_we & !reg_error; + assign hash_last_loaded_0_re = addr_hit[67] & reg_re & !reg_error; + assign hash_last_loaded_0_we = addr_hit[67] & reg_we & !reg_error; assign hash_last_loaded_0_wd = reg_wdata[31:0]; - assign hash_last_loaded_1_re = addr_hit[62] & reg_re & !reg_error; - assign hash_last_loaded_1_we = addr_hit[62] & reg_we & !reg_error; + assign hash_last_loaded_1_re = addr_hit[68] & reg_re & !reg_error; + assign hash_last_loaded_1_we = addr_hit[68] & reg_we & !reg_error; assign hash_last_loaded_1_wd = reg_wdata[31:0]; - assign hash_last_loaded_2_re = addr_hit[63] & reg_re & !reg_error; - assign hash_last_loaded_2_we = addr_hit[63] & reg_we & !reg_error; + assign hash_last_loaded_2_re = addr_hit[69] & reg_re & !reg_error; + assign hash_last_loaded_2_we = addr_hit[69] & reg_we & !reg_error; assign hash_last_loaded_2_wd = reg_wdata[31:0]; - assign hash_last_loaded_3_re = addr_hit[64] & reg_re & !reg_error; - assign hash_last_loaded_3_we = addr_hit[64] & reg_we & !reg_error; + assign hash_last_loaded_3_re = addr_hit[70] & reg_re & !reg_error; + assign hash_last_loaded_3_we = addr_hit[70] & reg_we & !reg_error; assign hash_last_loaded_3_wd = reg_wdata[31:0]; - assign hash_last_loaded_4_re = addr_hit[65] & reg_re & !reg_error; - assign hash_last_loaded_4_we = addr_hit[65] & reg_we & !reg_error; + assign hash_last_loaded_4_re = addr_hit[71] & reg_re & !reg_error; + assign hash_last_loaded_4_we = addr_hit[71] & reg_we & !reg_error; assign hash_last_loaded_4_wd = reg_wdata[31:0]; - assign hash_last_loaded_5_re = addr_hit[66] & reg_re & !reg_error; - assign hash_last_loaded_5_we = addr_hit[66] & reg_we & !reg_error; + assign hash_last_loaded_5_re = addr_hit[72] & reg_re & !reg_error; + assign hash_last_loaded_5_we = addr_hit[72] & reg_we & !reg_error; assign hash_last_loaded_5_wd = reg_wdata[31:0]; - assign hash_last_loaded_6_re = addr_hit[67] & reg_re & !reg_error; - assign hash_last_loaded_6_we = addr_hit[67] & reg_we & !reg_error; + assign hash_last_loaded_6_re = addr_hit[73] & reg_re & !reg_error; + assign hash_last_loaded_6_we = addr_hit[73] & reg_we & !reg_error; assign hash_last_loaded_6_wd = reg_wdata[31:0]; - assign hash_last_loaded_7_re = addr_hit[68] & reg_re & !reg_error; - assign hash_last_loaded_7_we = addr_hit[68] & reg_we & !reg_error; + assign hash_last_loaded_7_re = addr_hit[74] & reg_re & !reg_error; + assign hash_last_loaded_7_we = addr_hit[74] & reg_we & !reg_error; assign hash_last_loaded_7_wd = reg_wdata[31:0]; - assign hash_last_loaded_8_re = addr_hit[69] & reg_re & !reg_error; - assign hash_last_loaded_8_we = addr_hit[69] & reg_we & !reg_error; + assign hash_last_loaded_8_re = addr_hit[75] & reg_re & !reg_error; + assign hash_last_loaded_8_we = addr_hit[75] & reg_we & !reg_error; assign hash_last_loaded_8_wd = reg_wdata[31:0]; - assign hash_last_loaded_9_re = addr_hit[70] & reg_re & !reg_error; - assign hash_last_loaded_9_we = addr_hit[70] & reg_we & !reg_error; + assign hash_last_loaded_9_re = addr_hit[76] & reg_re & !reg_error; + assign hash_last_loaded_9_we = addr_hit[76] & reg_we & !reg_error; assign hash_last_loaded_9_wd = reg_wdata[31:0]; - assign hash_last_loaded_10_re = addr_hit[71] & reg_re & !reg_error; - assign hash_last_loaded_10_we = addr_hit[71] & reg_we & !reg_error; + assign hash_last_loaded_10_re = addr_hit[77] & reg_re & !reg_error; + assign hash_last_loaded_10_we = addr_hit[77] & reg_we & !reg_error; assign hash_last_loaded_10_wd = reg_wdata[31:0]; - assign hash_last_loaded_11_re = addr_hit[72] & reg_re & !reg_error; - assign hash_last_loaded_11_we = addr_hit[72] & reg_we & !reg_error; + assign hash_last_loaded_11_re = addr_hit[78] & reg_re & !reg_error; + assign hash_last_loaded_11_we = addr_hit[78] & reg_we & !reg_error; assign hash_last_loaded_11_wd = reg_wdata[31:0]; - assign hash_last_loaded_12_re = addr_hit[73] & reg_re & !reg_error; - assign hash_last_loaded_12_we = addr_hit[73] & reg_we & !reg_error; + assign hash_last_loaded_12_re = addr_hit[79] & reg_re & !reg_error; + assign hash_last_loaded_12_we = addr_hit[79] & reg_we & !reg_error; assign hash_last_loaded_12_wd = reg_wdata[31:0]; + assign hash_last_loaded_13_re = addr_hit[80] & reg_re & !reg_error; + assign hash_last_loaded_13_we = addr_hit[80] & reg_we & !reg_error; + + assign hash_last_loaded_13_wd = reg_wdata[31:0]; + assign hash_last_loaded_14_re = addr_hit[81] & reg_re & !reg_error; + assign hash_last_loaded_14_we = addr_hit[81] & reg_we & !reg_error; + + assign hash_last_loaded_14_wd = reg_wdata[31:0]; // Assign write-enables to checker logic vector. always_comb begin @@ -2365,28 +2559,36 @@ module bkdr_loader_regs_reg_top ( reg_we_check[49] = 1'b0; reg_we_check[50] = 1'b0; reg_we_check[51] = 1'b0; - reg_we_check[52] = write_data_0_we; - reg_we_check[53] = write_data_1_we; - reg_we_check[54] = write_data_2_we; - reg_we_check[55] = write_data_3_we; - reg_we_check[56] = write_data_4_we; - reg_we_check[57] = write_data_5_we; - reg_we_check[58] = write_data_6_we; - reg_we_check[59] = write_data_7_we; - reg_we_check[60] = index_we; - reg_we_check[61] = hash_last_loaded_0_we; - reg_we_check[62] = hash_last_loaded_1_we; - reg_we_check[63] = hash_last_loaded_2_we; - reg_we_check[64] = hash_last_loaded_3_we; - reg_we_check[65] = hash_last_loaded_4_we; - reg_we_check[66] = hash_last_loaded_5_we; - reg_we_check[67] = hash_last_loaded_6_we; - reg_we_check[68] = hash_last_loaded_7_we; - reg_we_check[69] = hash_last_loaded_8_we; - reg_we_check[70] = hash_last_loaded_9_we; - reg_we_check[71] = hash_last_loaded_10_we; - reg_we_check[72] = hash_last_loaded_11_we; - reg_we_check[73] = hash_last_loaded_12_we; + reg_we_check[52] = 1'b0; + reg_we_check[53] = 1'b0; + reg_we_check[54] = 1'b0; + reg_we_check[55] = 1'b0; + reg_we_check[56] = 1'b0; + reg_we_check[57] = 1'b0; + reg_we_check[58] = write_data_0_we; + reg_we_check[59] = write_data_1_we; + reg_we_check[60] = write_data_2_we; + reg_we_check[61] = write_data_3_we; + reg_we_check[62] = write_data_4_we; + reg_we_check[63] = write_data_5_we; + reg_we_check[64] = write_data_6_we; + reg_we_check[65] = write_data_7_we; + reg_we_check[66] = index_we; + reg_we_check[67] = hash_last_loaded_0_we; + reg_we_check[68] = hash_last_loaded_1_we; + reg_we_check[69] = hash_last_loaded_2_we; + reg_we_check[70] = hash_last_loaded_3_we; + reg_we_check[71] = hash_last_loaded_4_we; + reg_we_check[72] = hash_last_loaded_5_we; + reg_we_check[73] = hash_last_loaded_6_we; + reg_we_check[74] = hash_last_loaded_7_we; + reg_we_check[75] = hash_last_loaded_8_we; + reg_we_check[76] = hash_last_loaded_9_we; + reg_we_check[77] = hash_last_loaded_10_we; + reg_we_check[78] = hash_last_loaded_11_we; + reg_we_check[79] = hash_last_loaded_12_we; + reg_we_check[80] = hash_last_loaded_13_we; + reg_we_check[81] = hash_last_loaded_14_we; end // Read data return @@ -2471,229 +2673,261 @@ module bkdr_loader_regs_reg_top ( end addr_hit[18]: begin - reg_rdata_next[31:0] = width_info_0_qs; + reg_rdata_next[31:0] = target_info_13_qs; end addr_hit[19]: begin - reg_rdata_next[31:0] = width_info_1_qs; + reg_rdata_next[31:0] = target_info_14_qs; end addr_hit[20]: begin - reg_rdata_next[31:0] = width_info_2_qs; + reg_rdata_next[31:0] = width_info_0_qs; end addr_hit[21]: begin - reg_rdata_next[31:0] = width_info_3_qs; + reg_rdata_next[31:0] = width_info_1_qs; end addr_hit[22]: begin - reg_rdata_next[31:0] = width_info_4_qs; + reg_rdata_next[31:0] = width_info_2_qs; end addr_hit[23]: begin - reg_rdata_next[31:0] = width_info_5_qs; + reg_rdata_next[31:0] = width_info_3_qs; end addr_hit[24]: begin - reg_rdata_next[31:0] = width_info_6_qs; + reg_rdata_next[31:0] = width_info_4_qs; end addr_hit[25]: begin - reg_rdata_next[31:0] = width_info_7_qs; + reg_rdata_next[31:0] = width_info_5_qs; end addr_hit[26]: begin - reg_rdata_next[31:0] = width_info_8_qs; + reg_rdata_next[31:0] = width_info_6_qs; end addr_hit[27]: begin - reg_rdata_next[31:0] = width_info_9_qs; + reg_rdata_next[31:0] = width_info_7_qs; end addr_hit[28]: begin - reg_rdata_next[31:0] = width_info_10_qs; + reg_rdata_next[31:0] = width_info_8_qs; end addr_hit[29]: begin - reg_rdata_next[31:0] = width_info_11_qs; + reg_rdata_next[31:0] = width_info_9_qs; end addr_hit[30]: begin - reg_rdata_next[31:0] = width_info_12_qs; + reg_rdata_next[31:0] = width_info_10_qs; end addr_hit[31]: begin - reg_rdata_next[31:0] = depth_info_0_qs; + reg_rdata_next[31:0] = width_info_11_qs; end addr_hit[32]: begin - reg_rdata_next[31:0] = depth_info_1_qs; + reg_rdata_next[31:0] = width_info_12_qs; end addr_hit[33]: begin - reg_rdata_next[31:0] = depth_info_2_qs; + reg_rdata_next[31:0] = width_info_13_qs; end addr_hit[34]: begin - reg_rdata_next[31:0] = depth_info_3_qs; + reg_rdata_next[31:0] = width_info_14_qs; end addr_hit[35]: begin - reg_rdata_next[31:0] = depth_info_4_qs; + reg_rdata_next[31:0] = depth_info_0_qs; end addr_hit[36]: begin - reg_rdata_next[31:0] = depth_info_5_qs; + reg_rdata_next[31:0] = depth_info_1_qs; end addr_hit[37]: begin - reg_rdata_next[31:0] = depth_info_6_qs; + reg_rdata_next[31:0] = depth_info_2_qs; end addr_hit[38]: begin - reg_rdata_next[31:0] = depth_info_7_qs; + reg_rdata_next[31:0] = depth_info_3_qs; end addr_hit[39]: begin - reg_rdata_next[31:0] = depth_info_8_qs; + reg_rdata_next[31:0] = depth_info_4_qs; end addr_hit[40]: begin - reg_rdata_next[31:0] = depth_info_9_qs; + reg_rdata_next[31:0] = depth_info_5_qs; end addr_hit[41]: begin - reg_rdata_next[31:0] = depth_info_10_qs; + reg_rdata_next[31:0] = depth_info_6_qs; end addr_hit[42]: begin - reg_rdata_next[31:0] = depth_info_11_qs; + reg_rdata_next[31:0] = depth_info_7_qs; end addr_hit[43]: begin - reg_rdata_next[31:0] = depth_info_12_qs; + reg_rdata_next[31:0] = depth_info_8_qs; end addr_hit[44]: begin - reg_rdata_next[31:0] = read_data_0_qs; + reg_rdata_next[31:0] = depth_info_9_qs; end addr_hit[45]: begin - reg_rdata_next[31:0] = read_data_1_qs; + reg_rdata_next[31:0] = depth_info_10_qs; end addr_hit[46]: begin - reg_rdata_next[31:0] = read_data_2_qs; + reg_rdata_next[31:0] = depth_info_11_qs; end addr_hit[47]: begin - reg_rdata_next[31:0] = read_data_3_qs; + reg_rdata_next[31:0] = depth_info_12_qs; end addr_hit[48]: begin - reg_rdata_next[31:0] = read_data_4_qs; + reg_rdata_next[31:0] = depth_info_13_qs; end addr_hit[49]: begin - reg_rdata_next[31:0] = read_data_5_qs; + reg_rdata_next[31:0] = depth_info_14_qs; end addr_hit[50]: begin - reg_rdata_next[31:0] = read_data_6_qs; + reg_rdata_next[31:0] = read_data_0_qs; end addr_hit[51]: begin - reg_rdata_next[31:0] = read_data_7_qs; + reg_rdata_next[31:0] = read_data_1_qs; end addr_hit[52]: begin - reg_rdata_next[31:0] = write_data_0_qs; + reg_rdata_next[31:0] = read_data_2_qs; end addr_hit[53]: begin - reg_rdata_next[31:0] = write_data_1_qs; + reg_rdata_next[31:0] = read_data_3_qs; end addr_hit[54]: begin - reg_rdata_next[31:0] = write_data_2_qs; + reg_rdata_next[31:0] = read_data_4_qs; end addr_hit[55]: begin - reg_rdata_next[31:0] = write_data_3_qs; + reg_rdata_next[31:0] = read_data_5_qs; end addr_hit[56]: begin - reg_rdata_next[31:0] = write_data_4_qs; + reg_rdata_next[31:0] = read_data_6_qs; end addr_hit[57]: begin - reg_rdata_next[31:0] = write_data_5_qs; + reg_rdata_next[31:0] = read_data_7_qs; end addr_hit[58]: begin - reg_rdata_next[31:0] = write_data_6_qs; + reg_rdata_next[31:0] = write_data_0_qs; end addr_hit[59]: begin - reg_rdata_next[31:0] = write_data_7_qs; + reg_rdata_next[31:0] = write_data_1_qs; end addr_hit[60]: begin - reg_rdata_next[31:0] = index_qs; + reg_rdata_next[31:0] = write_data_2_qs; end addr_hit[61]: begin - reg_rdata_next[31:0] = hash_last_loaded_0_qs; + reg_rdata_next[31:0] = write_data_3_qs; end addr_hit[62]: begin - reg_rdata_next[31:0] = hash_last_loaded_1_qs; + reg_rdata_next[31:0] = write_data_4_qs; end addr_hit[63]: begin - reg_rdata_next[31:0] = hash_last_loaded_2_qs; + reg_rdata_next[31:0] = write_data_5_qs; end addr_hit[64]: begin - reg_rdata_next[31:0] = hash_last_loaded_3_qs; + reg_rdata_next[31:0] = write_data_6_qs; end addr_hit[65]: begin - reg_rdata_next[31:0] = hash_last_loaded_4_qs; + reg_rdata_next[31:0] = write_data_7_qs; end addr_hit[66]: begin - reg_rdata_next[31:0] = hash_last_loaded_5_qs; + reg_rdata_next[31:0] = index_qs; end addr_hit[67]: begin - reg_rdata_next[31:0] = hash_last_loaded_6_qs; + reg_rdata_next[31:0] = hash_last_loaded_0_qs; end addr_hit[68]: begin - reg_rdata_next[31:0] = hash_last_loaded_7_qs; + reg_rdata_next[31:0] = hash_last_loaded_1_qs; end addr_hit[69]: begin - reg_rdata_next[31:0] = hash_last_loaded_8_qs; + reg_rdata_next[31:0] = hash_last_loaded_2_qs; end addr_hit[70]: begin - reg_rdata_next[31:0] = hash_last_loaded_9_qs; + reg_rdata_next[31:0] = hash_last_loaded_3_qs; end addr_hit[71]: begin - reg_rdata_next[31:0] = hash_last_loaded_10_qs; + reg_rdata_next[31:0] = hash_last_loaded_4_qs; end addr_hit[72]: begin - reg_rdata_next[31:0] = hash_last_loaded_11_qs; + reg_rdata_next[31:0] = hash_last_loaded_5_qs; end addr_hit[73]: begin + reg_rdata_next[31:0] = hash_last_loaded_6_qs; + end + + addr_hit[74]: begin + reg_rdata_next[31:0] = hash_last_loaded_7_qs; + end + + addr_hit[75]: begin + reg_rdata_next[31:0] = hash_last_loaded_8_qs; + end + + addr_hit[76]: begin + reg_rdata_next[31:0] = hash_last_loaded_9_qs; + end + + addr_hit[77]: begin + reg_rdata_next[31:0] = hash_last_loaded_10_qs; + end + + addr_hit[78]: begin + reg_rdata_next[31:0] = hash_last_loaded_11_qs; + end + + addr_hit[79]: begin reg_rdata_next[31:0] = hash_last_loaded_12_qs; end + addr_hit[80]: begin + reg_rdata_next[31:0] = hash_last_loaded_13_qs; + end + + addr_hit[81]: begin + reg_rdata_next[31:0] = hash_last_loaded_14_qs; + end + default: begin reg_rdata_next = '1; end diff --git a/rules/opentitan/fpga.bzl b/rules/opentitan/fpga.bzl index cfd1fbeab8f54..650d2d9f33c7a 100644 --- a/rules/opentitan/fpga.bzl +++ b/rules/opentitan/fpga.bzl @@ -199,6 +199,7 @@ def _get_test_commands(ctx, param, exec_env): backdoor_writes = "--clear AON=ALL --clear SRAM=ALL --clear SRM2=ALL" backdoor_writes += " --clear FB0=ALL --clear FI00=ALL --clear FI01=ALL --clear FI02=ALL" backdoor_writes += " --clear FB1=ALL --clear FI10=ALL --clear FI11=ALL --clear FI12=ALL" + backdoor_writes += " --clear RRDA=ALL --clear RRIN=ALL" # Load the ROM & OTP over the backdoor loader. ROM is read-only once mission mode is # entered, so its content can't have changed since the last time this FPGA was preloaded diff --git a/sw/host/penetrationtests/python/util/hyperdebug.py b/sw/host/penetrationtests/python/util/hyperdebug.py index 0fb61be8cf5a8..87ea2fe84d1bc 100644 --- a/sw/host/penetrationtests/python/util/hyperdebug.py +++ b/sw/host/penetrationtests/python/util/hyperdebug.py @@ -134,7 +134,8 @@ def program_memories( # List of FPGA target memories to clear for each test to make sure state does not persist. # This encompasses Retention SRAM and Flash (both info & data pages). clear_targets = ( - "AON", "FB0", "FI00", "FI01", "FI02", "FB1", "FI10", "FI11", "FI12" + "AON", "FB0", "FI00", "FI01", "FI02", "FB1", "FI10", "FI11", "FI12", + "RRDA", "RRIN" ) backdoor_writes = " ".join(f"--clear {target}=ALL" for target in clear_targets) if rom_vmem: From 45a62762af5cd450fe8e5f8bc33cdb105c06e80d Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 11 Mar 2026 12:00:41 +0100 Subject: [PATCH 06/41] [rram_ctrl,utils] extend utils to generate rram image This script gen-rram-img is used to convert a vmem128 file into a loadable vmem128 file that contains address infection and scrambling Signed-off-by: Michael Gautschi --- util/design/BUILD | 13 + util/design/gen-rram-img.py | 428 +++++++++++++++++++ util/py/packages/impl/object_size/memory.py | 1 + util/py/scripts/mapfile_to_json.py | 3 +- util/topgen/lib.py | 2 +- util/topgen/templates/toplevel_memory.ld.tpl | 2 +- 6 files changed, 446 insertions(+), 3 deletions(-) create mode 100755 util/design/gen-rram-img.py diff --git a/util/design/BUILD b/util/design/BUILD index afae43a3fe139..d0f38f07da801 100644 --- a/util/design/BUILD +++ b/util/design/BUILD @@ -36,6 +36,19 @@ py_binary( ], ) +py_binary( + name = "gen-rram-img", + srcs = ["gen-rram-img.py"], + deps = [ + ":secded_gen", + "//util/design/lib:common", + "//util/design/lib:otp_mem_map", + "//util/design/lib:present", + "//util/topgen", + requirement("pyfinite"), + ], +) + py_binary( name = "gen-lc-state-enc", srcs = ["gen-lc-state-enc.py"], diff --git a/util/design/gen-rram-img.py b/util/design/gen-rram-img.py new file mode 100755 index 0000000000000..dc5d990b3bbe3 --- /dev/null +++ b/util/design/gen-rram-img.py @@ -0,0 +1,428 @@ +#!/usr/bin/env python3 +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +r"""Takes a compiled VMEM image and processes it for loading into the RRAM. + + Specifically, this takes a raw RRAM image, adds address infection and scrambles + the data using the same XEX scrambling scheme used in the RRAM controller. This + enables backdoor loading the RRAM on simulation platforms (e.g., DV and Verilator). +""" + +import argparse +import re +import sys +from dataclasses import dataclass +from enum import Enum +from pathlib import Path +from typing import List + +import hjson +from pyfinite import ffield +from lib.common import (check_int, + inverse_permute_bits, + validate_data_perm_option, + vmem_permutation_string) +from lib.Present import Present + +import prince + +MUBI4_TRUE = 0x6 + +# Fixed OTP data / scrambling parameters. +OTP_WORD_SIZE = 16 # bits +OTP_WORD_SIZE_WECC = 24 # bits +OTP_RRAM_DATA_DEFAULT_CFG_RE = re.compile( + r"CREATOR_SW_CFG: CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG") +OTP_RRAM_DATA_DEFAULT_CFG_BLOCK_SIZE = 32 # bits +OTP_SECRET1_RE = re.compile(r"SECRET1") +OTP_SECRET1_BLOCK_SIZE = 64 # bits +OTP_SECRET1_PRESENT_KEY_LENGTH = 128 # bits +OTP_SECRET1_PRESENT_NUM_ROUNDS = 32 +OTP_RRAM_ADDR_KEY_SEED_SIZE = 256 # bits +OTP_RRAM_DATA_KEY_SEED_SIZE = 256 # bits +OTP_SECRET1_RRAM_ADDR_KEY_SEED_START = 0 + +# RRAM data / scrambling parameters. +RRAM_ADDR_KEY_SIZE = 128 # bits +RRAM_DATA_KEY_SIZE = 128 # bits +RRAM_WORD_SIZE = 128 # bits +RRAM_ADDR_SIZE = 17 # bits +RRAM_PRINCE_NUM_HALF_ROUNDS = 5 + + +class RramScramblingKeyType(Enum): + ADDRESS = 1 + DATA = 2 + + +# RRAM scrambling key computation parameters. +# ------------------------------------------------------------------------------ +# DO NOT EDIT: edit fixed parameters above instead. +# ------------------------------------------------------------------------------ +# Computed OTP data / scrambling parameters. +OTP_SECRET1_RRAM_ADDR_KEY_SEED_STOP = (OTP_RRAM_ADDR_KEY_SEED_SIZE // OTP_SECRET1_BLOCK_SIZE) +OTP_SECRET1_RRAM_DATA_KEY_SEED_START = (OTP_RRAM_ADDR_KEY_SEED_SIZE // OTP_SECRET1_BLOCK_SIZE) +OTP_SECRET1_RRAM_DATA_KEY_SEED_STOP = OTP_SECRET1_RRAM_DATA_KEY_SEED_START + ( + OTP_RRAM_DATA_KEY_SEED_SIZE // OTP_SECRET1_BLOCK_SIZE) + +# Computed RRAM data / scrambling parameters. +RRAM_KEY_COMPUTATION_KEY_SIZE = OTP_RRAM_ADDR_KEY_SEED_SIZE // 2 +RRAM_KEY_COMPUTATION_KEY_MASK = (2**RRAM_KEY_COMPUTATION_KEY_SIZE) - 1 +RRAM_GF_OPERAND_B_MASK = (2**RRAM_WORD_SIZE) - 1 +RRAM_GF_OPERAND_A_MASK = (2**RRAM_ADDR_SIZE) - 1 +# Create GF(2^128) with irreducible_polynomial = x^128 + x^7 + x^2 + x + 1 +RRAM_GF_2_128 = ffield.FField(128, + gen=((0x1 << 128) | (0x1 << 7) | (0x1 << 2) | + (0x1 << 1) | 0x1)) + +# Format string for generating new VMEM file. +RRAM_VMEM_WORD_SIZE = (RRAM_WORD_SIZE) +VMEM_FORMAT_STR = " {:0" + f"{RRAM_VMEM_WORD_SIZE // 4}" + "X}" +# ------------------------------------------------------------------------------ + + +@dataclass +class RramScramblingConfigs: + scrambling_enabled: bool = False + otp_secret1_key: int = None + addr_key_iv: int = None + data_key_iv: int = None + addr_key_final_const: int = None + data_key_final_const: int = None + addr_key_seed: int = None + data_key_seed: int = None + addr_key: int = None + data_key: int = None + + def get_iv(self, key_type: RramScramblingKeyType): + if key_type == RramScramblingKeyType.ADDRESS: + return self.addr_key_iv + else: + return self.data_key_iv + + def get_final_cnst(self, key_type: RramScramblingKeyType): + if key_type == RramScramblingKeyType.ADDRESS: + return self.addr_key_final_const + else: + return self.data_key_final_const + + +def _interleave_split(data: int): + """ + Splits a 128-bit integer into two 64-bit operands. + operand_a: bits [127, 125, ..., 1] + operand_b: bits [126, 124, ..., 0] + """ + operand_a = 0 + operand_b = 0 + + # We loop 64 times because we are pulling 64 pairs of bits + for i in range(64): + # Extract bit at position (2*i + 1) for operand_a + bit_a = (data >> (2 * i + 1)) & 1 + operand_a |= (bit_a << i) + + # Extract bit at position (2*i) for operand_b + bit_b = (data >> (2 * i)) & 1 + operand_b |= (bit_b << i) + + return operand_a, operand_b + + +def _interleave_combine(operand_a, operand_b): + """ + Combines two 64-bit operands into a 128-bit integer. + operand_a provides bits [1, 3, 5, ..., 127] + operand_b provides bits [0, 2, 4, ..., 126] + """ + result = 0 + + for i in range(64): + # Place bit i from operand_b at the even position (2*i) + bit_b = (operand_b >> i) & 1 + result |= (bit_b << (2 * i)) + + # Place bit i from operand_a at the odd position (2*i + 1) + bit_a = (operand_a >> i) & 1 + result |= (bit_a << (2 * i + 1)) + + return result + + +def _xex_scramble(data: int, word_addr: int, rram_addr_key: int, + rram_data_key: int) -> int: + operand_a = word_addr & RRAM_GF_OPERAND_A_MASK + operand_b = rram_addr_key & RRAM_GF_OPERAND_B_MASK + mask = RRAM_GF_2_128.Multiply(operand_a, operand_b) + masked_data = data ^ mask + # interleave data in two chunks + masked_data_0, masked_data_1 = _interleave_split(masked_data) + data_0 = prince.prince(masked_data_0, rram_data_key, + RRAM_PRINCE_NUM_HALF_ROUNDS) + data_1 = prince.prince(masked_data_1, rram_data_key, + RRAM_PRINCE_NUM_HALF_ROUNDS) + # return combined data + return _interleave_combine(data_0, data_1) ^ mask + + +def _convert_array_2_int(data_array: List[int], + data_size: int, + little_endian=True) -> int: + """Converts array of data blocks to an int.""" + reformatted_data = 0 + if not little_endian: + data_array.reverse() + for i, data in enumerate(data_array): + reformatted_data |= (data << (i * data_size)) + return reformatted_data + + +def _get_otp_ctrl_netlist_consts(top_secret_cfg: dict, scrambling_configs: RramScramblingConfigs): + + for module in top_secret_cfg["module"]: + if module.get("template_type") == "otp_ctrl": + otp_map = module["otp_mmap"] + break + else: + raise RuntimeError("OTP memory map configuration not found in top secret configuration") + + # Extract OTP secret1 partition scrambling key. + for key in otp_map["scrambling"]["keys"]: + if key["name"] == "Secret1Key": + scrambling_configs.otp_secret1_key = check_int(key["value"]) + + # Extract OTP NVM scrambling key IVs. + for digest in otp_map["scrambling"]["digests"]: + if digest["name"] == "NvmAddrKey": + scrambling_configs.addr_key_iv = check_int(digest["iv_value"]) + scrambling_configs.addr_key_final_const = check_int(digest["cnst_value"]) + if digest["name"] == "NvmDataKey": + scrambling_configs.data_key_iv = check_int(digest["iv_value"]) + scrambling_configs.data_key_final_const = check_int(digest["cnst_value"]) + + +def _get_rram_scrambling_configs(otp_vmem_file: str, otp_data_perm: list, + configs: RramScramblingConfigs) -> None: + # Open OTP VMEM file and read into memory, skipping comment lines. + try: + otp_vmem = Path(otp_vmem_file).read_text() + except IOError: + raise Exception(f"Unable to open {otp_vmem_file}") + otp_vmem_lines = re.findall(r"^@.*$", otp_vmem, flags=re.MULTILINE) + + # Retrieve OTP data from the following partitions: + # - CREATOR_SW_CFG: which contains the RRAM scramble enablement flag, and + # - SECRET1: which contains the RRAM scrambling key seeds. + # Note, we strip ECC bits from each data word when processing. + rram_data_default_cfg = None + secret1_data_blocks = [] + otp_data_block = 0 + idx = 0 + for line in otp_vmem_lines: + if (OTP_RRAM_DATA_DEFAULT_CFG_RE.search(line) or + OTP_SECRET1_RE.search(line)): + # Convert OTP VMEM word from string to int. + otp_data_word_w_ecc = int(line.split()[1], 16) + # Un-permute bits if necessary. + if otp_data_perm: + otp_data_word_as_str = format( + otp_data_word_w_ecc, "0" + str(OTP_WORD_SIZE_WECC) + "b") + otp_data_word_w_ecc = int( + inverse_permute_bits(otp_data_word_as_str, otp_data_perm), + 2) + # Drop ECC bits. + otp_data_word = otp_data_word_w_ecc & (2**OTP_WORD_SIZE - 1) + otp_data_block |= otp_data_word << (idx * OTP_WORD_SIZE) + idx += 1 + if OTP_RRAM_DATA_DEFAULT_CFG_RE.search(line): + if idx == (OTP_RRAM_DATA_DEFAULT_CFG_BLOCK_SIZE // + OTP_WORD_SIZE): + rram_data_default_cfg = otp_data_block & 0xff + # If RRAM data scrambling is disabled, then we can return + # early to save execution time. + if rram_data_default_cfg != MUBI4_TRUE: + configs.scrambling_enabled = False + return + configs.scrambling_enabled = True + otp_data_block = 0 + idx = 0 + if OTP_SECRET1_RE.search(line): + if idx == (OTP_SECRET1_BLOCK_SIZE // OTP_WORD_SIZE): + secret1_data_blocks.append(otp_data_block) + otp_data_block = 0 + idx = 0 + + # Check we found the data we were looking for in the OTP image. + if rram_data_default_cfg is None: + raise RuntimeError( + "Cannot read RRAM scrambling enablement state from OTP.") + if not secret1_data_blocks: + raise RuntimeError("Cannot read RRAM scrambling key seeds from OTP.") + + # Descramble SECRET1 partition data blocks and extract RRAM scrambling key + # seeds. The SECRET1 partition layout looks like: + # {RRAM_ADDR_KEY_SEED, RRAM_DATA_KEY_SEED, SRAM_DATA_KEY_SEED, DIGEST} + otp_secret1_present_cipher = Present(configs.otp_secret1_key, + rounds=OTP_SECRET1_PRESENT_NUM_ROUNDS, + keylen=OTP_SECRET1_PRESENT_KEY_LENGTH) + descrambled_secret1_blocks = list( + map(otp_secret1_present_cipher.decrypt, secret1_data_blocks)) + configs.addr_key_seed = _convert_array_2_int( + descrambled_secret1_blocks[OTP_SECRET1_RRAM_ADDR_KEY_SEED_START: + OTP_SECRET1_RRAM_ADDR_KEY_SEED_STOP], + OTP_SECRET1_BLOCK_SIZE) + configs.data_key_seed = _convert_array_2_int( + descrambled_secret1_blocks[OTP_SECRET1_RRAM_DATA_KEY_SEED_START: + OTP_SECRET1_RRAM_DATA_KEY_SEED_STOP], + OTP_SECRET1_BLOCK_SIZE) + + +def _compute_rram_scrambling_key(scrambling_configs: RramScramblingConfigs, + key_type: RramScramblingKeyType) -> int: + if key_type == RramScramblingKeyType.ADDRESS: + key_seed = scrambling_configs.addr_key_seed + else: + key_seed = scrambling_configs.data_key_seed + full_key = 0 + for i in range(2): + round_1_present_key = (key_seed >> + (RRAM_KEY_COMPUTATION_KEY_SIZE * + i)) & RRAM_KEY_COMPUTATION_KEY_MASK + key_half = 0 + for j in range(2): + if j == 0: + cipher = Present(round_1_present_key) + key_half = cipher.encrypt(scrambling_configs.get_iv( + key_type)) ^ scrambling_configs.get_iv(key_type) + else: + cipher = Present(scrambling_configs.get_final_cnst(key_type)) + key_half = cipher.encrypt(key_half) ^ key_half + full_key |= key_half << (64 * i) + return full_key + + +def _compute_rram_scrambling_keys( + scrambling_configs: RramScramblingConfigs) -> None: + scrambling_configs.addr_key = _compute_rram_scrambling_key( + scrambling_configs, RramScramblingKeyType.ADDRESS) + scrambling_configs.data_key = _compute_rram_scrambling_key( + scrambling_configs, RramScramblingKeyType.DATA) + + +def _reformat_rram_vmem( + rram_vmem_file: str, + scrambling_configs: RramScramblingConfigs) -> List[str]: + # Open (raw) RRAM VMEM file and read into memory, skipping comment lines. + try: + rram_vmem = Path(rram_vmem_file).read_text() + except IOError: + raise Exception(f"Unable to open {rram_vmem_file}") + rram_vmem_lines = re.findall(r"^@.*$", rram_vmem, flags=re.MULTILINE) + + # Add addr-infection and potentially scramble, each RRAM word. + reformatted_vmem_lines = [] + for line in rram_vmem_lines: + line_items = line.split() + reformatted_line = "" + address = None + address_offset = 0 + data = None + for item in line_items: + # Process the address first. + if re.match(r"^@", item): + reformatted_line += item + address = int(item.lstrip("@"), 16) + address_offset = 0 + # Process the data words. + else: + data = int(item, 16) + # addr infection with word address + new_data = 0 + for word_idx in range(RRAM_WORD_SIZE // 32): + chunk = (data >> (32 * word_idx)) & 0xFFFFFFFF + word_addr = ((address + address_offset) * 4) + word_idx + new_data |= ((chunk ^ word_addr) << (32 * word_idx)) + data = new_data + if scrambling_configs.scrambling_enabled: + data = _xex_scramble(data, address + address_offset, + scrambling_configs.addr_key, + scrambling_configs.data_key) + reformatted_line += str.format(VMEM_FORMAT_STR, + data) + address_offset += 1 + + # Append reformatted line to what will be the new output VMEM file. + reformatted_vmem_lines.append(reformatted_line) + + return reformatted_vmem_lines + + +def main(argv: List[str]): + # Parse command line args. + parser = argparse.ArgumentParser() + parser.add_argument("--in-rram-vmem", + type=str, + help="Input VMEM file to reformat.") + + parser.add_argument("--in-otp-vmem", + type=str, + help="Input OTP (VMEM) file to retrieve data from.") + parser.add_argument('--top-secret-cfg', + type=Path, + metavar='', + required=True, + help=''' + Path to the top secret configuration in Hjson format. + ''') + parser.add_argument("--out-rram-vmem", type=str, help="Output VMEM file.") + parser.add_argument("--otp-data-perm", + type=vmem_permutation_string, + metavar="", + default=[], + help=""" + This is a post-processing option and allows permuting + the bit positions before writing the memfile. The bit + mapping needs to be supplied as a comma separated list + of bit slices, where the numbers refer to the bit + positions in the original data word before remapping, + for example: + + "[7:0],[15:8]". + + The mapping must be bijective - otherwise this will + generate an error. + """) + args = parser.parse_args(argv) + scrambling_configs = RramScramblingConfigs() + + # Validate OTP bit permutation configuration. + if args.otp_data_perm: + validate_data_perm_option(OTP_WORD_SIZE_WECC, args.otp_data_perm) + + # Read RRAM scrambling configurations (including: enablement, otp_ctrl + # netlist consts, address and data key seeds) directly from OTP VMEM file. + if args.in_otp_vmem: + with open(args.top_secret_cfg, 'r') as infile: + top_secret_cfg = hjson.load(infile) + + _get_otp_ctrl_netlist_consts(top_secret_cfg, scrambling_configs) + _get_rram_scrambling_configs(args.in_otp_vmem, args.otp_data_perm, + scrambling_configs) + + # Compute RRAM scrambling keys from seeds. + if scrambling_configs.scrambling_enabled: + _compute_rram_scrambling_keys(scrambling_configs) + + # Reformat RRAM VMEM file to add integrity/reliability ECC and scrambling. + reformatted_vmem_lines = _reformat_rram_vmem(args.in_rram_vmem, + scrambling_configs) + + # Write re-formatted output file. Use binary mode and a large buffer size + # to improve performance. + with open(args.out_rram_vmem, "wb", buffering=2097152) as of: + of.write("\n".join(reformatted_vmem_lines).encode('utf-8')) + + +if __name__ == "__main__": + main(sys.argv[1:]) diff --git a/util/py/packages/impl/object_size/memory.py b/util/py/packages/impl/object_size/memory.py index 20d7e61917dd1..cb126544f221a 100644 --- a/util/py/packages/impl/object_size/memory.py +++ b/util/py/packages/impl/object_size/memory.py @@ -13,6 +13,7 @@ def parse_memory_file() -> dict[str, Memory]: ("rom", range(0x00008000, 0x00008000 + 0x8000)), ("ram_main", range(0x10000000, 0x10000000 + 0x20000)), ("eflash", range(0x20000000, 0x20000000 + 0x100000)), + ("rram", range(0x30000000, 0x30000000 + 0x200000)), ("ram_ret_aon", range(0x40600000, 0x40600000 + 0x1000)), ("rom_ext_virtual", range(0x90000000, 0x90000000 + 0x80000)), ("owner_virtual", range(0xa0000000, 0xa0000000 + 0x80000)), diff --git a/util/py/scripts/mapfile_to_json.py b/util/py/scripts/mapfile_to_json.py index d93310c0f7bc6..6fbd2b0b6024e 100755 --- a/util/py/scripts/mapfile_to_json.py +++ b/util/py/scripts/mapfile_to_json.py @@ -21,7 +21,7 @@ default='', help='Emit a mapfile visualization to the named file') parser.add_argument('--regions', - default='rom,ram_main,eflash', + default='rom,ram_main,eflash,rram', help='Which memory regions to analyze') parser.add_argument('--target', default='', @@ -178,6 +178,7 @@ def __init__(self, regions=('rom', 'ram_main'), ignore_debug=True): # Punt and supply the earlgrey layout. 'ram_ret_aon': (0x40600000, 0x40601000), 'eflash': (0x20000000, 0x20100000), + 'rram': (0x30000000, 0x30200000), 'ram_main': (0x10000000, 0x10020000), 'rom': (0x00008000, 0x00010000), 'rom_ext_virtual': (0x90000000, 0x90080000), diff --git a/util/topgen/lib.py b/util/topgen/lib.py index bd34a776431cf..e321c42970eb3 100644 --- a/util/topgen/lib.py +++ b/util/topgen/lib.py @@ -835,7 +835,7 @@ def is_inst(module: ConfigT) -> bool: raise ValueError('Attribute {} in {} is not valid'.format( module['attr'], module['name'])) - if module['type'] in ['rom', 'ram_1p_scr', 'eflash']: + if module['type'] in ['rom', 'ram_1p_scr', 'eflash', 'rram']: top_level_mem = True return top_level_mem or top_level_module diff --git a/util/topgen/templates/toplevel_memory.ld.tpl b/util/topgen/templates/toplevel_memory.ld.tpl index e54e8c8266e2a..8d806582e7bd6 100644 --- a/util/topgen/templates/toplevel_memory.ld.tpl +++ b/util/topgen/templates/toplevel_memory.ld.tpl @@ -19,7 +19,7 @@ def memory_to_flags(memory): else: flags_str += "rw" - if memory_type in ["rom", "eflash"]: + if memory_type in ["rom", "eflash", "rram"]: flags_str += "x" return flags_str From 73cc5a5f630797c7016fb35b966fc98c6c9ef6ee Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 11 Mar 2026 12:03:21 +0100 Subject: [PATCH 07/41] [rram_ctrl,bzl] extend bazel rules to generate rram-image The RRAM image is 128b wide and requires new rules to call the right script. When building software for the RRAM the "kind" can be switched from "flash" to "rram". This will generate a 128b wide vmem file and call the RRAM specific scripts for scrambling, address infection, etc. (gen-rram-img.py) Signed-off-by: Michael Gautschi --- hw/top/doc/create_top.md | 1 + hw/top_earlgrey/BUILD | 3 ++ rules/opentitan/cc.bzl | 16 ++++--- rules/opentitan/defs.bzl | 2 +- rules/opentitan/exec_env.bzl | 6 +++ rules/opentitan/fpga.bzl | 4 ++ rules/opentitan/legacy.bzl | 34 +++++++++++++- rules/opentitan/qemu.bzl | 9 ++++ rules/opentitan/silicon.bzl | 23 ++++++++++ rules/opentitan/sim_dv.bzl | 34 ++++++++++++++ rules/opentitan/sim_verilator.bzl | 10 +++++ rules/opentitan/transform.bzl | 73 ++++++++++++++++++++++++++++++- 12 files changed, 205 insertions(+), 10 deletions(-) diff --git a/hw/top/doc/create_top.md b/hw/top/doc/create_top.md index f40f834a51f8c..2e068dbb98c82 100644 --- a/hw/top/doc/create_top.md +++ b/hw/top/doc/create_top.md @@ -143,6 +143,7 @@ sim_dv( exec_env = "sim_dv", extract_sw_logs = "//util/device_sw_utils:extract_sw_logs_db", flash_scramble_tool = "//util/design:gen-flash-img", + rram_scramble_tool = "//util/design:gen-rram-img", libs = [ "//sw/device/lib/arch:boot_stage_rom_ext", "//sw/device/lib/arch:sim_dv", diff --git a/hw/top_earlgrey/BUILD b/hw/top_earlgrey/BUILD index 1a2558890222b..a7602cbada00f 100644 --- a/hw/top_earlgrey/BUILD +++ b/hw/top_earlgrey/BUILD @@ -278,6 +278,7 @@ silicon( "exit_success": DEFAULT_TEST_SUCCESS_MSG, "exit_failure": DEFAULT_TEST_FAILURE_MSG, }, + rram_scramble_tool = "//util/design:gen-rram-img", slot_spec = EARLGREY_SLOTS, test_cmd = """ --exec="transport init" @@ -323,6 +324,7 @@ silicon( "//signing:test_keys": "//sw/device/silicon_creator/rom_ext/sival:rom_ext_dice_x509_fake_slot_a", "//conditions:default": "//sw/device/silicon_creator/rom_ext/sival/binaries:rom_ext_dice_x509_prod", }), + rram_scramble_tool = "//util/design:gen-rram-img", slot_spec = EARLGREY_SLOTS, test_cmd = """ --exec="transport init" @@ -412,6 +414,7 @@ sim_dv( otp = "//hw/top_earlgrey/data/otp:img_rma", otp_data_perm = "//util/design/data:data_perm", otp_mmap = "//hw/top_earlgrey/data/otp:otp_ctrl_mmap.hjson", + rram_scramble_tool = "//util/design:gen-rram-img", slot_spec = EARLGREY_SLOTS, ) diff --git a/rules/opentitan/cc.bzl b/rules/opentitan/cc.bzl index 141700f00d89d..213225d22e151 100644 --- a/rules/opentitan/cc.bzl +++ b/rules/opentitan/cc.bzl @@ -656,9 +656,9 @@ common_binary_attrs = { default = "{name}_{exec_env}", ), "kind": attr.string( - doc = "Binary kind: flash, ram or rom", + doc = "Binary kind: flash, rram, ram or rom", default = "flash", - values = ["flash", "ram", "rom"], + values = ["flash", "rram", "ram", "rom"], ), # FIXME(cfrantz): This should come from the ExecEnvInfo provider, but # I was unable to make that work. See the comment in `exec_env.bzl`. @@ -882,9 +882,12 @@ def _opentitan_binary_assemble_impl(ctx): name = "{}_{}".format(ctx.attr.name, exec_env_name) spec = [] input_bins = [] + last_kind = "flash" for binary, offset in ctx.attr.bins.items(): - if binary[exec_env_provider].kind != "flash": - fail("Only flash binaries can be assembled.") + # Fixed the fail() syntax here + last_kind = binary[exec_env_provider].kind + if last_kind not in ["flash", "rram"]: + fail("Only flash or rram binaries can be assembled") input_bins.append(binary[exec_env_provider].default) spec.append("{}@{}".format(binary[exec_env_provider].default.path, offset)) action_param = {} @@ -902,14 +905,15 @@ def _opentitan_binary_assemble_impl(ctx): # Multi-slot binaries are currently only used for bootstrap operations, # i.e., non-backdoor loaded sim environments and FPGA/silicon # environments. Therefore we only need unscrambled VMEM files. + vmem_word_size = 128 if last_kind == "rram" else 64 vmem = convert_to_vmem( ctx, name = name, src = bin, - word_size = 64, + word_size = vmem_word_size, ) - result.append(exec_env_provider(default = bin, kind = "flash", vmem = vmem)) + result.append(exec_env_provider(default = bin, kind = last_kind, vmem = vmem)) assembled_bins.append(bin) assembled_bins.append(vmem) ot_bin_env_info[exec_env_provider] = env diff --git a/rules/opentitan/defs.bzl b/rules/opentitan/defs.bzl index 57adf8f23833a..e247b5ee512da 100644 --- a/rules/opentitan/defs.bzl +++ b/rules/opentitan/defs.bzl @@ -310,7 +310,7 @@ def opentitan_test( name: The base name of the test. The name will be extended with the name of the execution environment. srcs: The source files for this test. - kind: The kind of test (flash, ram, rom). + kind: The kind of test (flash, rram, ram, rom). deps: Dependecies for this test. copts: Compiler options for this test. defines: Compiler defines for this test. diff --git a/rules/opentitan/exec_env.bzl b/rules/opentitan/exec_env.bzl index b4e601381fe07..57c3fee22d926 100644 --- a/rules/opentitan/exec_env.bzl +++ b/rules/opentitan/exec_env.bzl @@ -32,6 +32,7 @@ _FIELDS = { "top_secret_cfg": ("file.top_secret_cfg", False), "otp_data_perm": ("attr.otp_data_perm", False), "flash_scramble_tool": ("attr.flash_scramble_tool", False), + "rram_scramble_tool": ("attr.rram_scramble_tool", False), "openocd": ("attr.openocd", False), "openocd_adapter_config": ("attr.openocd_adapter_config", False), "slot_spec": ("attr.slot_spec", False), @@ -227,6 +228,11 @@ def exec_env_common_attrs(**kwargs): executable = True, cfg = "exec", ), + "rram_scramble_tool": attr.label( + default = kwargs.get("rram_scramble_tool"), + executable = True, + cfg = "exec", + ), "rom_scramble_tool": attr.label( doc = "ROM scrambling tool.", default = "//hw/ip/rom_ctrl/util:scramble_image", diff --git a/rules/opentitan/fpga.bzl b/rules/opentitan/fpga.bzl index 650d2d9f33c7a..c9417149474d7 100644 --- a/rules/opentitan/fpga.bzl +++ b/rules/opentitan/fpga.bzl @@ -109,6 +109,10 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil default = signed_bin if signed_bin else binary rom = None rom32 = None + elif ctx.attr.kind == "rram": + default = signed_bin if signed_bin else binary + rom = None + rom32 = None else: fail("Not implemented: kind ==", ctx.attr.kind) diff --git a/rules/opentitan/legacy.bzl b/rules/opentitan/legacy.bzl index 41bab2ec3d69a..e0fabc1113b66 100644 --- a/rules/opentitan/legacy.bzl +++ b/rules/opentitan/legacy.bzl @@ -6,6 +6,7 @@ load( "@lowrisc_opentitan//rules/opentitan:transform.bzl", "convert_to_vmem", "scramble_flash", + "scramble_rram", _obj_transform = "obj_transform", ) load("@lowrisc_opentitan//rules:rv.bzl", "rv_rule") @@ -99,7 +100,7 @@ vmem_file = rv_rule( default = 64, doc = "Word size of VMEM file", mandatory = True, - values = [32, 64], + values = [32, 64, 128], ), }, ) @@ -139,3 +140,34 @@ scramble_flash_vmem = rv_rule( ), }, ) + +def _scramble_rram_vmem_impl(ctx): + outputs = [scramble_rram(ctx, suffix = "src.vmem")] + return [ + DefaultInfo( + files = depset(outputs), + data_runfiles = ctx.runfiles(files = outputs), + ), + ] + +scramble_rram_vmem = rv_rule( + implementation = _scramble_rram_vmem_impl, + attrs = { + "src": attr.label(allow_single_file = True), + "otp": attr.label(allow_single_file = True), + "top_secret_cfg": attr.label( + allow_single_file = True, + default = "//hw/top:secrets", + doc = "Generated top configuration file including secrets.", + ), + "otp_data_perm": attr.label( + default = "//util/design/data:data_perm", + doc = "Option to indicate OTP VMEM file bit layout.", + ), + "_tool": attr.label( + default = "@//util/design:gen-rram-img", + executable = True, + cfg = "exec", + ), + }, +) diff --git a/rules/opentitan/qemu.bzl b/rules/opentitan/qemu.bzl index e5e9ccd2180e9..a87b12add54bf 100644 --- a/rules/opentitan/qemu.bzl +++ b/rules/opentitan/qemu.bzl @@ -285,6 +285,15 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil firmware_elf = elf, ) rom = exec_env.rom[SimQemuBinaryInfo].rom + elif ctx.attr.kind == "rram": + # TODO: add rram implementation + default = gen_flash( + ctx, + flashgen = exec_env.flashgen, + firmware_bin = signed_bin or binary, + firmware_elf = elf, + ) + rom = exec_env.rom[SimQemuBinaryInfo].rom else: fail("Not implemented: kind == ", ctx.attr.kind) diff --git a/rules/opentitan/silicon.bzl b/rules/opentitan/silicon.bzl index 50d1538d9c5ac..3200bad95f18f 100644 --- a/rules/opentitan/silicon.bzl +++ b/rules/opentitan/silicon.bzl @@ -12,6 +12,7 @@ load( "convert_to_vmem", "extract_software_logs", "scramble_flash", + "scramble_rram", ) load( "@lowrisc_opentitan//rules/opentitan:util.bzl", @@ -94,6 +95,28 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil otp_data_perm = exec_env.otp_data_perm, _tool = exec_env.flash_scramble_tool.files_to_run, ) + elif ctx.attr.kind == "rram": + default = signed_bin if signed_bin else binary + rom = None + + # Build VMEM images to enable GLS testing. + vmem_base = convert_to_vmem( + ctx, + name = name, + src = default, + word_size = 128, + ) + vmem = scramble_rram( + ctx, + name = name, + suffix = "128.scr.vmem", + src = vmem_base, + otp = get_fallback(ctx, "file.otp", exec_env), + otp_mmap = exec_env.otp_mmap, + top_secret_cfg = exec_env.top_secret_cfg, + otp_data_perm = exec_env.otp_data_perm, + _tool = exec_env.rram_scramble_tool.files_to_run, + ) else: fail("Not implemented: kind ==", ctx.attr.kind) diff --git a/rules/opentitan/sim_dv.bzl b/rules/opentitan/sim_dv.bzl index 99e0ac8fdea2e..121874f0658d0 100644 --- a/rules/opentitan/sim_dv.bzl +++ b/rules/opentitan/sim_dv.bzl @@ -17,6 +17,7 @@ load( "convert_to_vmem", "extract_software_logs", "scramble_flash", + "scramble_rram", ) load("//rules/opentitan:toolchain.bzl", "LOCALTOOLS_TOOLCHAIN") @@ -112,6 +113,39 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil rom32 = None default = vmem vmem = vmem_base + elif ctx.attr.kind == "rram": + # First convert to VMEM, then scramble according to rram + # scrambling settings. + # When dvsim and bazel use different otp image which has different scramble option, + # there is a corner case where dvsim can't find vmem file. + # Send scr.vmem and vmem to mitigate the issue + vmem_base = convert_to_vmem( + ctx, + name = name, + src = signed_bin if signed_bin else binary, + word_size = 128, + ) + vmem32 = convert_to_vmem( + ctx, + name = name, + src = signed_bin if signed_bin else binary, + word_size = 32, + ) + vmem = scramble_rram( + ctx, + name = name, + suffix = "128.scr.vmem", + src = vmem_base, + otp = get_fallback(ctx, "file.otp", exec_env), + otp_mmap = exec_env.otp_mmap, + top_secret_cfg = exec_env.top_secret_cfg, + otp_data_perm = exec_env.otp_data_perm, + _tool = exec_env.rram_scramble_tool.files_to_run, + ) + rom = None + rom32 = None + default = vmem + vmem = vmem_base else: fail("Not implemented: kind ==", ctx.attr.kind) diff --git a/rules/opentitan/sim_verilator.bzl b/rules/opentitan/sim_verilator.bzl index 2beb125b5713d..7230396eb8245 100644 --- a/rules/opentitan/sim_verilator.bzl +++ b/rules/opentitan/sim_verilator.bzl @@ -97,6 +97,16 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil default = vmem rom = None rom32 = None + elif ctx.attr.kind == "rram": + vmem = convert_to_vmem( + ctx, + name = name, + src = signed_bin if signed_bin else binary, + word_size = 128, + ) + default = vmem + rom = None + rom32 = None else: fail("Not implemented: kind ==", ctx.attr.kind) diff --git a/rules/opentitan/transform.bzl b/rules/opentitan/transform.bzl index e6a717db8a20f..06b522d0decb2 100644 --- a/rules/opentitan/transform.bzl +++ b/rules/opentitan/transform.bzl @@ -202,6 +202,12 @@ def convert_to_vmem(ctx, **kwargs): output = ctx.actions.declare_file(output) src = get_override(ctx, "file.src", kwargs) + # srec_cat for vmem128 does not work with byte_swap=16. We actually need to pass 128 + byte_swap = 128 if word_size == 128 else word_size // 8 + + # for RRAM we fill with 0x00 as this is the default state + fill_str = "0x00" if word_size == 128 else "0xff" + ctx.actions.run( outputs = [output], inputs = [src], @@ -212,10 +218,10 @@ def convert_to_vmem(ctx, **kwargs): "--offset", "0x0", "--byte-swap", - str(word_size // 8), + str(byte_swap), # Pad to word alignment "--fill", - "0xff", + fill_str, "-within", src.path, "-binary", @@ -297,6 +303,69 @@ def scramble_flash(ctx, **kwargs): ) return output +def scramble_rram(ctx, **kwargs): + """Scramble a VMEM file according to a RRAM scrambling configuration. + + Args: + ctx: The context object for this rule. + kwargs: Overrides of values normally retrived from the context object. + output: The name of the output file. Constructed from `name` and `suffix` + if not specified. + suffix: The suffix to give the file if the output isn't specified. + src: The src File object. + otp: The OTP settings. + otp_mmap: The OTP memory mapping file. + + top_secret_cfg: The secret configuration file. + otp_data_perm: The OTP data permutation configuration. + _tool: The rram scrambling script. + + Returns: + The transformed File. + """ + output = kwargs.get("output") + if not output: + name = get_override(ctx, "attr.name", kwargs) + suffix = get_override(ctx, "attr.suffix", kwargs) + output = "{}.{}".format(name, suffix) + + output = ctx.actions.declare_file(output) + src = get_override(ctx, "file.src", kwargs) + otp = get_override(ctx, "file.otp", kwargs) + + inputs = [src] + arguments = [ + "--in-rram-vmem", + src.path, + "--out-rram-vmem", + output.path, + ] + + # Always get top_secret_cfg since the tool requires it + top_secret_cfg = get_override(ctx, "file.top_secret_cfg", kwargs) + arguments.extend(["--top-secret-cfg", top_secret_cfg.path]) + inputs.append(top_secret_cfg) + + if otp: + arguments.extend([ + "--in-otp-vmem", + otp.path, + ]) + inputs.extend([otp]) + + otp_data_perm = get_override(ctx, "attr.otp_data_perm", kwargs) + if otp_data_perm: + arguments.extend(["--otp-data-perm", str(otp_data_perm[BuildSettingInfo].value)]) + + tool = get_override(ctx, "executable._tool", kwargs) + ctx.actions.run( + outputs = [output], + inputs = inputs, + arguments = arguments, + executable = tool, + ) + return output + def extract_software_logs(ctx, **kwargs): """Extract the software logs database from an ELF file. From 92c37038c9eb4d33610ec6fbfb594112a7e55e02 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 18 Jun 2026 10:41:39 +0200 Subject: [PATCH 08/41] [top,rtl] connect rram_ctrl to keymgr This commit connects rram_ctrl to the keymgr. This means that the seeds for the keys are now read from RRAM instead of flash. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/top_earlgrey.hjson | 5 +++-- hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl | 3 +++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 67d8908d8b56e..254897ba3dbc5 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1173,7 +1173,6 @@ 'aon_timer.nmi_wdog_timer_bark' : ['rv_core_ibex.nmi_wdog'], 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'], 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'], - 'flash_ctrl.keymgr' : ['keymgr.flash'], 'flash_ctrl.otp' : ['otp_ctrl.nvm_otp_key'], 'lc_ctrl.lc_nvm_rma_seed' : ['flash_ctrl.rma_seed', 'rram_ctrl.rma_seed'], 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', @@ -1191,7 +1190,6 @@ 'pwrmgr.fetch_en' : ['rv_core_ibex.pwrmgr_cpu_en'], 'rom_ctrl.pwrmgr_data' : ['pwrmgr.rom_ctrl'], 'rom_ctrl.keymgr_data' : ['keymgr.rom_digest'], - 'flash_ctrl.keymgr' : ['keymgr.flash'], 'alert_handler.crashdump' : ['rstmgr.alert_dump'], // LC RMA req/ack interface: LC --> Flash -> LC @@ -1364,6 +1362,9 @@ // Temporary RRAM helpers 'rram_ctrl.otp_key', + 'flash_ctrl.keymgr', + 'rram_ctrl.keymgr', + 'keymgr.flash', // Pinmux JTAG signals for the tool-inserted DFT TAP 'pinmux.dft_jtag', diff --git a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl index 765e32180ced9..ac029d4deddb0 100644 --- a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl +++ b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl @@ -78,6 +78,9 @@ module ${top["name"]}_pd_${domain.lower()} #( assign rram_ctrl_otp_key_rsp.key = '0; assign rram_ctrl_otp_key_rsp.rand_key = '0; assign rram_ctrl_otp_key_rsp.seed_valid = 1'b0; + + // TODO: remove once keymgr has been updated + assign keymgr_flash.seeds = rram_ctrl_keymgr.seeds; % endif % endfor From d8d494bc317e4b859b7cff8a41c0be0247072a54 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 18 Jun 2026 10:42:33 +0200 Subject: [PATCH 09/41] [top,rtl] autogen for rram_ctrl to keymgr This commit contains the autogen files for connecting rram_ctrl to keymgr. Signed-off-by: Michael Gautschi --- .../data/autogen/top_earlgrey.gen.hjson | 63 ++++++++++++------- .../rtl/autogen/earlgrey_pd_main.sv | 11 +++- 2 files changed, 47 insertions(+), 27 deletions(-) diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 231a9412a660c..d8604d2920643 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -6342,8 +6342,6 @@ width: 1 inst_name: flash_ctrl default: "" - end_idx: -1 - top_type: broadcast top_signame: flash_ctrl_keymgr index: -1 } @@ -6677,6 +6675,8 @@ act: req width: 1 inst_name: rram_ctrl + default: "" + top_signame: rram_ctrl_keymgr index: -1 } { @@ -8368,8 +8368,7 @@ width: 1 inst_name: keymgr default: "" - domain: Main - top_signame: flash_ctrl_keymgr + top_signame: keymgr_flash index: -1 } { @@ -10652,10 +10651,6 @@ [ entropy_src.entropy_src_hw_if ] - flash_ctrl.keymgr: - [ - keymgr.flash - ] flash_ctrl.otp: [ otp_ctrl.nvm_otp_key @@ -11224,6 +11219,9 @@ rv_core_ibex.hart_id rv_core_ibex.boot_addr rram_ctrl.otp_key + flash_ctrl.keymgr + rram_ctrl.keymgr + keymgr.flash pinmux.dft_jtag otp_ctrl.otp_broadcast csrng.otp_en_csrng_sw_app_read @@ -25190,8 +25188,6 @@ width: 1 inst_name: flash_ctrl default: "" - end_idx: -1 - top_type: broadcast top_signame: flash_ctrl_keymgr index: -1 } @@ -25434,6 +25430,8 @@ act: req width: 1 inst_name: rram_ctrl + default: "" + top_signame: rram_ctrl_keymgr index: -1 } { @@ -26407,8 +26405,7 @@ width: 1 inst_name: keymgr default: "" - domain: Main - top_signame: flash_ctrl_keymgr + top_signame: keymgr_flash index: -1 } { @@ -33060,18 +33057,6 @@ suffix: rsp default: entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT } - { - package: flash_ctrl_pkg - struct: keymgr_flash - domain: Main - signame: flash_ctrl_keymgr - width: 1 - type: uni - end_idx: -1 - act: req - suffix: "" - default: flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT - } { package: otp_ctrl_pkg struct: nvm_otp_key_req @@ -35214,6 +35199,36 @@ end_idx: -1 default: "" } + { + package: flash_ctrl_pkg + struct: keymgr_flash + signame: flash_ctrl_keymgr + domain: Main + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: rram_ctrl_pkg + struct: keymgr_rram + signame: rram_ctrl_keymgr + domain: Main + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: flash_ctrl_pkg + struct: keymgr_flash + signame: keymgr_flash + domain: Main + width: 1 + type: uni + end_idx: -1 + default: "" + } { package: jtag_pkg struct: jtag_req diff --git a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv index 0b327fd22aa3f..5f0c2a8d76759 100644 --- a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv +++ b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv @@ -642,7 +642,6 @@ module earlgrey_pd_main #( csrng_pkg::csrng_rsp_t [1:0] csrng_csrng_cmd_rsp; entropy_src_pkg::entropy_src_hw_if_req_t csrng_entropy_src_hw_if_req; entropy_src_pkg::entropy_src_hw_if_rsp_t csrng_entropy_src_hw_if_rsp; - flash_ctrl_pkg::keymgr_flash_t flash_ctrl_keymgr; otp_ctrl_pkg::nvm_otp_key_req_t flash_ctrl_otp_req; otp_ctrl_pkg::nvm_otp_key_rsp_t flash_ctrl_otp_rsp; lc_ctrl_pkg::lc_nvm_rma_seed_t lc_ctrl_lc_nvm_rma_seed; @@ -806,6 +805,9 @@ module earlgrey_pd_main #( logic [31:0] rv_core_ibex_boot_addr; otp_ctrl_pkg::nvm_otp_key_req_t rram_ctrl_otp_key_req; otp_ctrl_pkg::nvm_otp_key_rsp_t rram_ctrl_otp_key_rsp; + flash_ctrl_pkg::keymgr_flash_t flash_ctrl_keymgr; + rram_ctrl_pkg::keymgr_rram_t rram_ctrl_keymgr; + flash_ctrl_pkg::keymgr_flash_t keymgr_flash; jtag_pkg::jtag_req_t pinmux_dft_jtag_req; jtag_pkg::jtag_rsp_t pinmux_dft_jtag_rsp; otp_ctrl_part_pkg::otp_broadcast_t otp_ctrl_otp_broadcast; @@ -876,6 +878,9 @@ module earlgrey_pd_main #( assign rram_ctrl_otp_key_rsp.rand_key = '0; assign rram_ctrl_otp_key_rsp.seed_valid = 1'b0; + // TODO: remove once keymgr has been updated + assign keymgr_flash.seeds = rram_ctrl_keymgr.seeds; + // Ibex-specific assignments // TODO: This should be further automated in the future. assign rv_core_ibex_irq_timer = intr_rv_timer_timer_expired_hart0_timer0; @@ -2067,7 +2072,7 @@ module earlgrey_pd_main #( .rma_ack_o(), .rma_seed_i(lc_ctrl_lc_nvm_rma_seed), .pwrmgr_o(), - .keymgr_o(), + .keymgr_o(rram_ctrl_keymgr), .core_tl_i(rram_ctrl_core_tl_req), .core_tl_o(rram_ctrl_core_tl_rsp), .host_tl_i(rram_ctrl_host_tl_req), @@ -2391,7 +2396,7 @@ module earlgrey_pd_main #( .kmac_data_i(kmac_app_rsp[0]), .otp_key_i(keymgr_otp_key), .otp_device_id_i(keymgr_otp_device_id), - .flash_i(flash_ctrl_keymgr), + .flash_i(keymgr_flash), .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en), .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div), .rom_digest_i(rom_ctrl_keymgr_data), From bbed008d02aa38b81ebdb752b1a84fa1fa3cd0b9 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 27 May 2026 16:08:43 +0200 Subject: [PATCH 10/41] [top,sim,verilator] RRAM verilator support This commit allows to load RRAM images in verilator runs. The image can be scrambled and then loaded via memload to the RRAM data_array. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/BUILD | 5 +++- hw/top_earlgrey/dv/verilator/chip_sim_tb.cc | 7 ++++++ rules/opentitan/sim_dv.bzl | 25 +++++++++++-------- rules/opentitan/sim_verilator.bzl | 17 ++++++++++++- sw/host/ot_transports/verilator/src/lib.rs | 3 +++ .../ot_transports/verilator/src/subprocess.rs | 5 ++++ 6 files changed, 49 insertions(+), 13 deletions(-) diff --git a/hw/top_earlgrey/BUILD b/hw/top_earlgrey/BUILD index a7602cbada00f..87e48af5afaf3 100644 --- a/hw/top_earlgrey/BUILD +++ b/hw/top_earlgrey/BUILD @@ -351,6 +351,9 @@ sim_verilator( ], linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_a", otp = "//hw/top_earlgrey/data/otp:img_rma", + otp_data_perm = "//util/design/data:data_perm", + otp_mmap = "//hw/top_earlgrey/data/otp:otp_ctrl_mmap.hjson", + rram_scramble_tool = "//util/design:gen-rram-img", slot_spec = EARLGREY_SLOTS, test_cmd = "testing-not-supported", ) @@ -365,7 +368,7 @@ sim_verilator( "--verilator-bin=$(rootpath //hw:verilator)", "--verilator-rom={rom}", "--verilator-otp={otp}", - "--verilator-flash={firmware}", + "--verilator-rram={firmware}", ], base = ":sim_verilator_base", data = [ diff --git a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc index 70dfe412cc01a..82626e7417ccc 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc +++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc @@ -36,18 +36,25 @@ int main(int argc, char **argv) { ".u_flash_ctrl.u_eflash.u_flash." "gen_prim_flash_banks[1].u_prim_flash_bank.u_mem", 0x80000 / 8, 8); + MemArea rram(top_scope + ".u_rram_macro.u_data_array", 0x100000 / 16, 16); + // Start with the flash region erased. Future loads can overwrite. std::vector all_ones(flash0.GetSizeBytes()); std::fill(all_ones.begin(), all_ones.end(), 0xffu); flash0.Write(/*word_offset=*/0, all_ones); flash1.Write(/*word_offset=*/0, all_ones); + std::vector all_zeros(rram.GetSizeBytes()); + std::fill(all_zeros.begin(), all_zeros.end(), 0x00u); + rram.Write(/*word_offset=*/0, all_zeros); + MemArea otp(top_scope + ".u_otp_macro." + ram1p_adv_scope, 0x4000 / 4, 4); memutil.RegisterMemoryArea("rom0", 0x40000, &rom0); memutil.RegisterMemoryArea("ram", 0x10000000u, &ram); memutil.RegisterMemoryArea("flash0", 0x20000000u, &flash0); memutil.RegisterMemoryArea("flash1", 0x20080000u, &flash1); + memutil.RegisterMemoryArea("rram", 0x30000000u, &rram); memutil.RegisterMemoryArea("otp", 0x40000000u /* (bogus LMA) */, &otp); simctrl.RegisterExtension(&memutil); diff --git a/rules/opentitan/sim_dv.bzl b/rules/opentitan/sim_dv.bzl index 121874f0658d0..2a973a117ff20 100644 --- a/rules/opentitan/sim_dv.bzl +++ b/rules/opentitan/sim_dv.bzl @@ -131,17 +131,20 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil src = signed_bin if signed_bin else binary, word_size = 32, ) - vmem = scramble_rram( - ctx, - name = name, - suffix = "128.scr.vmem", - src = vmem_base, - otp = get_fallback(ctx, "file.otp", exec_env), - otp_mmap = exec_env.otp_mmap, - top_secret_cfg = exec_env.top_secret_cfg, - otp_data_perm = exec_env.otp_data_perm, - _tool = exec_env.rram_scramble_tool.files_to_run, - ) + if exec_env.rram_scramble_tool != None: + vmem = scramble_rram( + ctx, + name = name, + suffix = "128.scr.vmem", + src = vmem_base, + otp = get_fallback(ctx, "file.otp", exec_env), + otp_mmap = exec_env.otp_mmap, + top_secret_cfg = exec_env.top_secret_cfg, + otp_data_perm = exec_env.otp_data_perm, + _tool = exec_env.rram_scramble_tool.files_to_run, + ) + else: + vmem = vmem_base rom = None rom32 = None default = vmem diff --git a/rules/opentitan/sim_verilator.bzl b/rules/opentitan/sim_verilator.bzl index 7230396eb8245..2e33493eea27a 100644 --- a/rules/opentitan/sim_verilator.bzl +++ b/rules/opentitan/sim_verilator.bzl @@ -15,6 +15,7 @@ load( "@lowrisc_opentitan//rules/opentitan:transform.bzl", "convert_to_scrambled_rom_vmem", "convert_to_vmem", + "scramble_rram", ) load("//rules/opentitan:toolchain.bzl", "LOCALTOOLS_TOOLCHAIN") @@ -98,12 +99,26 @@ def _transform(ctx, exec_env, name, elf, binary, signed_bin, disassembly, mapfil rom = None rom32 = None elif ctx.attr.kind == "rram": - vmem = convert_to_vmem( + vmem_base = convert_to_vmem( ctx, name = name, src = signed_bin if signed_bin else binary, word_size = 128, ) + if exec_env.rram_scramble_tool != None: + vmem = scramble_rram( + ctx, + name = name, + suffix = "128.scr.vmem", + src = vmem_base, + otp = get_fallback(ctx, "file.otp", exec_env), + otp_mmap = exec_env.otp_mmap, + top_secret_cfg = exec_env.top_secret_cfg, + otp_data_perm = exec_env.otp_data_perm, + _tool = exec_env.rram_scramble_tool.files_to_run, + ) + else: + vmem = vmem_base default = vmem rom = None rom32 = None diff --git a/sw/host/ot_transports/verilator/src/lib.rs b/sw/host/ot_transports/verilator/src/lib.rs index 30e0df0de51a2..f7b884611c053 100644 --- a/sw/host/ot_transports/verilator/src/lib.rs +++ b/sw/host/ot_transports/verilator/src/lib.rs @@ -28,6 +28,8 @@ pub struct VerilatorOpts { #[arg(long, required = false)] verilator_flash: Vec, #[arg(long, default_value_t)] + verilator_rram: String, + #[arg(long, default_value_t)] verilator_ctn_ram: String, #[arg(long, default_value_t)] verilator_otp: String, @@ -50,6 +52,7 @@ impl Backend for VerilatorBackend { executable: args.verilator_bin.clone(), rom_images: args.verilator_rom.clone(), flash_images: args.verilator_flash.clone(), + rram_image: args.verilator_rram.clone(), ctn_ram_image: args.verilator_ctn_ram.clone(), otp_image: args.verilator_otp.clone(), extra_args: args.verilator_args.clone(), diff --git a/sw/host/ot_transports/verilator/src/subprocess.rs b/sw/host/ot_transports/verilator/src/subprocess.rs index 5f98158f7a91b..b5a4d57c14087 100644 --- a/sw/host/ot_transports/verilator/src/subprocess.rs +++ b/sw/host/ot_transports/verilator/src/subprocess.rs @@ -26,6 +26,8 @@ pub struct Options { /// slot number (defaults to 0). /// Example: ["app.bin", "app.bin:1", "data.bin:2"] pub flash_images: Vec, + /// The image to load into RRAM. + pub rram_image: String, /// The image to load into CTN RAM. pub ctn_ram_image: String, /// The OTP settings. @@ -81,6 +83,9 @@ impl Subprocess { args.push(format!("--meminit=flash{},{}", slot, image_file)); } } + if !options.rram_image.is_empty() { + args.push(format!("--meminit=rram,{}", options.rram_image)); + } if !options.ctn_ram_image.is_empty() { args.push(format!("--meminit=ctn_ram,{}", options.ctn_ram_image)); } From 47a520e8ce449359f9c574e0dd6eb1b5f5b23623 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 28 May 2026 09:38:49 +0200 Subject: [PATCH 11/41] [rom_ext,sw] rename section rom_ext_flash to rom_ext_nvm This commit renames the rom_ext_flash section to rom_ext_nvm which can be used for RRAM and flash. Signed-off-by: Michael Gautschi --- sw/device/lib/testing/test_rom/test_rom.c | 6 +++--- .../rom_ext/imm_section/imm_section_common.ld | 16 +++++++-------- .../rom_ext/imm_section/imm_section_slot_a.ld | 2 +- .../rom_ext/imm_section/imm_section_slot_b.ld | 2 +- .../imm_section/imm_section_slot_virtual.ld | 2 +- sw/device/silicon_creator/rom_ext/rom_ext.c | 6 +++--- .../silicon_creator/rom_ext/rom_ext_common.ld | 20 +++++++++---------- .../silicon_creator/rom_ext/rom_ext_slot_a.ld | 6 +++--- .../silicon_creator/rom_ext/rom_ext_slot_b.ld | 6 +++--- .../rom_ext/rom_ext_slot_virtual.ld | 2 +- .../ot_transports/verilator/src/subprocess.rs | 1 + 11 files changed, 35 insertions(+), 34 deletions(-) diff --git a/sw/device/lib/testing/test_rom/test_rom.c b/sw/device/lib/testing/test_rom/test_rom.c index da2b068f578ff..ac13fc7be15e3 100644 --- a/sw/device/lib/testing/test_rom/test_rom.c +++ b/sw/device/lib/testing/test_rom/test_rom.c @@ -231,12 +231,12 @@ bool rom_test_main(void) { entry_point = rom_ext_vma_get(manifest, entry_point); } - // Jump to the OTTF in flash. Within the flash binary, it is the + // Jump to the OTTF in NVM. Within the flash/RRAM binary, it is the // responsibily of the OTTF to set up its own stack, and to never return. - LOG_INFO("Test ROM complete, jumping to flash (addr: %x)!", entry_point); + LOG_INFO("Test ROM complete, jumping to NVM (addr: %x)!", entry_point); ((ottf_entry_point *)entry_point)(); - // If the flash image returns, we should abort anyway. + // If the NVM image returns, we should abort anyway. abort(); } diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld index 45d7904968f62..13e8e11b52616 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld @@ -19,7 +19,7 @@ _dv_log_offset = 0x10000; ENTRY(_imm_section_start_boot) -REGION_ALIAS("coverage_flash", rom_ext_flash); +REGION_ALIAS("coverage_flash", rom_ext_nvm); SECTIONS { /** @@ -32,14 +32,14 @@ SECTIONS { _text_start = .; _rom_ext_immutable_start = .; KEEP(*(.vectors)) - } > rom_ext_flash + } > rom_ext_nvm /** * C runtime (CRT) section, containing program initialization code. */ .crt : ALIGN(4) { KEEP(*(.crt)) - } > rom_ext_flash + } > rom_ext_nvm /** * Standard text section, containing program code. @@ -50,7 +50,7 @@ SECTIONS { /* Ensure section end is word-aligned. */ . = ALIGN(4); - } > rom_ext_flash + } > rom_ext_nvm /** * Shutdown text section, containing shutdown function(s). @@ -64,7 +64,7 @@ SECTIONS { /* Ensure section end is word-aligned. */ . = ALIGN(4); _text_end = .; - } > rom_ext_flash + } > rom_ext_nvm /** * Read-only data section, containing all large compile-time constants, like @@ -77,7 +77,7 @@ SECTIONS { *(.srodata.*) *(.rodata) *(.rodata.*) - } > rom_ext_flash + } > rom_ext_nvm INCLUDE sw/device/lib/coverage/rodata.ld @@ -136,7 +136,7 @@ SECTIONS { * * Using `AT>` means we don't have to keep track of the next free part of * flash, as we do in our other linker scripts. */ - } > ram_main AT> rom_ext_flash + } > ram_main AT> rom_ext_nvm /** * Standard BSS section. This will be zeroed at runtime by the CRT. @@ -173,5 +173,5 @@ SECTIONS { ASSERT( SIZEOF(.imm_section_version) == 32, "Error: immutable section version string should be exactly 32 bytes"); - } > rom_ext_flash + } > rom_ext_nvm } diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld index 51b26f9c70fb9..1313d3b9a063d 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld @@ -22,6 +22,6 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld MEMORY { imm_section_slot_a(rx) : ORIGIN = ORIGIN(eflash) + 0x400, LENGTH = LENGTH(eflash) / 2 - 0x400 } -REGION_ALIAS("rom_ext_flash", imm_section_slot_a); +REGION_ALIAS("rom_ext_nvm", imm_section_slot_a); INCLUDE sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld index 7dd0e412344e8..b48fd21d542b2 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld @@ -23,6 +23,6 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld MEMORY { imm_section_slot_b(rx) : ORIGIN = ORIGIN(eflash) + LENGTH(eflash) / 2 + 0x400, LENGTH = LENGTH(eflash) / 2 - 0x400 } -REGION_ALIAS("rom_ext_flash", imm_section_slot_b); +REGION_ALIAS("rom_ext_nvm", imm_section_slot_b); INCLUDE sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld index 9f5e9dfcdd1c9..2c2b133932793 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_virtual.ld @@ -22,6 +22,6 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld MEMORY { imm_section_virtual(rx) : ORIGIN = ORIGIN(rom_ext_virtual) + 0x400, LENGTH = 0x80000 - 0x400 } -REGION_ALIAS("rom_ext_flash", imm_section_virtual); +REGION_ALIAS("rom_ext_nvm", imm_section_virtual); INCLUDE sw/device/silicon_creator/rom_ext/imm_section/imm_section_common.ld diff --git a/sw/device/silicon_creator/rom_ext/rom_ext.c b/sw/device/silicon_creator/rom_ext/rom_ext.c index 67ee1179f40cc..700e7bb92516b 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext.c +++ b/sw/device/silicon_creator/rom_ext/rom_ext.c @@ -443,7 +443,7 @@ static rom_error_t rom_ext_try_next_stage(boot_data_t *boot_data, return error; } -static void rom_ext_flash_protect_self(uint32_t rom_ext_slot) { +static void rom_ext_nvm_protect_self(uint32_t rom_ext_slot) { nvm_page_cfg_t cfg = nvm_ctrl_data_default_cfg_get(); nvm_page_perms_t read = { .read = kMultiBitBool4True, @@ -568,8 +568,8 @@ static rom_error_t rom_ext_start(boot_data_t *boot_data, boot_log_t *boot_log) { // of `boot_data`. boot_log->primary_bl0_slot = boot_data->primary_bl0_slot; - // Protect the flash pages where the ROM_EXT is located. - rom_ext_flash_protect_self(boot_log->rom_ext_slot); + // Protect the NVM pages where the ROM_EXT is located. + rom_ext_nvm_protect_self(boot_log->rom_ext_slot); // Initialize the chip ownership state. rom_error_t error; diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_common.ld b/sw/device/silicon_creator/rom_ext/rom_ext_common.ld index 0b904b8c782b1..5f5af3e322cb8 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_common.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_common.ld @@ -56,7 +56,7 @@ _manifest_address_translation = (_text_start >= ORIGIN(eflash) && _text_start < (ORIGIN(eflash) + LENGTH(eflash))) ? 0x1d4 : 0x739; -REGION_ALIAS("coverage_flash", rom_ext_flash); +REGION_ALIAS("coverage_flash", rom_ext_nvm); /** * NOTE: We have to align each section to word boundaries as our current @@ -66,7 +66,7 @@ SECTIONS { .manifest _rom_ext_start_address : { KEEP(*(.manifest)) . = ALIGN(4); - } > rom_ext_flash + } > rom_ext_nvm /** * Immutable ROM_EXT section. @@ -81,7 +81,7 @@ SECTIONS { _rom_ext_immutable_end = .; _rom_ext_immutable_size = SIZEOF(.rom_ext_immutable); - } > rom_ext_flash + } > rom_ext_nvm /** * Ibex interrupt vector. @@ -91,14 +91,14 @@ SECTIONS { */ .vectors : ALIGN(256) { KEEP(*(.vectors)) - } > rom_ext_flash + } > rom_ext_nvm /** * C runtime (CRT) section, containing program initialization code. */ .crt : ALIGN(4) { KEEP(*(.crt)) - } > rom_ext_flash + } > rom_ext_nvm /** * Standard text section, containing program code. @@ -109,7 +109,7 @@ SECTIONS { /* Ensure section end is word-aligned. */ . = ALIGN(4); - } > rom_ext_flash + } > rom_ext_nvm /** * ROM_EXT ISRs text section, containing the exception handler entry/exit logic @@ -123,7 +123,7 @@ SECTIONS { /* Ensure section end is word-aligned. */ . = ALIGN(4); - } > rom_ext_flash + } > rom_ext_nvm /** * Shutdown text section, containing shutdown function(s). @@ -137,7 +137,7 @@ SECTIONS { /* Ensure section end is word-aligned. */ . = ALIGN(4); _text_end = .; - } > rom_ext_flash + } > rom_ext_nvm /** * Read-only data section, containing all large compile-time constants, like @@ -150,7 +150,7 @@ SECTIONS { *(.srodata.*) *(.rodata) *(.rodata.*) - } > rom_ext_flash + } > rom_ext_nvm INCLUDE sw/device/lib/coverage/rodata.ld @@ -208,7 +208,7 @@ SECTIONS { * * Using `AT>` means we don't have to keep track of the next free part of * flash, as we do in our other linker scripts. */ - } > ram_main AT> rom_ext_flash + } > ram_main AT> rom_ext_nvm /** * Standard BSS section. This will be zeroed at runtime by the CRT. diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld index 61fa142539e3e..9fc12083af6cc 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld @@ -15,9 +15,9 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld /* Slot A starts at begining of the eFlash. */ -_rom_ext_size = LENGTH(eflash) / 2; -_rom_ext_start_address = ORIGIN(eflash); +_rom_ext_size = LENGTH(rram) / 2; +_rom_ext_start_address = ORIGIN(rram); -REGION_ALIAS("rom_ext_flash", eflash); +REGION_ALIAS("rom_ext_nvm", rram); INCLUDE sw/device/silicon_creator/rom_ext/rom_ext_common.ld diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld index 0c4c2e4382290..377505266831d 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld @@ -15,9 +15,9 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld /* Slot B starts at the half-size mark of the eFlash. */ -_rom_ext_size = LENGTH(eflash) / 2; -_rom_ext_start_address = ORIGIN(eflash) + _rom_ext_size; +_rom_ext_size = LENGTH(rram) / 2; +_rom_ext_start_address = ORIGIN(rram) + _rom_ext_size; -REGION_ALIAS("rom_ext_flash", eflash); +REGION_ALIAS("rom_ext_nvm", rram); INCLUDE sw/device/silicon_creator/rom_ext/rom_ext_common.ld diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld index e7bcc43fe83a4..8774a8cdfb657 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld @@ -23,6 +23,6 @@ _rom_ext_start_address = ORIGIN(rom_ext_virtual); _rom_ext_size = LENGTH(rom_ext_virtual); ASSERT((_rom_ext_size <= (LENGTH(eflash) / 2)), "Error: rom ext flash is bigger than slot"); -REGION_ALIAS("rom_ext_flash", rom_ext_virtual); +REGION_ALIAS("rom_ext_nvm", rom_ext_virtual); INCLUDE sw/device/silicon_creator/rom_ext/rom_ext_common.ld diff --git a/sw/host/ot_transports/verilator/src/subprocess.rs b/sw/host/ot_transports/verilator/src/subprocess.rs index b5a4d57c14087..5822c5d9c3d46 100644 --- a/sw/host/ot_transports/verilator/src/subprocess.rs +++ b/sw/host/ot_transports/verilator/src/subprocess.rs @@ -164,6 +164,7 @@ mod test { executable: "/bin/echo".to_owned(), rom_images: vec!["/dev/null:1".to_owned()], flash_images: vec!["/dev/null:1".to_owned()], + rram_image: "".to_owned(), otp_image: "".to_owned(), ctn_ram_image: "".to_owned(), extra_args: vec!["abc 123 def 456".to_owned()], From 93085fecf9b318ddfa258260a66bd2243d282918 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 18 Jun 2026 10:53:17 +0200 Subject: [PATCH 12/41] [top,rtl] Connect rram_ctrl to otp_ctrl This commits removes the connection from flash_ctrl to otp_ctrl to fetch the scrambling keys and adds them to rram_ctrl. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/top_earlgrey.hjson | 4 ++-- hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 254897ba3dbc5..ea23ef360cfea 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1173,7 +1173,7 @@ 'aon_timer.nmi_wdog_timer_bark' : ['rv_core_ibex.nmi_wdog'], 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'], 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'], - 'flash_ctrl.otp' : ['otp_ctrl.nvm_otp_key'], + 'rram_ctrl.otp_key' : ['otp_ctrl.nvm_otp_key'], 'lc_ctrl.lc_nvm_rma_seed' : ['flash_ctrl.rma_seed', 'rram_ctrl.rma_seed'], 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', 'sram_ctrl_sec.sram_otp_key', @@ -1361,7 +1361,7 @@ // Xbars // Temporary RRAM helpers - 'rram_ctrl.otp_key', + 'flash_ctrl.otp', 'flash_ctrl.keymgr', 'rram_ctrl.keymgr', 'keymgr.flash', diff --git a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl index ac029d4deddb0..160caaae67749 100644 --- a/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl +++ b/hw/top_earlgrey/templates/earlgrey_pd_main.sv.tpl @@ -72,12 +72,12 @@ module ${top["name"]}_pd_${domain.lower()} #( % endif % if m.get("name") == "rram_ctrl": - // TODO: remove once RRAM is connected to OTP - assign rram_ctrl_otp_key_rsp.data_ack = rram_ctrl_otp_key_req.data_req; - assign rram_ctrl_otp_key_rsp.addr_ack = rram_ctrl_otp_key_req.addr_req; - assign rram_ctrl_otp_key_rsp.key = '0; - assign rram_ctrl_otp_key_rsp.rand_key = '0; - assign rram_ctrl_otp_key_rsp.seed_valid = 1'b0; + // TODO: remove once flash_ctrl is removed + assign flash_ctrl_otp_rsp.data_ack = flash_ctrl_otp_req.data_req; + assign flash_ctrl_otp_rsp.addr_ack = flash_ctrl_otp_req.addr_req; + assign flash_ctrl_otp_rsp.key = '0; + assign flash_ctrl_otp_rsp.rand_key = '0; + assign flash_ctrl_otp_rsp.seed_valid = 1'b0; // TODO: remove once keymgr has been updated assign keymgr_flash.seeds = rram_ctrl_keymgr.seeds; From 19105ab395023e173b9b3049a025d15683203eb4 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 18 Jun 2026 10:53:44 +0200 Subject: [PATCH 13/41] [top,rtl] Autogen files for rram_ctrl to otp_ctrl This commit contains the autogen changes to connect rram_ctrl to otp_ctrl to fetch the scrambling keys Signed-off-by: Michael Gautschi --- .../data/autogen/top_earlgrey.gen.hjson | 24 +++++++++---------- .../rtl/autogen/earlgrey_pd_main.sv | 24 +++++++++---------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index d8604d2920643..f8e8252e6d4c6 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -1955,7 +1955,7 @@ default: "'0" inst_name: otp_ctrl domain: Main - top_signame: flash_ctrl_otp + top_signame: rram_ctrl_otp_key index: -1 } { @@ -6113,8 +6113,6 @@ width: 1 inst_name: flash_ctrl default: "" - end_idx: -1 - top_type: one-to-one top_signame: flash_ctrl_otp index: -1 } @@ -6528,6 +6526,8 @@ width: 1 inst_name: rram_ctrl default: "" + end_idx: -1 + top_type: one-to-one top_signame: rram_ctrl_otp_key index: -1 } @@ -10651,7 +10651,7 @@ [ entropy_src.entropy_src_hw_if ] - flash_ctrl.otp: + rram_ctrl.otp_key: [ otp_ctrl.nvm_otp_key ] @@ -11218,7 +11218,7 @@ rv_core_ibex.irq_timer rv_core_ibex.hart_id rv_core_ibex.boot_addr - rram_ctrl.otp_key + flash_ctrl.otp flash_ctrl.keymgr rram_ctrl.keymgr keymgr.flash @@ -22154,7 +22154,7 @@ default: "'0" inst_name: otp_ctrl domain: Main - top_signame: flash_ctrl_otp + top_signame: rram_ctrl_otp_key index: -1 } { @@ -24959,8 +24959,6 @@ width: 1 inst_name: flash_ctrl default: "" - end_idx: -1 - top_type: one-to-one top_signame: flash_ctrl_otp index: -1 } @@ -25283,6 +25281,8 @@ width: 1 inst_name: rram_ctrl default: "" + end_idx: -1 + top_type: one-to-one top_signame: rram_ctrl_otp_key index: -1 } @@ -33061,7 +33061,7 @@ package: otp_ctrl_pkg struct: nvm_otp_key_req domain: Main - signame: flash_ctrl_otp_req + signame: rram_ctrl_otp_key_req width: 1 type: req_rsp end_idx: -1 @@ -33073,7 +33073,7 @@ package: otp_ctrl_pkg struct: nvm_otp_key_rsp domain: Main - signame: flash_ctrl_otp_rsp + signame: rram_ctrl_otp_key_rsp width: 1 type: req_rsp end_idx: -1 @@ -35183,7 +35183,7 @@ package: otp_ctrl_pkg struct: nvm_otp_key_req domain: Main - signame: rram_ctrl_otp_key_req + signame: flash_ctrl_otp_req width: 1 type: req_rsp end_idx: -1 @@ -35193,7 +35193,7 @@ package: otp_ctrl_pkg struct: nvm_otp_key_rsp domain: Main - signame: rram_ctrl_otp_key_rsp + signame: flash_ctrl_otp_rsp width: 1 type: req_rsp end_idx: -1 diff --git a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv index 5f0c2a8d76759..1243cba2f86d6 100644 --- a/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv +++ b/hw/top_earlgrey/rtl/autogen/earlgrey_pd_main.sv @@ -642,8 +642,8 @@ module earlgrey_pd_main #( csrng_pkg::csrng_rsp_t [1:0] csrng_csrng_cmd_rsp; entropy_src_pkg::entropy_src_hw_if_req_t csrng_entropy_src_hw_if_req; entropy_src_pkg::entropy_src_hw_if_rsp_t csrng_entropy_src_hw_if_rsp; - otp_ctrl_pkg::nvm_otp_key_req_t flash_ctrl_otp_req; - otp_ctrl_pkg::nvm_otp_key_rsp_t flash_ctrl_otp_rsp; + otp_ctrl_pkg::nvm_otp_key_req_t rram_ctrl_otp_key_req; + otp_ctrl_pkg::nvm_otp_key_rsp_t rram_ctrl_otp_key_rsp; lc_ctrl_pkg::lc_nvm_rma_seed_t lc_ctrl_lc_nvm_rma_seed; otp_ctrl_pkg::sram_otp_key_req_t [3:0] otp_ctrl_sram_otp_key_req; otp_ctrl_pkg::sram_otp_key_rsp_t [3:0] otp_ctrl_sram_otp_key_rsp; @@ -803,8 +803,8 @@ module earlgrey_pd_main #( logic rv_core_ibex_irq_timer; logic [31:0] rv_core_ibex_hart_id; logic [31:0] rv_core_ibex_boot_addr; - otp_ctrl_pkg::nvm_otp_key_req_t rram_ctrl_otp_key_req; - otp_ctrl_pkg::nvm_otp_key_rsp_t rram_ctrl_otp_key_rsp; + otp_ctrl_pkg::nvm_otp_key_req_t flash_ctrl_otp_req; + otp_ctrl_pkg::nvm_otp_key_rsp_t flash_ctrl_otp_rsp; flash_ctrl_pkg::keymgr_flash_t flash_ctrl_keymgr; rram_ctrl_pkg::keymgr_rram_t rram_ctrl_keymgr; flash_ctrl_pkg::keymgr_flash_t keymgr_flash; @@ -871,12 +871,12 @@ module earlgrey_pd_main #( otp_ctrl_keymgr_owner_seed }; - // TODO: remove once RRAM is connected to OTP - assign rram_ctrl_otp_key_rsp.data_ack = rram_ctrl_otp_key_req.data_req; - assign rram_ctrl_otp_key_rsp.addr_ack = rram_ctrl_otp_key_req.addr_req; - assign rram_ctrl_otp_key_rsp.key = '0; - assign rram_ctrl_otp_key_rsp.rand_key = '0; - assign rram_ctrl_otp_key_rsp.seed_valid = 1'b0; + // TODO: remove once flash_ctrl is removed + assign flash_ctrl_otp_rsp.data_ack = flash_ctrl_otp_req.data_req; + assign flash_ctrl_otp_rsp.addr_ack = flash_ctrl_otp_req.addr_req; + assign flash_ctrl_otp_rsp.key = '0; + assign flash_ctrl_otp_rsp.rand_key = '0; + assign flash_ctrl_otp_rsp.seed_valid = 1'b0; // TODO: remove once keymgr has been updated assign keymgr_flash.seeds = rram_ctrl_keymgr.seeds; @@ -1549,8 +1549,8 @@ module earlgrey_pd_main #( .keymgr_creator_root_key_o(otp_ctrl_keymgr_creator_root_key), .keymgr_creator_seed_o(otp_ctrl_keymgr_creator_seed), .keymgr_owner_seed_o(otp_ctrl_keymgr_owner_seed), - .nvm_otp_key_i(flash_ctrl_otp_req), - .nvm_otp_key_o(flash_ctrl_otp_rsp), + .nvm_otp_key_i(rram_ctrl_otp_key_req), + .nvm_otp_key_o(rram_ctrl_otp_key_rsp), .sram_otp_key_i(otp_ctrl_sram_otp_key_req), .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp), .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), From f747d0002bda60d2693efbaca729acda2e6cba80 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Thu, 18 Jun 2026 11:06:06 +0200 Subject: [PATCH 14/41] [CI,rram_ctrl,flash_ctrl] Disable chip_sw_flash_scrambling_smoketest This test needs to be ported to RRAM because the scrambling keys are now read from RRAM instead of flash. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/data/chip_testplan.hjson | 2 +- hw/top_earlgrey/dv/chip_sim_cfg.hjson | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson index ae6864e9aa32b..ca80407abf40f 100644 --- a/hw/top_earlgrey/data/chip_testplan.hjson +++ b/hw/top_earlgrey/data/chip_testplan.hjson @@ -448,7 +448,7 @@ "chip_sw_rstmgr_smoketest", "chip_sw_sram_ctrl_smoketest", "chip_sw_uart_smoketest", - "chip_sw_flash_scrambling_smoketest", + #"chip_sw_flash_scrambling_smoketest", TODO: Replace with RRAM test ] bazel: [ "//sw/device/tests:aes_smoketest", diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index ba5326536b314..2c30f3f6738fd 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -2196,7 +2196,7 @@ "//sw/device/tests:flash_scrambling_smoketest:1:new_rules", "//sw/device/tests:flash_scrambling_smoketest_otp_img_rma:4", ] - en_run_modes: ["sw_test_mode_test_rom"] + en_run_modes: [] // disabled: needs to be ported to RRAM run_opts: ["+use_otp_image=OtpTypeCustom"] } { @@ -2225,7 +2225,7 @@ "chip_sw_spi_device_pass_through", "chip_sw_i2c_host_tx_rx", "chip_sw_i2c_device_tx_rx", - "chip_sw_flash_scrambling_smoketest", + # "chip_sw_flash_scrambling_smoketest", TODO: port to RRAM "chip_plic_all_irqs_0", "chip_plic_all_irqs_10", "chip_plic_all_irqs_20", From e330c248709459febbb3d96cd60c31c524452f0f Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 11 Mar 2026 11:55:22 +0100 Subject: [PATCH 15/41] [rram_ctrl,sw] rram_ctrl dif functions Add dif_rram_ctrl to initialize and configure the RRAM controller aswell as simple functions to perform read/write operations to the RRAM Signed-off-by: Michael Gautschi --- sw/device/lib/dif/BUILD | 1 + sw/device/lib/dif/dif_rram_ctrl.c | 993 ++++++++++++++++++++ sw/device/lib/dif/dif_rram_ctrl.h | 922 ++++++++++++++++++ sw/device/lib/dif/dif_rram_ctrl.md | 58 ++ sw/device/lib/dif/dif_rram_ctrl_unittest.cc | 41 + sw/device/lib/testing/test_rom/BUILD | 12 + 6 files changed, 2027 insertions(+) create mode 100644 sw/device/lib/dif/dif_rram_ctrl.c create mode 100644 sw/device/lib/dif/dif_rram_ctrl.h create mode 100644 sw/device/lib/dif/dif_rram_ctrl.md create mode 100644 sw/device/lib/dif/dif_rram_ctrl_unittest.cc diff --git a/sw/device/lib/dif/BUILD b/sw/device/lib/dif/BUILD index 1d1e0fa4a0229..55dfa88d78671 100644 --- a/sw/device/lib/dif/BUILD +++ b/sw/device/lib/dif/BUILD @@ -55,6 +55,7 @@ DIFS = { }, "entropy_src": {}, "flash_ctrl": {}, + "rram_ctrl": {}, "gpio": {}, "hmac": {}, "i2c": {}, diff --git a/sw/device/lib/dif/dif_rram_ctrl.c b/sw/device/lib/dif/dif_rram_ctrl.c new file mode 100644 index 0000000000000..2fc1b1af860e2 --- /dev/null +++ b/sw/device/lib/dif/dif_rram_ctrl.c @@ -0,0 +1,993 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/dif/dif_rram_ctrl.h" + +#include + +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/base/multibits.h" + +// Generated. +#include "hw/top/rram_ctrl_regs.h" + +/** + * Helper function to get the offset of a data region's configuration register. + * Does not check that the region actually exists, which is deferred to callers. + * Since data region registers are split into two (one containing properties the + * other containing address info), there are two helper functions below. + * + * @param region The data region's index. + * @return The offset from the RRAM controller's base address where the region + * configuration register is located. + */ +OT_WARN_UNUSED_RESULT +static ptrdiff_t get_data_region_mp_reg_offset(uint32_t region) { + return RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET + + (ptrdiff_t)region * (ptrdiff_t)sizeof(uint32_t); +} + +OT_WARN_UNUSED_RESULT +static ptrdiff_t get_data_region_reg_offset(uint32_t region) { + return RRAM_CTRL_MP_REGION_0_REG_OFFSET + + (ptrdiff_t)region * (ptrdiff_t)sizeof(uint32_t); +} + +OT_WARN_UNUSED_RESULT +static ptrdiff_t get_data_region_lock_reg_offset(uint32_t region) { + return RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET + + (ptrdiff_t)region * (ptrdiff_t)sizeof(uint32_t); +} + +// generated parameters from hjson +static const uint32_t kNumInfoPages = RRAM_CTRL_PARAM_NUM_INFO_PAGES; +static const uint32_t kNumDataPages = RRAM_CTRL_PARAM_NUM_DATA_PAGES; +static const uint32_t kBytesPerWord = RRAM_CTRL_PARAM_BYTES_PER_WORD; +static const uint32_t kBytesPerPage = RRAM_CTRL_PARAM_BYTES_PER_PAGE; +static const uint32_t kExecEn = RRAM_CTRL_PARAM_EXEC_EN; +static const uint32_t kNumRegions = RRAM_CTRL_PARAM_NUM_REGIONS; + +/** + * Helper function to get the offset of an info region's configuration register. + * Does not check that the region actually exists, which is deferred to callers. + * + * @param region The info region's description. + * @return The offset from the RRAM controller's base address where the region + * configuration register is located. + */ +OT_WARN_UNUSED_RESULT +static ptrdiff_t get_info_region_mp_reg_offset( + dif_rram_ctrl_info_region_t region) { + return RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET + + (ptrdiff_t)region.page * (ptrdiff_t)sizeof(uint32_t); +} + +OT_WARN_UNUSED_RESULT +static ptrdiff_t get_info_region_lock_reg_offset( + dif_rram_ctrl_info_region_t region) { + return RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET + + (ptrdiff_t)region.page * (ptrdiff_t)sizeof(uint32_t); +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_init_state(dif_rram_ctrl_state_t *handle, + mmio_region_t base_addr) { + if (handle == NULL) { + return kDifBadArg; + } + dif_result_t result = dif_rram_ctrl_init(base_addr, &handle->dev); + if (result != kDifOk) { + return result; + } + handle->words_remaining = 0; + handle->transaction_pending = false; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_init_state_from_dt(dif_rram_ctrl_state_t *handle, + dt_rram_ctrl_t dt) { + return dif_rram_ctrl_init_state( + handle, mmio_region_from_addr(dt_rram_ctrl_primary_reg_block(dt))); +} + +OT_WARN_UNUSED_RESULT +dif_rram_ctrl_device_info_t dif_rram_ctrl_get_device_info(void) { + const dif_rram_ctrl_device_info_t info = { + .bytes_per_word = kBytesPerWord, + .bytes_per_page = kBytesPerPage, + .data_pages = kNumDataPages, + .info_pages = kNumInfoPages, + }; + return info; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_rram_enablement(dif_rram_ctrl_state_t *handle, + dif_toggle_t enable) { + enum multi_bit_bool disable_rram; + if (handle == NULL) { + return kDifBadArg; + } + switch (enable) { + case kDifToggleEnabled: + disable_rram = kMultiBitBool4False; + break; + case kDifToggleDisabled: + disable_rram = kMultiBitBool4True; + break; + default: + return kDifBadArg; + } + uint32_t reg; + reg = mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_DIS_REG_OFFSET); + reg = bitfield_field32_write(reg, RRAM_CTRL_DIS_SW_DIS_FIELD, disable_rram); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_DIS_REG_OFFSET, reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_rram_enablement( + const dif_rram_ctrl_state_t *handle, dif_toggle_t *enabled_out) { + if (handle == NULL || enabled_out == NULL) { + return kDifBadArg; + } + uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_DIS_REG_OFFSET); + enum multi_bit_bool rram_disabled = + bitfield_field32_read(reg, RRAM_CTRL_DIS_SW_DIS_FIELD); + if (rram_disabled == kMultiBitBool4False) { + *enabled_out = kDifToggleEnabled; + } else { + *enabled_out = kDifToggleDisabled; + } + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_exec_enablement(dif_rram_ctrl_state_t *handle, + dif_toggle_t enable) { + uint32_t value; + if (handle == NULL) { + return kDifBadArg; + } + switch (enable) { + case kDifToggleEnabled: + value = kExecEn; + break; + case kDifToggleDisabled: + value = 0; + break; + default: + return kDifBadArg; + } + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_EXEC_REG_OFFSET, value); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_exec_enablement( + const dif_rram_ctrl_state_t *handle, dif_toggle_t *enabled_out) { + if (handle == NULL || enabled_out == NULL) { + return kDifBadArg; + } + uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_EXEC_REG_OFFSET); + if (reg == kExecEn) { + *enabled_out = kDifToggleEnabled; + } else { + *enabled_out = kDifToggleDisabled; + } + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_start_controller_init( + dif_rram_ctrl_state_t *handle) { + if (handle == NULL) { + return kDifBadArg; + } + const uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_INIT_REG_OFFSET); + if (bitfield_bit32_read(reg, RRAM_CTRL_INIT_VAL_BIT)) { + // Controller initialization may only be requested once. + return kDifError; + } + uint32_t value = bitfield_bit32_write(0, RRAM_CTRL_INIT_VAL_BIT, true); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_INIT_REG_OFFSET, value); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_status(const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_status_t *status_out) { + if (handle == NULL || status_out == NULL) { + return kDifBadArg; + } + uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_STATUS_REG_OFFSET); + dif_rram_ctrl_status_t status = { + .read_fifo_full = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_RD_FULL_BIT), + .read_fifo_empty = + bitfield_bit32_read(reg, RRAM_CTRL_STATUS_RD_EMPTY_BIT), + .write_fifo_full = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_WR_FULL_BIT), + .write_fifo_empty = + bitfield_bit32_read(reg, RRAM_CTRL_STATUS_WR_EMPTY_BIT), + .controller_init_done = + bitfield_bit32_read(reg, RRAM_CTRL_STATUS_INIT_DONE_BIT), + .controller_keys_valid = + bitfield_bit32_read(reg, RRAM_CTRL_STATUS_KEYS_VALID_BIT), + }; + *status_out = status; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_start_unsafe( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_transaction_t transaction) { + if (handle == NULL) { + return kDifBadArg; + } + uint32_t ctrl_regwen = mmio_region_read32(handle->dev.base_addr, + RRAM_CTRL_CTRL_REGWEN_REG_OFFSET); + if (!bitfield_bit32_read(ctrl_regwen, RRAM_CTRL_CTRL_REGWEN_EN_BIT)) { + return kDifUnavailable; + } + + // Hardware ignores the NUM field for kDifRramCtrlOpRewrite (a rewrite always + // affects exactly one word), so `transaction.word_count` is not meaningful + // for that operation and isn't validated in `dif_rram_ctrl_start()`. + uint32_t control_reg = bitfield_field32_write(0, RRAM_CTRL_CONTROL_NUM_FIELD, + transaction.word_count - 1); + switch (transaction.op) { + case kDifRramCtrlOpRead: + control_reg = + bitfield_field32_write(control_reg, RRAM_CTRL_CONTROL_OP_FIELD, + RRAM_CTRL_CONTROL_OP_VALUE_READ); + break; + case kDifRramCtrlOpWrite: + control_reg = + bitfield_field32_write(control_reg, RRAM_CTRL_CONTROL_OP_FIELD, + RRAM_CTRL_CONTROL_OP_VALUE_WRITE); + break; + case kDifRramCtrlOpRewrite: + control_reg = + bitfield_field32_write(control_reg, RRAM_CTRL_CONTROL_OP_FIELD, + RRAM_CTRL_CONTROL_OP_VALUE_REWRITE); + break; + default: + return kDifBadArg; + } + + switch (transaction.partition_type) { + case kDifRramCtrlPartitionTypeData: + control_reg = bitfield_bit32_write( + control_reg, RRAM_CTRL_CONTROL_PARTITION_BIT, false); + break; + case kDifRramCtrlPartitionTypeInfo: + control_reg = bitfield_bit32_write(control_reg, + RRAM_CTRL_CONTROL_PARTITION_BIT, true); + break; + default: + return kDifBadArg; + } + + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_CONTROL_REG_OFFSET, + control_reg); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_ADDR_REG_OFFSET, + transaction.byte_address); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_CONTROL_REG_OFFSET, + control_reg | (1u << RRAM_CTRL_CONTROL_START_BIT)); + if (transaction.op == kDifRramCtrlOpRewrite) { + // Rewrite operations don't use the FIFO + handle->words_remaining = 0; + } else { + handle->words_remaining = transaction.word_count; + } + handle->transaction_pending = true; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_start(dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_transaction_t transaction) { + if (handle == NULL) { + return kDifBadArg; + } + + const uint32_t max_word_count = RRAM_CTRL_CONTROL_NUM_MASK; + if (transaction.op != kDifRramCtrlOpRewrite) { + if (transaction.word_count - 1 > max_word_count || + transaction.word_count == 0) { + return kDifBadArg; + } + } + // We can only write a multiple of 4 32b words + if (transaction.op == kDifRramCtrlOpWrite) { + if (transaction.word_count % 4 != 0) { + return kDifBadArg; + } + } + + // start address must be aligned to 16 bytes for write operations + if (transaction.op == kDifRramCtrlOpWrite) { + if (transaction.byte_address % 16 != 0) { + return kDifBadArg; + } + } + + if (handle->transaction_pending) { + return kDifUnavailable; + } + + // Disallow starting a new transaction if the FIFOs haven't been emptied yet. + dif_rram_ctrl_status_t status; + dif_result_t result = dif_rram_ctrl_get_status(handle, &status); + if (result != kDifOk) { + return result; + } + if (!status.read_fifo_empty || !status.write_fifo_empty) { + return kDifIpFifoFull; + } + + return dif_rram_ctrl_start_unsafe(handle, transaction); +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_wr_fifo_push_unsafe(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + const uint32_t *data) { + if (handle == NULL || data == NULL) { + return kDifBadArg; + } + uint32_t written = 0; + while (written < word_count) { + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_WR_FIFO_REG_OFFSET, + data[written]); + ++written; + } + handle->words_remaining -= written; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_wr_fifo_push(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + const uint32_t *data) { + if (handle == NULL || data == NULL) { + return kDifBadArg; + } + if (!handle->transaction_pending) { + return kDifError; + } + if (handle->words_remaining < word_count) { + return kDifBadArg; + } + const uint32_t control_reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_CONTROL_REG_OFFSET); + const uint32_t op = + bitfield_field32_read(control_reg, RRAM_CTRL_CONTROL_OP_FIELD); + if (op != RRAM_CTRL_CONTROL_OP_VALUE_WRITE) { + return kDifError; + } + return dif_rram_ctrl_wr_fifo_push_unsafe(handle, word_count, data); +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_read_fifo_pop_unsafe(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + uint32_t *data) { + if (handle == NULL || data == NULL) { + return kDifBadArg; + } + uint32_t read = 0; + while (read < word_count) { + data[read] = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_RD_FIFO_REG_OFFSET); + ++read; + } + handle->words_remaining -= read; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_read_fifo_pop(dif_rram_ctrl_state_t *handle, + uint32_t word_count, uint32_t *data) { + if (handle == NULL || data == NULL) { + return kDifBadArg; + } + if (!handle->transaction_pending) { + return kDifError; + } + if (handle->words_remaining < word_count) { + return kDifBadArg; + } + const uint32_t control_reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_CONTROL_REG_OFFSET); + const uint32_t op = + bitfield_field32_read(control_reg, RRAM_CTRL_CONTROL_OP_FIELD); + if (op != RRAM_CTRL_CONTROL_OP_VALUE_READ) { + return kDifError; + } + return dif_rram_ctrl_read_fifo_pop_unsafe(handle, word_count, data); +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_error_codes( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_error_t *error_code_out) { + if (handle == NULL || error_code_out == NULL) { + return kDifBadArg; + } + const uint32_t code_reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_ERR_CODE_REG_OFFSET); + dif_rram_ctrl_error_codes_t codes = { + .operation_error = + bitfield_bit32_read(code_reg, RRAM_CTRL_ERR_CODE_OP_ERR_BIT), + .memory_protection_error = + bitfield_bit32_read(code_reg, RRAM_CTRL_ERR_CODE_MP_ERR_BIT), + .read_error = + bitfield_bit32_read(code_reg, RRAM_CTRL_ERR_CODE_RD_ERR_BIT), + .write_error = + bitfield_bit32_read(code_reg, RRAM_CTRL_ERR_CODE_WR_ERR_BIT), + }; + + const uint32_t address_reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_ERR_ADDR_REG_OFFSET); + dif_rram_ctrl_error_t error_code = { + .address = address_reg, + .codes = codes, + }; + *error_code_out = error_code; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_clear_error_codes( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_error_codes_t codes) { + if (handle == NULL) { + return kDifBadArg; + } + uint32_t code_reg = 0; + code_reg = bitfield_bit32_write(code_reg, RRAM_CTRL_ERR_CODE_OP_ERR_BIT, + codes.operation_error); + code_reg = bitfield_bit32_write(code_reg, RRAM_CTRL_ERR_CODE_MP_ERR_BIT, + codes.memory_protection_error); + code_reg = bitfield_bit32_write(code_reg, RRAM_CTRL_ERR_CODE_RD_ERR_BIT, + codes.read_error); + code_reg = bitfield_bit32_write(code_reg, RRAM_CTRL_ERR_CODE_WR_ERR_BIT, + codes.write_error); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_ERR_CODE_REG_OFFSET, + code_reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_end(dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_output_t *out) { + if (handle == NULL || out == NULL) { + return kDifBadArg; + } + if (!handle->transaction_pending) { + return kDifError; + } + uint32_t status_reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_OP_STATUS_REG_OFFSET); + if (!bitfield_bit32_read(status_reg, RRAM_CTRL_OP_STATUS_DONE_BIT)) { + return kDifUnavailable; + } + if (handle->words_remaining != 0) { + return kDifIpFifoFull; + } + dif_rram_ctrl_error_t error_code_tmp; + DIF_RETURN_IF_ERROR(dif_rram_ctrl_get_error_codes(handle, &error_code_tmp)); + dif_rram_ctrl_output_t output = { + .operation_done = + bitfield_bit32_read(status_reg, RRAM_CTRL_OP_STATUS_DONE_BIT), + .operation_error = + bitfield_bit32_read(status_reg, RRAM_CTRL_OP_STATUS_ERR_BIT), + .error_code = error_code_tmp}; + // Clear the operation status + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_OP_STATUS_REG_OFFSET, 0); + handle->transaction_pending = false; + *out = output; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_data_region_enablement( + dif_rram_ctrl_state_t *handle, uint32_t region, dif_toggle_t enable) { + if (handle == NULL || region >= kNumRegions) { + return kDifBadArg; + } + + bool locked; + DIF_RETURN_IF_ERROR( + dif_rram_ctrl_data_region_is_locked(handle, region, &locked)); + if (locked) { + return kDifLocked; + } + + ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region); + uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + switch (enable) { + case kDifToggleEnabled: + mp_reg = bitfield_field32_write( + mp_reg, RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4True); + break; + case kDifToggleDisabled: + mp_reg = bitfield_field32_write( + mp_reg, RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4False); + break; + default: + return kDifBadArg; + } + mmio_region_write32(handle->dev.base_addr, mp_reg_offset, mp_reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_data_region_enablement( + const dif_rram_ctrl_state_t *handle, uint32_t region, + dif_toggle_t *enabled_out) { + if (handle == NULL || enabled_out == NULL || region >= kNumRegions) { + return kDifBadArg; + } + ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region); + uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + if (bitfield_field32_read(mp_reg, RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD) == + kMultiBitBool4True) { + *enabled_out = kDifToggleEnabled; + } else { + *enabled_out = kDifToggleDisabled; + } + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_info_region_enablement( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_toggle_t enable) { + if (handle == NULL || region.page >= kNumInfoPages) { + return kDifBadArg; + } + bool locked; + DIF_RETURN_IF_ERROR( + dif_rram_ctrl_info_region_is_locked(handle, region, &locked)); + if (locked) { + return kDifLocked; + } + + ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region); + uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + switch (enable) { + case kDifToggleEnabled: + mp_reg = bitfield_field32_write( + mp_reg, RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD, kMultiBitBool4True); + break; + case kDifToggleDisabled: + mp_reg = bitfield_field32_write( + mp_reg, RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD, kMultiBitBool4False); + break; + default: + return kDifBadArg; + } + mmio_region_write32(handle->dev.base_addr, mp_reg_offset, mp_reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_info_region_enablement( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_toggle_t *enabled_out) { + if (handle == NULL || enabled_out == NULL || region.page >= kNumInfoPages) { + return kDifBadArg; + } + ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region); + uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + if (bitfield_field32_read(mp_reg, RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD) == + kMultiBitBool4True) { + *enabled_out = kDifToggleEnabled; + } else { + *enabled_out = kDifToggleDisabled; + } + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_default_region_properties( + dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_region_properties_t properties) { + if (handle == NULL) { + return kDifBadArg; + } + uint32_t reg = 0; + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD, + properties.rd_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD, + properties.wr_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD, + properties.scramble_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD, + properties.ecc_en); + mmio_region_write32(handle->dev.base_addr, + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET, reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_default_region_properties( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_region_properties_t *properties_out) { + if (handle == NULL || properties_out == NULL) { + return kDifBadArg; + } + const uint32_t reg = mmio_region_read32(handle->dev.base_addr, + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET); + dif_rram_ctrl_region_properties_t properties = { + .rd_en = bitfield_field32_read(reg, RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD), + .wr_en = bitfield_field32_read(reg, RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD), + .scramble_en = bitfield_field32_read( + reg, RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD), + .ecc_en = + bitfield_field32_read(reg, RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD), + }; + *properties_out = properties; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_data_region_properties( + dif_rram_ctrl_state_t *handle, uint32_t region, + dif_rram_ctrl_data_region_properties_t config) { + const uint32_t page_limit = kNumDataPages; + if (handle == NULL || region >= kNumRegions || + config.base + config.size > page_limit) { + return kDifBadArg; + } + + bool locked; + DIF_RETURN_IF_ERROR( + dif_rram_ctrl_data_region_is_locked(handle, region, &locked)); + if (locked) { + return kDifLocked; + } + + ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region); + uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + reg = bitfield_field32_write(reg, RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD, + config.properties.rd_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD, + config.properties.wr_en); + reg = + bitfield_field32_write(reg, RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD, + config.properties.scramble_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD, + config.properties.ecc_en); + + mmio_region_write32(handle->dev.base_addr, mp_reg_offset, reg); + + // size and base are stored in different registers + mp_reg_offset = get_data_region_reg_offset(region); + + reg = bitfield_field32_write(0, RRAM_CTRL_MP_REGION_0_BASE_0_FIELD, + config.base); + reg = bitfield_field32_write(reg, RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD, + config.size); + mmio_region_write32(handle->dev.base_addr, mp_reg_offset, reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_data_region_properties( + const dif_rram_ctrl_state_t *handle, uint32_t region, + dif_rram_ctrl_data_region_properties_t *config_out) { + if (handle == NULL || config_out == NULL || region >= kNumRegions) { + return kDifBadArg; + } + + ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region); + uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + dif_rram_ctrl_data_region_properties_t config; + config.properties.rd_en = + bitfield_field32_read(reg, RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD); + config.properties.wr_en = + bitfield_field32_read(reg, RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD); + config.properties.scramble_en = + bitfield_field32_read(reg, RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD); + config.properties.ecc_en = + bitfield_field32_read(reg, RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD); + + mp_reg_offset = get_data_region_reg_offset(region); + reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + config.base = bitfield_field32_read(reg, RRAM_CTRL_MP_REGION_0_BASE_0_FIELD); + config.size = bitfield_field32_read(reg, RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD); + *config_out = config; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_info_region_properties( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_rram_ctrl_region_properties_t properties) { + if (handle == NULL || region.page >= kNumInfoPages) { + return kDifBadArg; + } + + bool locked; + DIF_RETURN_IF_ERROR( + dif_rram_ctrl_info_region_is_locked(handle, region, &locked)); + if (locked) { + return kDifLocked; + } + + ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region); + uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD, + properties.rd_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD, + properties.wr_en); + reg = + bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD, + properties.scramble_en); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD, + properties.ecc_en); + mmio_region_write32(handle->dev.base_addr, mp_reg_offset, reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_info_region_properties( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_rram_ctrl_region_properties_t *properties_out) { + if (handle == NULL || properties_out == NULL || + region.page >= kNumInfoPages) { + return kDifBadArg; + } + + ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region); + const uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset); + dif_rram_ctrl_region_properties_t properties; + properties.rd_en = + bitfield_field32_read(reg, RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD); + properties.wr_en = + bitfield_field32_read(reg, RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD); + properties.scramble_en = + bitfield_field32_read(reg, RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD); + properties.ecc_en = + bitfield_field32_read(reg, RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD); + *properties_out = properties; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_lock_data_region_properties( + dif_rram_ctrl_state_t *handle, uint32_t region) { + if (handle == NULL || region >= kNumRegions) { + return kDifBadArg; + } + + bool locked; + DIF_RETURN_IF_ERROR( + dif_rram_ctrl_data_region_is_locked(handle, region, &locked)); + if (locked) { + return kDifLocked; + } + + ptrdiff_t lock_reg_offset = get_data_region_lock_reg_offset(region); + uint32_t reg = bitfield_bit32_write( + 0, RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT, false); + mmio_region_write32(handle->dev.base_addr, lock_reg_offset, reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_lock_info_region_properties( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region) { + if (handle == NULL || region.page >= kNumInfoPages) { + return kDifBadArg; + } + + bool locked; + DIF_RETURN_IF_ERROR( + dif_rram_ctrl_info_region_is_locked(handle, region, &locked)); + if (locked) { + return kDifLocked; + } + + ptrdiff_t lock_reg_offset = get_info_region_lock_reg_offset(region); + uint32_t reg = + bitfield_bit32_write(0, RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT, false); + mmio_region_write32(handle->dev.base_addr, lock_reg_offset, reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_data_region_is_locked( + const dif_rram_ctrl_state_t *handle, uint32_t region, bool *locked_out) { + if (handle == NULL || locked_out == NULL || region >= kNumRegions) { + return kDifBadArg; + } + ptrdiff_t lock_reg_offset = get_data_region_lock_reg_offset(region); + uint32_t reg = mmio_region_read32(handle->dev.base_addr, lock_reg_offset); + *locked_out = + !bitfield_bit32_read(reg, RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_info_region_is_locked( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + bool *locked_out) { + if (handle == NULL || locked_out == NULL || region.page >= kNumInfoPages) { + return kDifBadArg; + } + + ptrdiff_t lock_reg_offset = get_info_region_lock_reg_offset(region); + uint32_t reg = mmio_region_read32(handle->dev.base_addr, lock_reg_offset); + *locked_out = !bitfield_bit32_read(reg, RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_wr_fifo_watermark(dif_rram_ctrl_state_t *handle, + uint32_t level) { + if (handle == NULL || level > RRAM_CTRL_FIFO_LVL_WR_MASK) { + return kDifBadArg; + } + uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_FIFO_LVL_REG_OFFSET); + reg = bitfield_field32_write(reg, RRAM_CTRL_FIFO_LVL_WR_FIELD, level); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_FIFO_LVL_REG_OFFSET, + reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_read_fifo_watermark( + dif_rram_ctrl_state_t *handle, uint32_t level) { + if (handle == NULL || level > RRAM_CTRL_FIFO_LVL_RD_MASK) { + return kDifBadArg; + } + uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_FIFO_LVL_REG_OFFSET); + reg = bitfield_field32_write(reg, RRAM_CTRL_FIFO_LVL_RD_FIELD, level); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_FIFO_LVL_REG_OFFSET, + reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_fifo_watermarks( + const dif_rram_ctrl_state_t *handle, uint32_t *write_out, + uint32_t *read_out) { + if (handle == NULL) { + return kDifBadArg; + } + const uint32_t reg = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_FIFO_LVL_REG_OFFSET); + if (write_out != NULL) { + *write_out = bitfield_field32_read(reg, RRAM_CTRL_FIFO_LVL_WR_FIELD); + } + if (read_out != NULL) { + *read_out = bitfield_field32_read(reg, RRAM_CTRL_FIFO_LVL_RD_FIELD); + } + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_clear_wr_fifo(dif_rram_ctrl_state_t *handle) { + if (handle == NULL) { + return kDifBadArg; + } + uint32_t reg = bitfield_bit32_write(0, RRAM_CTRL_FIFO_CLR_WR_BIT, true); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_FIFO_CLR_REG_OFFSET, + reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_clear_rd_fifo(dif_rram_ctrl_state_t *handle) { + if (handle == NULL) { + return kDifBadArg; + } + uint32_t reg = bitfield_bit32_write(0, RRAM_CTRL_FIFO_CLR_RD_BIT, true); + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_FIFO_CLR_REG_OFFSET, + reg); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_faults(const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_faults_t *faults_out) { + if (handle == NULL || faults_out == NULL) { + return kDifBadArg; + } + uint32_t reg = mmio_region_read32(handle->dev.base_addr, + RRAM_CTRL_FAULT_STATUS_REG_OFFSET); + dif_rram_ctrl_faults_t faults; + faults.lcmgr_operation_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_LCMGR_OP_ERR_BIT); + faults.lcmgr_memory_protection_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_LCMGR_MP_ERR_BIT); + faults.lcmgr_read_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_LCMGR_RD_ERR_BIT); + faults.lcmgr_write_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_LCMGR_WR_ERR_BIT); + faults.otp_operation_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_OTP_OP_ERR_BIT); + faults.otp_memory_protection_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_OTP_MP_ERR_BIT); + faults.otp_read_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_OTP_RD_ERR_BIT); + faults.otp_write_error = + bitfield_bit32_read(reg, RRAM_CTRL_FAULT_STATUS_OTP_WR_ERR_BIT); + // TODO: Add more faults? + *faults_out = faults; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_ecc_errors( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_ecc_errors_t *errors_out) { + if (handle == NULL || errors_out == NULL) { + return kDifBadArg; + } + + uint32_t reg = mmio_region_read32(handle->dev.base_addr, + RRAM_CTRL_CORR_ERR_CNT_REG_OFFSET); + errors_out->corr_error_count = + bitfield_field32_read(reg, RRAM_CTRL_CORR_ERR_CNT_VAL_FIELD); + + reg = mmio_region_read32(handle->dev.base_addr, + RRAM_CTRL_CORR_ERR_LOC_REG_OFFSET); + + errors_out->last_error_address = + bitfield_field32_read(reg, RRAM_CTRL_CORR_ERR_LOC_ADDR_FIELD); + errors_out->last_error_partition = + bitfield_bit32_read(reg, RRAM_CTRL_CORR_ERR_LOC_PART_BIT); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_phy_status( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_phy_status_t *status_out) { + if (handle == NULL || status_out == NULL) { + return kDifBadArg; + } + const uint32_t reg = mmio_region_read32(handle->dev.base_addr, + RRAM_CTRL_PHY_STATUS_REG_OFFSET); + dif_rram_ctrl_phy_status_t status = { + .phy_init_done = + bitfield_bit32_read(reg, RRAM_CTRL_PHY_STATUS_INIT_DONE_BIT), + .phy_wr_busy = bitfield_bit32_read(reg, RRAM_CTRL_PHY_STATUS_WR_BUSY_BIT), + }; + *status_out = status; + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_scratch(dif_rram_ctrl_state_t *handle, + uint32_t value) { + if (handle == NULL) { + return kDifBadArg; + } + mmio_region_write32(handle->dev.base_addr, RRAM_CTRL_SCRATCH_REG_OFFSET, + value); + return kDifOk; +} + +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_scratch(const dif_rram_ctrl_state_t *handle, + uint32_t *value_out) { + if (handle == NULL || value_out == NULL) { + return kDifBadArg; + } + *value_out = + mmio_region_read32(handle->dev.base_addr, RRAM_CTRL_SCRATCH_REG_OFFSET); + return kDifOk; +} diff --git a/sw/device/lib/dif/dif_rram_ctrl.h b/sw/device/lib/dif/dif_rram_ctrl.h new file mode 100644 index 0000000000000..feca840e0e634 --- /dev/null +++ b/sw/device/lib/dif/dif_rram_ctrl.h @@ -0,0 +1,922 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_RRAM_CTRL_H_ +#define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_RRAM_CTRL_H_ + +/** + * @file + * @brief RRAM + * Controller Device Interface Functions + */ + +#include +#include + +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/base/multibits.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "sw/device/lib/dif/autogen/dif_rram_ctrl_autogen.h" + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * Carries transaction state for a RRAM controller device. + * + * All members except `dev` should be considered private and should not be + * accessed directly outside of the DIF implementation. + */ +typedef struct dif_rram_ctrl_state { + /** + * Contains autogenerated device information, like the base address for + * registers in the RRAM controller device. + */ + dif_rram_ctrl_t dev; + + /** Number of words remaining for the current transaction. */ + uint32_t words_remaining; + /** Whether a transaction is pending completion. */ + bool transaction_pending; +} dif_rram_ctrl_state_t; + +/** + * Initialize the DIF state for the RRAM controller. + * + * @param handle The RRAM controller DIF state to initialize. + * @param base_addr The base address for the RRAM controller. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_init_state(dif_rram_ctrl_state_t *handle, + mmio_region_t base_addr); + +/** + * Initialize the DIF state for the RRAM controller from a device tree handle. + * + * @param handle The RRAM controller DIF state to initialize. + * @param dt The RRAM controller device tree handle. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_init_state_from_dt(dif_rram_ctrl_state_t *handle, + dt_rram_ctrl_t dt); + +typedef struct dif_rram_ctrl_device_info { + /** Number of bytes per RRAM word. */ + uint32_t bytes_per_word; + /** Number of bytes per RRAM page. */ + uint32_t bytes_per_page; + /** Number of pages in the data partition. */ + uint32_t data_pages; + /** Number of pages in the info partition. */ + uint32_t info_pages; +} dif_rram_ctrl_device_info_t; + +/** + * Get information on the RRAM controller sizes. + * + * @return A `dif_rram_ctrl_device_info_t` representing the feature sizes for + * various components of the RRAM. + */ +OT_WARN_UNUSED_RESULT +dif_rram_ctrl_device_info_t dif_rram_ctrl_get_device_info(void); + +/** + * Set whether the RRAM is enabled. + * + * Generally, this is used to disable RRAM functionality in case of an + * emergency. RRAM functionality is ordinarily enabled. + * + * @param handle The RRAM controller DIF state. + * @param enable Enable/disable RRAM functionality. + * @return `kDifBadArg` if `handle` is null. `kDifOk` on success. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_rram_enablement(dif_rram_ctrl_state_t *handle, + dif_toggle_t enable); + +/** + * Get whether RRAM functionality is enabled. + * + * @param handle The RRAM controller DIF state. + * @param enabled_out Out parameter, where to store whether RRAM is enabled. + * @return `kDifBadArg` if `handle` or `enabled_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_rram_enablement( + const dif_rram_ctrl_state_t *handle, dif_toggle_t *enabled_out); + +/** + * Set whether execution / fetch access is enabled. + * + * @param handle The RRAM controller DIF state. + * @param enable Enable/disable execution / fetch access. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_exec_enablement(dif_rram_ctrl_state_t *handle, + dif_toggle_t enable); + +/** + * Get whether execution / fetch access is enabled. + * + * @param handle The RRAM controller DIF state. + * @param enabled_out Out parameter, whether execution / fetch access is + * allowed. + * @return `kDifBadArg` if `handle` or `enabled_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_exec_enablement( + const dif_rram_ctrl_state_t *handle, dif_toggle_t *enabled_out); + +/** + * Begins the RRAM controller's initialization sequence. The RRAM controller + * will read out the root seeds before allowing other usage of the controller. + * This operation will only be performed once, and controller initialization + * cannot be requested again until after a reset. + * + * @param handle The RRAM controller DIF state. + * @return `kDifError` if initialization has already been started, and + * `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_start_controller_init(dif_rram_ctrl_state_t *handle); + +/** + * Status bits that can be queried. + */ +typedef struct dif_rram_ctrl_status { + /** + * RRAM read FIFO full, software must consume data. + */ + bool read_fifo_full : 1; + /** + * RRAM read FIFO empty. + */ + bool read_fifo_empty : 1; + /** + * RRAM write FIFO full. + */ + bool write_fifo_full : 1; + /** + * RRAM write FIFO empty, software must provide data. + */ + bool write_fifo_empty : 1; + /** + * RRAM controller init complete. + */ + bool controller_init_done : 1; + /** + * RRAM controller keys valid. + */ + bool controller_keys_valid : 1; +} dif_rram_ctrl_status_t; + +/** + * Query the status registers on the RRAM controller. + * + * This function checks the various status bits as described in + * `dif_rram_ctrl_status_t`. + * + * @param handle The RRAM controller DIF state. + * @param status_out Out parameter. The current status of the RRAM controller. + * @return `kDifBadArg` if `handle` or `status_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_status(const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_status_t *status_out); + +/** + * Enum to represent the RRAM partition type (data or info). + */ +typedef enum dif_rram_ctrl_partition_type { + kDifRramCtrlPartitionTypeData = 0, + kDifRramCtrlPartitionTypeInfo = 1 +} dif_rram_ctrl_partition_type_t; + +typedef enum dif_rram_ctrl_operation { + /** Read the specified number of words. */ + kDifRramCtrlOpRead = 0, + /** Write the specified number of words. */ + kDifRramCtrlOpWrite = 1, + /** Rewrite a specific word to repair it. */ + kDifRramCtrlOpRewrite = 2, +} dif_rram_ctrl_operation_t; + +typedef struct dif_rram_ctrl_transaction { + dif_rram_ctrl_operation_t op; + /** + * The partition type for the transaction. + * + */ + dif_rram_ctrl_partition_type_t partition_type; + /** + * Byte address (in the RRAM address space) to start the operation. + * + * For operations at a granularity of words, the RRAM controller will + * truncate to the closest, lower word aligned address. For example, if 0x13 + * is supplied for a read, the controller will perform a read at address 0x10. + * + * For write operations, the granularity is 4 words or 16 bytes. The RRAM + * controller will truncate the address to closest, lower aligned 16 byte + * address. + */ + uint32_t byte_address; + /** + * Number of 32-bit words in the operation. Must be in the range [1,4096] + * (inclusive) for write or read operations. + * For write operations the number of 32-bit words must be a multiple of 4. + */ + uint32_t word_count; +} dif_rram_ctrl_transaction_t; + +/** + * Start a RRAM controller operation. + * + * @param handle The RRAM controller DIF state. + * @param transaction The parameters that constitute the operation to start. + * @return `kDifBadArg` if `handle` is null or `transaction` contains an + * invalid or unsupported operation, `kDifUnavailable` if a RRAM transaction is + * in progress at the controller, `kDifIpFifoFull` if the FIFOs are not empty, + * and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_start(dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_transaction_t transaction); + +/** + * Start a RRAM controller operation, with fewer safeguards. (unsafe version) + * + * Unlike `dif_rram_ctrl_start()`, this variant does not check whether the info + * partition id is valid, whether the word count is valid, or whether the FIFOs + * have been emptied. This function is intended to be used to trigger errors on + * purpose, for testing the hardware responses. + * + * @param handle The RRAM controller DIF state. + * @param transaction The parameters that constitute the operation to start. + * @return `kDifBadArg` if `handle` is null, `kDifUnavailable` if a RRAM + * transaction is in progress, and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_start_unsafe( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_transaction_t transaction); + +/** + * Push data to the write FIFO. (unsafe version) + * + * This function is primarily for testing hardware error responses. If you are + * not specifically trying to force an error, consider + * `dif_rram_ctrl_wr_fifo_push()` instead. This function does not check if a + * write transaction has begun, nor if the number of words would exceed the + * size of the current transaction. + * + * Attempts to write the contents of `data` to the write FIFO without + * consideration for the current controller state. + * + * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the + * RRAM controller completed this transaction successfully. + * + * @param handle The RRAM controller DIF state. + * @param word_count The number of words to write. + * @param data The data to write. + * @return `kDifBadArg` if `handle` or `data` are null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_wr_fifo_push_unsafe(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + const uint32_t *data); + +/** + * Push data to the write FIFO. + * + * Attempts to write the contents of `data` to the write FIFO. It is required + * that a write transaction be started prior to calling this function, else + * the call will fail with `kDifError`. + * + * The following conditions are also required: + * - `data` must reference a contiguous, allocated, readable region of at + * least `word_count` words, violation of this will produce undefined + * behavior. + * - The first call to this function after starting the write transaction + * the same `word_count` must not exceed what was supplied at the start of + * the write transaction. + * - Each subsequent call the new `word_count` must not exceed `word_count - + * words_sent_out` from the previous call. + * All deviations on the above will produce a `kDifBadArg` error + * unless otherwise specified. + * + * If the FIFO fills up, this function will cause the CPU to block until the + * RRAM controller frees up more space. + * + * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the + * RRAM controller completed this transaction successfully. + * + * @param handle The RRAM controller DIF state. + * @param word_count The number of words to write. + * @param data The data to write. + * @return `kDifBadArg` if `handle` or `data` are null or if the value of + * `word_count` is illegal. `kDifError` if a write transaction was not + * started. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_wr_fifo_push(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + const uint32_t *data); + +/** + * Read data from the read FIFO. (unsafe version) + * + * This function is primarily for testing hardware error responses. If you are + * not specifically trying to force an error, consider + * `dif_rram_ctrl_read_fifo_pop()` instead. This function does not check if a + * transaction is currently in progress, nor if this would cause a read beyond + * the number of words for the current operation. + * + * Attempts to read `word_count` words from the read FIFO without consideration + * for the current controller state. + * + * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the + * RRAM controller completed this transaction successfully. + * + * @param handle The RRAM controller DIF state. + * @param word_count The number of words to read. + * @param data_out The region in memory to store the data read off the FIFO. + * @return `kDifBadArg` if `handle` or `data_out` are null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_read_fifo_pop_unsafe(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + uint32_t *data_out); + +/** + * Read data from the read FIFO. + * + * Attempts to read `word_count` words from the read FIFO. + * + * The following conditions are required: + * - `data_out` must reference a contiguous, allocated, writable region of at + * least `word_count` words, violation of this will produce undefined + * behavior. + * - The first call to this function after starting the write transaction + * the same `word_count` must not exceed what was supplied at the start of + * the read transaction. + * - Each subsequent call the new `word_count` must not exceed `word_count - + * words_received` from the previous call. + * All deviations on the above will produce a `kDifBadArg` error unless + * otherwise specified. + * + * If the FIFO empties this function will cause the CPU to block until the RRAM + * controller fills the FIFO with more data. + * + * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the + * RRAM controller completed this transaction successfully. + * + * @param handle The RRAM controller DIF state. + * @param word_count The number of words to read. + * @param data_out The region in memory to store the data read off the FIFO. + * @return `kDifBadArg` if `handle` or `data_out` are null, or if the value of + * `word_count` is illegal. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_read_fifo_pop(dif_rram_ctrl_state_t *handle, + uint32_t word_count, + uint32_t *data_out); + +typedef struct dif_rram_ctrl_error_codes { + /** + * Controller operation error. + */ + bool operation_error : 1; + /** + * Access permission error. + */ + bool memory_protection_error : 1; + /** + * Uncorrectable RRAM read data error. + */ + bool read_error : 1; + /** + * RRAM write error. + */ + bool write_error : 1; +} dif_rram_ctrl_error_codes_t; + +/** + * Represents recoverable errors and synchronous errors caused by software. + */ +typedef struct dif_rram_ctrl_error { + /** + * For errors associated with an address, the address where the error + * occurred. + */ + uint32_t address; + + /** + * A set of error codes. + */ + dif_rram_ctrl_error_codes_t codes; +} dif_rram_ctrl_error_t; + +/** + * Get the error codes and address of the last associated error. + * + * @param handle The RRAM controller DIF state. + * @param error_code_out Output parameter. The location where the current status + * is to be stored. + * @return `kDifBadArg` if `handle` or `error_code_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_error_codes( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_error_t *error_code_out); + +/** + * Clear the error codes. + * + * @param handle The RRAM controller DIF state. + * @param codes The error codes to clear. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_clear_error_codes(dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_error_codes_t codes); + +typedef struct dif_rram_ctrl_output { + /** + * The error code associated with an `operation_error`. This field is only + * valid if `operation_error` is true. + */ + dif_rram_ctrl_error_t error_code; + /** + * RRAM operation done. + */ + bool operation_done : 1; + /** + * RRAM operation error. + */ + bool operation_error : 1; + +} dif_rram_ctrl_output_t; + +/** + * Check that the transaction has completed and return any resulting error + * codes. Does not clear the error codes, but does clear the operation status if + * the operation has terminated. + * + * @param handle The RRAM controller DIF state. + * @param out Out parameter. Contains the transaction status and error codes. + * @return `kDifBadArg` if `handle` or `out` are null, `kDifError` if no + * transaction was pending, `kDifUnavailable` if the controller is still + * processing the transaction, `kDifIpFifoFull` if there are still words + * remaining for the FIFOs, and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_end(dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_output_t *out); + +/** + * Memory protection configuration options. + */ +typedef struct dif_rram_ctrl_region_properties { + /** Read enable flag. */ + multi_bit_bool_t rd_en; + /** Write enable flag. */ + multi_bit_bool_t wr_en; + /** Scramble enable flag*/ + multi_bit_bool_t scramble_en; + /** ECC enable flag. */ + multi_bit_bool_t ecc_en; +} dif_rram_ctrl_region_properties_t; + +/** + * A composite of a data region and its memory properties. + */ +typedef struct dif_rram_ctrl_data_region_properties { + /** Region base page index. */ + uint32_t base; + /** Region config size (in number of pages). */ + uint32_t size; + /** Memory properties of the region. */ + dif_rram_ctrl_region_properties_t properties; +} dif_rram_ctrl_data_region_properties_t; + +/** + * Representation of the memory protection regions for the info pages. + */ +typedef struct dif_rram_ctrl_info_region { + /** Region page index. */ + uint32_t page; +} dif_rram_ctrl_info_region_t; + +/** + * Enable/disable the data region of RRAM indexed by `region`. + * + * This may only be done if region configuration has not been locked. + * + * @param handle The RRAM controller DIF state. + * @param region The region to operate on. + * @param enable Enable or disable this `region`. + * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked` + * if region configuration has been locked, and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_data_region_enablement( + dif_rram_ctrl_state_t *handle, uint32_t region, dif_toggle_t enable); + +/** + * Get the enabled/disabled state for the indicated data `region`. + * + * @param handle The RRAM controller DIF state. + * @param region The region in question. + * @param enabled_out Out-parameter, the enabled/disabled state of this region. + * @return `kDifBadArg` if `handle` or `enabled_out` is null, or if `region` is + * invalid, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_data_region_enablement( + const dif_rram_ctrl_state_t *handle, uint32_t region, + dif_toggle_t *enabled_out); + +/** + * Enable/disable the info region of RRAM identified by `region`. + * + * This may only be done if region configuration has not been locked. + * + * @param handle The RRAM controller DIF state. + * @param region The region to operate on. + * @param enable Enable or disable this `region`. + * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked` + * if region configuration has been locked, and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_info_region_enablement( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_toggle_t enable); + +/** + * Get the enabled/disabled state for the indicated info `region`. + * + * @param handle The RRAM controller DIF state. + * @param region The region in question. + * @param enabled_out Out-parameter, the enabled/disabled state of this region. + * @return `kDifBadArg` if `handle` or `enabled_out` is null, or if `region` is + * invalid, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_info_region_enablement( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_toggle_t *enabled_out); + +/** + * Set the default memory properties for data regions, when not overridden by a + * specific entry in the data region memory properties table. + * + * @param handle The RRAM controller DIF state. + * @param properties The memory properties to control. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_default_region_properties( + dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_region_properties_t properties); + +/** + * Get the default memory properties for data regions, when they are not + * overridden by a specific entry in the data region memory properties table. + * + * @param handle The RRAM controller DIF state. + * @param properties_out Out-parameter, a pointer to a + * `dif_rram_ctrl_region_properties_t` struct for writing the memory + * properties. + * @return `kDifBadArg` if `handle` or `properties_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_default_region_properties( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_region_properties_t *properties_out); + +/** + * Set memory properties for the data region of RRAM indexed by `region`. + * + * This may only be done if region configuration has not been locked. + * + * @param handle The RRAM controller DIF state. + * @param region The region to operate on. + * @param config The memory properties to control for this `region`. + * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked` + * if region configuration has been locked, and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_data_region_properties( + dif_rram_ctrl_state_t *handle, uint32_t region, + dif_rram_ctrl_data_region_properties_t config); + +/** + * Get the memory properties for the data region of RRAM indexed by `region`. + * + * @param handle The RRAM controller DIF state. + * @param region The index of the region entry in question. + * @param config_out Out-parameter, a pointer to a + * `dif_rram_ctrl_data_region_properties_t` struct for writing the full entry + * showing the region configuration and its memory properties. + * @return `kDifBadArg` if `handle` or `config_out` is null or if `region` + * is invalid. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_data_region_properties( + const dif_rram_ctrl_state_t *handle, uint32_t region, + dif_rram_ctrl_data_region_properties_t *config_out); + +/** + * Set memory properties for the info region of RRAM identified by `region`. + * + * This may only be done if region configuration has not been locked. + * + * @param handle The RRAM controller DIF state. + * @param region The region to operate on. + * @param properties The memory properties to control for this `region`. + * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked` + * if region configuration has been locked, and `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_info_region_properties( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_rram_ctrl_region_properties_t properties); + +/** + * Get the memory properties for the info region of RRAM identified by + * `region`. + * + * @param handle The RRAM controller DIF state. + * @param region The index of the region entry in question. + * @param properties_out Out-parameter, a pointer to a + * `dif_rram_ctrl_region_properties_t` struct for writing memory properties + * associated with the indicated `region`. + * @return `kDifBadArg` if `handle` or `properties_out` is null or if `region` + * is invalid. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_info_region_properties( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + dif_rram_ctrl_region_properties_t *properties_out); + +/** + * Lock data region memory properties configuration until the device is reset. + * + * This will prevent any further configuration of region properties until device + * reset. Future calls to functions that set data region memory properties will + * return `kDifLocked`. + * + * @param handle The RRAM controller DIF state. + * @param region The region to lock. + * @return `kDifBadArg` if `handle` is null or `region` is invalid, + * `kDifLocked` if configuration is already locked, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_lock_data_region_properties( + dif_rram_ctrl_state_t *handle, uint32_t region); + +/** + * Lock info region memory properties configuration until the device is reset. + * + * This will prevent any further configuration of region properties until device + * reset. Future calls to functions that set info region memory properties will + * return `kDifLocked`. + * + * @param handle The RRAM controller DIF state. + * @param region The region to lock. + * @return `kDifBadArg` if `handle` is null or `region` is invalid, + * `kDifLocked` if configuration is already locked, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_lock_info_region_properties( + dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region); + +/** + * Query the state of the region configuration lock for the given data `region` + * entry's index. + * + * This function checks if memory region configuration is still enabled or if it + * has been locked. Once locked, region configuration cannot be enabled again, + * and all calls to region configuration functions will return `kDifLocked` + * until the device is restarted. + * + * @param handle The RRAM controller DIF state. + * @param region The region in question. + * @param locked_out Out-parameter, the current state of the region's + * configuration lock. + * @return `kDifBadArg` if `handle` or `locked_out` is null, or if `region` is + * invalid, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_data_region_is_locked( + const dif_rram_ctrl_state_t *handle, uint32_t region, bool *locked_out); + +/** + * Query the state of the region configuration lock for the given info `region`. + * + * This function checks if memory region configuration is still enabled or if it + * has been locked. Once locked, region configuration cannot be enabled again, + * and all calls to region configuration functions will return `kDifLocked` + * until the device is restarted. + * + * @param handle The RRAM controller DIF state. + * @param region The region in question. + * @param locked_out Out-parameter, the current state of the region's + * configuration lock. + * @return `kDifBadArg` if `handle` or `locked_out` is null, or if `region` is + * invalid, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_info_region_is_locked( + const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_info_region_t region, + bool *locked_out); + +/** + * Set the interrupt watermarks for the write FIFO. + * + * The value of `level` defines the level the write FIFO must drain to before + * triggering a `wr_lvl` interrupt. + * + * This interrupts will only trigger if enabled through the interrupt API. + * + * @param handle The RRAM controller DIF state. + * @param level Trigger an interrupt when the write FIFO drains to this level. + * @return `kDifBadArg` if `handle` is null or the value `level` is out of + * range, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_wr_fifo_watermark(dif_rram_ctrl_state_t *handle, + uint32_t level); + +/** + * Set the interrupt watermarks for the read FIFO. + * + * The value of `level` defines the level the read FIFO must fill to before + * triggering a `rd_lvl` interrupt. + * + * This interrupt will only trigger if enabled through the interrupt API. + * + * @param handle The RRAM controller DIF state. + * @param level Trigger an interrupt when the read FIFO fills to this level. + * @return `kDifBadArg` if `handle` is null or the value of `level` is out of + * range, `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_read_fifo_watermark( + dif_rram_ctrl_state_t *handle, uint32_t level); + +/** + * Get the interrupt watermarks for the write and read FIFOs. + * + * @param handle The RRAM controller DIF state. + * @param write_out Out-parameter, the write FIFO watermark level. If the write + * FIFO empties to this level, a corresponding status bit and possibly an + * interrupt may be generated. May be null. + * @param read_out Out-parameter, the read FIFO watermark level. If the read + * FIFO fills to this level, a corresponding status bit and possibly an + * interrupt may be generated. May be null. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_fifo_watermarks( + const dif_rram_ctrl_state_t *handle, uint32_t *write_out, + uint32_t *read_out); + +/** + * Clears the write FIFO. + * + * This is useful in the event of an unexpected error as a means of reseting + * state. + * + * @param handle The RRAM controller DIF state. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_clear_wr_fifo(dif_rram_ctrl_state_t *handle); + +/** + * Clears the read FIFO. + * + * This is useful in the event of an unexpected error as a means of reseting + * state. + * + * @param handle The RRAM controller DIF state. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_clear_rd_fifo(dif_rram_ctrl_state_t *handle); + +typedef struct dif_rram_ctrl_faults { + /** The lcmgr hardware interface encountered an invalid operation. */ + bool lcmgr_operation_error : 1; + /** The lcmgr hardware interface encountered a memory permission error. */ + bool lcmgr_memory_protection_error : 1; + /** The lcmgr hardware interface encountered a read data error. */ + bool lcmgr_read_error : 1; + /** The lcmgr hardware interface encountered a write data error. */ + bool lcmgr_write_error : 1; + /** The otp hardware interface encountered an invalid operation. */ + bool otp_operation_error : 1; + /** The otp hardware interface encountered a memory permission error. */ + bool otp_memory_protection_error : 1; + /** The otp hardware interface encountered a read data error. */ + bool otp_read_error : 1; + /** The otp hardware interface encountered a write data error. */ + bool otp_write_error : 1; +} dif_rram_ctrl_faults_t; + +/** + * Gets the unrecoverable or hardware faults. + * + * @param handle The RRAM controller DIF state. + * @param faults_out Out parameter, a pointer to the location to write the fault + * values. + * @return `kDifBadArg` if `handle` or `faults_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_faults(const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_faults_t *faults_out); + +typedef struct dif_rram_ctrl_ecc_errors { + /** Count of the number of correctable ECC errors. */ + uint32_t corr_error_count; + /** The last address that produced a correctable ECC error. */ + uint32_t last_error_address; + /** The last partition that produced a correctable ECC error. */ + dif_rram_ctrl_partition_type_t last_error_partition; +} dif_rram_ctrl_ecc_errors_t; + +/** + * Get the ECC error information of the RRAM. + * + * @param handle The RRAM controller DIF state. + * @param errors_out Out parameter. `kDifBadArg` if `errors_out` is null. + * `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_ecc_errors( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_ecc_errors_t *errors_out); + +typedef struct dif_rram_ctrl_phy_status { + /** RRAM phy controller initialization complete. */ + bool phy_init_done : 1; + /** RRAM phy write operation in progress. */ + bool phy_wr_busy : 1; +} dif_rram_ctrl_phy_status_t; + +/** + * Query the status registers on the RRAM controller. + * + * This function checks the various status bits as described in + * `dif_rram_ctrl_phy_status_t`. + * + * @param handle The RRAM controller DIF state. + * @param status_out Out-parameter, the current status of the RRAM phy. + * @return `kDifBadArg` if `handle` or `status_out` is null. `kDifOk` + * otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_phy_status( + const dif_rram_ctrl_state_t *handle, + dif_rram_ctrl_phy_status_t *status_out); + +/** + * Set the value of the scratch register. + * + * @param handle The RRAM controller DIF state. + * @param value The value to set the scratch register to. + * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_set_scratch(dif_rram_ctrl_state_t *handle, + uint32_t value); + +/** + * Get the value of the scratch register. + * + * @param handle The RRAM controller DIF state. + * @param value_out Out parameter. The location to write the scratch register's + * value to. + * @return `kDifBadArg` if `handle` or `value_out` is null. `kDifOk` otherwise. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_rram_ctrl_get_scratch(const dif_rram_ctrl_state_t *handle, + uint32_t *value_out); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_RRAM_CTRL_H_ diff --git a/sw/device/lib/dif/dif_rram_ctrl.md b/sw/device/lib/dif/dif_rram_ctrl.md new file mode 100644 index 0000000000000..3182c02e68614 --- /dev/null +++ b/sw/device/lib/dif/dif_rram_ctrl.md @@ -0,0 +1,58 @@ +--- +title: "RRAM Controller DIF Checklist" +--- + + + + +This checklist is for [Development Stage](/doc/project_governance/development_stages.md) transitions for the [RRAM Controller DIF](/hw/ip/rram_ctrl/README.md). +All checklist items refer to the content in the [Checklist](/doc/project_governance/checklist/README.md). + +

DIF Checklist

+ +

S1

+ +Type | Item | Resolution | Note/Collaterals +---------------|------------------------|-------------|------------------ +Implementation | [DIF_EXISTS][] | Not Started | +Implementation | [DIF_USED_IN_TREE][] | Not Started | +Tests | [DIF_TEST_ON_DEVICE][] | Not Started | + +[DIF_EXISTS]: /doc/project_governance/checklist/README.md#dif_exists +[DIF_USED_IN_TREE]: /doc/project_governance/checklist/README.md#dif_used_in_tree +[DIF_TEST_ON_DEVICE]: /doc/project_governance/checklist/README.md#dif_test_on_device + +

S2

+ +Type | Item | Resolution | Note/Collaterals +---------------|-----------------------------|-------------|------------------ +Coordination | [DIF_HW_FEATURE_COMPLETE][] | Not Started | [HW Dashboard](/hw/README.md) +Implementation | [DIF_FEATURES][] | Not Started | + +[DIF_HW_FEATURE_COMPLETE]: /doc/project_governance/checklist/README.md#dif_hw_feature_complete +[DIF_FEATURES]: /doc/project_governance/checklist/README.md#dif_features + +

S3

+ +Type | Item | Resolution | Note/Collaterals +---------------|----------------------------------|-------------|------------------ +Coordination | [DIF_HW_DESIGN_COMPLETE][] | Not Started | +Coordination | [DIF_HW_VERIFICATION_COMPLETE][] | Not Started | +Documentation | [DIF_DOC_HW][] | Not Started | +Code Quality | [DIF_CODE_STYLE][] | Not Started | +Tests | [DIF_TEST_UNIT][] | Not Started | +Review | [DIF_TODO_COMPLETE][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DIF_HW_DESIGN_COMPLETE]: /doc/project_governance/checklist/README.md#dif_hw_design_complete +[DIF_HW_VERIFICATION_COMPLETE]: /doc/project_governance/checklist/README.md#dif_hw_verification_complete +[DIF_DOC_HW]: /doc/project_governance/checklist/README.md#dif_doc_hw +[DIF_CODE_STYLE]: /doc/project_governance/checklist/README.md#dif_code_style +[DIF_TEST_UNIT]: /doc/project_governance/checklist/README.md#dif_test_unit +[DIF_TODO_COMPLETE]: /doc/project_governance/checklist/README.md#dif_todo_complete diff --git a/sw/device/lib/dif/dif_rram_ctrl_unittest.cc b/sw/device/lib/dif/dif_rram_ctrl_unittest.cc new file mode 100644 index 0000000000000..670a2159d928b --- /dev/null +++ b/sw/device/lib/dif/dif_rram_ctrl_unittest.cc @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/dif/dif_rram_ctrl.h" + +#include "gtest/gtest.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/base/mock_mmio.h" +#include "sw/device/lib/base/multibits.h" +#include "sw/device/lib/dif/dif_base.h" +#include "sw/device/lib/dif/dif_test_base.h" + +#include "hw/top/rram_ctrl_regs.h" // Generated. + +namespace dif_rram_ctrl_unittest { +namespace { +using mock_mmio::MmioTest; +using mock_mmio::MockDevice; +using testing::Test; + +class RramCtrlTest : public Test, public MmioTest { + protected: + void SetUp() { + ASSERT_DIF_OK(dif_rram_ctrl_init_state(&dif_rram_ctrl_, dev().region())); + } + + dif_rram_ctrl_state_t dif_rram_ctrl_; +}; + +TEST_F(RramCtrlTest, SimpleQueries) { + uint32_t scratch; + EXPECT_READ32(RRAM_CTRL_SCRATCH_REG_OFFSET, 0x89abcdefu); + EXPECT_DIF_OK(dif_rram_ctrl_get_scratch(&dif_rram_ctrl_, &scratch)); + EXPECT_EQ(scratch, 0x89abcdefu); +} + +// TODO: add more tests + +} // namespace +} // namespace dif_rram_ctrl_unittest diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD index 89ce28e4a2478..dc6b44dc5d572 100644 --- a/sw/device/lib/testing/test_rom/BUILD +++ b/sw/device/lib/testing/test_rom/BUILD @@ -187,6 +187,10 @@ cc_library( "flash_ctrl", ["HAS_FLASH_CTRL"], [], + ) + opentitan_if_ip( + "rram_ctrl", + ["HAS_RRAM_CTRL"], + [], ) + opentitan_if_ip( "otp_ctrl", ["HAS_OTP_CTRL"], @@ -245,6 +249,14 @@ cc_library( "//sw/device/lib/testing:nvm_testutils", ], [], + ) + opentitan_if_ip( + "rram_ctrl", + [ + "//hw/top:rram_ctrl_c_regs", + "//hw/top/dt:rram_ctrl", + "//sw/device/lib/dif:rram_ctrl", + ], + [], ) + opentitan_if_ip( "sensor_ctrl", ["//hw/top:sensor_ctrl_c_regs"], From 47b63f8d40ca9ba9dbd5c5cd2a4ffc0bfff2064e Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Fri, 17 Jul 2026 13:40:27 +0200 Subject: [PATCH 16/41] [sw,flash,rram] Link RRAM image instead of flash image This commit switches from executing from flash to RRAM. Signed-off-by: Michael Gautschi --- sw/device/lib/testing/test_framework/ottf_ld_top_config.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld b/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld index 073a9e00acac5..8d3b897e5b658 100644 --- a/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld +++ b/sw/device/lib/testing/test_framework/ottf_ld_top_config.ld @@ -11,7 +11,7 @@ MEMORY { } REGION_ALIAS("ottf_storage", ctn_ram) #else -REGION_ALIAS("ottf_storage", eflash) +REGION_ALIAS("ottf_storage", rram) #endif #ifdef OPENTITAN_IS_ENGLISHBREAKFAST From fd014471041a53b5e438fa8e7f4d430b5b5ec0e5 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Fri, 20 Mar 2026 09:37:21 +0100 Subject: [PATCH 17/41] [top, dv] fix various tests for RRAM Adjust the backdoor write operation for the RRAM. This adds the address infection for the backdoor write operation. This commit also adds a task that can wait for the rram_ctrl read-buffers to be idle. This is necessary because the RRAM issues every read twice and a backdoor write between the two reads would result in an integrity error. Signed-off-by: Michael Gautschi --- hw/top_earlgrey/dv/env/chip_if.sv | 2 + .../dv/env/seq_lib/chip_sw_base_vseq.sv | 39 ++++++++++++++++--- .../seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv | 2 +- .../seq_lib/chip_sw_power_sleep_load_vseq.sv | 1 + .../chip_sw_sysrst_ctrl_inputs_vseq.sv | 1 + 5 files changed, 39 insertions(+), 6 deletions(-) diff --git a/hw/top_earlgrey/dv/env/chip_if.sv b/hw/top_earlgrey/dv/env/chip_if.sv index 8cac1276af44e..d981d08f2f89e 100644 --- a/hw/top_earlgrey/dv/env/chip_if.sv +++ b/hw/top_earlgrey/dv/env/chip_if.sv @@ -658,6 +658,8 @@ interface chip_if; wire flash_core1_host_req = `FLASH_CTRL_HIER.u_eflash.gen_flash_cores[1].u_core.host_req_i; `endif wire adc_data_valid = `AST_HIER.u_ast_aon.u_adc.adc_d_val_o; + wire rram_rd_buf_rdy = ~((|`RRAM_CTRL_HIER.u_rram_phy.u_rram_phy_rd.buf_valid) || + (|`RRAM_CTRL_HIER.u_rram_phy.u_rram_phy_rd.buf_wip)); task static force_adc_d_o(input bit [9:0] channel_val); force `AST_HIER.u_ast_aon.adc_d_o = channel_val; diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv index b7a67f06132cc..2d1b7c8ea7359 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv @@ -95,6 +95,10 @@ class chip_sw_base_vseq extends chip_base_vseq; cfg.mem_bkdr_util_h[FlashBank0Data].set_mem(); cfg.mem_bkdr_util_h[FlashBank1Data].set_mem(); + // Initialize the info and data partition of the RRAM to all 0s. + cfg.mem_bkdr_util_h[RramInfo].clear_mem(); + cfg.mem_bkdr_util_h[RramData].clear_mem(); + // Randomize retention memory. This is done intentionally with wrong integrity // as early portions of ROM will initialize it to the correct value. // The randomization here is just to ensure we do not have x's in the memory. @@ -308,6 +312,14 @@ class chip_sw_base_vseq extends chip_base_vseq; join endtask + // Wait for RRAM read-buffer to be ready for a backdoor write operation. This is + // required because the RRAM controller reads every word two times. A backdoor + // write to a location that has not yet been verified with a second read will + // lead to an integrity error. + virtual task wait_rram_rd_buf_rdy(); + `DV_WAIT(cfg.chip_vif.rram_rd_buf_rdy === 1'b1, "RRAM-rd-buf timeout occurred!", 1000); + endtask + // Print pass / fail message to the log. virtual function void log_sw_test_status(); case (cfg.sw_test_status_vif.sw_test_status) @@ -675,7 +687,7 @@ class chip_sw_base_vseq extends chip_base_vseq; // Infer mem from address. `DV_CHECK(cfg.get_mem_from_addr(addr, mem)) - `DV_CHECK_FATAL(mem inside {Rom, [RamMain0:RamMain15], FlashBank0Data, FlashBank1Data}, + `DV_CHECK_FATAL(mem inside {Rom, [RamMain0:RamMain15], RramData, FlashBank0Data, FlashBank1Data}, $sformatf("SW symbol %0s is not expected to appear in %0s mem", symbol, mem)) addr_mask = (2**$clog2(cfg.mem_bkdr_util_h[mem].get_size_bytes()))-1; @@ -685,9 +697,17 @@ class chip_sw_base_vseq extends chip_base_vseq; `uvm_info(`gfn, $sformatf({"Overwriting symbol \"%s\" via backdoor in %0s: ", "abs addr = 0x%0h, mem addr = 0x%0h, size = %0d, ", "addr_mask = 0x%0h"}, - symbol, mem, addr, mem_addr, size, addr_mask), UVM_LOW) - for (int i = 0; i < size; i++) mem_bkdr_write8(mem, mem_addr + i, data[i]); - + symbol, mem.name, addr, mem_addr, size, addr_mask), UVM_LOW) + for (int i = 0; i < size; i++) begin + if (mem == RramData) begin + logic [7:0] xor_addr_byte; + int byte_offset = (mem_addr+i)%4; + // add addr infection + xor_addr_byte = (mem_addr + i) >> (byte_offset*8 + 2); + data[i] = xor_addr_byte ^ data[i]; + end + mem_bkdr_write8(mem, mem_addr + i, data[i]); + end if (mem == Rom) begin rom_ctrl_bkdr_util rom; `downcast(rom, cfg.mem_bkdr_util_h[mem]) @@ -699,7 +719,16 @@ class chip_sw_base_vseq extends chip_base_vseq; "abs addr = 0x%0h, mem addr = 0x%0h, size = %0d, ", "addr_mask = 0x%0h"}, symbol, mem, addr, mem_addr, size, addr_mask), UVM_LOW) - for (int i = 0; i < size; i++) mem_bkdr_read8(mem, mem_addr + i, data[i]); + for (int i = 0; i < size; i++) begin + mem_bkdr_read8(mem, mem_addr + i, data[i]); + if (mem == RramData) begin + logic [7:0] xor_addr_byte; + int byte_offset = (mem_addr+i)%4; + // remove addr infection + xor_addr_byte = (mem_addr + i) >> (byte_offset*8 + 2); + data[i] = xor_addr_byte ^ data[i]; + end + end end endfunction diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv index 321426a2a269d..d205c6392e645 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_i2c_device_tx_rx_vseq.sv @@ -71,7 +71,7 @@ class chip_sw_i2c_device_tx_rx_vseq extends chip_sw_i2c_tx_rx_vseq; super.cpu_init(); // Pass the symbols to test software via the backdoor - + wait_rram_rd_buf_rdy(); sw_symbol_backdoor_overwrite("kClockPeriodNanos", clock_period_nanos_arr); sw_symbol_backdoor_overwrite("kI2cRiseFallNanos", rise_fall_nanos_arr); sw_symbol_backdoor_overwrite("kI2cClockPeriodNanos", i2c_clock_period_nanos_arr); diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_sleep_load_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_sleep_load_vseq.sv index 25b1c4c12f655..8121aa107b320 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_sleep_load_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_sleep_load_vseq.sv @@ -62,6 +62,7 @@ class chip_sw_power_sleep_load_vseq extends chip_sw_base_vseq; virtual task sw_symbol_bkdr_overwr_scalar(string str, bit [7:0] data); bit [7:0] array_data[1] = {data}; + wait_rram_rd_buf_rdy(); sw_symbol_backdoor_overwrite(str, array_data); endtask diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sysrst_ctrl_inputs_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sysrst_ctrl_inputs_vseq.sv index ee367a7b273b8..aabcd29834824 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sysrst_ctrl_inputs_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sysrst_ctrl_inputs_vseq.sv @@ -58,6 +58,7 @@ class chip_sw_sysrst_ctrl_inputs_vseq extends chip_sw_base_vseq; set_pads(pads_to_set); #1us; + wait_rram_rd_buf_rdy(); write_test_phase_and_expected(current_phase, pads_to_set); `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest) From fa4983ccbadcc3dfedb484147d56f0ece10a2c22 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:05:55 +0200 Subject: [PATCH 18/41] [rram,sw] add rram_ctrl_testutils Adds a testutils layer over the silicon_creator RRAM driver, mirroring flash_ctrl_testutils, so DV/on-device tests can exercise rram_ctrl without depending on silicon_creator internals directly. Signed-off-by: Michael Gautschi --- sw/device/lib/testing/BUILD | 16 ++ sw/device/lib/testing/rram_ctrl_testutils.c | 272 ++++++++++++++++++++ sw/device/lib/testing/rram_ctrl_testutils.h | 234 +++++++++++++++++ 3 files changed, 522 insertions(+) create mode 100644 sw/device/lib/testing/rram_ctrl_testutils.c create mode 100644 sw/device/lib/testing/rram_ctrl_testutils.h diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD index 76ef89e67d8bf..62891092b8a49 100644 --- a/sw/device/lib/testing/BUILD +++ b/sw/device/lib/testing/BUILD @@ -181,6 +181,22 @@ cc_library( ], ) +cc_library( + name = "rram_ctrl_testutils", + srcs = ["rram_ctrl_testutils.c"], + hdrs = ["rram_ctrl_testutils.h"], + target_compatible_with = [OPENTITAN_CPU], + deps = [ + "//hw/top:rram_ctrl_c_regs", + "//sw/device/lib/base:abs_mmio", + "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:rram_ctrl", + "//sw/device/lib/runtime:hart", + "//sw/device/lib/runtime:ibex", + "//sw/device/lib/testing/test_framework:check", + ], +) + cc_library( name = "nvm_testutils", srcs = ["nvm_testutils.c"], diff --git a/sw/device/lib/testing/rram_ctrl_testutils.c b/sw/device/lib/testing/rram_ctrl_testutils.c new file mode 100644 index 0000000000000..2ab58bd9153d2 --- /dev/null +++ b/sw/device/lib/testing/rram_ctrl_testutils.c @@ -0,0 +1,272 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/testing/rram_ctrl_testutils.h" + +#include +#include +#include + +#include "sw/device/lib/base/abs_mmio.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_rram_ctrl.h" +#include "sw/device/lib/runtime/hart.h" +#include "sw/device/lib/runtime/ibex.h" +#include "sw/device/lib/testing/test_framework/check.h" + +#include "hw/top/rram_ctrl_regs.h" // Generated + +#define MODULE_ID MAKE_MODULE_ID('r', 'c', 't') + +status_t rram_ctrl_testutils_wait_for_init(dif_rram_ctrl_state_t *rram_state) { + dif_rram_ctrl_status_t status; + do { + TRY(dif_rram_ctrl_get_status(rram_state, &status)); + } while (status.controller_init_done == 0); + return OK_STATUS(); +} + +status_t rram_ctrl_testutils_wait_transaction_end( + dif_rram_ctrl_state_t *rram_state) { + dif_rram_ctrl_output_t output; + dif_result_t dif_result; + do { + dif_result = dif_rram_ctrl_end(rram_state, &output); + TRY_CHECK(dif_result != kDifBadArg); + TRY_CHECK(dif_result != kDifError); + } while (dif_result != kDifOk); + + if (output.operation_error) { + dif_rram_ctrl_error_codes_t codes = output.error_code.codes; + uint32_t error_reg = 0; + error_reg = bitfield_bit32_write(error_reg, RRAM_CTRL_ERR_CODE_OP_ERR_BIT, + codes.operation_error); + error_reg = bitfield_bit32_write(error_reg, RRAM_CTRL_ERR_CODE_MP_ERR_BIT, + codes.memory_protection_error); + error_reg = bitfield_bit32_write(error_reg, RRAM_CTRL_ERR_CODE_RD_ERR_BIT, + codes.read_error); + error_reg = bitfield_bit32_write(error_reg, RRAM_CTRL_ERR_CODE_WR_ERR_BIT, + codes.write_error); + } + TRY(dif_rram_ctrl_clear_error_codes(rram_state, output.error_code.codes)); + return output.operation_error == 0 ? OK_STATUS() : INTERNAL(); +} + +status_t rram_ctrl_testutils_data_region_setup_properties( + dif_rram_ctrl_state_t *rram_state, uint32_t base_page_index, + uint32_t data_region, uint32_t region_size, + dif_rram_ctrl_region_properties_t region_properties, uint32_t *offset) { + dif_rram_ctrl_data_region_properties_t data_region_properties = { + .base = base_page_index, + .properties = region_properties, + .size = region_size}; + + TRY(dif_rram_ctrl_set_data_region_properties(rram_state, data_region, + data_region_properties)); + TRY(dif_rram_ctrl_set_data_region_enablement(rram_state, data_region, + kDifToggleEnabled)); + + if (offset != NULL) { + dif_rram_ctrl_device_info_t device_info = dif_rram_ctrl_get_device_info(); + *offset = base_page_index * device_info.bytes_per_page; + } + return OK_STATUS(); +} + +status_t rram_ctrl_testutils_data_region_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t base_page_index, + uint32_t data_region, uint32_t region_size, uint32_t *offset) { + dif_rram_ctrl_region_properties_t region_properties = { + .ecc_en = kMultiBitBool4True, + .wr_en = kMultiBitBool4True, + .rd_en = kMultiBitBool4True, + .scramble_en = kMultiBitBool4False}; + return rram_ctrl_testutils_data_region_setup_properties( + rram_state, base_page_index, data_region, region_size, region_properties, + offset); +} + +status_t rram_ctrl_testutils_data_region_scrambled_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t base_page_index, + uint32_t data_region, uint32_t region_size, uint32_t *offset) { + dif_rram_ctrl_region_properties_t region_properties = { + .ecc_en = kMultiBitBool4True, + .wr_en = kMultiBitBool4True, + .rd_en = kMultiBitBool4True, + .scramble_en = kMultiBitBool4True}; + return rram_ctrl_testutils_data_region_setup_properties( + rram_state, base_page_index, data_region, region_size, region_properties, + offset); +} + +status_t rram_ctrl_testutils_info_region_setup_properties( + dif_rram_ctrl_state_t *rram_state, uint32_t page_id, + dif_rram_ctrl_region_properties_t region_properties, uint32_t *offset) { + dif_rram_ctrl_info_region_t info_region = {.page = page_id}; + + TRY(dif_rram_ctrl_set_info_region_properties(rram_state, info_region, + region_properties)); + TRY(dif_rram_ctrl_set_info_region_enablement(rram_state, info_region, + kDifToggleEnabled)); + + if (offset != NULL) { + dif_rram_ctrl_device_info_t device_info = dif_rram_ctrl_get_device_info(); + *offset = page_id * device_info.bytes_per_page; + } + return OK_STATUS(); +} + +status_t rram_ctrl_testutils_info_region_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t page_id, uint32_t *offset) { + dif_rram_ctrl_region_properties_t region_properties = { + .ecc_en = kMultiBitBool4True, + .wr_en = kMultiBitBool4True, + .rd_en = kMultiBitBool4True, + .scramble_en = kMultiBitBool4False}; + return rram_ctrl_testutils_info_region_setup_properties( + rram_state, page_id, region_properties, offset); +} + +status_t rram_ctrl_testutils_info_region_scrambled_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t page_id, uint32_t *offset) { + dif_rram_ctrl_region_properties_t region_properties = { + .ecc_en = kMultiBitBool4True, + .wr_en = kMultiBitBool4True, + .rd_en = kMultiBitBool4True, + .scramble_en = kMultiBitBool4True}; + return rram_ctrl_testutils_info_region_setup_properties( + rram_state, page_id, region_properties, offset); +} + +status_t rram_ctrl_testutils_write( + dif_rram_ctrl_state_t *rram_state, uint32_t byte_address, + const uint32_t *data, dif_rram_ctrl_partition_type_t partition_type, + uint32_t word_count) { + dif_rram_ctrl_transaction_t transaction = {.byte_address = byte_address, + .op = kDifRramCtrlOpWrite, + .partition_type = partition_type, + .word_count = 0x0}; + uint32_t words_written = 0; + uint32_t word_address = byte_address / sizeof(uint32_t); + const uint32_t max_words = (uint32_t)RRAM_CTRL_CONTROL_NUM_MASK + 1; + + status_t status = OK_STATUS(); + while (words_written < word_count) { + uint32_t words_remaining = word_count - words_written; + uint32_t words_to_write = + (words_remaining < max_words) ? words_remaining : max_words; + transaction.byte_address = word_address * sizeof(uint32_t); + transaction.word_count = words_to_write; + TRY(dif_rram_ctrl_start(rram_state, transaction)); + TRY(dif_rram_ctrl_wr_fifo_push(rram_state, words_to_write, + data + words_written)); + status = rram_ctrl_testutils_wait_transaction_end(rram_state); + word_address += words_to_write; + words_written += words_to_write; + } + return status; +} + +status_t rram_ctrl_testutils_write_word( + dif_rram_ctrl_state_t *rram_state, uint32_t byte_address, + const uint32_t *data, dif_rram_ctrl_partition_type_t partition_type) { + dif_rram_ctrl_transaction_t transaction = {.byte_address = byte_address, + .op = kDifRramCtrlOpWrite, + .partition_type = partition_type, + .word_count = 0x0}; + uint32_t word_addr_aligned = byte_address & ~(uintptr_t)0xF; + uint32_t word_idx = (byte_address >> 2) % 4; + + status_t status = OK_STATUS(); + + uint32_t data_short[4]; + CHECK_STATUS_OK(rram_ctrl_testutils_read(rram_state, word_addr_aligned, + data_short, partition_type, 4, 0)); + data_short[word_idx] = *data; + + transaction.byte_address = word_addr_aligned; + transaction.word_count = 4; + TRY(dif_rram_ctrl_start(rram_state, transaction)); + TRY(dif_rram_ctrl_wr_fifo_push(rram_state, 4, data_short)); + status = rram_ctrl_testutils_wait_transaction_end(rram_state); + return status; +} + +status_t rram_ctrl_testutils_read(dif_rram_ctrl_state_t *rram_state, + uint32_t byte_address, uint32_t *data_out, + dif_rram_ctrl_partition_type_t partition_type, + uint32_t word_count, uint32_t delay_micros) { + dif_rram_ctrl_transaction_t transaction = {.byte_address = byte_address, + .op = kDifRramCtrlOpRead, + .partition_type = partition_type, + .word_count = word_count}; + + // Read Page. + TRY(dif_rram_ctrl_start(rram_state, transaction)); + // Optional delay to allow for read fifo fill testing. + busy_spin_micros(delay_micros); + TRY(dif_rram_ctrl_read_fifo_pop(rram_state, word_count, data_out)); + return rram_ctrl_testutils_wait_transaction_end(rram_state); +} + +status_t rram_ctrl_testutils_default_region_access( + dif_rram_ctrl_state_t *rram_state, bool rd_en, bool wr_en, bool scramble_en, + bool ecc_en) { + dif_rram_ctrl_region_properties_t default_properties = { + .rd_en = rd_en ? kMultiBitBool4True : kMultiBitBool4False, + .wr_en = wr_en ? kMultiBitBool4True : kMultiBitBool4False, + .scramble_en = scramble_en ? kMultiBitBool4True : kMultiBitBool4False, + .ecc_en = ecc_en ? kMultiBitBool4True : kMultiBitBool4False}; + + TRY(dif_rram_ctrl_set_default_region_properties(rram_state, + default_properties)); + return OK_STATUS(); +} + +status_t rram_ctrl_testutils_show_faults( + const dif_rram_ctrl_state_t *rram_ctrl) { + dif_rram_ctrl_faults_t faults = {.lcmgr_memory_protection_error = false}; + CHECK_DIF_OK(dif_rram_ctrl_get_faults(rram_ctrl, &faults)); +#define LOG_IF_FIELD_SET(_struct, _field) \ + if (_struct._field != 0) { \ + LOG_INFO("rram_ctrl fault status has " #_field); \ + } + + LOG_IF_FIELD_SET(faults, lcmgr_operation_error); + LOG_IF_FIELD_SET(faults, lcmgr_memory_protection_error); + LOG_IF_FIELD_SET(faults, lcmgr_read_error); + LOG_IF_FIELD_SET(faults, lcmgr_write_error); +#undef LOG_IF_FIELD_SET + + return OK_STATUS(); +} + +static const char *mubi_prop(multi_bit_bool_t val, const char *name) { + switch (val) { + case kMultiBitBool4True: + return name; + case kMultiBitBool4False: + return "xx"; + default: + return "uu"; + } +} + +void rram_ctrl_testutils_data_region_print( + size_t index, dif_rram_ctrl_data_region_properties_t *p, bool locked) { + LOG_INFO("data region n=%u st=%u sz=%u %s-%s-%s-%s %s", index, p->base, + p->size, mubi_prop(p->properties.rd_en, "RD"), + mubi_prop(p->properties.wr_en, "WR"), + mubi_prop(p->properties.scramble_en, "SC"), + mubi_prop(p->properties.ecc_en, "EC"), locked ? "LK" : "UN"); +} + +void rram_ctrl_testutils_info_region_print(dif_rram_ctrl_info_region_t region, + dif_rram_ctrl_region_properties_t *p, + bool locked) { + LOG_INFO("info region page=%u %s-%s-%s-%s %s", region.page, + mubi_prop(p->rd_en, "RD"), mubi_prop(p->wr_en, "WR"), + mubi_prop(p->scramble_en, "SC"), mubi_prop(p->ecc_en, "EC"), + locked ? "LK" : "UN"); +} diff --git a/sw/device/lib/testing/rram_ctrl_testutils.h b/sw/device/lib/testing/rram_ctrl_testutils.h new file mode 100644 index 0000000000000..ebe888fbfa6f5 --- /dev/null +++ b/sw/device/lib/testing/rram_ctrl_testutils.h @@ -0,0 +1,234 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_RRAM_CTRL_TESTUTILS_H_ +#define OPENTITAN_SW_DEVICE_LIB_TESTING_RRAM_CTRL_TESTUTILS_H_ + +#include + +#include "sw/device/lib/base/status.h" +#include "sw/device/lib/dif/dif_rram_ctrl.h" + +/** + * Wait for the rram_ctrl to initialize. + * + * @param rram_state A rram_ctrl state handle. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_wait_for_init(dif_rram_ctrl_state_t *rram_state); + +/** + * Wait for a rram_ctrl operation to end. + * + * Calls dif_rram_ctrl_end in a loop and waits for a dif_result of Ok. If at + * any time the result is BadArg or Error this will fail. + * Clears any error codes and returns the value of operation_error. + * + * @param rram_state A rram_ctrl state handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_wait_transaction_end( + dif_rram_ctrl_state_t *rram_state); + +/** + * Setup and enable for a data region taking region properties as a parameter. + * + * @param rram_state A rram_ctrl state handle. + * @param base_page_index The region base page index. + * @param data_region The region index. + * @param region_size The region size (in number of pages). + * @param region_properties The properties for the data region. + * @param[out] offset The byte address offset of the region. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_data_region_setup_properties( + dif_rram_ctrl_state_t *rram_state, uint32_t base_page_index, + uint32_t data_region, uint32_t region_size, + dif_rram_ctrl_region_properties_t region_properties, uint32_t *offset); + +/** + * Setup and enable for a data region with scrambling disabled. + * + * @param rram_state A rram_ctrl state handle. + * @param base_page_index The region base page index. + * @param data_region The region index. + * @param region_size The region size (in number of pages). + * @param[out] offset The byte address offset of the region. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_data_region_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t base_page_index, + uint32_t data_region, uint32_t region_size, uint32_t *offset); + +/** + * Setup and enable for a data region with scrambling enabled. + * + * @param rram_state A rram_ctrl state handle. + * @param base_page_index The region base page index. + * @param data_region The region index. + * @param region_size The region size (in number of pages). + * @param[out] offset The byte address offset of the region. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_data_region_scrambled_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t base_page_index, + uint32_t data_region, uint32_t region_size, uint32_t *offset); + +/** + * Setup and enable for an info region taking region properties as a parameter. + * + * @param rram_state A rram_ctrl state handle. + * @param page_id Region page index. + * @param region_properties The properties for the info region. + * @param[out] offset The byte address offset of the region. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_info_region_setup_properties( + dif_rram_ctrl_state_t *rram_state, uint32_t page_id, + dif_rram_ctrl_region_properties_t region_properties, uint32_t *offset); + +/** + * Setup and enable for an info region with scrambling disabled. + * + * @param rram_state A rram_ctrl state handle. + * @param page_id Region page index. + * @param[out] offset The byte address offset of the region. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_info_region_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t page_id, uint32_t *offset); + +/** + * Setup and enable for an info region with scrambling enabled. + * + * @param rram_state A rram_ctrl state handle. + * @param page_id Region page index. + * @param[out] offset The byte address offset of the region. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_info_region_scrambled_setup( + dif_rram_ctrl_state_t *rram_state, uint32_t page_id, uint32_t *offset); + +/** + * Write RRAM starting from byte_address. + * The write is broken into as many transactions as required for the supplied + * word_count exceeds the maximum supported size. + * Returns the result of transaction_end. + * + * @param rram_state A rram_ctrl state handle. + * @param byte_address The byte address of the page to program. + * @param data The data to program. + * @param partition_type The partition type, data or info. + * @param word_count The number of uint32_t words to program. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_write( + dif_rram_ctrl_state_t *rram_state, uint32_t byte_address, + const uint32_t *data, dif_rram_ctrl_partition_type_t partition_type, + uint32_t word_count); + +/** + * Write a single 32b word to RRAM. + * A full RRAM line is read, modified and written back to the RRAM + * Returns the result of transaction_end. + * + * @param rram_state A rram_ctrl state handle. + * @param byte_address The byte address of the page to program. + * @param data The data to program. + * @param partition_type The partition type, data or info. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_write_word( + dif_rram_ctrl_state_t *rram_state, uint32_t byte_address, + const uint32_t *data, dif_rram_ctrl_partition_type_t partition_type); + +/** + * Reads data starting from byte_address. + * Returns the result of transaction_end. + * + * @param rram_state A rram_ctrl state handle. + * @param byte_address The byte address of the page to erase and program. + * @param data_out The data read from the page. + * @param partition_type The partition type, data or info. + * @param word_count The number of uint32_t words to read. + * @param delay_micros Optional delay (in us) for read FIFO fill testing. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_read(dif_rram_ctrl_state_t *rram_state, + uint32_t byte_address, uint32_t *data_out, + dif_rram_ctrl_partition_type_t partition_type, + uint32_t word_count, uint32_t delay); + +/** + * Sets the RRAM default configuration. + * + * @param rram_state A rram_ctrl state handle. + * @param rd_en Default read enable. + * @param wr_en Default program enable. + * @param scramble_en Default scramble enable. + * @param ecc_en Default ECC enable. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_default_region_access( + dif_rram_ctrl_state_t *rram_state, bool rd_en, bool wr_en, bool scramble_en, + bool ecc_en); + +/** + * Write to log any faults set in the status register. + * + * @param rram_state A rram_ctrl state handle. + */ +OT_WARN_UNUSED_RESULT +status_t rram_ctrl_testutils_show_faults( + const dif_rram_ctrl_state_t *rram_state); + +/** + * Print the properties of a RRAM data region configuration. + * + * This prints: + * + * data region n= st= sz= RD-WR-SC-EC LK + * + * The various properties are printed depending on their mubi bool value: + * - The property (e.g. `RD`, `WR`, etc) is printed if enabled by Mubi4True. + * - The string `xx` is printed if disabled by Mubi4False. + * - The string `uu` is printed if disabled by any other non-True value. + * + * @param index The index of the region. + * @param p The properties of the region. + * @param locked Whether or not the region is locked. + */ +void rram_ctrl_testutils_data_region_print( + size_t index, dif_rram_ctrl_data_region_properties_t *p, bool locked); + +/** + * Print the properties of a RRAM data region configuration. + * + * This prints: + * + * info region page= RD-WR-SC-EC LK + * + * The various properties are printed depending on their mubi bool value: + * - The property (e.g. `RD`, `WR`, etc) is printed if enabled by Mubi4True. + * - The string `xx` is printed if disabled by Mubi4False. + * - The string `uu` is printed if disabled by any other non-True value. + * + * @param region The info region descriptor. + * @param p The properties of the region. + * @param locked Whether or not the region is locked. + */ +void rram_ctrl_testutils_info_region_print(dif_rram_ctrl_info_region_t region, + dif_rram_ctrl_region_properties_t *p, + bool locked); +#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_RRAM_CTRL_TESTUTILS_H_ From 2769a8cdae3710f26d588a3090758eea975b948c Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:06:35 +0200 Subject: [PATCH 19/41] [rram_ctrl,sw] add RRAM support to nv_counter_testutils and nvm_testutils nv_counter_testutils now stores counters directly in RRAM (via rram_ctrl_testutils) instead of flash_ctrl, since RRAM has no program/erase distinction. nvm_testutils gains an nvm_ctrl-backed implementation alongside its existing flash_ctrl one. Signed-off-by: Michael Gautschi --- sw/device/lib/testing/BUILD | 25 +- sw/device/lib/testing/nv_counter_testutils.c | 109 +++- sw/device/lib/testing/nv_counter_testutils.h | 14 - sw/device/lib/testing/nvm_testutils.c | 513 +++++++++++++++++-- sw/device/lib/testing/nvm_testutils.h | 30 +- 5 files changed, 617 insertions(+), 74 deletions(-) diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD index 62891092b8a49..ac806429af08c 100644 --- a/sw/device/lib/testing/BUILD +++ b/sw/device/lib/testing/BUILD @@ -201,15 +201,26 @@ cc_library( name = "nvm_testutils", srcs = ["nvm_testutils.c"], hdrs = ["nvm_testutils.h"], + local_defines = opentitan_if_ip( + "flash_ctrl", + ["HAS_FLASH_CTRL"], + [], + ) + opentitan_if_ip( + "rram_ctrl", + ["HAS_RRAM_CTRL"], + [], + ), target_compatible_with = [OPENTITAN_CPU], deps = [ ":flash_ctrl_testutils", + ":rram_ctrl_testutils", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:bitfield", "//sw/device/lib/base:macros", "//sw/device/lib/base:mmio", "//sw/device/lib/base:multibits", "//sw/device/lib/dif:flash_ctrl", + "//sw/device/lib/dif:rram_ctrl", "//sw/device/lib/testing/test_framework:check", "//sw/device/silicon_creator/lib:nvm_ctrl", "//sw/device/silicon_creator/lib/drivers:flash_ctrl", @@ -220,6 +231,11 @@ cc_library( name = "nv_counter_testutils", srcs = ["nv_counter_testutils.c"], hdrs = ["nv_counter_testutils.h"], + local_defines = opentitan_if_ip( + "rram_ctrl", + ["HAS_RRAM_CTRL"], + [], + ), target_compatible_with = [OPENTITAN_CPU], deps = [ ":flash_ctrl_testutils", @@ -228,7 +244,14 @@ cc_library( "//sw/device/lib/base:mmio", "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/testing/test_framework:check", - ], + ] + opentitan_if_ip( + "rram_ctrl", + [ + ":rram_ctrl_testutils", + "//sw/device/lib/dif:rram_ctrl", + ], + [], + ), ) cc_library( diff --git a/sw/device/lib/testing/nv_counter_testutils.c b/sw/device/lib/testing/nv_counter_testutils.c index ffdac98491d13..e084b47570e3d 100644 --- a/sw/device/lib/testing/nv_counter_testutils.c +++ b/sw/device/lib/testing/nv_counter_testutils.c @@ -9,12 +9,96 @@ #include #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/testing/test_framework/check.h" + +#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" + +#ifdef HAS_RRAM_CTRL +#include "sw/device/lib/dif/dif_rram_ctrl.h" +#include "sw/device/lib/testing/rram_ctrl_testutils.h" +#else #include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/testing/flash_ctrl_testutils.h" -#include "sw/device/lib/testing/test_framework/check.h" #include "hw/top/flash_ctrl_regs.h" // Generated. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#endif // HAS_RRAM_CTRL + +#ifdef HAS_RRAM_CTRL + +enum { + // One aligned RRAM write granule: {value, valid marker, reserved, + // reserved}. The shared linker script (ottf_common.ld) still reserves a + // much larger flash-oriented region per counter (256 8-byte words = 2048 + // bytes); RRAM only needs this single 4-word (16-byte) line and simply + // uses the first bytes of that reserved space. + kNvRramCounterWords = 4, +}; + +static_assert(kNvRramCounterWords * sizeof(uint32_t) <= 2048, + "RRAM counter storage must fit within the non_volatile_counter " + "section reserved by ottf_common.ld."); + +static const uint32_t kNvCounterValid = 0xABBAABBA; + +OT_SET_BSS_SECTION(".non_volatile_counter_0", + uint32_t nv_counter_0[kNvRramCounterWords];) +OT_SET_BSS_SECTION(".non_volatile_counter_1", + uint32_t nv_counter_1[kNvRramCounterWords];) +OT_SET_BSS_SECTION(".non_volatile_counter_2", + uint32_t nv_counter_2[kNvRramCounterWords];) +OT_SET_BSS_SECTION(".non_volatile_counter_3", + uint32_t nv_counter_3[kNvRramCounterWords];) + +static uint32_t *const kNvCounters[] = { + nv_counter_0, + nv_counter_1, + nv_counter_2, + nv_counter_3, +}; + +static status_t nv_counter_rram_init(dif_rram_ctrl_state_t *rram) { + TRY(dif_rram_ctrl_init_state( + rram, mmio_region_from_addr(TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR))); + TRY(rram_ctrl_testutils_default_region_access(rram, /*rd_en=*/true, + /*wr_en=*/true, + /*scramble_en=*/false, + /*ecc_en=*/false)); + return OK_STATUS(); +} + +status_t nv_counter_testutils_counter_get(size_t counter, uint32_t *value) { + TRY_CHECK(value != NULL); + TRY_CHECK(counter < ARRAYSIZE(kNvCounters)); + + *value = 0; + if (kNvCounters[counter][1] == kNvCounterValid) { + *value = kNvCounters[counter][0]; + } + return OK_STATUS(); +} + +status_t nv_counter_testutils_counter_increment(size_t counter) { + dif_rram_ctrl_state_t rram; + TRY(nv_counter_rram_init(&rram)); + + uint32_t before; + TRY(nv_counter_testutils_counter_get(counter, &before)); + // RRAM writes must be a multiple of 4 words; leaving the last two words + // unused is simpler than a read-modify-write. + uint32_t new_val[kNvRramCounterWords] = {before + 1, kNvCounterValid, 0, 0}; + TRY(rram_ctrl_testutils_write(&rram, + (uint32_t)&kNvCounters[counter][0] - + TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR, + new_val, kDifRramCtrlPartitionTypeData, + kNvRramCounterWords)); + + uint32_t value; + TRY(nv_counter_testutils_counter_get(counter, &value)); + TRY_CHECK(value == before + 1, "Counter increment failed"); + return OK_STATUS(); +} + +#else // HAS_RRAM_CTRL enum { kNonVolatileCounterFlashWords = 256, @@ -100,23 +184,4 @@ status_t nv_counter_testutils_counter_increment(size_t counter) { return OK_STATUS(); } -// At the beginning of the simulation (Verilator, VCS,etc.), -// the content of the flash might be all-zeros, and thus, -// the NVM counter's initial value might be 256. -// In that case, nv_counter_testutils_counter_set_at_least() will not increment. -// This function can be used to initialize a NVM counter to zero by filling -// its flash region with non-zero values. -status_t nv_counter_testutils_counter_init_zero(size_t counter) { - dif_flash_ctrl_state_t flash; - TRY(nv_counter_flash_init(&flash)); - uint32_t new_val[FLASH_CTRL_PARAM_BYTES_PER_WORD / sizeof(uint32_t)] = {0xaa, - 0xbb}; - for (int ii = 0; ii < kNonVolatileCounterFlashWords; ii++) { - TRY(flash_ctrl_testutils_erase_and_write_page( - &flash, - (uint32_t)&kNvCounters[counter][ii] - - TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR, - 0, new_val, kDifFlashCtrlPartitionTypeData, ARRAYSIZE(new_val))); - } - return OK_STATUS(); -} +#endif // HAS_RRAM_CTRL diff --git a/sw/device/lib/testing/nv_counter_testutils.h b/sw/device/lib/testing/nv_counter_testutils.h index 9a5d864fec052..de12bdf19318b 100644 --- a/sw/device/lib/testing/nv_counter_testutils.h +++ b/sw/device/lib/testing/nv_counter_testutils.h @@ -28,18 +28,4 @@ status_t nv_counter_testutils_counter_get(size_t counter, uint32_t *value); OT_WARN_UNUSED_RESULT status_t nv_counter_testutils_counter_increment(size_t counter); -/** - * At the beginning of the simulation (Verilator, VCS,etc.), - * the content of the flash might be all-zeros, and thus, - * the NVM counter's initial value might be 256. - * In that case, nv_counter_testutils_counter_set_at_least() will not increment. - * This function can be used to initialize a NVM counter to zero by filling - * its flash region with non-zero values. - * - * @param counter The ID of the NVM counter, [0, 2]. - * @return The result of the operation. - **/ -OT_WARN_UNUSED_RESULT -status_t nv_counter_testutils_counter_init_zero(size_t counter); - #endif // OPENTITAN_SW_DEVICE_LIB_TESTING_NV_COUNTER_TESTUTILS_H_ diff --git a/sw/device/lib/testing/nvm_testutils.c b/sw/device/lib/testing/nvm_testutils.c index a6d2795c87b00..a71798cf5f462 100644 --- a/sw/device/lib/testing/nvm_testutils.c +++ b/sw/device/lib/testing/nvm_testutils.c @@ -10,16 +10,470 @@ #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/mmio.h" #include "sw/device/lib/base/multibits.h" -#include "sw/device/lib/dif/dif_flash_ctrl.h" -#include "sw/device/lib/testing/flash_ctrl_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" +#ifdef HAS_RRAM_CTRL +#include "sw/device/lib/dif/dif_rram_ctrl.h" +#include "sw/device/lib/testing/rram_ctrl_testutils.h" +#else +#include "sw/device/lib/dif/dif_flash_ctrl.h" +#include "sw/device/lib/testing/flash_ctrl_testutils.h" +#endif // HAS_RRAM_CTRL + #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Chunk size for readback verification — small enough to live on the stack. enum { kNvmMaxWordCount = 16 }; +#ifdef HAS_RRAM_CTRL +// RRAM controller implementation + +const nvm_page_perms_t kPageReadOnly = {.read = kMultiBitBool4True, + .write = kMultiBitBool4False}; + +const nvm_page_perms_t kPageReadWrite = {.read = kMultiBitBool4True, + .write = kMultiBitBool4True}; + +const nvm_page_perms_t kPageWriteOnly = {.read = kMultiBitBool4False, + .write = kMultiBitBool4True}; + +const nvm_page_cfg_t kPageScrambleCfg = {.scrambling = kMultiBitBool4True, + .ecc = kMultiBitBool4True}; + +const nvm_page_cfg_t kPagePlainCfg = {.scrambling = kMultiBitBool4False, + .ecc = kMultiBitBool4True}; + +const nvm_page_cfg_t kPageRawCfg = {.scrambling = kMultiBitBool4False, + .ecc = kMultiBitBool4False}; + +// Physical location of a logical NVM info page on RRAM. +// +// RRAM has only 8 physical info pages (`emul` = 0, `page_id` 0-7), too few +// for the 20 logical nvm_info_page_t entries inherited from flash. The +// remainder are relocated onto reserved pages of the (much larger) RRAM data +// partition instead (`emul` = 1). +typedef struct { + uint32_t page_id; + uint32_t emul; +} nvm_page_phys_t; + +// TODO(#XXXX): pages relocated onto the data partition (`emul` = 1) all share +// a single memory-protection region (`kRramRelocatedRegion`), covering +// `kRramRelocatedPageCount` reserved data pages starting at +// `kRramEmulPageBase`, with read and write always enabled and never +// locked — RRAM only has 8 configurable data regions, fewer than the 14 +// relocated pages, so there is no room for per-page permissions yet. Giving +// relocated pages (or groups of them) their own protection will require +// hardware changes to add more data regions. +enum { + kRramRelocatedRegion = 0, + // First data-partition page reserved for relocated pages. kPageMap's + // `page_id` values for `emul` = 1 entries are absolute data-partition page + // indices already offset by this base. + kRramEmulPageBase = 4064, + kRramRelocatedPageCount = 14, +}; + +// Mapping from nvm_info_page_t to a physical RRAM location. Only 6 of the 8 +// physical info pages are assigned so far (pages 3-4 are reserved/unused for +// now); everything else is relocated to reserved data pages starting at +// kRramEmulPageBase. +// clang-format off +static const nvm_page_phys_t kPageMap[] = { + // Info partition + [kNvmInfoPageFactoryId] = {.page_id = 0, .emul = 0}, + [kNvmInfoPageAttestationKeySeeds] = {.page_id = 1, .emul = 0}, + [kNvmInfoPageFactoryCerts] = {.page_id = 2, .emul = 0}, + // pages 3-4 reserved/unused for now + [kNvmInfoPageCreatorSecret] = {.page_id = 5, .emul = 0}, // fixed in hardware + [kNvmInfoPageOwnerSecret] = {.page_id = 6, .emul = 0}, // fixed in hardware + [kNvmInfoPageWaferAuthSecret] = {.page_id = 7, .emul = 0}, // fixed in hardware + // Data partition, reserved pages kRramEmulPageBase + 0-13 + [kNvmInfoPageOwnerReserved0] = {.page_id = kRramEmulPageBase + 0, .emul = 1}, + [kNvmInfoPageOwnerReserved1] = {.page_id = kRramEmulPageBase + 1, .emul = 1}, + [kNvmInfoPageOwnerReserved2] = {.page_id = kRramEmulPageBase + 2, .emul = 1}, + [kNvmInfoPageOwnerReserved3] = {.page_id = kRramEmulPageBase + 3, .emul = 1}, + [kNvmInfoPageBootData0] = {.page_id = kRramEmulPageBase + 4, .emul = 1}, + [kNvmInfoPageBootData1] = {.page_id = kRramEmulPageBase + 5, .emul = 1}, + [kNvmInfoPageOwnerSlot0] = {.page_id = kRramEmulPageBase + 6, .emul = 1}, + [kNvmInfoPageOwnerSlot1] = {.page_id = kRramEmulPageBase + 7, .emul = 1}, + [kNvmInfoPageCreatorReserved0] = {.page_id = kRramEmulPageBase + 8, .emul = 1}, + [kNvmInfoPageOwnerReserved4] = {.page_id = kRramEmulPageBase + 9, .emul = 1}, + [kNvmInfoPageOwnerReserved5] = {.page_id = kRramEmulPageBase + 10, .emul = 1}, + [kNvmInfoPageOwnerReserved6] = {.page_id = kRramEmulPageBase + 11, .emul = 1}, + [kNvmInfoPageOwnerReserved7] = {.page_id = kRramEmulPageBase + 12, .emul = 1}, + [kNvmInfoPageDiceCerts] = {.page_id = kRramEmulPageBase + 13, .emul = 1}, +}; +// clang-format on + +static status_t dif_rram_state_init(dif_rram_ctrl_state_t *rram) { + TRY(dif_rram_ctrl_init_state( + rram, mmio_region_from_addr(TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR))); + return OK_STATUS(); +} + +status_t nvm_testutils_wait_for_init(void) { + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_phy_status_t phy_status; + do { + TRY(dif_rram_ctrl_get_phy_status(&rram, &phy_status)); + } while (!phy_status.phy_init_done); + return OK_STATUS(); +} + +status_t nvm_testutils_rom_init(uint32_t otp_nvm_default_cfg) { + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + TRY(dif_rram_ctrl_start_controller_init(&rram)); + dif_rram_ctrl_status_t status; + do { + TRY(dif_rram_ctrl_get_status(&rram, &status)); + } while (!status.controller_init_done); + + // Unlike for flash_ctrl, where the memory protection only gates the + // controller's own transaction-based (FIFO) reads/writes, the memory + // protection regions of rram_ctrl also gate the direct read path. Hence, + // RD_EN needs to be set in order to be able to read from RRAM. + dif_rram_ctrl_region_properties_t props; + TRY(dif_rram_ctrl_get_default_region_properties(&rram, &props)); + props.rd_en = kMultiBitBool4True; + if (otp_nvm_default_cfg != 0) { + // RRAM has no high-endurance concept, so FLASH_CTRL_OTP_FIELD_HE is not + // applied here. + props.scramble_en = bitfield_field32_read(otp_nvm_default_cfg, + FLASH_CTRL_OTP_FIELD_SCRAMBLING); + props.ecc_en = + bitfield_field32_read(otp_nvm_default_cfg, FLASH_CTRL_OTP_FIELD_ECC); + } + TRY(dif_rram_ctrl_set_default_region_properties(&rram, props)); + TRY(dif_rram_ctrl_set_rram_enablement(&rram, kDifToggleEnabled)); + TRY(dif_rram_ctrl_set_exec_enablement(&rram, kDifToggleEnabled)); + return OK_STATUS(); +} + +static status_t rram_info_page_get_props( + dif_rram_ctrl_state_t *rram, uint32_t page_id, + dif_rram_ctrl_region_properties_t *props) { + dif_rram_ctrl_info_region_t region = {.page = page_id}; + TRY(dif_rram_ctrl_get_info_region_properties(rram, region, props)); + return OK_STATUS(); +} + +static status_t rram_info_page_set_props( + dif_rram_ctrl_state_t *rram, uint32_t page_id, + dif_rram_ctrl_region_properties_t props) { + return rram_ctrl_testutils_info_region_setup_properties(rram, page_id, props, + /*offset=*/NULL); +} + +static status_t rram_relocated_region_enable(dif_rram_ctrl_state_t *rram, + nvm_page_cfg_t cfg) { + dif_rram_ctrl_region_properties_t properties = { + .rd_en = kMultiBitBool4True, + .wr_en = kMultiBitBool4True, + .scramble_en = cfg.scrambling, + .ecc_en = cfg.ecc, + }; + return rram_ctrl_testutils_data_region_setup_properties( + rram, kRramEmulPageBase, kRramRelocatedRegion, kRramRelocatedPageCount, + properties, /*offset=*/NULL); +} + +status_t nvm_testutils_info_page_setup(nvm_info_page_t page, + nvm_page_perms_t perms, + nvm_page_cfg_t cfg) { + TRY_CHECK(page < ARRAYSIZE(kPageMap), "invalid page %d", page); + const nvm_page_phys_t p = kPageMap[page]; + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + if (p.emul != 0) { + // `perms` is ignored: the shared region is always readable/writable. + TRY(rram_relocated_region_enable(&rram, cfg)); + return OK_STATUS(); + } + // RRAM has no separate erase permission or high-endurance concept, so + // `perms.erase` and `cfg.he` are ignored here. + dif_rram_ctrl_region_properties_t props = { + .rd_en = perms.read, + .wr_en = perms.write, + .scramble_en = cfg.scrambling, + .ecc_en = cfg.ecc, + }; + TRY(rram_info_page_set_props(&rram, p.page_id, props)); + return OK_STATUS(); +} + +status_t nvm_testutils_info_page_set(nvm_info_page_t page, + nvm_page_perms_t perms, + nvm_page_cfg_t cfg) { + TRY_CHECK(page < ARRAYSIZE(kPageMap), "invalid page %d", page); + const nvm_page_phys_t p = kPageMap[page]; + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + if (p.emul != 0) { + // `perms` is ignored: the shared region is always readable/writable. + TRY(rram_relocated_region_enable(&rram, cfg)); + return OK_STATUS(); + } + dif_rram_ctrl_region_properties_t props; + TRY(rram_info_page_get_props(&rram, p.page_id, &props)); + if (perms.read == kMultiBitBool4True) { + props.rd_en = kMultiBitBool4True; + } + if (perms.write == kMultiBitBool4True) { + props.wr_en = kMultiBitBool4True; + } + if (cfg.scrambling == kMultiBitBool4True) { + props.scramble_en = kMultiBitBool4True; + } + if (cfg.ecc == kMultiBitBool4True) { + props.ecc_en = kMultiBitBool4True; + } + TRY(rram_info_page_set_props(&rram, p.page_id, props)); + return OK_STATUS(); +} + +status_t nvm_testutils_info_page_clear(nvm_info_page_t page, + nvm_page_perms_t perms, + nvm_page_cfg_t cfg) { + TRY_CHECK(page < ARRAYSIZE(kPageMap), "invalid page %d", page); + const nvm_page_phys_t p = kPageMap[page]; + TRY_CHECK(p.emul == 0, + "page %d shares mp region %d with other relocated pages; " + "clearing permissions there would affect them too", + page, kRramRelocatedRegion); + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_region_properties_t props; + TRY(rram_info_page_get_props(&rram, p.page_id, &props)); + if (perms.read == kMultiBitBool4True) { + props.rd_en = kMultiBitBool4False; + } + if (perms.write == kMultiBitBool4True) { + props.wr_en = kMultiBitBool4False; + } + if (cfg.scrambling == kMultiBitBool4True) { + props.scramble_en = kMultiBitBool4False; + } + if (cfg.ecc == kMultiBitBool4True) { + props.ecc_en = kMultiBitBool4False; + } + TRY(rram_info_page_set_props(&rram, p.page_id, props)); + return OK_STATUS(); +} + +status_t nvm_testutils_write_info_page(nvm_info_page_t page, + uint32_t byte_offset, + const uint32_t *data, size_t word_count, + bool erase_before_write, bool readback) { + TRY_CHECK(page < ARRAYSIZE(kPageMap), "invalid page %d", page); + const nvm_page_phys_t p = kPageMap[page]; + // RRAM has no erase step; writes overwrite in place. + (void)erase_before_write; + + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_device_info_t info = dif_rram_ctrl_get_device_info(); + dif_rram_ctrl_partition_type_t partition_type = + p.emul == 0 ? kDifRramCtrlPartitionTypeInfo + : kDifRramCtrlPartitionTypeData; + uint32_t address = p.page_id * info.bytes_per_page + byte_offset; + + // RRAM writes must start at a 16-byte-aligned address and cover a multiple + // of 4 32-bit words (see dif_rram_ctrl_start()'s checks); unlike flash, + // there's no "just write these bytes" primitive. Fall back to the existing + // single-word read-modify-write helper for any misaligned/sub-4-word + // leading or trailing words, so callers can still request an arbitrary + // byte_offset/word_count, as flash allowed; write fully-aligned interior + // blocks directly, in as few transactions as possible. + enum { kRramWriteWords = 4, kRramWriteBytes = kRramWriteWords * 4 }; + size_t write_remaining = word_count; + const uint32_t *src = data; + uint32_t addr = address; + while (write_remaining > 0) { + if (addr % kRramWriteBytes == 0 && write_remaining >= kRramWriteWords) { + size_t full_words = (write_remaining / kRramWriteWords) * kRramWriteWords; + TRY(rram_ctrl_testutils_write(&rram, addr, src, partition_type, + (uint32_t)full_words)); + addr += (uint32_t)(full_words * sizeof(uint32_t)); + src += full_words; + write_remaining -= full_words; + continue; + } + TRY(rram_ctrl_testutils_write_word(&rram, addr, src, partition_type)); + addr += sizeof(uint32_t); + src += 1; + write_remaining -= 1; + } + + if (readback) { + uint32_t rb_buf[kNvmMaxWordCount]; + size_t remaining = word_count; + size_t chunk_offset = 0; + while (remaining > 0) { + size_t chunk = + remaining < kNvmMaxWordCount ? remaining : kNvmMaxWordCount; + TRY(rram_ctrl_testutils_read(&rram, + address + chunk_offset * sizeof(uint32_t), + rb_buf, partition_type, (uint32_t)chunk, + /*delay_micros=*/0)); + TRY_CHECK( + memcmp(data + chunk_offset, rb_buf, chunk * sizeof(uint32_t)) == 0, + "NVM write readback mismatch at page %d offset %d", page, + byte_offset + chunk_offset * sizeof(uint32_t)); + chunk_offset += chunk; + remaining -= chunk; + } + } + return OK_STATUS(); +} + +status_t nvm_testutils_read_info_page(nvm_info_page_t page, + uint32_t byte_offset, uint32_t *data, + size_t word_count) { + TRY_CHECK(page < ARRAYSIZE(kPageMap), "invalid page %d", page); + const nvm_page_phys_t p = kPageMap[page]; + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_device_info_t info = dif_rram_ctrl_get_device_info(); + dif_rram_ctrl_partition_type_t partition_type = + p.emul == 0 ? kDifRramCtrlPartitionTypeInfo + : kDifRramCtrlPartitionTypeData; + uint32_t address = p.page_id * info.bytes_per_page + byte_offset; + TRY(rram_ctrl_testutils_read(&rram, address, data, partition_type, + (uint32_t)word_count, /*delay_micros=*/0)); + return OK_STATUS(); +} + +status_t nvm_testutils_info_page_lock(nvm_info_page_t page, bool lock) { + if (!lock) { + return OK_STATUS(); + } + TRY_CHECK(page < ARRAYSIZE(kPageMap), "invalid page %d", page); + const nvm_page_phys_t p = kPageMap[page]; + if (p.emul != 0) { + // The shared relocated-page region is intentionally never locked (see + // TODO above): locking it would freeze every relocated page at once. + return OK_STATUS(); + } + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_info_region_t region = {.page = p.page_id}; + TRY(dif_rram_ctrl_lock_info_region_properties(&rram, region)); + return OK_STATUS(); +} + +// TODO(#XXXX): `base`/`size` are expressed in flash-page units +// (NVM_BYTES_PER_PAGE); RRAM's data pages are a different size, so the unit +// conversion is not yet decided. +status_t nvm_testutils_data_region_setup(uint32_t region, uint32_t base, + uint32_t size, nvm_page_perms_t perms, + nvm_page_cfg_t cfg) { + (void)region; + (void)base; + (void)size; + (void)perms; + (void)cfg; + return UNIMPLEMENTED(); +} + +status_t nvm_testutils_data_region_lock(uint32_t region, bool lock) { + if (!lock) { + return OK_STATUS(); + } + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + TRY(dif_rram_ctrl_lock_data_region_properties(&rram, region)); + return OK_STATUS(); +} + +status_t nvm_testutils_show_faults(void) { + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_faults_t faults; + TRY(dif_rram_ctrl_get_faults(&rram, &faults)); +#define LOG_IF_FIELD_SET(_struct, _field) \ + if (_struct._field) { \ + LOG_INFO("Rram_ctrl fault status has " #_field); \ + } + LOG_IF_FIELD_SET(faults, lcmgr_operation_error); + LOG_IF_FIELD_SET(faults, lcmgr_memory_protection_error); + LOG_IF_FIELD_SET(faults, lcmgr_read_error); + LOG_IF_FIELD_SET(faults, lcmgr_write_error); + LOG_IF_FIELD_SET(faults, otp_operation_error); + LOG_IF_FIELD_SET(faults, otp_memory_protection_error); + LOG_IF_FIELD_SET(faults, otp_read_error); + LOG_IF_FIELD_SET(faults, otp_write_error); +#undef LOG_IF_FIELD_SET + return OK_STATUS(); +} + +status_t nvm_testutils_default_region_setup(nvm_page_perms_t perms, + nvm_page_cfg_t cfg) { + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + // RRAM has no separate erase permission or high-endurance concept, so + // `perms.erase` and `cfg.he` are ignored here. + dif_rram_ctrl_region_properties_t props = { + .rd_en = perms.read, + .wr_en = perms.write, + .scramble_en = cfg.scrambling, + .ecc_en = cfg.ecc, + }; + TRY(dif_rram_ctrl_set_default_region_properties(&rram, props)); + return OK_STATUS(); +} + +status_t nvm_testutils_default_region_get(nvm_page_perms_t *perms, + nvm_page_cfg_t *cfg) { + dif_rram_ctrl_state_t rram; + TRY(dif_rram_state_init(&rram)); + dif_rram_ctrl_region_properties_t props; + TRY(dif_rram_ctrl_get_default_region_properties(&rram, &props)); + if (perms != NULL) { + perms->read = props.rd_en; + perms->write = props.wr_en; + // RRAM has no separate erase permission. + perms->erase = kMultiBitBool4False; + } + if (cfg != NULL) { + cfg->scrambling = props.scramble_en; + cfg->ecc = props.ecc_en; + // RRAM has no high-endurance concept. + cfg->he = kMultiBitBool4False; + } + return OK_STATUS(); +} + +#else +// Flash controller implementation + +const nvm_page_perms_t kPageReadOnly = {.read = kMultiBitBool4True, + .write = kMultiBitBool4False, + .erase = kMultiBitBool4False}; + +const nvm_page_perms_t kPageReadWrite = {.read = kMultiBitBool4True, + .write = kMultiBitBool4True, + .erase = kMultiBitBool4True}; + +const nvm_page_perms_t kPageWriteOnly = {.read = kMultiBitBool4False, + .write = kMultiBitBool4True, + .erase = kMultiBitBool4True}; + +const nvm_page_cfg_t kPageScrambleCfg = {.scrambling = kMultiBitBool4True, + .ecc = kMultiBitBool4True, + .he = kMultiBitBool4False}; + +const nvm_page_cfg_t kPagePlainCfg = {.scrambling = kMultiBitBool4False, + .ecc = kMultiBitBool4True, + .he = kMultiBitBool4False}; + +const nvm_page_cfg_t kPageRawCfg = {.scrambling = kMultiBitBool4False, + .ecc = kMultiBitBool4False, + .he = kMultiBitBool4False}; + // Physical location of a logical NVM info page. typedef struct { uint32_t page_id; @@ -56,30 +510,6 @@ static const nvm_page_phys_t kPageMap[] = { }; // clang-format on -const nvm_page_perms_t kPageReadOnly = {.read = kMultiBitBool4True, - .write = kMultiBitBool4False, - .erase = kMultiBitBool4False}; - -const nvm_page_perms_t kPageReadWrite = {.read = kMultiBitBool4True, - .write = kMultiBitBool4True, - .erase = kMultiBitBool4True}; - -const nvm_page_perms_t kPageWriteOnly = {.read = kMultiBitBool4False, - .write = kMultiBitBool4True, - .erase = kMultiBitBool4True}; - -const nvm_page_cfg_t kPageScrambleCfg = {.scrambling = kMultiBitBool4True, - .ecc = kMultiBitBool4True, - .he = kMultiBitBool4False}; - -const nvm_page_cfg_t kPagePlainCfg = {.scrambling = kMultiBitBool4False, - .ecc = kMultiBitBool4True, - .he = kMultiBitBool4False}; - -const nvm_page_cfg_t kPageRawCfg = {.scrambling = kMultiBitBool4False, - .ecc = kMultiBitBool4False, - .he = kMultiBitBool4False}; - static status_t dif_flash_state_init(dif_flash_ctrl_state_t *flash) { TRY(dif_flash_ctrl_init_state( flash, mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR))); @@ -119,20 +549,20 @@ static status_t info_page_set_props(dif_flash_ctrl_state_t *flash, return OK_STATUS(); } -status_t nvm_testutils_rom_init(uint32_t otp_flash_default_cfg) { +status_t nvm_testutils_rom_init(uint32_t otp_nvm_default_cfg) { dif_flash_ctrl_state_t flash; TRY(dif_flash_state_init(&flash)); TRY(dif_flash_ctrl_start_controller_init(&flash)); TRY(flash_ctrl_testutils_wait_for_init(&flash)); - if (otp_flash_default_cfg != 0) { + if (otp_nvm_default_cfg != 0) { dif_flash_ctrl_region_properties_t props; TRY(dif_flash_ctrl_get_default_region_properties(&flash, &props)); - props.scramble_en = bitfield_field32_read(otp_flash_default_cfg, + props.scramble_en = bitfield_field32_read(otp_nvm_default_cfg, FLASH_CTRL_OTP_FIELD_SCRAMBLING); props.ecc_en = - bitfield_field32_read(otp_flash_default_cfg, FLASH_CTRL_OTP_FIELD_ECC); + bitfield_field32_read(otp_nvm_default_cfg, FLASH_CTRL_OTP_FIELD_ECC); props.high_endurance_en = - bitfield_field32_read(otp_flash_default_cfg, FLASH_CTRL_OTP_FIELD_HE); + bitfield_field32_read(otp_nvm_default_cfg, FLASH_CTRL_OTP_FIELD_HE); TRY(dif_flash_ctrl_set_default_region_properties(&flash, props)); } TRY(dif_flash_ctrl_set_flash_enablement(&flash, kDifToggleEnabled)); @@ -347,3 +777,24 @@ status_t nvm_testutils_default_region_setup(nvm_page_perms_t perms, TRY(dif_flash_ctrl_set_default_region_properties(&flash, props)); return OK_STATUS(); } + +status_t nvm_testutils_default_region_get(nvm_page_perms_t *perms, + nvm_page_cfg_t *cfg) { + dif_flash_ctrl_state_t flash; + TRY(dif_flash_state_init(&flash)); + dif_flash_ctrl_region_properties_t props; + TRY(dif_flash_ctrl_get_default_region_properties(&flash, &props)); + if (perms != NULL) { + perms->read = props.rd_en; + perms->write = props.prog_en; + perms->erase = props.erase_en; + } + if (cfg != NULL) { + cfg->scrambling = props.scramble_en; + cfg->ecc = props.ecc_en; + cfg->he = props.high_endurance_en; + } + return OK_STATUS(); +} + +#endif // HAS_RRAM_CTRL diff --git a/sw/device/lib/testing/nvm_testutils.h b/sw/device/lib/testing/nvm_testutils.h index 3e336da71a8d0..7064199d11f6a 100644 --- a/sw/device/lib/testing/nvm_testutils.h +++ b/sw/device/lib/testing/nvm_testutils.h @@ -138,17 +138,19 @@ status_t nvm_testutils_read_info_page(nvm_info_page_t page, /** * Initialize the NVM controller at ROM/boot time. * - * Starts the flash controller, waits for initialization to complete, - * optionally applies default region properties read from OTP, and enables - * flash access and instruction fetch. Call this once from test ROM before any - * other NVM operation. + * Starts the flash and/or RRAM controller, waits for initialization to + * complete, optionally applies default region scrambling/ECC config read + * from OTP, and enables NVM access and instruction fetch. Call this once + * from test ROM before any other NVM operation. * - * @param otp_flash_default_cfg CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG OTP word; + * @param otp_nvm_default_cfg CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG OTP word; * pass 0 when HAS_OTP_CTRL is not available or the field reads as zero. + * Applied to both flash and RRAM default region scrambling/ECC config; the + * high-endurance field is ignored for RRAM, which has no such concept. * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -status_t nvm_testutils_rom_init(uint32_t otp_flash_default_cfg); +status_t nvm_testutils_rom_init(uint32_t otp_nvm_default_cfg); /** * Lock the region configuration for an NVM info page. @@ -222,4 +224,20 @@ OT_WARN_UNUSED_RESULT status_t nvm_testutils_default_region_setup(nvm_page_perms_t perms, nvm_page_cfg_t cfg); +/** + * Get the NVM controller's current default data region properties. + * + * RRAM has no separate erase permission or high-endurance concept; on RRAM + * `perms->erase` and `cfg->he` are always reported as `kMultiBitBool4False`. + * + * @param[out] perms Current permission values (read, write, erase). May be + * NULL if not needed. + * @param[out] cfg Current configuration values (scrambling, ECC, HE). May + * be NULL if not needed. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t nvm_testutils_default_region_get(nvm_page_perms_t *perms, + nvm_page_cfg_t *cfg); + #endif // OPENTITAN_SW_DEVICE_LIB_TESTING_NVM_TESTUTILS_H_ From e8bbc6b091be0288ecd9b9767610e5831d922631 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:06:45 +0200 Subject: [PATCH 20/41] [rram_ctrl,sw] use nvm_testutils instead of dif_flash_ctrl Reads the default NVM region's scrambling/ECC/high-endurance config through the tech-agnostic nvm_testutils API instead of calling dif_flash_ctrl directly, so this power virus test isn't hardcoded to flash anymore. Signed-off-by: Michael Gautschi --- sw/device/tests/BUILD | 2 +- sw/device/tests/power_virus_systemtest.c | 17 ++++++----------- 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 7bd19147854ac..98a7afd4721fc 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -5892,7 +5892,6 @@ opentitan_test( "//sw/device/lib/dif:csrng_shared", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:flash_ctrl", "//sw/device/lib/dif:gpio", "//sw/device/lib/dif:hmac", "//sw/device/lib/dif:i2c", @@ -5909,6 +5908,7 @@ opentitan_test( "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:hmac_testutils", "//sw/device/lib/testing:i2c_testutils", + "//sw/device/lib/testing:nvm_testutils", "//sw/device/lib/testing:otbn_testutils_rsa", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing:spi_device_testutils", diff --git a/sw/device/tests/power_virus_systemtest.c b/sw/device/tests/power_virus_systemtest.c index 847f6cf908288..a0a352cd87810 100644 --- a/sw/device/tests/power_virus_systemtest.c +++ b/sw/device/tests/power_virus_systemtest.c @@ -12,7 +12,6 @@ #include "sw/device/lib/dif/dif_csrng_shared.h" #include "sw/device/lib/dif/dif_edn.h" #include "sw/device/lib/dif/dif_entropy_src.h" -#include "sw/device/lib/dif/dif_flash_ctrl.h" #include "sw/device/lib/dif/dif_gpio.h" #include "sw/device/lib/dif/dif_hmac.h" #include "sw/device/lib/dif/dif_i2c.h" @@ -29,6 +28,7 @@ #include "sw/device/lib/testing/entropy_testutils.h" #include "sw/device/lib/testing/hmac_testutils.h" #include "sw/device/lib/testing/i2c_testutils.h" +#include "sw/device/lib/testing/nvm_testutils.h" #include "sw/device/lib/testing/otbn_testutils_rsa.h" #include "sw/device/lib/testing/pinmux_testutils.h" #include "sw/device/lib/testing/spi_device_testutils.h" @@ -62,7 +62,6 @@ static dif_csrng_t csrng; static dif_edn_t edn_0; static dif_edn_t edn_1; static dif_entropy_src_t entropy_src; -static dif_flash_ctrl_state_t flash_ctrl; static dif_gpio_t gpio; static dif_hmac_t hmac; static dif_i2c_t i2c_0; @@ -372,9 +371,6 @@ static void init_peripheral_handles(void) { dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); CHECK_DIF_OK(dif_rstmgr_init( mmio_region_from_addr(TOP_EARLGREY_RSTMGR_BASE_ADDR), &rstmgr)); - CHECK_DIF_OK(dif_flash_ctrl_init_state( - &flash_ctrl, - mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR))); CHECK_DIF_OK(dif_rv_plic_init( mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR), &rv_plic)); } @@ -1338,12 +1334,11 @@ static void max_power_task(void *task_parameters) { } static void check_otp_csr_configs(void) { - dif_flash_ctrl_region_properties_t default_properties; - CHECK_DIF_OK(dif_flash_ctrl_get_default_region_properties( - &flash_ctrl, &default_properties)); - CHECK(default_properties.scramble_en == kMultiBitBool4True); - CHECK(default_properties.ecc_en == kMultiBitBool4True); - CHECK(default_properties.high_endurance_en == kMultiBitBool4False); + nvm_page_cfg_t cfg; + CHECK_STATUS_OK(nvm_testutils_default_region_get(/*perms=*/NULL, &cfg)); + CHECK(cfg.scrambling == kMultiBitBool4True); + CHECK(cfg.ecc == kMultiBitBool4True); + CHECK(cfg.he == kMultiBitBool4False); } bool test_main(void) { From d32239b21b14e70e4380125482b95ab3ccafb0bc Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:14:53 +0200 Subject: [PATCH 21/41] [rram_ctrl,sw] add RRAM error codes Adds kModuleRramCtrl and the four kErrorRramCtrl* codes, mirroring the existing kModuleFlashCtrl/kErrorFlashCtrl* codes, for use by the upcoming RRAM driver and nvm_ctrl RRAM backend. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/error.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sw/device/silicon_creator/lib/error.h b/sw/device/silicon_creator/lib/error.h index da2e37c7e4105..4096ef703909e 100644 --- a/sw/device/silicon_creator/lib/error.h +++ b/sw/device/silicon_creator/lib/error.h @@ -60,6 +60,7 @@ enum module_ { kModuleGpio = MODULE_CODE('G', 'I'), kModuleUsb = MODULE_CODE('U', 'S'), kModuleNvmCtrl = MODULE_CODE('N', 'V'), + kModuleRramCtrl = MODULE_CODE('R', 'M'), // clang-format on }; @@ -147,6 +148,11 @@ enum module_ { X(kErrorFlashCtrlInfoErase, ERROR_(6, kModuleFlashCtrl, kInternal)), \ X(kErrorFlashCtrlDataEraseVerify, ERROR_(7, kModuleFlashCtrl, kInternal)), \ \ + X(kErrorRramCtrlDataRead, ERROR_(1, kModuleRramCtrl, kInternal)), \ + X(kErrorRramCtrlInfoRead, ERROR_(2, kModuleRramCtrl, kInternal)), \ + X(kErrorRramCtrlDataWrite, ERROR_(3, kModuleRramCtrl, kInternal)), \ + X(kErrorRramCtrlInfoWrite, ERROR_(4, kModuleRramCtrl, kInternal)), \ + \ X(kErrorBootPolicyBadIdentifier, ERROR_(1, kModuleBootPolicy, kInternal)), \ X(kErrorBootPolicyBadLength, ERROR_(2, kModuleBootPolicy, kInternal)), \ X(kErrorBootPolicyRollback, ERROR_(3, kModuleBootPolicy, kInternal)), \ From 3ef5218811580b0413bf3d3de4aa875c970609f5 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:15:04 +0200 Subject: [PATCH 22/41] [rram_ctrl,sw] add silicon_creator RRAM driver Adds the register-level RRAM controller driver: data/info partition read/write, default-region and per-info-page permissions/config, region protection, and info-page lockdown. write() transparently read-modify-writes unaligned leading/trailing partial write granules, so callers can write arbitrary addr/word_count without worrying about RRAM's 4-word write granularity. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/drivers/BUILD | 21 + .../silicon_creator/lib/drivers/rram_ctrl.c | 599 ++++++++++++++++++ .../silicon_creator/lib/drivers/rram_ctrl.h | 476 ++++++++++++++ 3 files changed, 1096 insertions(+) create mode 100644 sw/device/silicon_creator/lib/drivers/rram_ctrl.c create mode 100644 sw/device/silicon_creator/lib/drivers/rram_ctrl.h diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD index d76a49589e29b..04fe2c0f15aed 100644 --- a/sw/device/silicon_creator/lib/drivers/BUILD +++ b/sw/device/silicon_creator/lib/drivers/BUILD @@ -723,6 +723,27 @@ opentitan_test( ], ) +cc_library( + name = "rram_ctrl", + srcs = ["rram_ctrl.c"], + hdrs = ["rram_ctrl.h"], + deps = [ + ":flash_ctrl", + ":otp", + "//hw/top:otp_ctrl_c_regs", + "//hw/top:rram_ctrl_c_regs", + "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/device/lib/base:abs_mmio", + "//sw/device/lib/base:bitfield", + "//sw/device/lib/base:hardened", + "//sw/device/lib/base:macros", + "//sw/device/lib/base:memory", + "//sw/device/lib/base:multibits", + "//sw/device/silicon_creator/lib:error", + "//sw/device/silicon_creator/lib/base:sec_mmio", + ], +) + dual_cc_library( name = "rstmgr", srcs = dual_inputs( diff --git a/sw/device/silicon_creator/lib/drivers/rram_ctrl.c b/sw/device/silicon_creator/lib/drivers/rram_ctrl.c new file mode 100644 index 0000000000000..c35729fe1d86e --- /dev/null +++ b/sw/device/silicon_creator/lib/drivers/rram_ctrl.c @@ -0,0 +1,599 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/silicon_creator/lib/drivers/rram_ctrl.h" + +#include + +#include "sw/device/lib/base/abs_mmio.h" +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/hardened.h" +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/base/memory.h" +#include "sw/device/lib/base/multibits.h" +#include "sw/device/silicon_creator/lib/base/sec_mmio.h" +#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" +#include "sw/device/silicon_creator/lib/drivers/otp.h" +#include "sw/device/silicon_creator/lib/error.h" + +#include "hw/top/otp_ctrl_regs.h" +#include "hw/top/rram_ctrl_regs.h" +#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" + +// Info pages. +#define INFO_PAGE_STRUCT_DEF_(name_, page_id_, emulated_) \ + const rram_ctrl_info_page_t name_ = { \ + .page_id = (page_id_), \ + .emulated = (emulated_), \ + }; +RRAM_CTRL_INFO_PAGES_DEFINE(INFO_PAGE_STRUCT_DEF_); +#undef INFO_PAGE_STRUCT_DEF_ + +/** + * Base address of the rram_ctrl registers. + * + * There is no devicetree (`dt_rram_ctrl`) support yet, unlike flash_ctrl, + * so the base address is taken directly from the autogenerated top-level + * memory map instead of `dt_rram_ctrl_primary_reg_block()`. + */ +static inline uint32_t rram_ctrl_core_base(void) { + return TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR; +} + +/** + * RRAM transaction parameters. + */ +typedef struct transaction_params { + /** + * Start address of a RRAM transaction. Full byte address; the controller + * truncates to the closest word-aligned address. + */ + uint32_t addr; + /** + * Operation type. Must be one of `RRAM_CTRL_CONTROL_OP_VALUE_*`. + */ + uint32_t op_type; + /** + * Whether the transaction targets the info partition (true) or the data + * partition (false). + */ + bool is_info; + /** + * Number of 32-bit words. + */ + uint32_t word_count; +} transaction_params_t; + +/** + * Starts a RRAM transaction. + * + * @param params Transaction parameters, see `transaction_params_t`. + */ +static void transaction_start(transaction_params_t params) { + abs_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_ADDR_REG_OFFSET, + params.addr); + uint32_t reg = bitfield_bit32_write(0, RRAM_CTRL_CONTROL_START_BIT, true); + reg = bitfield_field32_write(reg, RRAM_CTRL_CONTROL_OP_FIELD, params.op_type); + reg = bitfield_bit32_write(reg, RRAM_CTRL_CONTROL_PARTITION_BIT, + params.is_info); + reg = bitfield_field32_write(reg, RRAM_CTRL_CONTROL_NUM_FIELD, + params.word_count - 1); + abs_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_CONTROL_REG_OFFSET, reg); +} + +/** + * Copies `word_count` words from the read FIFO to the given buffer. + * + * @param word_count Number of words to read from the FIFO. + * @param[out] data Output buffer. + */ +static void fifo_read(size_t word_count, void *data) { + size_t i = 0, r = word_count - 1; + for (; launder32(i) < word_count && launder32(r) < word_count; ++i, --r) { + write_32( + abs_mmio_read32(rram_ctrl_core_base() + RRAM_CTRL_RD_FIFO_REG_OFFSET), + data); + data = (char *)data + sizeof(uint32_t); + } + HARDENED_CHECK_EQ(i, word_count); + HARDENED_CHECK_EQ(r, SIZE_MAX); +} + +/** + * Copies `word_count` words from the given buffer to the write FIFO. + * + * @param word_count Number of words to write to the FIFO. + * @param data Input buffer. + */ +static void fifo_write(size_t word_count, const void *data) { + size_t i = 0, r = word_count - 1; + for (; launder32(i) < word_count && launder32(r) < word_count; ++i, --r) { + abs_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_WR_FIFO_REG_OFFSET, + read_32(data)); + data = (const char *)data + sizeof(uint32_t); + } + HARDENED_CHECK_EQ(i, word_count); + HARDENED_CHECK_EQ(r, SIZE_MAX); +} + +/** + * Blocks until the current RRAM transaction is complete. + * + * @param error Error code to return in case of a RRAM controller error. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t wait_for_done(rom_error_t error) { + uint32_t op_status; + do { + op_status = + abs_mmio_read32(rram_ctrl_core_base() + RRAM_CTRL_OP_STATUS_REG_OFFSET); + } while (!bitfield_bit32_read(op_status, RRAM_CTRL_OP_STATUS_DONE_BIT)); + abs_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_OP_STATUS_REG_OFFSET, 0u); + + if (bitfield_bit32_read(op_status, RRAM_CTRL_OP_STATUS_ERR_BIT)) { + return error; + } + return kErrorOk; +} + +/** + * RRAM controller write transaction word granularity: `write_aligned()` can + * only write a whole number of `kRramWriteGranuleWords`-word granules. All + * other addr/word_count combinations go through `write()`'s read-modify-write + * of the leading/trailing partial granules, so callers (like `nvm_ctrl.c`) + * never have to worry about alignment themselves. + */ +enum { + kRramWriteGranuleWords = 4, + kRramWriteGranuleBytes = kRramWriteGranuleWords * (uint32_t)sizeof(uint32_t), +}; +static_assert((kRramWriteGranuleBytes & (kRramWriteGranuleBytes - 1)) == 0, + "RRAM write granule must be a power of two."); + +/** + * Reads data from the given partition. + * + * @param addr Full byte address to read from. + * @param is_info Whether to read from the info partition (true) or the data + * partition (false). + * @param word_count Number of bus words to read. + * @param[out] data Output buffer. + * @param error Error code to return in case of a RRAM controller error. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t read(uint32_t addr, bool is_info, uint32_t word_count, + void *data, rom_error_t error) { + transaction_start((transaction_params_t){ + .addr = addr, + .op_type = RRAM_CTRL_CONTROL_OP_VALUE_READ, + .is_info = is_info, + .word_count = word_count, + }); + fifo_read(word_count, data); + return wait_for_done(error); +} + +/** + * Writes a `kRramWriteGranuleWords`-aligned, `kRramWriteGranuleWords`-sized + * number of words to the given partition. + * + * RRAM has no equivalent of flash's program-window restriction; writes are + * simply chunked to the maximum transaction word count. + * + * @param addr Full byte address to write to; must be + * `kRramWriteGranuleBytes`-aligned. + * @param is_info Whether to write to the info partition (true) or the data + * partition (false). + * @param word_count Number of bus words to write; must be a multiple of + * `kRramWriteGranuleWords`. + * @param data Data to write. + * @param error Error code to return in case of a RRAM controller error. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t write_aligned(uint32_t addr, bool is_info, + uint32_t word_count, const void *data, + rom_error_t error) { + enum { + kMaxWordCount = RRAM_CTRL_CONTROL_NUM_MASK + 1, + }; + if (word_count % kRramWriteGranuleWords != 0) { + return error; + } + + while (word_count > 0) { + uint32_t chunk_word_count = + word_count < kMaxWordCount ? word_count : kMaxWordCount; + + transaction_start((transaction_params_t){ + .addr = addr, + .op_type = RRAM_CTRL_CONTROL_OP_VALUE_WRITE, + .is_info = is_info, + .word_count = chunk_word_count, + }); + + fifo_write(chunk_word_count, data); + RETURN_IF_ERROR(wait_for_done(error)); + + addr += chunk_word_count * sizeof(uint32_t); + data = (const char *)data + chunk_word_count * sizeof(uint32_t); + word_count -= chunk_word_count; + } + + return kErrorOk; +} + +/** + * Read-modify-writes a single `kRramWriteGranuleBytes`-sized, + * `kRramWriteGranuleBytes`-aligned granule: reads the granule at + * `aligned_addr`, splices in `len` bytes of `data` at byte offset `lead` + * within it (`lead + len` must not exceed `kRramWriteGranuleBytes`), and + * writes the granule back. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t granule_rmw(uint32_t aligned_addr, bool is_info, size_t lead, + const void *data, size_t len, + rom_error_t write_error, + rom_error_t read_error) { + uint8_t buf[kRramWriteGranuleBytes]; + RETURN_IF_ERROR( + read(aligned_addr, is_info, kRramWriteGranuleWords, buf, read_error)); + memcpy(buf + lead, data, len); + return write_aligned(aligned_addr, is_info, kRramWriteGranuleWords, buf, + write_error); +} + +/** + * Writes `word_count` words (need not be a multiple of + * `kRramWriteGranuleWords`) to `addr` (need not be + * `kRramWriteGranuleBytes`-aligned) in the given partition. + * + * Handles any size via read-modify-write on only the leading and trailing + * partial granules (at most `kRramWriteGranuleBytes` of stack buffer at a + * time); the aligned middle portion, if any, is written directly with no + * read. Unbounded in `word_count`. + * + * @param addr Full byte address to write to. + * @param is_info Whether to write to the info partition (true) or the data + * partition (false). + * @param word_count Number of bus words to write. + * @param data Data to write. + * @param write_error Error code to return in case of a write-transaction + * controller error. + * @param read_error Error code to return in case of a read-transaction + * controller error (only reachable via the RMW path). + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t write(uint32_t addr, bool is_info, uint32_t word_count, + const void *data, rom_error_t write_error, + rom_error_t read_error) { + if (word_count == 0) { + return kErrorOk; + } + + size_t byte_count = (size_t)word_count * sizeof(uint32_t); + uint32_t aligned_addr = addr & ~(uint32_t)(kRramWriteGranuleBytes - 1); + size_t lead = addr - aligned_addr; + + if (lead == 0 && byte_count % kRramWriteGranuleBytes == 0) { + // Already granule-aligned on both ends: no RMW needed. + return write_aligned(addr, is_info, word_count, data, write_error); + } + + // Leading (possibly partial) granule. + size_t first_chunk_len = kRramWriteGranuleBytes - lead; + if (first_chunk_len > byte_count) { + first_chunk_len = byte_count; + } + RETURN_IF_ERROR(granule_rmw(aligned_addr, is_info, lead, data, + first_chunk_len, write_error, read_error)); + data = (const char *)data + first_chunk_len; + byte_count -= first_chunk_len; + aligned_addr += kRramWriteGranuleBytes; + + // Aligned middle portion, written directly with no read. + size_t middle_words = + (byte_count / kRramWriteGranuleBytes) * kRramWriteGranuleWords; + if (middle_words > 0) { + RETURN_IF_ERROR(write_aligned(aligned_addr, is_info, (uint32_t)middle_words, + data, write_error)); + size_t middle_bytes = middle_words * sizeof(uint32_t); + data = (const char *)data + middle_bytes; + byte_count -= middle_bytes; + aligned_addr += middle_bytes; + } + + // Trailing partial granule. + if (byte_count > 0) { + RETURN_IF_ERROR(granule_rmw(aligned_addr, is_info, 0, data, byte_count, + write_error, read_error)); + } + return kErrorOk; +} + +void rram_ctrl_init(void) { + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioInit, + kRramCtrlSecMmioDataDefaultCfgSet); + + // Set `HW_INFO_CFG_OVERRIDE` register if needed. Reuses the same OTP word + // and bit layout as flash_ctrl. This must be done before initializing the + // rram_ctrl. + uint32_t reg_val = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL; + uint32_t otp_val = otp_read32( + OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_OFFSET); + multi_bit_bool_t scramble_dis = bitfield_field32_read( + otp_val, FLASH_CTRL_OTP_FIELD_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS); + if (scramble_dis == kMultiBitBool4True) { + reg_val = bitfield_field32_write( + reg_val, RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD, + scramble_dis); + } + multi_bit_bool_t ecc_dis = bitfield_field32_read( + otp_val, FLASH_CTRL_OTP_FIELD_HW_INFO_CFG_OVERRIDE_ECC_DIS); + if (ecc_dis == kMultiBitBool4True) { + reg_val = bitfield_field32_write( + reg_val, RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD, ecc_dis); + } + if (reg_val != RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL) { + sec_mmio_write32( + rram_ctrl_core_base() + RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET, + reg_val); + } + + // Kick off RRAM controller initialization and wait for completion. Unlike + // flash_ctrl, where memory protection only gates the controller's own + // transaction-based (FIFO) reads/writes, rram_ctrl's memory protection also + // gates the direct read path, so RD_EN must be set for the default region + // below before RRAM can be read at all. + abs_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_INIT_REG_OFFSET, + bitfield_bit32_write(0, RRAM_CTRL_INIT_VAL_BIT, true)); + rram_ctrl_status_t status; + do { + rram_ctrl_status_get(&status); + } while (!status.init_done); + + // Configure default scrambling and ECC settings for the data partition. + // Reuses the same `CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG` OTP word and bit + // layout as flash_ctrl; the high-endurance field does not apply to RRAM. + otp_val = + otp_read32(OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_OFFSET); + rram_ctrl_cfg_t data_default_cfg = { + .scrambling = + bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_SCRAMBLING), + .ecc = bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_ECC), + }; + rram_ctrl_data_default_cfg_set(data_default_cfg); +} + +void rram_ctrl_disable(void) { + abs_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_DIS_REG_OFFSET, 0); +} + +void rram_ctrl_status_get(rram_ctrl_status_t *status) { + uint32_t reg = + abs_mmio_read32(rram_ctrl_core_base() + RRAM_CTRL_STATUS_REG_OFFSET); + status->rd_full = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_RD_FULL_BIT); + status->rd_empty = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_RD_EMPTY_BIT); + status->wr_full = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_WR_FULL_BIT); + status->wr_empty = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_WR_EMPTY_BIT); + status->init_done = bitfield_bit32_read(reg, RRAM_CTRL_STATUS_INIT_DONE_BIT); +} + +void rram_ctrl_error_code_get(rram_ctrl_error_code_t *error_code) { + uint32_t code = + abs_mmio_read32(rram_ctrl_core_base() + RRAM_CTRL_ERR_CODE_REG_OFFSET); + error_code->op_err = bitfield_bit32_read(code, RRAM_CTRL_ERR_CODE_OP_ERR_BIT); + error_code->mp_err = bitfield_bit32_read(code, RRAM_CTRL_ERR_CODE_MP_ERR_BIT); + error_code->rd_err = bitfield_bit32_read(code, RRAM_CTRL_ERR_CODE_RD_ERR_BIT); + error_code->wr_err = bitfield_bit32_read(code, RRAM_CTRL_ERR_CODE_WR_ERR_BIT); +} + +rom_error_t rram_ctrl_data_read(uint32_t addr, uint32_t word_count, + void *data) { + return read(addr, /*is_info=*/false, word_count, data, + kErrorRramCtrlDataRead); +} + +static uint32_t info_page_addr(const rram_ctrl_info_page_t *info_page, + uint32_t offset) { + HARDENED_CHECK_EQ(info_page->emulated, false); + return info_page->page_id * RRAM_CTRL_PARAM_BYTES_PER_PAGE + offset; +} + +rom_error_t rram_ctrl_info_read(const rram_ctrl_info_page_t *info_page, + uint32_t offset, uint32_t word_count, + void *data) { + return read(info_page_addr(info_page, offset), /*is_info=*/true, word_count, + data, kErrorRramCtrlInfoRead); +} + +rom_error_t rram_ctrl_info_read_zeros_on_read_error( + const rram_ctrl_info_page_t *info_page, uint32_t offset, + uint32_t word_count, void *data) { + rom_error_t err = rram_ctrl_info_read(info_page, offset, word_count, data); + if (err != kErrorOk) { + rram_ctrl_error_code_t rram_ctrl_err_code; + rram_ctrl_error_code_get(&rram_ctrl_err_code); + if (rram_ctrl_err_code.rd_err) { + // If we encountered a read error, return all 0s. + memset(data, 0, word_count * sizeof(uint32_t)); + return kErrorOk; + } + } + return err; +} + +rom_error_t rram_ctrl_data_write(uint32_t addr, uint32_t word_count, + const void *data) { + return write(addr, /*is_info=*/false, word_count, data, + kErrorRramCtrlDataWrite, kErrorRramCtrlDataRead); +} + +rom_error_t rram_ctrl_info_write(const rram_ctrl_info_page_t *info_page, + uint32_t offset, uint32_t word_count, + const void *data) { + return write(info_page_addr(info_page, offset), /*is_info=*/true, word_count, + data, kErrorRramCtrlInfoWrite, kErrorRramCtrlInfoRead); +} + +void rram_ctrl_exec_set(uint32_t exec_val) { + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioExecSet, 1); + sec_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_EXEC_REG_OFFSET, exec_val); +} + +void rram_ctrl_data_default_perms_set(rram_ctrl_perms_t perms) { + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioDataDefaultPermsSet, 1); + + // Read first to preserve ECC and scrambling bits. + uint32_t reg = sec_mmio_read32(rram_ctrl_core_base() + + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD, + perms.read); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD, + perms.write); + sec_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET, + reg); +} + +void rram_ctrl_info_perms_set(const rram_ctrl_info_page_t *info_page, + rram_ctrl_perms_t perms) { + HARDENED_CHECK_EQ(info_page->emulated, false); + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioInfoPermsSet, 1); + + uint32_t cfg_offset = RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET + + info_page->page_id * sizeof(uint32_t); + // Read first to preserve ECC and scrambling bits. + uint32_t reg = sec_mmio_read32(rram_ctrl_core_base() + cfg_offset); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD, + kMultiBitBool4True); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD, + perms.read); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD, + perms.write); + sec_mmio_write32(rram_ctrl_core_base() + cfg_offset, reg); +} + +void rram_ctrl_data_default_cfg_set(rram_ctrl_cfg_t cfg) { + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioDataDefaultCfgSet, 1); + + // Read first to preserve permission bits. + uint32_t reg = sec_mmio_read32(rram_ctrl_core_base() + + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD, + cfg.scrambling); + reg = bitfield_field32_write(reg, RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD, + cfg.ecc); + sec_mmio_write32(rram_ctrl_core_base() + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET, + reg); +} + +rram_ctrl_cfg_t rram_ctrl_data_default_cfg_get(void) { + const uint32_t default_region = sec_mmio_read32( + rram_ctrl_core_base() + RRAM_CTRL_DEFAULT_REGION_REG_OFFSET); + return (rram_ctrl_cfg_t){ + .scrambling = bitfield_field32_read( + default_region, RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD), + .ecc = bitfield_field32_read(default_region, + RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD), + }; +} + +rram_ctrl_cfg_t rram_ctrl_boot_data_cfg_get(void) { + uint32_t otp_val = + otp_read32(OTP_CTRL_PARAM_CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_OFFSET); + return (rram_ctrl_cfg_t){ + .scrambling = + bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_SCRAMBLING), + .ecc = bitfield_field32_read(otp_val, FLASH_CTRL_OTP_FIELD_ECC), + }; +} + +void rram_ctrl_data_region_protect(rram_ctrl_region_index_t region, + uint32_t page_offset, uint32_t num_pages, + rram_ctrl_perms_t perms, rram_ctrl_cfg_t cfg, + hardened_bool_t lock) { + const uint32_t kBase = rram_ctrl_core_base(); + HARDENED_CHECK_GE(region, 0); + HARDENED_CHECK_LT(region, RRAM_CTRL_PARAM_NUM_REGIONS); + region *= sizeof(uint32_t); + + // Reset the region's configuration via the MP_REGION_CFG_${region} + // register. This temporarily disables memory protection for the region. + // + // We use abs_mmio here because we're going to re-write this value later + // and the intermediate REG_RESVAL should not be considered a valid data + // pattern in this register when we perform a sec_mmio check. + abs_mmio_write32(kBase + RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET + region, + RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL); + + // Set the region's bounds in the MP_REGION_${region} register. + uint32_t mp_region = RRAM_CTRL_MP_REGION_0_REG_RESVAL; + mp_region = bitfield_field32_write( + mp_region, RRAM_CTRL_MP_REGION_0_BASE_0_FIELD, page_offset); + mp_region = bitfield_field32_write( + mp_region, RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD, num_pages); + sec_mmio_write32(kBase + RRAM_CTRL_MP_REGION_0_REG_OFFSET + region, + mp_region); + + // Write the new value of MP_REGION_CFG_${region}. + uint32_t mp_region_cfg = RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL; + mp_region_cfg = bitfield_field32_write( + mp_region_cfg, RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD, cfg.ecc); + mp_region_cfg = bitfield_field32_write( + mp_region_cfg, RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD, + cfg.scrambling); + mp_region_cfg = bitfield_field32_write( + mp_region_cfg, RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD, perms.write); + mp_region_cfg = bitfield_field32_write( + mp_region_cfg, RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD, perms.read); + mp_region_cfg = bitfield_field32_write( + mp_region_cfg, RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4True); + + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioDataRegionProtect, 1); + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioDataRegionProtectLock, 1); + sec_mmio_write32(kBase + RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET + region, + mp_region_cfg); + if (lock != kHardenedBoolFalse) { + sec_mmio_write32(kBase + RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET + region, + 0); + } +} + +void rram_ctrl_info_cfg_set(const rram_ctrl_info_page_t *info_page, + rram_ctrl_cfg_t cfg) { + HARDENED_CHECK_EQ(info_page->emulated, false); + SEC_MMIO_ASSERT_WRITE_INCREMENT(kRramCtrlSecMmioInfoCfgSet, 1); + + uint32_t cfg_offset = RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET + + info_page->page_id * sizeof(uint32_t); + // Read first to preserve permission bits. + uint32_t reg = sec_mmio_read32(rram_ctrl_core_base() + cfg_offset); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD, + kMultiBitBool4True); + reg = bitfield_field32_write( + reg, RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD, cfg.scrambling); + reg = bitfield_field32_write(reg, RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD, + cfg.ecc); + sec_mmio_write32(rram_ctrl_core_base() + cfg_offset, reg); +} + +void rram_ctrl_info_cfg_lock(const rram_ctrl_info_page_t *info_page) { + HARDENED_CHECK_EQ(info_page->emulated, false); + uint32_t regwen_offset = RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET + + info_page->page_id * sizeof(uint32_t); + sec_mmio_write32(rram_ctrl_core_base() + regwen_offset, 0); +} + +void rram_ctrl_info_page_lockdown(const rram_ctrl_info_page_t *info_page) { + HARDENED_CHECK_EQ(info_page->emulated, false); + uint32_t cfg_offset = RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET + + info_page->page_id * sizeof(uint32_t); + uint32_t regwen_offset = RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET + + info_page->page_id * sizeof(uint32_t); + sec_mmio_write32(rram_ctrl_core_base() + cfg_offset, 0); + sec_mmio_write32(rram_ctrl_core_base() + regwen_offset, 0); +} diff --git a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h new file mode 100644 index 0000000000000..95f05c536b787 --- /dev/null +++ b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h @@ -0,0 +1,476 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +#ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_RRAM_CTRL_H_ +#define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_RRAM_CTRL_H_ + +#include + +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/hardened.h" +#include "sw/device/lib/base/multibits.h" +#include "sw/device/silicon_creator/lib/error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * A logical RRAM info page. + * + * Unlike flash, RRAM has only `RRAM_CTRL_PARAM_NUM_INFO_PAGES` (8) physical + * info pages, too few for the 20 logical pages named in `nvm_info_page_t`. + * The 6 most security-sensitive pages (including the ones + * `nvm_ctrl_creator_info_pages_lockdown()` must revoke creator access to) get + * a real, individually-protected info page (`emulated` = false). The + * remaining 14 are "emulated": relocated onto reserved pages of the (much + * larger) RRAM data partition, all sharing a single memory-protection region + * with permissions that can't be restricted per-page. + * + * TODO(#XXXX): because 3 of the 7 pages `nvm_ctrl_creator_info_pages_lockdown` + * must revoke (`BootData0`, `BootData1`, `CreatorReserved0`) are emulated and + * share a region with owner-needed pages (`OwnerSlot0`, `OwnerSlot1`, + * `DiceCerts`), lockdown cannot actually revoke creator access to those 3 + * pages without also breaking owner access to the others. This is a known, + * accepted gap pending hardware changes to add more RRAM info/data + * memory-protection regions. + */ +typedef struct rram_ctrl_info_page { + /** + * Physical page index. + * + * For a real page (`emulated` = false), this is an info-partition page + * index in [0, `RRAM_CTRL_PARAM_NUM_INFO_PAGES` - 1]. For an emulated page + * (`emulated` = true), this is a data-partition page index at or after + * `kRramCtrlEmulPageBase`. + */ + uint32_t page_id; + /** + * Whether this page is emulated on the data partition rather than backed by + * a real RRAM info page. + */ + bool emulated; +} rram_ctrl_info_page_t; + +/** + * First data-partition page reserved for emulated info pages, and the number + * of data pages reserved. All emulated pages share a single + * memory-protection region covering this range. + */ +enum { + kRramCtrlEmulPageBase = 4064, + kRramCtrlEmulPageCount = 14, + /** + * Memory-protection region index (of `RRAM_CTRL_PARAM_NUM_REGIONS`) used + * for the shared emulated-page region. + */ + kRramCtrlEmulRegion = 0, +}; + +/** + * Table of RRAM information pages. + * + * Columns: Name, physical page index, whether emulated. + * We use an X macro to facilitate writing enums, switch statements, and unit + * tests using the constants here, mirroring `FLASH_CTRL_INFO_PAGES_DEFINE`. + */ +// clang-format off +#define RRAM_CTRL_INFO_PAGES_DEFINE(X) \ + /** + * Real, individually-protected info pages. + */ \ + X(kRramCtrlInfoPageFactoryId, 0, false) \ + X(kRramCtrlInfoPageAttestationKeySeeds, 1, false) \ + X(kRramCtrlInfoPageFactoryCerts, 2, false) \ + X(kRramCtrlInfoPageCreatorSecret, 5, false) \ + X(kRramCtrlInfoPageOwnerSecret, 6, false) \ + X(kRramCtrlInfoPageWaferAuthSecret, 7, false) \ + /** + * Emulated info pages, relocated onto the data partition. All share + * `kRramCtrlEmulRegion`'s memory protection; see the TODO on + * `rram_ctrl_info_page_t`. + */ \ + X(kRramCtrlInfoPageOwnerReserved0, kRramCtrlEmulPageBase + 0, true) \ + X(kRramCtrlInfoPageOwnerReserved1, kRramCtrlEmulPageBase + 1, true) \ + X(kRramCtrlInfoPageOwnerReserved2, kRramCtrlEmulPageBase + 2, true) \ + X(kRramCtrlInfoPageOwnerReserved3, kRramCtrlEmulPageBase + 3, true) \ + X(kRramCtrlInfoPageBootData0, kRramCtrlEmulPageBase + 4, true) \ + X(kRramCtrlInfoPageBootData1, kRramCtrlEmulPageBase + 5, true) \ + X(kRramCtrlInfoPageOwnerSlot0, kRramCtrlEmulPageBase + 6, true) \ + X(kRramCtrlInfoPageOwnerSlot1, kRramCtrlEmulPageBase + 7, true) \ + X(kRramCtrlInfoPageCreatorReserved0, kRramCtrlEmulPageBase + 8, true) \ + X(kRramCtrlInfoPageOwnerReserved4, kRramCtrlEmulPageBase + 9, true) \ + X(kRramCtrlInfoPageOwnerReserved5, kRramCtrlEmulPageBase + 10, true) \ + X(kRramCtrlInfoPageOwnerReserved6, kRramCtrlEmulPageBase + 11, true) \ + X(kRramCtrlInfoPageOwnerReserved7, kRramCtrlEmulPageBase + 12, true) \ + X(kRramCtrlInfoPageDiceCerts, kRramCtrlEmulPageBase + 13, true) \ +// clang-format on + +/** + * Helper macro for declaring an extern `rram_ctrl_info_page_t`. + * @param name_ Name of the enumeration constant. + * @param page_id_ Physical page index of the info page. + * @param emulated_ Whether the page is emulated on the data partition. + */ +#define INFO_PAGE_STRUCT_DECL_(name_, page_id_, emulated_) \ + extern const rram_ctrl_info_page_t name_; + +/** + * Info pages. + */ +RRAM_CTRL_INFO_PAGES_DEFINE(INFO_PAGE_STRUCT_DECL_); + +#undef INFO_PAGE_STRUCT_DECL_ + +/** + * The following constants represent the expected number of sec_mmio + * register writes performed by functions provided in this module. See + * `SEC_MMIO_WRITE_INCREMENT()` for more details. + */ +enum { + kRramCtrlSecMmioDataDefaultPermsSet = 1, + kRramCtrlSecMmioDataDefaultCfgSet = 1, + kRramCtrlSecMmioInfoPermsSet = 1, + kRramCtrlSecMmioInfoCfgSet = 1, + kRramCtrlSecMmioInfoCfgLock = 1, + kRramCtrlSecMmioInfoPageLockdown = 2, + kRramCtrlSecMmioExecSet = 1, + kRramCtrlSecMmioDataRegionProtect = 1, + kRramCtrlSecMmioDataRegionProtectLock = 1, + kRramCtrlSecMmioInit = 1, +}; + +/** + * Kicks off the initialization of the RRAM controller. + * + * This must complete before RRAM can be accessed. The init status can be + * queried by calling `rram_ctrl_status_get()` and checking `init_done`. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioInit)` when sec_mmio is being + * used to check expectations. + */ +void rram_ctrl_init(void); + +/** + * Permanently disable the RRAM controller. + */ +void rram_ctrl_disable(void); + +/** + * Status bits. + */ +typedef struct rram_ctrl_status { + /** + * RRAM read FIFO full, software must consume data. + */ + bool rd_full; + /** + * RRAM read FIFO empty. + */ + bool rd_empty; + /** + * RRAM write FIFO full. + */ + bool wr_full; + /** + * RRAM write FIFO empty, software must provide data. + */ + bool wr_empty; + /** + * RRAM controller undergoing init. + */ + bool init_done; +} rram_ctrl_status_t; + +/** + * Query the status registers on the RRAM controller. + * + * @param[out] status The current status of the RRAM controller. + */ +void rram_ctrl_status_get(rram_ctrl_status_t *status); + +/** + * Error code bits. + */ +typedef struct rram_ctrl_error_code { + /** + * Software has supplied an undefined RRAM operation. + */ + bool op_err; + /** + * RRAM access permission error. Read the ERR_ADDR register for the + * faulting address. + */ + bool mp_err; + /** + * RRAM read error, could be an integrity error. + */ + bool rd_err; + /** + * RRAM write error. + */ + bool wr_err; +} rram_ctrl_error_code_t; + +/** + * Query the error code register on the RRAM controller. + * + * @param[out] error_code The current error code of the RRAM controller. + */ +void rram_ctrl_error_code_get(rram_ctrl_error_code_t *error_code); + +/** + * Reads data from the data partition. + * + * @param addr Address to read from. + * @param word_count Number of bus words to read. + * @param[out] data Buffer to store the read data. Must be word aligned. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t rram_ctrl_data_read(uint32_t addr, uint32_t word_count, void *data); + +/** + * Reads data from an information page. + * + * @param info_page Information page to read from. + * @param offset Offset from the start of the page. + * @param word_count Number of bus words to read. + * @param[out] data Buffer to store the read data. Must be word aligned. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t rram_ctrl_info_read(const rram_ctrl_info_page_t *info_page, + uint32_t offset, uint32_t word_count, + void *data); + +/** + * Reads data from an information page, returning all zeros if a read error + * code is encountered. + * + * @param info_page Information page to read from. + * @param offset Offset from the start of the page. + * @param word_count Number of bus words to read. + * @param[out] data Buffer to store the read data. Must be word aligned. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t rram_ctrl_info_read_zeros_on_read_error( + const rram_ctrl_info_page_t *info_page, uint32_t offset, + uint32_t word_count, void *data); + +/** + * Writes data to the data partition. + * + * RRAM supports direct overwrite; unlike flash, no erase is required before + * writing. + * + * @param addr Address to write to. + * @param word_count Number of bus words to write. Must be a multiple of 4. + * @param data Data to write. Must be word aligned. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t rram_ctrl_data_write(uint32_t addr, uint32_t word_count, + const void *data); + +/** + * Writes data to an information page. + * + * @param info_page Information page to write to. + * @param offset Offset from the start of the page. + * @param word_count Number of bus words to write. Must be a multiple of 4. + * @param data Data to write. Must be word aligned. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t rram_ctrl_info_write(const rram_ctrl_info_page_t *info_page, + uint32_t offset, uint32_t word_count, + const void *data); + +/** + * A struct for specifying access permissions. + * + * RRAM has no separate erase permission; unlike flash, write operations + * overwrite in place. + * + * rram_ctrl config registers use 4-bits for boolean values. Use + * `kMultiBitBool4True` to enable and `kMultiBitBool4False` to disable + * permissions. + */ +typedef struct rram_ctrl_perms { + uint32_t _pad0 : 4; + /** + * Read. + */ + uint32_t read : 4; + /** + * Write. + */ + uint32_t write : 4; + uint32_t _pad1 : 20; +} rram_ctrl_perms_t; +OT_ASSERT_SIZE(rram_ctrl_perms_t, 4); + +/** + * Sets default access permissions for the data partition. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioDataDefaultPermsSet)` when + * sec_mmio is being used to check expectations. + * + * @param perms New permissions. + */ +void rram_ctrl_data_default_perms_set(rram_ctrl_perms_t perms); + +/** + * Sets access permissions for a real (non-emulated) info page. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioInfoPermsSet)` when sec_mmio is + * being used to check expectations. + * + * @param info_page A real information page (`emulated` = false). + * @param perms New permissions. + */ +void rram_ctrl_info_perms_set(const rram_ctrl_info_page_t *info_page, + rram_ctrl_perms_t perms); + +/** + * A struct for RRAM configuration settings. + * + * RRAM has no high-endurance concept; unlike flash, no wear-leveling + * configuration is needed. + * + * rram_ctrl config registers use 4-bits for boolean values. Use + * `kMultiBitBool4True` to enable and `kMultiBitBool4False` to disable these + * settings. + */ +typedef struct rram_ctrl_cfg { + uint32_t _pad0 : 12; + /** + * Scrambling. + */ + uint32_t scrambling : 4; + /** + * ECC. + */ + uint32_t ecc : 4; + uint32_t _pad1 : 12; +} rram_ctrl_cfg_t; +OT_ASSERT_SIZE(rram_ctrl_cfg_t, 4); + +/** + * Sets default configuration settings for the data partition. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioDataDefaultCfgSet)` when + * sec_mmio is being used to check expectations. + * + * @param cfg New configuration settings. + */ +void rram_ctrl_data_default_cfg_set(rram_ctrl_cfg_t cfg); + +/** + * Reads the current default configuration settings for the data partition. + * + * @return Current configuration settings. + */ +rram_ctrl_cfg_t rram_ctrl_data_default_cfg_get(void); + +/** + * Reads the boot data info page configuration settings from OTP. + * + * Reuses the same `CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG` OTP word and bit + * layout as flash; the high-endurance field is ignored for RRAM. + * + * @return Current OTP configuration settings. + */ +rram_ctrl_cfg_t rram_ctrl_boot_data_cfg_get(void); + +/** + * A type for rram_ctrl memory protection region indices. + */ +typedef uint32_t rram_ctrl_region_index_t; + +/** + * Configure memory protection for a region of data-partition pages. + * + * Based on the `region` parameter, this function overwrites the + * `MP_REGION_${region}` and `MP_REGION_CFG_${region}` registers. Calling + * this function invalidates previously-configured protections for `region`. + * + * @param region The index of the region to protect. + * @param page_offset The index of the first page in the region. + * @param num_pages The number of pages in the region. + * @param perms The read/write permissions for this region. + * @param cfg RRAM config values that are used to fill in some fields of the + * `MP_REGION_CFG_${region}` register. + * @param lock Lock the configuration for this region. + */ +void rram_ctrl_data_region_protect(rram_ctrl_region_index_t region, + uint32_t page_offset, uint32_t num_pages, + rram_ctrl_perms_t perms, rram_ctrl_cfg_t cfg, + hardened_bool_t lock); + +/** + * Sets configuration settings for a real (non-emulated) info page. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioInfoCfgSet)` when sec_mmio is + * being used to check expectations. + * + * @param info_page A real information page (`emulated` = false). + * @param cfg New configuration settings. + */ +void rram_ctrl_info_cfg_set(const rram_ctrl_info_page_t *info_page, + rram_ctrl_cfg_t cfg); + +/** + * Write-locks configuration settings for a real (non-emulated) info page. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioInfoCfgLock)` when sec_mmio is + * being used to check expectations. + * + * @param info_page A real information page (`emulated` = false). + */ +void rram_ctrl_info_cfg_lock(const rram_ctrl_info_page_t *info_page); + +/** + * Disables all access to a real (non-emulated) info page and locks its + * configuration until reset. + * + * Zeroes both the cfg register (clearing all permissions and configuration + * bits) and the regwen register (preventing further writes to cfg). + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioInfoPageLockdown)` when sec_mmio + * is being used to check expectations. + * + * @param info_page A real information page (`emulated` = false). + */ +void rram_ctrl_info_page_lockdown(const rram_ctrl_info_page_t *info_page); + +/** + * Enable execution from RRAM. + * + * Note: an ePMP region must also be configured in order to execute code in + * RRAM. + * + * The caller is responsible for calling + * `SEC_MMIO_WRITE_INCREMENT(kRramCtrlSecMmioExecSet)` when sec_mmio is being + * used to check expectations. + * + * @param exec_val Value to write to the `rram_ctrl.EXEC` register. + * `RRAM_CTRL_PARAM_EXEC_EN` will enable execution, all other values will + * disable execution. + */ +void rram_ctrl_exec_set(uint32_t exec_val); + +#ifdef __cplusplus +} +#endif + +#endif // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_RRAM_CTRL_H_ From dd826f111253ca191225063b388759d65fdddb7a Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:16:09 +0200 Subject: [PATCH 23/41] [rram_ctrl,sw] add RRAM backend to nvm_ctrl Adds an RRAM implementation of every nvm_ctrl_* entry point alongside the existing flash_ctrl one, selected at build time via HAS_RRAM_CTRL. RRAM has no program/erase distinction, no bank-erase concept, and needs its DEFAULT_REGION read/write permissions bracketed or persistently enabled around data-partition access, unlike flash. Introduces NVM_PROG_PAGE_SIZE (512 B RRAM / 256 B flash) to represent the program/SPI-wrap granularity distinctly from NVM_BYTES_PER_PAGE (the erase granularity), which coincide for RRAM but not for flash. Also adds the "1 bank, 2 slots" NVM_PAGES_PER_SLOT/NVM_BYTES_PER_SLOT addressing macros used by boot policy and ownership code. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/BUILD | 44 ++- sw/device/silicon_creator/lib/nvm_ctrl.c | 423 ++++++++++++++++++++--- sw/device/silicon_creator/lib/nvm_ctrl.h | 118 ++++++- 3 files changed, 527 insertions(+), 58 deletions(-) diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index 246d49032e62e..38be27d6308d0 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -524,17 +524,35 @@ dual_cc_library( name = "nvm_ctrl", srcs = dual_inputs(shared = ["nvm_ctrl.c"]), hdrs = dual_inputs(shared = ["nvm_ctrl.h"]), + # HAS_RRAM_CTRL must be a `defines` (not `copts`/`local_defines`): every + # other target that includes nvm_ctrl.h (bootstrap, ownership, boot_data, + # rom_ext, cert/dice_chain, manuf/ft_personalize, ...) needs to see the + # same macro value nvm_ctrl.c itself was compiled with, since the header + # branches on it too (NVM_BYTES_PER_PAGE, kNvmCtrlSecMmio*, ...). + # Device-only: host-side (unittest) builds always compile the flash + # branch, regardless of which NVM technology the device variant uses + # below. Existing tests mock at the flash_ctrl layer (boot_data_unittest, + # owner_block_unittest, etc.) and nvm_ctrl.c's page_ptr() maps each + # nvm_info_page_t back to the same flash_ctrl_info_page_t pointers those + # tests already expect. + defines = dual_inputs(device = opentitan_if_ip( + "rram_ctrl", + ["HAS_RRAM_CTRL"], + [], + )), deps = dual_inputs( - # The device variant always links the real flash_ctrl driver, even - # when force-included in a host build (e.g. a future shutdown_unittest - # FlashKill-style test verifying real register-level behavior). - device = [dual_cc_device_library_of("//sw/device/silicon_creator/lib/drivers:flash_ctrl")], - # The host variant links the plain flash_ctrl alias, which resolves to - # mock_flash_ctrl on host builds. This lets tests that mock at the - # flash_ctrl layer (boot_data_unittest, owner_block_unittest, etc.) - # keep working unchanged, since nvm_ctrl.c's page_ptr() maps each - # nvm_info_page_t back to the same flash_ctrl_info_page_t pointers - # those tests already expect. + # The device variant links the real flash_ctrl driver, even when + # force-included in a host build (e.g. a future shutdown_unittest + # FlashKill-style test verifying real register-level behavior); on + # tops with rram_ctrl, it links that driver instead. + device = [dual_cc_device_library_of("//sw/device/silicon_creator/lib/drivers:flash_ctrl")] + + opentitan_if_ip( + "rram_ctrl", + ["//sw/device/silicon_creator/lib/drivers:rram_ctrl"], + [], + ), + # The host variant always links the plain flash_ctrl alias (see the + # comment above), regardless of the top's actual NVM technology. host = ["//sw/device/silicon_creator/lib/drivers:flash_ctrl"], shared = [ ":error", @@ -543,7 +561,11 @@ dual_cc_library( "//sw/device/lib/base:hardened", "//sw/device/lib/base:macros", "//sw/device/lib/base:multibits", - ], + ] + opentitan_if_ip( + "rram_ctrl", + ["//hw/top:rram_ctrl_c_regs"], + [], + ), ), ) diff --git a/sw/device/silicon_creator/lib/nvm_ctrl.c b/sw/device/silicon_creator/lib/nvm_ctrl.c index fa0d95a6fe39d..aa08b22ea2553 100644 --- a/sw/device/silicon_creator/lib/nvm_ctrl.c +++ b/sw/device/silicon_creator/lib/nvm_ctrl.c @@ -7,17 +7,59 @@ #include "sw/device/lib/base/hardened.h" #include "sw/device/lib/base/macros.h" #include "sw/device/silicon_creator/lib/base/sec_mmio.h" + +#ifdef HAS_RRAM_CTRL +#include "sw/device/lib/base/memory.h" +#include "sw/device/silicon_creator/lib/drivers/rram_ctrl.h" +#else #include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" +#endif // HAS_RRAM_CTRL // --------------------------------------------------------------------------- -// Internal: info page count per bank in the type-0 info partition. +// Internal: info page count per bank in the wire-format (bank, page) address +// bridge (see `nvm_ctrl_info_page_lookup`). +// +// These are fixed constants independent of NVM technology: on-flash owner +// config structs encode info pages as (bank, page) pairs assuming 2 banks of +// 10 pages each, matching flash's original type-0 info partition layout. +// `NVM_NUM_BANKS` must not be used here instead of `kNvmWireFormatBankCount`: +// it is a hardware-derived value (1 for RRAM, which has no bank concept) and +// would incorrectly reject bank-1 pages (BootData0/1, OwnerSlot0/1, +// DiceCerts, ...) that owner configs still legitimately encode. // --------------------------------------------------------------------------- -enum { kNvmInfoPagesPerBank = FLASH_CTRL_PARAM_NUM_INFOS0 }; +enum { + kNvmInfoPagesPerBank = 10, + kNvmWireFormatBankCount = 2, +}; // --------------------------------------------------------------------------- -// Internal: mapping from nvm_info_page_t enum to flash_ctrl page pointer. +// Internal: mapping from nvm_info_page_t enum to a driver-level page pointer. // Order must match nvm_info_page_t definition in nvm_ctrl.h. // --------------------------------------------------------------------------- +#ifdef HAS_RRAM_CTRL +static const rram_ctrl_info_page_t *const kPageTable[] = { + [kNvmInfoPageFactoryId] = &kRramCtrlInfoPageFactoryId, + [kNvmInfoPageCreatorSecret] = &kRramCtrlInfoPageCreatorSecret, + [kNvmInfoPageOwnerSecret] = &kRramCtrlInfoPageOwnerSecret, + [kNvmInfoPageWaferAuthSecret] = &kRramCtrlInfoPageWaferAuthSecret, + [kNvmInfoPageAttestationKeySeeds] = &kRramCtrlInfoPageAttestationKeySeeds, + [kNvmInfoPageOwnerReserved0] = &kRramCtrlInfoPageOwnerReserved0, + [kNvmInfoPageOwnerReserved1] = &kRramCtrlInfoPageOwnerReserved1, + [kNvmInfoPageOwnerReserved2] = &kRramCtrlInfoPageOwnerReserved2, + [kNvmInfoPageOwnerReserved3] = &kRramCtrlInfoPageOwnerReserved3, + [kNvmInfoPageFactoryCerts] = &kRramCtrlInfoPageFactoryCerts, + [kNvmInfoPageBootData0] = &kRramCtrlInfoPageBootData0, + [kNvmInfoPageBootData1] = &kRramCtrlInfoPageBootData1, + [kNvmInfoPageOwnerSlot0] = &kRramCtrlInfoPageOwnerSlot0, + [kNvmInfoPageOwnerSlot1] = &kRramCtrlInfoPageOwnerSlot1, + [kNvmInfoPageCreatorReserved0] = &kRramCtrlInfoPageCreatorReserved0, + [kNvmInfoPageOwnerReserved4] = &kRramCtrlInfoPageOwnerReserved4, + [kNvmInfoPageOwnerReserved5] = &kRramCtrlInfoPageOwnerReserved5, + [kNvmInfoPageOwnerReserved6] = &kRramCtrlInfoPageOwnerReserved6, + [kNvmInfoPageOwnerReserved7] = &kRramCtrlInfoPageOwnerReserved7, + [kNvmInfoPageDiceCerts] = &kRramCtrlInfoPageDiceCerts, +}; +#else static const flash_ctrl_info_page_t *const kPageTable[] = { [kNvmInfoPageFactoryId] = &kFlashCtrlInfoPageFactoryId, [kNvmInfoPageCreatorSecret] = &kFlashCtrlInfoPageCreatorSecret, @@ -40,15 +82,78 @@ static const flash_ctrl_info_page_t *const kPageTable[] = { [kNvmInfoPageOwnerReserved7] = &kFlashCtrlInfoPageOwnerReserved7, [kNvmInfoPageDiceCerts] = &kFlashCtrlInfoPageDiceCerts, }; +#endif // HAS_RRAM_CTRL -// Software page count must not exceed hardware capacity -static_assert(ARRAYSIZE(kPageTable) <= NVM_NUM_BANKS * kNvmInfoPagesPerBank, - "More named pages than hardware supports"); +// The wire format reserves 2 banks x kNvmInfoPagesPerBank addressable slots, +// independent of the number of banks the underlying technology actually has. +static_assert(ARRAYSIZE(kPageTable) <= 2 * kNvmInfoPagesPerBank, + "More named pages than the wire format supports"); // --------------------------------------------------------------------------- // Internal helpers // --------------------------------------------------------------------------- +#ifdef HAS_RRAM_CTRL +static const rram_ctrl_info_page_t *page_ptr(nvm_info_page_t page) { + HARDENED_CHECK_LT((uint32_t)page, ARRAYSIZE(kPageTable)); + return kPageTable[(uint32_t)page]; +} + +static rram_ctrl_perms_t perms_to_rram(nvm_page_perms_t p) { + return (rram_ctrl_perms_t){ + .read = (uint32_t)p.read, + .write = (uint32_t)p.write, + }; +} + +static rram_ctrl_cfg_t cfg_to_rram(nvm_page_cfg_t c) { + return (rram_ctrl_cfg_t){ + .scrambling = (uint32_t)c.scrambling, + .ecc = (uint32_t)c.ecc, + }; +} + +static nvm_page_cfg_t cfg_from_rram(rram_ctrl_cfg_t c) { + return (nvm_page_cfg_t){ + .scrambling = (multi_bit_bool_t)c.scrambling, + .ecc = (multi_bit_bool_t)c.ecc, + .he = kMultiBitBool4False, + }; +} + +/** + * Overwrites an info page with the all-1s "erased" pattern. + * + * RRAM has no erase primitive; this approximates flash's per-page erase by + * directly overwriting the page's contents, for both real and emulated pages + * (emulated pages are addressed individually within the shared data-partition + * region, so this only touches the target page's own bytes). + */ +OT_WARN_UNUSED_RESULT +static rom_error_t rram_info_page_erase(const rram_ctrl_info_page_t *p) { + enum { kChunkWords = 64 }; + uint32_t chunk[kChunkWords]; + memset(chunk, 0xff, sizeof(chunk)); + + uint32_t words_left = NVM_BYTES_PER_PAGE / sizeof(uint32_t); + uint32_t word_offset = 0; + while (words_left > 0) { + uint32_t n = words_left < kChunkWords ? words_left : kChunkWords; + rom_error_t err; + if (p->emulated) { + err = rram_ctrl_data_write( + p->page_id * NVM_BYTES_PER_PAGE + word_offset * sizeof(uint32_t), n, + chunk); + } else { + err = rram_ctrl_info_write(p, word_offset * sizeof(uint32_t), n, chunk); + } + HARDENED_RETURN_IF_ERROR(err); + word_offset += n; + words_left -= n; + } + return kErrorOk; +} +#else static const flash_ctrl_info_page_t *page_ptr(nvm_info_page_t page) { HARDENED_CHECK_LT((uint32_t)page, ARRAYSIZE(kPageTable)); return kPageTable[(uint32_t)page]; @@ -77,6 +182,7 @@ static nvm_page_cfg_t cfg_from_flash(flash_ctrl_cfg_t c) { .he = (multi_bit_bool_t)c.he, }; } +#endif // HAS_RRAM_CTRL // --------------------------------------------------------------------------- // Named constants @@ -117,20 +223,13 @@ const nvm_page_perms_t kNvmCertInfoPageOwnerAccess = { .write = kMultiBitBool4False, .erase = kMultiBitBool4False}; -// --------------------------------------------------------------------------- -// Lifecycle -// --------------------------------------------------------------------------- - -void nvm_ctrl_init(void) { flash_ctrl_init(); } -void nvm_ctrl_disable(void) { flash_ctrl_disable(); } - // --------------------------------------------------------------------------- // Wire-format bridge // --------------------------------------------------------------------------- rom_error_t nvm_ctrl_info_page_lookup(uint8_t bank, uint8_t page, nvm_info_page_t *out) { - if ((uint32_t)bank >= (uint32_t)NVM_NUM_BANKS || + if ((uint32_t)bank >= (uint32_t)kNvmWireFormatBankCount || (uint32_t)page >= (uint32_t)kNvmInfoPagesPerBank) { return kErrorNvmCtrlInvalidInfoPage; } @@ -138,10 +237,269 @@ rom_error_t nvm_ctrl_info_page_lookup(uint8_t bank, uint8_t page, return kErrorOk; } +static const nvm_info_page_t kNvmPagesNoOwnerAccess[] = { + kNvmInfoPageFactoryId, kNvmInfoPageCreatorSecret, + kNvmInfoPageOwnerSecret, kNvmInfoPageWaferAuthSecret, + kNvmInfoPageBootData0, kNvmInfoPageBootData1, + kNvmInfoPageCreatorReserved0, +}; + +enum { + kNvmPagesNoOwnerAccessCount = ARRAYSIZE(kNvmPagesNoOwnerAccess), +}; + // --------------------------------------------------------------------------- -// Data partition I/O +// Technology-specific implementation. +// +// Every `nvm_ctrl_*` function declared in nvm_ctrl.h (besides the +// tech-independent ones above and the cert-page helpers below, which are +// built on top of these) is implemented once here for RRAM and once for +// flash, rather than function-by-function, to keep each technology's full +// behavior readable as a single, self-contained unit. // --------------------------------------------------------------------------- +#ifdef HAS_RRAM_CTRL + +void nvm_ctrl_init(void) { + rram_ctrl_init(); + // `DEFAULT_REGION.RD_EN` resets to false in hardware, and boot data lives + // on an emulated info page (mapped onto the data partition), so it must be + // persistently enabled here rather than only bracketing individual + // operations like `nvm_ctrl_page_program` does. + rram_ctrl_data_default_perms_set((rram_ctrl_perms_t){ + .read = kMultiBitBool4True, + .write = kMultiBitBool4False, + }); +} + +void nvm_ctrl_disable(void) { rram_ctrl_disable(); } + +rom_error_t nvm_ctrl_data_read(uint32_t addr, uint32_t word_count, void *data) { + return rram_ctrl_data_read(addr, word_count, data); +} + +rom_error_t nvm_ctrl_data_write(uint32_t addr, uint32_t word_count, + const void *data) { + return rram_ctrl_data_write(addr, word_count, data); +} + +rom_error_t nvm_ctrl_data_erase(uint32_t addr) { + // RRAM supports direct overwrite; no erase step is required before a + // write. + (void)addr; + return kErrorOk; +} + +rom_error_t nvm_ctrl_data_erase_verify(uint32_t addr) { + (void)addr; + return kErrorOk; +} + +rom_error_t nvm_ctrl_chip_erase(void) { return kErrorOk; } + +rom_error_t nvm_ctrl_chip_erase_verify(void) { return kErrorOk; } + +rom_error_t nvm_ctrl_page_program(uint32_t addr, size_t byte_count, + uint8_t *data) { + enum { + kProgPageSize = NVM_PROG_PAGE_SIZE, + kProgPageMask = kProgPageSize - 1, + }; + + // Round up to next NVM word and fill missing bytes with 0xff. + size_t word_misalignment = byte_count & (NVM_BYTES_PER_WORD - 1); + if (word_misalignment > 0) { + size_t pad = NVM_BYTES_PER_WORD - word_misalignment; + for (size_t i = 0; i < pad; ++i) { + data[byte_count++] = 0xff; + } + } + size_t rem_word_count = byte_count / sizeof(uint32_t); + + // Unlike flash, RRAM's memory protection also gates the FIFO-transaction + // read path used by `rram_ctrl_data_write()`'s internal read-modify-write + // of unaligned partial granules, so read must be enabled here in addition + // to write. + rram_ctrl_data_default_perms_set((rram_ctrl_perms_t){ + .read = kMultiBitBool4True, + .write = kMultiBitBool4True, + }); + // Split the write if addr is not `kProgPageSize`-aligned: first chunk fills + // up to the page boundary, second chunk starts at the aligned address (SPI + // PAGE_PROGRAM wrapping semantics). `rram_ctrl_data_write` itself handles + // any addr/word_count alignment, so no further splitting is needed within + // each chunk. + rom_error_t err_0 = kErrorOk; + size_t prog_page_misalignment = addr & kProgPageMask; + if (prog_page_misalignment > 0) { + size_t word_count = + (kProgPageSize - prog_page_misalignment) / sizeof(uint32_t); + if (word_count > rem_word_count) { + word_count = rem_word_count; + } + err_0 = rram_ctrl_data_write(addr, (uint32_t)word_count, data); + rem_word_count -= word_count; + data += word_count * sizeof(uint32_t); + addr &= ~(uint32_t)kProgPageMask; + } + rom_error_t err_1 = kErrorOk; + if (rem_word_count > 0) { + err_1 = rram_ctrl_data_write(addr, (uint32_t)rem_word_count, data); + } + rram_ctrl_data_default_perms_set((rram_ctrl_perms_t){ + .read = kMultiBitBool4False, + .write = kMultiBitBool4False, + }); + HARDENED_RETURN_IF_ERROR(err_0); + return err_1; +} + +rom_error_t nvm_ctrl_sector_erase(uint32_t addr) { + // RRAM supports direct overwrite; no erase step is required. + (void)addr; + return kErrorOk; +} + +rom_error_t nvm_ctrl_info_read(nvm_info_page_t page, uint32_t offset, + uint32_t word_count, void *data) { + const rram_ctrl_info_page_t *p = page_ptr(page); + if (p->emulated) { + return rram_ctrl_data_read(p->page_id * NVM_BYTES_PER_PAGE + offset, + word_count, data); + } + return rram_ctrl_info_read(p, offset, word_count, data); +} + +rom_error_t nvm_ctrl_info_read_zeros_on_read_error(nvm_info_page_t page, + uint32_t offset, + uint32_t word_count, + void *data) { + const rram_ctrl_info_page_t *p = page_ptr(page); + if (p->emulated) { + // Emulated pages are plain data-partition reads; there is no separate + // "zeros on read error" data-partition primitive to fall back to. + return rram_ctrl_data_read(p->page_id * NVM_BYTES_PER_PAGE + offset, + word_count, data); + } + return rram_ctrl_info_read_zeros_on_read_error(p, offset, word_count, data); +} + +rom_error_t nvm_ctrl_info_write(nvm_info_page_t page, uint32_t offset, + uint32_t word_count, const void *data) { + const rram_ctrl_info_page_t *p = page_ptr(page); + if (p->emulated) { + return rram_ctrl_data_write(p->page_id * NVM_BYTES_PER_PAGE + offset, + word_count, data); + } + return rram_ctrl_info_write(p, offset, word_count, data); +} + +rom_error_t nvm_ctrl_info_erase(nvm_info_page_t page) { + return rram_info_page_erase(page_ptr(page)); +} + +void nvm_ctrl_data_default_perms_set(nvm_page_perms_t perms) { + rram_ctrl_data_default_perms_set(perms_to_rram(perms)); +} + +// clang-format off +// NOTE (RRAM): the functions below are no-ops for emulated info pages, since +// emulated pages share one memory-protection region with a fixed, +// always-open policy and cannot be configured individually; see the TODO on +// `rram_ctrl_info_page_t`. Callers at existing SEC_MMIO_WRITE_INCREMENT() +// call sites assume a fixed number of actual register writes regardless of +// which page they target; on an emulated page these no-ops perform fewer +// (typically zero) writes than that, so `sec_mmio_check_counters()` will see +// fewer actual writes than expected on any boot path that calls one of these +// on an emulated page. Auditing/adjusting those call sites (in ownership.c, +// boot_data.c, owner_block.c, cert/dice_chain.c, manuf/ft_personalize.c, +// rom_ext.c, etc.) to account for real vs. emulated pages is a known, +// accepted follow-up, not solved here. +// clang-format on +void nvm_ctrl_info_perms_set(nvm_info_page_t page, nvm_page_perms_t perms) { + const rram_ctrl_info_page_t *p = page_ptr(page); + if (p->emulated) { + return; + } + rram_ctrl_info_perms_set(p, perms_to_rram(perms)); +} + +void nvm_ctrl_data_default_cfg_set(nvm_page_cfg_t cfg) { + rram_ctrl_data_default_cfg_set(cfg_to_rram(cfg)); +} + +nvm_page_cfg_t nvm_ctrl_data_default_cfg_get(void) { + return cfg_from_rram(rram_ctrl_data_default_cfg_get()); +} + +nvm_page_cfg_t nvm_ctrl_boot_data_cfg_get(void) { + return cfg_from_rram(rram_ctrl_boot_data_cfg_get()); +} + +// See the RRAM emulated-page NOTE above `nvm_ctrl_info_perms_set`. +void nvm_ctrl_info_cfg_set(nvm_info_page_t page, nvm_page_cfg_t cfg) { + const rram_ctrl_info_page_t *p = page_ptr(page); + if (p->emulated) { + return; + } + rram_ctrl_info_cfg_set(p, cfg_to_rram(cfg)); +} + +// See the RRAM emulated-page NOTE above `nvm_ctrl_info_perms_set`. +void nvm_ctrl_info_cfg_lock(nvm_info_page_t page) { + const rram_ctrl_info_page_t *p = page_ptr(page); + if (p->emulated) { + return; + } + rram_ctrl_info_cfg_lock(p); +} + +void nvm_ctrl_data_region_protect(uint32_t region, uint32_t page_offset, + uint32_t num_pages, nvm_page_perms_t perms, + nvm_page_cfg_t cfg, hardened_bool_t lock) { + rram_ctrl_data_region_protect(region, page_offset, num_pages, + perms_to_rram(perms), cfg_to_rram(cfg), lock); +} + +void nvm_ctrl_bank_erase_perms_set(hardened_bool_t enable) { + // RRAM has no bank-erase concept; nothing to permission-gate. The only + // caller, `nvm_ctrl_chip_erase`, is itself a no-op for RRAM. + (void)enable; +} + +void nvm_ctrl_exec_set(uint32_t exec_val) { rram_ctrl_exec_set(exec_val); } + +void nvm_ctrl_creator_info_pages_lockdown(void) { + // Only 4 of the 7 pages below are real (non-emulated) RRAM info pages; see + // the loop below and the TODO on `rram_ctrl_info_page_t`. + SEC_MMIO_ASSERT_WRITE_INCREMENT(kNvmCtrlSecMmioCreatorInfoPagesLockdown, 8); + size_t i = 0, r = kNvmPagesNoOwnerAccessCount - 1; + for (; launder32(i) < kNvmPagesNoOwnerAccessCount && + launder32(r) < kNvmPagesNoOwnerAccessCount; + ++i, --r) { + const rram_ctrl_info_page_t *p = page_ptr(kNvmPagesNoOwnerAccess[i]); + // Of the 7 pages above, 3 (BootData0, BootData1, CreatorReserved0) are + // emulated and share a memory-protection region with owner-needed pages + // (OwnerSlot0/1, DiceCerts, ...); lockdown cannot revoke creator access + // to an emulated page without also breaking owner access to the others + // sharing its region. Known, accepted gap; see the TODO on + // `rram_ctrl_info_page_t`. `kNvmCtrlSecMmioCreatorInfoPagesLockdown` is + // tech-conditional in nvm_ctrl.h and already accounts for only the real + // pages below being written. + if (!p->emulated) { + rram_ctrl_info_page_lockdown(p); + } + } + HARDENED_CHECK_EQ(i, kNvmPagesNoOwnerAccessCount); + HARDENED_CHECK_EQ(r, SIZE_MAX); +} + +#else // !HAS_RRAM_CTRL + +void nvm_ctrl_init(void) { flash_ctrl_init(); } + +void nvm_ctrl_disable(void) { flash_ctrl_disable(); } + rom_error_t nvm_ctrl_data_read(uint32_t addr, uint32_t word_count, void *data) { return flash_ctrl_data_read(addr, word_count, data); } @@ -184,7 +542,7 @@ rom_error_t nvm_ctrl_page_program(uint32_t addr, size_t byte_count, "Bytes per NVM word must be a power of two."); enum { kWordMask = FLASH_CTRL_PARAM_BYTES_PER_WORD - 1, - kProgPageSize = 256, + kProgPageSize = NVM_PROG_PAGE_SIZE, kProgPageMask = kProgPageSize - 1, }; @@ -203,8 +561,8 @@ rom_error_t nvm_ctrl_page_program(uint32_t addr, size_t byte_count, .write = kMultiBitBool4True, .erase = kMultiBitBool4False, }); - // Split the write if addr is not 256-byte aligned: first chunk fills up to - // the 256-byte boundary, second chunk starts at the aligned address (SPI + // Split the write if addr is not `kProgPageSize`-aligned: first chunk fills + // up to the page boundary, second chunk starts at the aligned address (SPI // PAGE_PROGRAM wrapping semantics). rom_error_t err_0 = kErrorOk; size_t prog_page_misalignment = addr & kProgPageMask; @@ -254,10 +612,6 @@ rom_error_t nvm_ctrl_sector_erase(uint32_t addr) { return err_1; } -// --------------------------------------------------------------------------- -// Info page I/O -// --------------------------------------------------------------------------- - rom_error_t nvm_ctrl_info_read(nvm_info_page_t page, uint32_t offset, uint32_t word_count, void *data) { return flash_ctrl_info_read(page_ptr(page), offset, word_count, data); @@ -280,10 +634,6 @@ rom_error_t nvm_ctrl_info_erase(nvm_info_page_t page) { return flash_ctrl_info_erase(page_ptr(page), kFlashCtrlEraseTypePage); } -// --------------------------------------------------------------------------- -// Permissions and configuration -// --------------------------------------------------------------------------- - void nvm_ctrl_data_default_perms_set(nvm_page_perms_t perms) { flash_ctrl_data_default_perms_set(perms_to_flash(perms)); } @@ -312,10 +662,6 @@ void nvm_ctrl_info_cfg_lock(nvm_info_page_t page) { flash_ctrl_info_cfg_lock(page_ptr(page)); } -// --------------------------------------------------------------------------- -// Data region protection -// --------------------------------------------------------------------------- - void nvm_ctrl_data_region_protect(uint32_t region, uint32_t page_offset, uint32_t num_pages, nvm_page_perms_t perms, nvm_page_cfg_t cfg, hardened_bool_t lock) { @@ -330,21 +676,6 @@ void nvm_ctrl_bank_erase_perms_set(hardened_bool_t enable) { void nvm_ctrl_exec_set(uint32_t exec_val) { flash_ctrl_exec_set(exec_val); } -// --------------------------------------------------------------------------- -// Lockdown and certificate page management -// --------------------------------------------------------------------------- - -static const nvm_info_page_t kNvmPagesNoOwnerAccess[] = { - kNvmInfoPageFactoryId, kNvmInfoPageCreatorSecret, - kNvmInfoPageOwnerSecret, kNvmInfoPageWaferAuthSecret, - kNvmInfoPageBootData0, kNvmInfoPageBootData1, - kNvmInfoPageCreatorReserved0, -}; - -enum { - kNvmPagesNoOwnerAccessCount = ARRAYSIZE(kNvmPagesNoOwnerAccess), -}; - void nvm_ctrl_creator_info_pages_lockdown(void) { SEC_MMIO_ASSERT_WRITE_INCREMENT(kNvmCtrlSecMmioCreatorInfoPagesLockdown, 2 * kNvmPagesNoOwnerAccessCount); @@ -358,6 +689,8 @@ void nvm_ctrl_creator_info_pages_lockdown(void) { HARDENED_CHECK_EQ(r, SIZE_MAX); } +#endif // HAS_RRAM_CTRL + void nvm_ctrl_cert_info_page_creator_cfg(nvm_info_page_t page) { SEC_MMIO_ASSERT_WRITE_INCREMENT(kNvmCtrlSecMmioCertInfoPageCreatorCfg, 2); nvm_ctrl_info_cfg_set(page, kNvmCertInfoPageCfg); diff --git a/sw/device/silicon_creator/lib/nvm_ctrl.h b/sw/device/silicon_creator/lib/nvm_ctrl.h index d67c572fbe570..0ac0cfbdf6bf7 100644 --- a/sw/device/silicon_creator/lib/nvm_ctrl.h +++ b/sw/device/silicon_creator/lib/nvm_ctrl.h @@ -17,6 +17,10 @@ #include "hw/top/flash_ctrl_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#ifdef HAS_RRAM_CTRL +#include "hw/top/rram_ctrl_regs.h" +#endif // HAS_RRAM_CTRL + #ifdef __cplusplus extern "C" { #endif @@ -25,6 +29,46 @@ extern "C" { // NVM layout constants // --------------------------------------------------------------------------- +#ifdef HAS_RRAM_CTRL +/** Byte size of one NVM page. */ +#define NVM_BYTES_PER_PAGE RRAM_CTRL_PARAM_BYTES_PER_PAGE +/** + * Byte size of one NVM program/read word. + * + * This is a fixed, tech-agnostic value (matching flash's + * `FLASH_CTRL_PARAM_BYTES_PER_WORD`), not `RRAM_CTRL_PARAM_BYTES_PER_WORD` + * (16): callers like `boot_data.c` use it to size wire-format struct fields + * (e.g. `boot_data_t.is_valid`) that must stay identical regardless of NVM + * technology. RRAM's actual write granularity (4x this, 16 bytes) is a + * separate, driver-internal detail handled by `nvm_ctrl.c`/`rram_ctrl.c`. + */ +#define NVM_BYTES_PER_WORD 8 +/** + * Number of NVM banks. + * + * RRAM has no bank-erase concept, so the whole data partition is treated as + * a single bank; `NVM_BYTES_PER_BANK`/`NVM_PAGES_PER_BANK` describe the full + * data partition. Slot A/B addressing (the only thing that matters for + * dual-bank redundancy) is computed from `NVM_DATA_BASE_ADDR`/ + * `NVM_DATA_SIZE_BYTES` directly and does not depend on this value. + */ +#define NVM_NUM_BANKS 1u +/** Number of data pages per NVM bank. */ +#define NVM_PAGES_PER_BANK RRAM_CTRL_PARAM_NUM_DATA_PAGES +/** Byte size of one NVM bank. */ +#define NVM_BYTES_PER_BANK (NVM_PAGES_PER_BANK * NVM_BYTES_PER_PAGE) +/** + * Base address of the NVM data partition in the system memory map. + * + * This is the CPU-visible, memory-mapped execute-in-place window (used e.g. + * to determine the current boot slot from the program counter), distinct + * from the 0-based byte offsets `rram_ctrl_data_read`/`_write` operate on. + */ +#define NVM_DATA_BASE_ADDR TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR +/** Total byte size of the NVM data partition. */ +#define NVM_DATA_SIZE_BYTES \ + (RRAM_CTRL_PARAM_NUM_DATA_PAGES * RRAM_CTRL_PARAM_BYTES_PER_PAGE) +#else /** Byte size of one NVM page. */ #define NVM_BYTES_PER_PAGE FLASH_CTRL_PARAM_BYTES_PER_PAGE /** Byte size of one NVM program/read word. */ @@ -39,6 +83,40 @@ extern "C" { #define NVM_DATA_BASE_ADDR TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR /** Total byte size of the NVM data partition. */ #define NVM_DATA_SIZE_BYTES TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES +#endif // HAS_RRAM_CTRL + +/** + * Page/byte count of one firmware slot (A or B). + * + * There are always exactly two slots, splitting the NVM data partition in + * half regardless of technology: two banks of one slot each for flash, or one + * bank of two slots for RRAM. + */ +#define NVM_PAGES_PER_SLOT ((NVM_NUM_BANKS * NVM_PAGES_PER_BANK) / 2) +#define NVM_BYTES_PER_SLOT (NVM_PAGES_PER_SLOT * NVM_BYTES_PER_PAGE) + +/** + * Byte size of one NVM program transaction / SPI `PAGE_PROGRAM` "page". + * + * This is the SPI `PAGE_PROGRAM` wrap-around unit `nvm_ctrl_page_program()` + * uses internally, and the natural write-transaction size for the + * underlying NVM technology. It is NOT the same concept as + * `NVM_BYTES_PER_PAGE` (the erase granularity) -- the two happen to coincide + * for RRAM (both 512), but differ for flash (2048 erase vs. 256 + * program/SPI-wrap). + * + * For RRAM, this matches `rram_phy_wr`'s store-buffer size (`BytesPerPage` + * in `rram_ctrl.hjson`): a write up to this size commits to the array as a + * single physical operation, and a write that straddles two of these units + * costs an extra one. For flash, it's simply the SPI NOR industry-standard + * `PAGE_PROGRAM` wrap size, with no known equivalent benefit to writing + * more than one at a time. + */ +#ifdef HAS_RRAM_CTRL +#define NVM_PROG_PAGE_SIZE 512 +#else +#define NVM_PROG_PAGE_SIZE 256 +#endif /** Value of a word in NVM after erase. */ enum { kNvmErasedWord = UINT32_MAX }; @@ -131,11 +209,39 @@ typedef enum nvm_info_page { // Drop-in replacements for kFlashCtrlSecMmio* — identical numeric values. // Callers keep their SEC_MMIO_WRITE_INCREMENT() call sites; only the constant // name changes during migration. +// +// RRAM caveat: `kNvmCtrlSecMmioInfoPermsSet`, `kNvmCtrlSecMmioInfoCfgSet`, +// `kNvmCtrlSecMmioInfoCfgLock`, `kNvmCtrlSecMmioCertInfoPageCreatorCfg`, and +// `kNvmCtrlSecMmioCertInfoPageOwnerRestrict` are single constants shared by +// call sites that each target a caller-chosen `nvm_info_page_t`. For RRAM, +// `nvm_ctrl_info_perms_set`/`_cfg_set`/`_cfg_lock` are no-ops on an emulated +// info page (see the TODO on `rram_ctrl_info_page_t`), so any call site +// targeting an emulated page (e.g. OwnerSlot0/1, DiceCerts, OwnerReserved4-7) +// performs fewer actual register writes than these constants assume. This is +// a known, accepted gap for call sites whose target page varies at runtime: +// making those fully correct would require auditing every call site +// (ownership.c, owner_block.c, cert/dice_chain.c, manuf/ft_personalize.c, +// rom_ext.c, ...) to conditionally increment based on the specific page +// targeted. Call sites with a FIXED, statically-known page set don't have +// this excuse and must account for emulated pages precisely: +// `kNvmCtrlSecMmioCreatorInfoPagesLockdown` (fixed inside nvm_ctrl.c) does so +// below, and `boot_data.c`'s three call sites (always BootData0/BootData1, +// always emulated on RRAM) do so with their own `#ifdef HAS_RRAM_CTRL` at +// each `SEC_MMIO_WRITE_INCREMENT` rather than via this shared constant. enum { kNvmCtrlSecMmioCertInfoPageCreatorCfg = 2, kNvmCtrlSecMmioCertInfoPageOwnerRestrict = 2, kNvmCtrlSecMmioCertInfoPagesOwnerRestrict = 5, +#ifdef HAS_RRAM_CTRL + // 2 writes for each of the 4 pages (of the 7 in kNvmPagesNoOwnerAccess) + // that are real (non-emulated) RRAM info pages: FactoryId, CreatorSecret, + // OwnerSecret, WaferAuthSecret. The other 3 (BootData0, BootData1, + // CreatorReserved0) are emulated and are skipped (see the TODO on + // `rram_ctrl_info_page_t`). + kNvmCtrlSecMmioCreatorInfoPagesLockdown = 8, +#else kNvmCtrlSecMmioCreatorInfoPagesLockdown = 14, +#endif kNvmCtrlSecMmioDataDefaultCfgSet = 1, kNvmCtrlSecMmioDataDefaultPermsSet = 1, kNvmCtrlSecMmioExecSet = 1, @@ -144,7 +250,13 @@ enum { kNvmCtrlSecMmioInfoPageLockdown = 2, kNvmCtrlSecMmioInfoPermsSet = 1, kNvmCtrlSecMmioBankErasePermsSet = 1, +#ifdef HAS_RRAM_CTRL + // 1 write from `rram_ctrl_data_default_cfg_set` (via `rram_ctrl_init`) plus + // 1 from the `rram_ctrl_data_default_perms_set` call in `nvm_ctrl_init`. + kNvmCtrlSecMmioInit = 2, +#else kNvmCtrlSecMmioInit = 3, +#endif kNvmCtrlSecMmioDataRegionProtect = 1, kNvmCtrlSecMmioDataRegionProtectLock = 1, }; @@ -177,8 +289,10 @@ void nvm_ctrl_disable(void); * are read from on-flash owner configuration structs that store raw bank and * page integers. All NVM I/O then proceeds through the enum-based API. * - * @param bank Bank index (must be < NVM_NUM_BANKS). - * @param page Page index within the info partition type 0. + * @param bank Bank index (must be < 2; this is a fixed wire-format constant, + * independent of the number of banks the underlying NVM + * technology actually has). + * @param page Page index within the info partition type 0 (must be < 10). * @param[out] out Translated info page enum value. * @return kErrorOk on success, kErrorNvmCtrlInvalidInfoPage if out of range. */ From 58ba173c0801ee6cbdee1868fca7bfa763af72ee Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:16:17 +0200 Subject: [PATCH 24/41] [rram_ctrl,bazel] add defines support to dual_cc_library nvm_ctrl's HAS_RRAM_CTRL macro needs to reach every target that includes nvm_ctrl.h, not just nvm_ctrl.c itself, so it has to be a `defines` (which propagates to dependents), not `copts`. Adds a `defines` dual_inputs()-aware parameter to dual_cc_library alongside the existing srcs/hdrs/deps/target_compatible_with ones. Also fixes _merge_and_split_inputs' struct-detection check: it used `type(inputs) != "list"` to mean "already a dual_inputs() struct", but a bare select() (as returned by e.g. opentitan_if_ip()) is neither a list nor a struct, and the old check would misroute it to a `.shared` attribute access that doesn't exist on a select(). This already affects the existing shutdown target, which passes a bare select() as `defines`; the fix (`type(inputs) == "struct"`) correctly treats any non-dual_inputs() value, list or select() alike, as shared. Signed-off-by: Michael Gautschi --- rules/cross_platform.bzl | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/rules/cross_platform.bzl b/rules/cross_platform.bzl index d3cdb9e75168c..905c6bc153e67 100644 --- a/rules/cross_platform.bzl +++ b/rules/cross_platform.bzl @@ -17,7 +17,10 @@ def dual_cc_device_library_of(label): return "{}_on_device_do_not_use_directly".format(label) def _merge_and_split_inputs(inputs): - inputs = inputs if type(inputs) != "list" else dual_inputs(shared = inputs) + # Only a `dual_inputs()` struct carries a real device/host split; a plain + # list or a `select()` (as returned by e.g. `opentitan_if_ip()`) is + # treated as shared, applying identically to both variants. + inputs = inputs if type(inputs) == "struct" else dual_inputs(shared = inputs) return inputs.shared + inputs.device, inputs.shared + inputs.host def dual_cc_library( @@ -27,6 +30,7 @@ def dual_cc_library( hdrs = [], copts = [], deps = [], + defines = [], visibility = ["//visibility:private"], target_compatible_with = [], **kwargs): @@ -35,10 +39,10 @@ def dual_cc_library( depended on in an on-device or on-host setting. The macro takes the same arguments as cc_library, but has special - behavior for `hdrs`, `srcs`, and `deps`, which may either be a list of - labels that would usually be inputs to a cc_library, or a dual_inputs object. - The later case allows inputs to be designated as being shared, on-device-only, - or off-device-only. + behavior for `hdrs`, `srcs`, `deps`, and `defines`, which may either be a + list of labels/strings that would usually be inputs to a cc_library, or a + dual_inputs object. The later case allows inputs to be designated as + being shared, on-device-only, or off-device-only. This rule only needs to be used when the sources for on-device are different from on-host, such as for mockable interfaces. In this case, the on-device @@ -54,6 +58,11 @@ def dual_cc_library( @param hdrs: `cc_library()` headers; may be a list or a `dual_inputs()`. @params copts: `cc_library() copts; may be a list or a `dual_inputs()`. @param deps: `cc_library()` dependencies; may be a list or a `dual_inputs()`. + @param defines: `cc_library()` defines (propagate to dependents, unlike + `copts`); may be a list or a `dual_inputs()`. Needed whenever a + shared header (not just a device/host-split source file) branches + on the macro, since every other target that includes that header + must see the same value the device/host source was compiled with. @param visibility: The visibility to be used for the targets. @param **kwargs: Arguments to forward to each `cc_library()`. @@ -67,6 +76,7 @@ def dual_cc_library( srcs_d, srcs_h = _merge_and_split_inputs(srcs) copts_d, copts_h = _merge_and_split_inputs(copts) deps_d, deps_h = _merge_and_split_inputs(deps) + defines_d, defines_h = _merge_and_split_inputs(defines) tgts_d, tgts_h = _merge_and_split_inputs(target_compatible_with) native.cc_library( @@ -75,6 +85,7 @@ def dual_cc_library( srcs = srcs_d, copts = copts_d, deps = deps_d, + defines = defines_d, target_compatible_with = tgts_d, visibility = visibility, **kwargs @@ -87,6 +98,7 @@ def dual_cc_library( srcs = srcs_h, copts = copts_h, deps = deps_h, + defines = defines_h, target_compatible_with = tgts_h, visibility = visibility, **kwargs From 78b019c4e2f8fe1ce6035d4431183b2818b5c698 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:17:22 +0200 Subject: [PATCH 25/41] [rram_ctrl,sw] adopt 1-bank/2-slot NVM addressing for boot policy, ownership, rescue RRAM has no bank concept (NVM_NUM_BANKS == 1), but firmware slots A/B still need to exist as two equal halves of the NVM data partition. Renames kNvmBankSize to kNvmSlotSize (backed by the new NVM_PAGES_PER_SLOT/NVM_BYTES_PER_SLOT macros) across owner_block.c, rom_ext.c, and rescue.c, and makes boot_policy_ptrs.h address the manifest via NVM_DATA_BASE_ADDR/NVM_BYTES_PER_SLOT instead of flash_ctrl's base address/size directly, so slot A/B addressing is correct under both 2-bank flash and 1-bank RRAM. Signed-off-by: Michael Gautschi --- .../lib/ownership/owner_block.c | 30 ++++++++++--------- sw/device/silicon_creator/lib/rescue/rescue.c | 7 +++-- sw/device/silicon_creator/rom/BUILD | 1 + .../silicon_creator/rom/boot_policy_ptrs.h | 14 ++++----- sw/device/silicon_creator/rom_ext/rom_ext.c | 7 +++-- 5 files changed, 32 insertions(+), 27 deletions(-) diff --git a/sw/device/silicon_creator/lib/ownership/owner_block.c b/sw/device/silicon_creator/lib/ownership/owner_block.c index a16f1c0ed2a95..d3469220a900a 100644 --- a/sw/device/silicon_creator/lib/ownership/owner_block.c +++ b/sw/device/silicon_creator/lib/ownership/owner_block.c @@ -22,19 +22,21 @@ owner_block_t owner_page[2]; owner_page_status_t owner_page_valid[2]; enum { - kNvmBankSize = NVM_PAGES_PER_BANK, + // Page count of one firmware slot (A or B). Each NVM bank holds + // `NVM_NUM_BANKS == 1 ? 2 : 1` slot(s); see `NVM_PAGES_PER_SLOT`. + kNvmSlotSize = NVM_PAGES_PER_SLOT, kNvmPageSize = NVM_BYTES_PER_PAGE, - kNvmTotalSize = NVM_NUM_BANKS * kNvmBankSize, + kNvmTotalSize = 2 * kNvmSlotSize, kNvmSlotAStart = 0, - kNvmSlotAEnd = kNvmSlotAStart + kNvmBankSize, - kNvmSlotBStart = kNvmBankSize, - kNvmSlotBEnd = kNvmSlotBStart + kNvmBankSize, + kNvmSlotAEnd = kNvmSlotAStart + kNvmSlotSize, + kNvmSlotBStart = kNvmSlotSize, + kNvmSlotBEnd = kNvmSlotBStart + kNvmSlotSize, kRomExtSizeInPages = CHIP_ROM_EXT_SIZE_MAX / kNvmPageSize, kRomExtAStart = 0 / kNvmPageSize, kRomExtAEnd = kRomExtAStart + kRomExtSizeInPages, - kRomExtBStart = kNvmBankSize + kRomExtAStart, + kRomExtBStart = kNvmSlotSize + kRomExtAStart, kRomExtBEnd = kRomExtBStart + kRomExtSizeInPages, kRomExtRegions = 2, @@ -179,7 +181,7 @@ rom_error_t owner_block_rescue_check(const owner_rescue_config_t *rescue) { return kErrorOwnershipInvalidTagLength; } uint32_t end = rescue->start + rescue->size; - if (rescue->start < kRomExtSizeInPages || end > kNvmBankSize) { + if (rescue->start < kRomExtSizeInPages || end > kNvmSlotSize) { return kErrorOwnershipInvalidRescueBounds; } return kErrorOk; @@ -304,11 +306,11 @@ rom_error_t owner_block_parse(const owner_block_t *block, return kErrorOk; } -static hardened_bool_t in_nvm_slot(uint32_t bank_start, uint32_t start, +static hardened_bool_t in_nvm_slot(uint32_t slot_start, uint32_t start, uint32_t end) { - uint32_t bank_end = bank_start + kNvmBankSize; - return (bank_start <= start && start < bank_end && bank_start < end && - end <= bank_end) + uint32_t slot_end = slot_start + kNvmSlotSize; + return (slot_start <= start && start < slot_end && slot_start < end && + end <= slot_end) ? kHardenedBoolTrue : kHardenedBoolFalse; } @@ -391,10 +393,10 @@ rom_error_t owner_block_nvm_apply(const owner_nvm_config_t *nvm, // TODO: Hardening: lockdown should be one of kBootSlotA, kBootSlotB or // kHardenedBoolFalse. uint32_t start = config_side == kBootSlotA ? 0 - : config_side == kBootSlotB ? kNvmBankSize + : config_side == kBootSlotB ? kNvmSlotSize : 0xFFFFFFFF; - uint32_t end = config_side == kBootSlotA ? kNvmBankSize - : config_side == kBootSlotB ? 2 * kNvmBankSize + uint32_t end = config_side == kBootSlotA ? kNvmSlotSize + : config_side == kBootSlotB ? 2 * kNvmSlotSize : 0; size_t len = (nvm->header.length - sizeof(owner_nvm_config_t)) / sizeof(owner_nvm_region_t); diff --git a/sw/device/silicon_creator/lib/rescue/rescue.c b/sw/device/silicon_creator/lib/rescue/rescue.c index 5c4c72adc6a02..83906203cd6fc 100644 --- a/sw/device/silicon_creator/lib/rescue/rescue.c +++ b/sw/device/silicon_creator/lib/rescue/rescue.c @@ -45,7 +45,8 @@ typedef enum rescue_request { static rescue_request_t rescue_requested; const uint32_t kNvmPageSize = NVM_BYTES_PER_PAGE; -const uint32_t kNvmBankSize = NVM_PAGES_PER_BANK * NVM_BYTES_PER_PAGE; +// Byte size of one firmware slot (A or B); see `NVM_BYTES_PER_SLOT`. +const uint32_t kNvmSlotSize = NVM_BYTES_PER_SLOT; static inline bool is_rom_ext(const void *data) { const manifest_t *manifest = (const manifest_t *)data; @@ -63,7 +64,7 @@ static inline bool is_rom_ext_update_allowed(rescue_state_t *state) { rom_error_t nvm_firmware_block(rescue_state_t *state) { uint32_t bank_offset = - state->mode == kRescueModeFirmwareSlotB ? kNvmBankSize : 0; + state->mode == kRescueModeFirmwareSlotB ? kNvmSlotSize : 0; if (state->nvm_offset == 0) { // TODO(#24428): Make sure we interact correctly with owner flash region // configuration. @@ -346,7 +347,7 @@ void rescue_state_init(rescue_state_t *state, boot_data_t *bootdata, // If there is no rescue config, then the rescue region starts immediately // after the ROM_EXT and ends at the end of the flash bank. state->nvm_start = CHIP_ROM_EXT_SIZE_MAX; - state->nvm_limit = kNvmBankSize; + state->nvm_limit = kNvmSlotSize; state->inactivity_deadline = 0; } else { state->nvm_start = (uint32_t)config->start * kNvmPageSize; diff --git a/sw/device/silicon_creator/rom/BUILD b/sw/device/silicon_creator/rom/BUILD index fc960894998b3..18cb9c7289924 100644 --- a/sw/device/silicon_creator/rom/BUILD +++ b/sw/device/silicon_creator/rom/BUILD @@ -49,6 +49,7 @@ dual_cc_library( ], shared = [ "//sw/device/silicon_creator/lib:manifest", + "//sw/device/silicon_creator/lib:nvm_ctrl", "//hw/top_earlgrey/sw/autogen:top_earlgrey", ], ), diff --git a/sw/device/silicon_creator/rom/boot_policy_ptrs.h b/sw/device/silicon_creator/rom/boot_policy_ptrs.h index ee5a7d7665a6d..cb8170f94de30 100644 --- a/sw/device/silicon_creator/rom/boot_policy_ptrs.h +++ b/sw/device/silicon_creator/rom/boot_policy_ptrs.h @@ -6,6 +6,7 @@ #define OPENTITAN_SW_DEVICE_SILICON_CREATOR_ROM_BOOT_POLICY_PTRS_H_ #include "sw/device/silicon_creator/lib/manifest.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" @@ -13,31 +14,30 @@ extern "C" { #endif // __cplusplus -static_assert((TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES % 2) == 0, - "Flash size is not divisible by 2"); +static_assert((NVM_DATA_SIZE_BYTES % 2) == 0, + "NVM data partition size is not divisible by 2"); #ifdef OT_PLATFORM_RV32 /** - * Returns a pointer to the manifest of the ROM_EXT image stored in flash + * Returns a pointer to the manifest of the ROM_EXT image stored in NVM * slot A. * * @return Pointer to the manifest of the ROM_EXT image in slot A. */ OT_WARN_UNUSED_RESULT inline const manifest_t *boot_policy_manifest_a_get(void) { - return (const manifest_t *)TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + return (const manifest_t *)NVM_DATA_BASE_ADDR; } /** - * Returns a pointer to the manifest of the ROM_EXT image stored in flash + * Returns a pointer to the manifest of the ROM_EXT image stored in NVM * slot B. * * @return Pointer to the manifest of the ROM_EXT image in slot B. */ OT_WARN_UNUSED_RESULT inline const manifest_t *boot_policy_manifest_b_get(void) { - return (const manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - (TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2)); + return (const manifest_t *)(NVM_DATA_BASE_ADDR + NVM_BYTES_PER_SLOT); } #else /** diff --git a/sw/device/silicon_creator/rom_ext/rom_ext.c b/sw/device/silicon_creator/rom_ext/rom_ext.c index 700e7bb92516b..9a064d9a4a33a 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext.c +++ b/sw/device/silicon_creator/rom_ext/rom_ext.c @@ -66,14 +66,15 @@ // Useful constants for NVM sizes and ROM_EXT locations. enum { - kNvmBankSize = NVM_PAGES_PER_BANK, + // Page count of one firmware slot (A or B); see `NVM_PAGES_PER_SLOT`. + kNvmSlotSize = NVM_PAGES_PER_SLOT, kNvmPageSize = NVM_BYTES_PER_PAGE, - kNvmTotalSize = 2 * kNvmBankSize, + kNvmTotalSize = 2 * kNvmSlotSize, kRomExtSizeInPages = CHIP_ROM_EXT_SIZE_MAX / kNvmPageSize, kRomExtAStart = 0 / kNvmPageSize, kRomExtAEnd = kRomExtAStart + kRomExtSizeInPages, - kRomExtBStart = kNvmBankSize + kRomExtAStart, + kRomExtBStart = kNvmSlotSize + kRomExtAStart, kRomExtBEnd = kRomExtBStart + kRomExtSizeInPages, }; From 2da0a22426dfc2e24975121c9cbb8d606763c65b Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:17:48 +0200 Subject: [PATCH 26/41] [rram_ctrl,sw] skip sec_mmio increment for always-emulated BootData pages under RRAM On RRAM, BootData0/BootData1 are always emulated info pages, so nvm_ctrl_info_perms_set() on them is a no-op that performs zero real register writes; the existing SEC_MMIO_WRITE_INCREMENT(2 * kNvmCtrlSecMmioInfoPermsSet) at each of boot_data's 3 write call sites assumed flash's real per-call writes and must be skipped for RRAM to keep sec_mmio_check_counters() accurate. This will be changed in the future once emulated info pages are fully supported in hardware. kBootDataEntriesPerPage now derives from NVM_BYTES_PER_PAGE instead of a hardcoded 16, since RRAM's page size differs from flash's and the old constant was wrong for RRAM. This constant is only used by boot_data.c and boot_data_functest.c, so it is defined directly in each of those (which already depend on nvm_ctrl.h) rather than in the shared boot_data.h. That header backs boot_data_header, a lightweight, broadly-depended-on target that must stay buildable on tops with neither flash_ctrl nor rram_ctrl (e.g. Darjeeling): pulling nvm_ctrl.h into it drags in nvm_ctrl's device deps, which unconditionally require flash_ctrl, breaking every such consumer. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/boot_data.c | 41 ++++++++++++++++--- sw/device/silicon_creator/lib/boot_data.h | 10 ----- .../silicon_creator/lib/boot_data_functest.c | 7 ++++ 3 files changed, 43 insertions(+), 15 deletions(-) diff --git a/sw/device/silicon_creator/lib/boot_data.c b/sw/device/silicon_creator/lib/boot_data.c index d750fda6702d8..83ad9d332ea97 100644 --- a/sw/device/silicon_creator/lib/boot_data.c +++ b/sw/device/silicon_creator/lib/boot_data.c @@ -17,21 +17,37 @@ #include "hw/top/otp_ctrl_regs.h" +enum { + /** + * Number of boot data entries per info page. + * + * Boot data pages are used as append-only logs where new data is written to + * the first empty entry of the active page. If all entries of the currently + * active page are used when `boot_data_write()` is called, the other page + * will be erased and new data will be written to its first entry, making it + * the new active page. + * + * Not part of `boot_data.h`: unlike the rest of that header, this depends on + * `nvm_ctrl.h`, which in turn requires a top with `flash_ctrl` or + * `rram_ctrl`. `boot_data.h` is also consumed by `boot_data_header`, a much + * more broadly-depended-on target that must stay buildable on tops with + * neither. + */ + kBootDataEntriesPerPage = NVM_BYTES_PER_PAGE / sizeof(boot_data_t), +}; + static_assert(kBootDataValidEntry == ((uint64_t)kNvmErasedWord << 32 | kNvmErasedWord), "kBootDataValidEntry words must be kNvmErasedWord"); -static_assert(kBootDataEntriesPerPage == - NVM_BYTES_PER_PAGE / sizeof(boot_data_t), - "Number of boot data entries per page is incorrect"); static_assert(sizeof(boot_data_t) % NVM_BYTES_PER_WORD == 0, - "Size of `boot_data_t` must be a multiple of flash word size."); + "Size of `boot_data_t` must be a multiple of nvm word size."); static_assert(!(NVM_BYTES_PER_PAGE & (NVM_BYTES_PER_PAGE - 1)), "Size of a flash page must be a power of two."); static_assert(!(sizeof(boot_data_t) & (sizeof(boot_data_t) - 1)), "Size of `boot_data_t` must be a power of two."); OT_ASSERT_MEMBER_SIZE(boot_data_t, is_valid, NVM_BYTES_PER_WORD); static_assert(offsetof(boot_data_t, is_valid) % NVM_BYTES_PER_WORD == 0, - "`is_valid` must be flash word aligned."); + "`is_valid` must be nvm word aligned."); enum { /** @@ -234,7 +250,12 @@ static rom_error_t boot_data_entry_write(nvm_info_page_t page, size_t index, }); rom_error_t error = boot_data_entry_write_impl(page, index, boot_data, erase); nvm_ctrl_info_perms_set(page, kNvmPagePermsNone); +#ifdef HAS_RRAM_CTRL + // `page` is always BootData0/BootData1, which are always emulated on RRAM, + // so `nvm_ctrl_info_perms_set` is a no-op above: no actual writes happen. +#else SEC_MMIO_WRITE_INCREMENT(2 * kNvmCtrlSecMmioInfoPermsSet); +#endif return error; } @@ -269,7 +290,12 @@ static rom_error_t boot_data_entry_invalidate(nvm_info_page_t page, .erase = kMultiBitBool4False}); rom_error_t error = nvm_ctrl_info_write(page, offset, 2, val); nvm_ctrl_info_perms_set(page, kNvmPagePermsNone); +#ifdef HAS_RRAM_CTRL + // `page` is always BootData0/BootData1, which are always emulated on RRAM, + // so `nvm_ctrl_info_perms_set` is a no-op above: no actual writes happen. +#else SEC_MMIO_WRITE_INCREMENT(2 * kNvmCtrlSecMmioInfoPermsSet); +#endif return error; } @@ -434,7 +460,12 @@ static rom_error_t boot_data_page_info_update(nvm_info_page_t page, rom_error_t error = boot_data_page_info_update_impl(page, page_info, boot_data); nvm_ctrl_info_perms_set(page, kNvmPagePermsNone); +#ifdef HAS_RRAM_CTRL + // `page` is always BootData0/BootData1, which are always emulated on RRAM, + // so `nvm_ctrl_info_perms_set` is a no-op above: no actual writes happen. +#else SEC_MMIO_WRITE_INCREMENT(2 * kNvmCtrlSecMmioInfoPermsSet); +#endif return error; } diff --git a/sw/device/silicon_creator/lib/boot_data.h b/sw/device/silicon_creator/lib/boot_data.h index ed819bce899e5..c963a79b04485 100644 --- a/sw/device/silicon_creator/lib/boot_data.h +++ b/sw/device/silicon_creator/lib/boot_data.h @@ -144,16 +144,6 @@ enum { * Size of `boot_data_t` in words. */ kBootDataNumWords = sizeof(boot_data_t) / sizeof(uint32_t), - /** - * Number of boot data entries per info page. - * - * Boot data pages are used as append-only logs where new data is written to - * the first empty entry of the active page. If all entries of the currently - * active page are used when `boot_data_write()` is called, the other page - * will be erased and new data will be written to its first entry, making it - * the new active page. - */ - kBootDataEntriesPerPage = 16, }; static_assert(kBootDataInvalidEntry != kBootDataValidEntry, "Invalidation values cannot be equal."); diff --git a/sw/device/silicon_creator/lib/boot_data_functest.c b/sw/device/silicon_creator/lib/boot_data_functest.c index 689fc0aba6073..1d64626e670d4 100644 --- a/sw/device/silicon_creator/lib/boot_data_functest.c +++ b/sw/device/silicon_creator/lib/boot_data_functest.c @@ -15,6 +15,13 @@ OTTF_DEFINE_TEST_CONFIG(); +enum { + // See the identically-named, identically-defined enum in boot_data.c: not + // part of `boot_data.h` since that header must stay buildable without + // `nvm_ctrl.h` (see the comment there for why). + kBootDataEntriesPerPage = NVM_BYTES_PER_PAGE / sizeof(boot_data_t), +}; + /** * Boot data NVM info pages. */ From dc2dc26130a11f1fc2c70d8c3d2b6d237c4d7194 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:20:26 +0200 Subject: [PATCH 27/41] [rram_ctrl,sw] retarget EPMP/linker regions from eflash to rram Mechanically retargets the ROM's EPMP region and the ROM_EXT/bare-metal linker scripts' address-translation checks from the eflash memory region to rram (TOP_EARLGREY_RRAM_CTRL_HOST_*), matching the "1 bank, 2 slots" RRAM addressing already adopted elsewhere. Comments updated from flash-specific wording to generic NVM wording where they no longer apply only to flash. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/rom/rom_epmp.c | 8 ++++---- sw/device/silicon_creator/rom/rom_epmp_init.S | 6 +++--- .../rom_ext/imm_section/imm_section_slot_a.ld | 2 +- .../rom_ext/imm_section/imm_section_slot_b.ld | 2 +- sw/device/silicon_creator/rom_ext/rom_ext_common.ld | 8 ++++---- sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld | 8 ++++---- sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld | 6 +++--- sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld | 8 ++++---- sw/device/silicon_owner/bare_metal/bare_metal_common.ld | 8 ++++---- 9 files changed, 28 insertions(+), 28 deletions(-) diff --git a/sw/device/silicon_creator/rom/rom_epmp.c b/sw/device/silicon_creator/rom/rom_epmp.c index 4cee975694a09..d46910e327357 100644 --- a/sw/device/silicon_creator/rom/rom_epmp.c +++ b/sw/device/silicon_creator/rom/rom_epmp.c @@ -40,9 +40,9 @@ void rom_epmp_state_init(lifecycle_state_t lc_state) { const epmp_region_t rom = {.start = (uintptr_t)_text_end, .end = TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES}; - const epmp_region_t eflash = {.start = TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR, - .end = TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES}; + const epmp_region_t rram = {.start = TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR, + .end = TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR + + TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES}; const epmp_region_t mmio = { .start = TOP_EARLGREY_MMIO_BASE_ADDR, .end = TOP_EARLGREY_MMIO_BASE_ADDR + TOP_EARLGREY_MMIO_SIZE_BYTES}; @@ -93,7 +93,7 @@ void rom_epmp_state_init(lifecycle_state_t lc_state) { memset(&epmp_state, 0, sizeof(epmp_state)); epmp_state_configure_tor(1, rom_text, kEpmpPermLockedReadExecute); epmp_state_configure_tor(2, rom, kEpmpPermLockedReadOnly); - epmp_state_configure_napot(5, eflash, kEpmpPermLockedReadOnly); + epmp_state_configure_napot(5, rram, kEpmpPermLockedReadOnly); epmp_state_configure_tor(11, mmio, kEpmpPermLockedReadWrite); epmp_state_configure_napot(13, debug_rom, debug_rom_access); epmp_state_configure_na4(14, stack_guard, kEpmpPermLockedNoAccess); diff --git a/sw/device/silicon_creator/rom/rom_epmp_init.S b/sw/device/silicon_creator/rom/rom_epmp_init.S index 8a9ef9f097fc8..50ce69eeb11d8 100644 --- a/sw/device/silicon_creator/rom/rom_epmp_init.S +++ b/sw/device/silicon_creator/rom/rom_epmp_init.S @@ -78,8 +78,8 @@ rom_epmp_init: csrw pmpaddr3, zero // ROM_EXT TEXT low csrw pmpaddr4, zero // ROM_EXT TEXT high - // eFLASH - li t0, NAPOT(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR, TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES) + // RRAM + li t0, NAPOT(TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR, TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES) csrw pmpaddr5, t0 // MMIO @@ -106,7 +106,7 @@ rom_epmp_init: // Set the remaining PMP configuration registers (pmpcfg0 was already set // above). - li t1, CFG_INDEX(5 % 4, EPMP_CFG_A_NAPOT | EPMP_CFG_LR) /* eFLASH */ + li t1, CFG_INDEX(5 % 4, EPMP_CFG_A_NAPOT | EPMP_CFG_LR) /* RRAM */ li t2, CFG_INDEX(11 % 4, EPMP_CFG_A_TOR | EPMP_CFG_LRW) /* MMIO */ li t3, CFG_INDEX(12 % 4, EPMP_CFG_A_NAPOT | EPMP_CFG_LRW) | /* Secondary RAM */ \ CFG_INDEX(13 % 4, EPMP_CFG_A_NAPOT | EPMP_CFG_LRWX)| /* Debug ROM */ \ diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld index 1313d3b9a063d..8e0b457351931 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_a.ld @@ -20,7 +20,7 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld */ MEMORY { - imm_section_slot_a(rx) : ORIGIN = ORIGIN(eflash) + 0x400, LENGTH = LENGTH(eflash) / 2 - 0x400 + imm_section_slot_a(rx) : ORIGIN = ORIGIN(rram) + 0x400, LENGTH = LENGTH(rram) / 2 - 0x400 } REGION_ALIAS("rom_ext_nvm", imm_section_slot_a); diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld index b48fd21d542b2..1e674ade45039 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_slot_b.ld @@ -21,7 +21,7 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld /* Slot B starts at the half-size mark of the eFlash. */ MEMORY { - imm_section_slot_b(rx) : ORIGIN = ORIGIN(eflash) + LENGTH(eflash) / 2 + 0x400, LENGTH = LENGTH(eflash) / 2 - 0x400 + imm_section_slot_b(rx) : ORIGIN = ORIGIN(rram) + LENGTH(rram) / 2 + 0x400, LENGTH = LENGTH(rram) / 2 - 0x400 } REGION_ALIAS("rom_ext_nvm", imm_section_slot_b); diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_common.ld b/sw/device/silicon_creator/rom_ext/rom_ext_common.ld index 5f5af3e322cb8..06a7a7e35ddb2 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_common.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_common.ld @@ -49,12 +49,12 @@ _manifest_code_end = _text_end - _rom_ext_start_address; _manifest_entry_point = _rom_ext_start_boot - _rom_ext_start_address; /* * The value kHardenedBoolFalse (0x1d4) is selected if the code is linked in - * the flash region. Otherwise, the value kHardenedBoolTrue (0x739) is + * the RRAM region. Otherwise, the value kHardenedBoolTrue (0x739) is * selected. */ -_manifest_address_translation = (_text_start >= ORIGIN(eflash) && - _text_start < (ORIGIN(eflash) - + LENGTH(eflash))) ? 0x1d4 : 0x739; +_manifest_address_translation = (_text_start >= ORIGIN(rram) && + _text_start < (ORIGIN(rram) + + LENGTH(rram))) ? 0x1d4 : 0x739; REGION_ALIAS("coverage_flash", rom_ext_nvm); diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld index 9fc12083af6cc..022164f353cb6 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_a.ld @@ -7,14 +7,14 @@ * * Portions of this file are Ibex-specific. * - * The ROM_EXT is actually kept in flash, rather than ROM. While a ROM_EXT can - * be loaded into either Slot A (the start of flash), or Slot B (the start of - * the upper half of flash), this linker script only targets Slot A. + * The ROM_EXT is actually kept in NVM, rather than ROM. While a ROM_EXT can + * be loaded into either Slot A (the start of NVM), or Slot B (the start of + * the upper half of NVM), this linker script only targets Slot A. */ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld -/* Slot A starts at begining of the eFlash. */ +/* Slot A starts at begining of the NVM. */ _rom_ext_size = LENGTH(rram) / 2; _rom_ext_start_address = ORIGIN(rram); diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld index 377505266831d..df34133b04fe5 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_b.ld @@ -7,9 +7,9 @@ * * Portions of this file are Ibex-specific. * - * The ROM_EXT is actually kept in flash, rather than ROM. While a ROM_EXT can - * be loaded into either Slot A (the start of flash), or Slot B (the start of - * the upper half of flash), this linker script only targets Slot B. + * The ROM_EXT is actually kept in NVM, rather than ROM. While a ROM_EXT can + * be loaded into either Slot A (the start of NVM), or Slot B (the start of + * the upper half of NVM), this linker script only targets Slot B. */ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld index 8774a8cdfb657..6c04bed29a895 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld +++ b/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual.ld @@ -7,9 +7,9 @@ * * Portions of this file are Ibex-specific. * - * The ROM_EXT is actually kept in flash, rather than ROM. While a ROM_EXT can - * be loaded into either Slot A (the start of flash), or Slot B (the start of - * the upper half of flash), this linker script targets both by using a virtual + * The ROM_EXT is actually kept in NVM, rather than ROM. While a ROM_EXT can + * be loaded into either Slot A (the start of NVM), or Slot B (the start of + * the upper half of NVM), this linker script targets both by using a virtual * address. The ROM must configure the address translation before jumping to * to the virtual address. */ @@ -21,7 +21,7 @@ INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld */ _rom_ext_start_address = ORIGIN(rom_ext_virtual); _rom_ext_size = LENGTH(rom_ext_virtual); -ASSERT((_rom_ext_size <= (LENGTH(eflash) / 2)), "Error: rom ext flash is bigger than slot"); +ASSERT((_rom_ext_size <= (LENGTH(rram) / 2)), "Error: rom ext NVM is bigger than slot"); REGION_ALIAS("rom_ext_nvm", rom_ext_virtual); diff --git a/sw/device/silicon_owner/bare_metal/bare_metal_common.ld b/sw/device/silicon_owner/bare_metal/bare_metal_common.ld index 4f495a0067d4c..5c47cec43c216 100644 --- a/sw/device/silicon_owner/bare_metal/bare_metal_common.ld +++ b/sw/device/silicon_owner/bare_metal/bare_metal_common.ld @@ -43,12 +43,12 @@ _manifest_code_end = _text_end - _slot_start_address; _manifest_entry_point = _start_boot - _slot_start_address; /* * The value kHardenedBoolFalse (0x1d4) is selected if the code is linked in - * the flash region. Otherwise, the value kHardenedBoolTrue (0x739) is + * the RRAM region. Otherwise, the value kHardenedBoolTrue (0x739) is * selected. */ -_manifest_address_translation = (_text_start >= ORIGIN(eflash) && - _text_start < (ORIGIN(eflash) - + LENGTH(eflash))) ? 0x1d4 : 0x739; +_manifest_address_translation = (_text_start >= ORIGIN(rram) && + _text_start < (ORIGIN(rram) + + LENGTH(rram))) ? 0x1d4 : 0x739; /** * NOTE: We have to align each section to word boundaries as our current From 0c27cea3cc1a62a3c1a2a8923b5c16cb6fad8707 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:20:45 +0200 Subject: [PATCH 28/41] [rram_ctrl,bazel] switch to default kind=rram, fix scramble_rram_vmem, add 128-bit vmem rules Changes opentitan_test()'s default kind from "flash" to "rram", matching this branch's default NVM technology. Fixes scramble_rram_vmem's output suffix (was "src.vmem", should be "scr.vmem" like scramble_flash_vmem) and adds an optional out attr so callers can control the output name. rom/e2e/BUILD gains 128-bit-word vmem/scr_vmem rules alongside the existing 64-bit ones, needed for RRAM's backdoor-load VMEM format, and chip_rom_tests.hjson is updated for the corresponding empty_test_slot_*_prod_key_0/test_key_0 target renames (no longer fake_ecdsa_-prefixed, since that prefix is now added only where the corrupted-image genrules need it). Signed-off-by: Michael Gautschi --- hw/top_earlgrey/dv/chip_rom_tests.hjson | 54 ++++++++++++------------- rules/opentitan/defs.bzl | 2 +- rules/opentitan/legacy.bzl | 6 ++- sw/device/silicon_creator/rom/e2e/BUILD | 50 +++++++++++++++++++---- 4 files changed, 75 insertions(+), 37 deletions(-) diff --git a/hw/top_earlgrey/dv/chip_rom_tests.hjson b/hw/top_earlgrey/dv/chip_rom_tests.hjson index b234741137190..928c61998adca 100644 --- a/hw/top_earlgrey/dv/chip_rom_tests.hjson +++ b/hw/top_earlgrey/dv/chip_rom_tests.hjson @@ -55,8 +55,8 @@ name: rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_test_unlocked0:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -71,8 +71,8 @@ name: rom_e2e_boot_policy_valid_a_good_b_good_dev uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_dev:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -87,8 +87,8 @@ name: rom_e2e_boot_policy_valid_a_good_b_good_prod uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_prod:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -103,8 +103,8 @@ name: rom_e2e_boot_policy_valid_a_good_b_good_prod_end uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_prod_end:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -119,8 +119,8 @@ name: rom_e2e_boot_policy_valid_a_good_b_good_rma uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_rma:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -135,7 +135,7 @@ name: rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_test_unlocked0:4", ] @@ -151,7 +151,7 @@ name: rom_e2e_boot_policy_valid_a_good_b_bad_dev uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_dev:4", ] @@ -167,7 +167,7 @@ name: rom_e2e_boot_policy_valid_a_good_b_bad_prod uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_prod:4", ] @@ -183,7 +183,7 @@ name: rom_e2e_boot_policy_valid_a_good_b_bad_prod_end uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_prod_end:4", ] @@ -199,7 +199,7 @@ name: rom_e2e_boot_policy_valid_a_good_b_bad_rma uvm_test_seq: chip_sw_base_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_rma:4", ] @@ -216,7 +216,7 @@ uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_test_unlocked0:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -232,7 +232,7 @@ uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_dev:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -248,7 +248,7 @@ uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_prod:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -264,7 +264,7 @@ uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_prod_end:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -280,7 +280,7 @@ uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_prod_key_0:2:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/boot_policy_valid:otp_img_boot_policy_valid_rma:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -535,7 +535,7 @@ name: rom_e2e_asm_init_test_unlocked0 uvm_test_seq: chip_sw_rom_e2e_asm_init_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/rom_e2e_bootstrap_entry:otp_img_e2e_bootstrap_entry_test_unlocked0:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -549,7 +549,7 @@ name: rom_e2e_asm_init_dev uvm_test_seq: chip_sw_rom_e2e_asm_init_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/rom_e2e_bootstrap_entry:otp_img_e2e_bootstrap_entry_dev:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -563,7 +563,7 @@ name: rom_e2e_asm_init_prod uvm_test_seq: chip_sw_rom_e2e_asm_init_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/rom_e2e_bootstrap_entry:otp_img_e2e_bootstrap_entry_prod:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -577,7 +577,7 @@ name: rom_e2e_asm_init_prod_end uvm_test_seq: chip_sw_rom_e2e_asm_init_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/rom_e2e_bootstrap_entry:otp_img_e2e_bootstrap_entry_prod_end:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -591,7 +591,7 @@ name: rom_e2e_asm_init_rma uvm_test_seq: chip_sw_rom_e2e_asm_init_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_prod_key_0:1:ot_flash_binary", "//sw/device/silicon_creator/rom/e2e/rom_e2e_bootstrap_entry:otp_img_e2e_bootstrap_entry_rma:4", ] en_run_modes: ["sw_test_mode_mask_rom"] @@ -753,7 +753,7 @@ name: rom_volatile_raw_unlock uvm_test_seq: chip_sw_lc_volatile_raw_unlock_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_test_key_0:1:ot_flash_binary", ] en_run_modes: ["sw_test_mode_mask_rom"] run_opts: [ @@ -769,7 +769,7 @@ name: rom_raw_unlock uvm_test_seq: chip_sw_lc_raw_unlock_vseq sw_images: [ - "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary", + "//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_test_key_0:1:ot_flash_binary", ] en_run_modes: ["sw_test_mode_mask_rom"] run_opts: [ diff --git a/rules/opentitan/defs.bzl b/rules/opentitan/defs.bzl index e247b5ee512da..fada7a9b9e6a5 100644 --- a/rules/opentitan/defs.bzl +++ b/rules/opentitan/defs.bzl @@ -283,7 +283,7 @@ def opentitan_binary(name, exec_env, **kwargs): def opentitan_test( name, srcs = [], - kind = "flash", + kind = "rram", deps = [], copts = [], defines = [], diff --git a/rules/opentitan/legacy.bzl b/rules/opentitan/legacy.bzl index e0fabc1113b66..c129a4153e9fc 100644 --- a/rules/opentitan/legacy.bzl +++ b/rules/opentitan/legacy.bzl @@ -142,7 +142,7 @@ scramble_flash_vmem = rv_rule( ) def _scramble_rram_vmem_impl(ctx): - outputs = [scramble_rram(ctx, suffix = "src.vmem")] + outputs = [scramble_rram(ctx, suffix = "scr.vmem", name = ctx.attr.out or None)] return [ DefaultInfo( files = depset(outputs), @@ -155,6 +155,10 @@ scramble_rram_vmem = rv_rule( attrs = { "src": attr.label(allow_single_file = True), "otp": attr.label(allow_single_file = True), + "out": attr.string( + default = "", + doc = "Optional name for the output file. If provided the output name will be .scr.vmem otherwise .scr.vmem.", + ), "top_secret_cfg": attr.label( allow_single_file = True, default = "//hw/top:secrets", diff --git a/sw/device/silicon_creator/rom/e2e/BUILD b/sw/device/silicon_creator/rom/e2e/BUILD index 2c7da719e5023..6cd668627621f 100644 --- a/sw/device/silicon_creator/rom/e2e/BUILD +++ b/sw/device/silicon_creator/rom/e2e/BUILD @@ -4,7 +4,7 @@ load("@bazel_skylib//lib:dicts.bzl", "dicts") load("//rules:const.bzl", "CONST", "hex_digits") -load("//rules/opentitan:legacy.bzl", "scramble_flash_vmem", "vmem_file") +load("//rules/opentitan:legacy.bzl", "scramble_flash_vmem", "scramble_rram_vmem", "vmem_file") load("//rules/opentitan:keyutils.bzl", "ECDSA_ONLY_KEY_STRUCTS") load( "//rules:otp.bzl", @@ -207,8 +207,8 @@ opentitan_test( # Corrupt binaries # Note: the naming of the files is important for dvsim. The code expects file to be named: # - binary: ..signed.bin -# - vmem: ..signed.64.vmem -# - flash vmem: ..signed.64.scr.vmem +# - vmem: ..signed.64.vmem (flash) or .128.vmem (rram) +# - scrambled vmem: ..signed.64.scr.vmem (flash) or .128.scr.vmem (rram) [ genrule( name = "empty_test_slot_{}_{}_corrupted_{}_signed_bin".format(slot, key, group), @@ -225,8 +225,11 @@ opentitan_test( ] ] -# The below three rule sets (vmem_file, scramble_flash_vmem, and filegroup) -# are needed to run `sigverify_always` tests in DV. +# The below rule sets (vmem_file, scramble_flash_vmem/scramble_rram_vmem, and +# filegroup) are needed to run `sigverify_always` tests in DV. Tops with +# rram_ctrl (e.g. top_earlgrey) need 128-bit-word rram-scrambled vmem; other +# tops keep the pre-existing 64-bit-word flash-scrambled vmem, hence +# vmem_file/scramble_*_vmem each appearing twice below, once per word size. [ vmem_file( name = "empty_test_slot_{}_{}_corrupted_sim_dv_vmem64_signed".format(slot, key), @@ -243,8 +246,33 @@ opentitan_test( name = "empty_test_slot_{}_{}_corrupted_sim_dv_scr_vmem64_signed".format(slot, key), testonly = True, src = ":empty_test_slot_{}_{}_corrupted_sim_dv_vmem64_signed".format(slot, key), - # Override the name to match what the dv testbench expects. - out = "empty_test_slot_{}_corrupted_sim_dv.{}.signed.64".format(slot, key), + # Override the name to match what the dv testbench expects. All + # SIGVERIFY_LC_KEYS entries are fake ECDSA keys, hence the prefix. + out = "empty_test_slot_{}_corrupted_sim_dv.fake_ecdsa_{}.signed.64".format(slot, key), + ) + for slot in SLOTS + for key in SIGVERIFY_LC_KEYS +] + +[ + vmem_file( + name = "empty_test_slot_{}_{}_corrupted_sim_dv_vmem128_signed".format(slot, key), + testonly = True, + src = ":empty_test_slot_{}_{}_corrupted_sim_dv_signed_bin".format(slot, key), + word_size = 128, # RRAM backdoor-load VMEM image uses 128-bit words + ) + for slot in SLOTS + for key in SIGVERIFY_LC_KEYS +] + +[ + scramble_rram_vmem( + name = "empty_test_slot_{}_{}_corrupted_sim_dv_scr_vmem128_signed".format(slot, key), + testonly = True, + src = ":empty_test_slot_{}_{}_corrupted_sim_dv_vmem128_signed".format(slot, key), + # Override the name to match what the dv testbench expects. All + # SIGVERIFY_LC_KEYS entries are fake ECDSA keys, hence the prefix. + out = "empty_test_slot_{}_corrupted_sim_dv.fake_ecdsa_{}.signed.128".format(slot, key), ) for slot in SLOTS for key in SIGVERIFY_LC_KEYS @@ -252,7 +280,11 @@ opentitan_test( # This file group is here to simplify the naming of the files in the hjson testplan: # the file group contains the files for all possible keys that follow the expected -# name format specified by the tags. +# name format specified by the tags. Both the 64-bit-word (flash) and +# 128-bit-word (rram) variants are always included unconditionally, since +# dvsim's collateral-deployment script fetches all runfiles from this label +# regardless of which top is active; the testbench only reads whichever +# variant it actually needs. [ filegroup( name = "empty_test_slot_{}_corrupted_sim_dv".format(slot), @@ -263,6 +295,8 @@ opentitan_test( "signed_bin", "vmem64_signed", "scr_vmem64_signed", + "vmem128_signed", + "scr_vmem128_signed", ] for key in SIGVERIFY_LC_KEYS ], From cb591eaac428a10e72781718a04efe76eb46e80f Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:20:58 +0200 Subject: [PATCH 29/41] [rram_ctrl,bootstrap,dv] parse 128-bit-word RRAM VMEM in backdoor bootstrap load The spi_device backdoor-load path pointed at flash's ".64.vmem"/ ".64.scr.vmem" and backdoor-loaded FlashBank0Data/FlashBank1Data; RRAM builds never produce a ".64.vmem" file (only ".128.vmem"), and both slots map onto the single RramData memory. Also rewrites read_sw_frames() to a generic, word-size-parametric VMEM tokenizer: the previous fixed 4-token/64-bit-per-line $fscanf parse silently misparsed RRAM's 2-token/128-bit-per-line format (srec_cat varies both the token count and hex-digit width per line with word size), corrupting manifest data read back post-bootstrap. Signed-off-by: Michael Gautschi --- .../dv/env/seq_lib/chip_sw_base_vseq.sv | 66 +++++++++++++------ 1 file changed, 45 insertions(+), 21 deletions(-) diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv index 2d1b7c8ea7359..12aa0c54875f0 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv @@ -121,19 +121,19 @@ class chip_sw_base_vseq extends chip_base_vseq; if (!cfg.sw_images.exists(SwTypeTestSlotA)) begin `uvm_error(get_name(), "Cannot load slot A over SPI: no SW image defined.") end - spi_device_load_bootstrap({cfg.sw_images[SwTypeTestSlotA], ".64.vmem"}); + spi_device_load_bootstrap({cfg.sw_images[SwTypeTestSlotA], ".128.vmem"}); cfg.use_spi_load_bootstrap = 1'b0; // TODO: support bootstrapping entire flash address space, not just slot A. end else begin if (cfg.sw_images.exists(SwTypeTestSlotA)) begin - string image_path = {cfg.sw_images[SwTypeTestSlotA], ".64.scr.vmem"}; - cfg.mem_bkdr_util_h[FlashBank0Data].load_mem_from_file(image_path); + string image_path = {cfg.sw_images[SwTypeTestSlotA], ".128.scr.vmem"}; + cfg.mem_bkdr_util_h[RramData].load_mem_from_file(image_path); end if (cfg.sw_images.exists(SwTypeTestSlotB)) begin - string image_path = {cfg.sw_images[SwTypeTestSlotB], ".64.scr.vmem"}; - cfg.mem_bkdr_util_h[FlashBank1Data].load_mem_from_file(image_path); + string image_path = {cfg.sw_images[SwTypeTestSlotB], ".128.scr.vmem"}; + cfg.mem_bkdr_util_h[RramData].load_mem_from_file(image_path); end end @@ -586,7 +586,7 @@ class chip_sw_base_vseq extends chip_base_vseq; wait_for_flash_command_load(); `uvm_info(`gfn, $sformatf("Reading SW image frames from %0s ...", sw_image), UVM_LOW) - read_sw_frames(sw_image, sw_byte_q); + read_sw_frames(sw_image, sw_byte_q, 128); `uvm_info(`gfn, "Sending SPI flash erase command ...", UVM_LOW) erase_flash_over_spi(); @@ -624,27 +624,51 @@ class chip_sw_base_vseq extends chip_base_vseq; spi_host_flash_issue_write_cmd(page_seq); endtask - // Read the flash image pointed to by the `sw_image` path, and place the - // data into the `sw_byte_q`. The flash image is assumed to consist of - // contiguous data starting from the base of flash. - virtual function void read_sw_frames(string sw_image, ref byte sw_byte_q[$]); - int num_returns; + // Parses a VMEM file (the `@ [ ...]` format srec_cat + // produces) into a flat byte queue, in address order. `word_size_bits` must + // match the word size the file was generated with: both the hex-digit width + // of each token AND the number of tokens packed per line vary with it (e.g. + // flash `.64.vmem` packs 4 64-bit words/line, RRAM `.128.vmem` packs 2 + // 128-bit words/line) -- a fixed 4-token, 64-bit-wide parse silently + // misparses any other word size. + virtual function void read_sw_frames(string sw_image, ref byte sw_byte_q[$], + input int word_size_bits = 64); int mem_fd = $fopen(sw_image, "r"); - bit [63:0] word_data[4]; - string addr; + string line; + int word_size_bytes = word_size_bits / 8; if (!mem_fd) begin `uvm_error(get_name(), $sformatf("Failed to open sw_image file at %0s.", sw_image)) end - while (!$feof(mem_fd)) begin - num_returns = $fscanf(mem_fd, "%s %h %h %h %h", addr, word_data[0], word_data[1], - word_data[2], word_data[3]); - if (num_returns <= 1) continue; - for (int i = 0; i < num_returns - 1; i++) begin - repeat (8) begin - sw_byte_q.push_back(word_data[i][7:0]); - word_data[i] = word_data[i] >> 8; + while ($fgets(line, mem_fd)) begin + string tokens[$]; + int pos = 0; + if (line.len() == 0 || line[0] != "@") continue; + + while (pos < line.len()) begin + string tok; + while (pos < line.len() && + (line[pos] == " " || line[pos] == "\t" || + line[pos] == "\n" || line[pos] == "\r")) pos++; + if (pos >= line.len()) break; + tok = ""; + while (pos < line.len() && + !(line[pos] == " " || line[pos] == "\t" || + line[pos] == "\n" || line[pos] == "\r")) begin + tok = {tok, line[pos]}; + pos++; + end + tokens.push_back(tok); + end + + // tokens[0] is the "@addr" marker; the rest are data words. + for (int i = 1; i < tokens.size(); i++) begin + bit [255:0] word_data; + void'($sscanf(tokens[i], "%h", word_data)); + repeat (word_size_bytes) begin + sw_byte_q.push_back(word_data[7:0]); + word_data = word_data >> 8; end end end From 575b42d6567dd53db4d6012e18d4aced70be3bcc Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Mon, 27 Jul 2026 17:21:35 +0200 Subject: [PATCH 30/41] [rram_ctrl,sw] coalesce PAGE_PROGRAM writes to NVM_PROG_PAGE_SIZE boundaries Each SPI PAGE_PROGRAM command carries at most one 256-byte SPI upload payload, well below NVM_PROG_PAGE_SIZE (512 B on RRAM). Buffers consecutive, contiguous PAGE_PROGRAM payloads up to NVM_PROG_PAGE_SIZE before issuing a single nvm_ctrl_page_program() write, flushing early on a non-contiguous next chunk, a page-boundary crossing, or any non-PAGE_PROGRAM opcode (in particular RESET, so a staged chunk is never silently dropped at the end of a session). On RRAM this halves the number of physical write operations for a full-speed bootstrap image load, since NVM_PROG_PAGE_SIZE matches RRAM's store-buffer size and a write that straddles two of them costs an extra operation. No hardware or protocol change; flash's PROG_PAGE_SIZE equals one SPI payload, so it fills and flushes every command, unchanged from before. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/bootstrap.c | 106 +++++++++++++++++++++- 1 file changed, 102 insertions(+), 4 deletions(-) diff --git a/sw/device/silicon_creator/lib/bootstrap.c b/sw/device/silicon_creator/lib/bootstrap.c index 97e3d07599f4c..cd79d8abd04f2 100644 --- a/sw/device/silicon_creator/lib/bootstrap.c +++ b/sw/device/silicon_creator/lib/bootstrap.c @@ -10,6 +10,7 @@ #include "sw/device/lib/base/bitfield.h" #include "sw/device/lib/base/hardened.h" +#include "sw/device/lib/base/memory.h" #include "sw/device/silicon_creator/lib/drivers/rstmgr.h" #include "sw/device/silicon_creator/lib/drivers/spi_device.h" #include "sw/device/silicon_creator/lib/error.h" @@ -75,8 +76,11 @@ static rom_error_t bootstrap_sector_erase(uint32_t addr) { } /** - * Handles access permissions and programs up to 256 bytes of flash memory - * starting at `addr`. + * Handles access permissions and programs flash memory starting at `addr`. + * + * Called with up to `kProgramCoalesceBufBytes` bytes at a time (see + * `bootstrap_program_coalesce()`), not just a single SPI `PAGE_PROGRAM` + * command's payload. * * If `byte_count` is not a multiple of flash word size, it's rounded up to next * flash word and missing bytes in `data` are set to `0xff`. @@ -98,6 +102,93 @@ static rom_error_t bootstrap_page_program(uint32_t addr, size_t byte_count, return nvm_ctrl_page_program(addr, byte_count, data); } +enum { + // Each SPI `PAGE_PROGRAM` command carries at most one SPI upload payload + // buffer's worth of data (`kSpiDevicePayloadAreaNumBytes`, a fixed 256-byte + // hardware SRAM partition; see `spi_device.h`). Coalescing consecutive, + // contiguous commands up to `NVM_PROG_PAGE_SIZE` -- the same unit + // `nvm_ctrl_page_program()` uses internally -- lets each NVM write + // transaction cover as much of it as the underlying technology can + // usefully absorb in one go, without any hardware or protocol change. + // + // For RRAM, `NVM_PROG_PAGE_SIZE` (512) is two SPI payloads, matching + // `rram_phy_wr`'s store-buffer size: a write up to this size commits to + // the array as a single physical operation, and one that straddles two of + // these units costs an extra one (see the doc comment on + // `NVM_PROG_PAGE_SIZE`). Flash does not perform coalescing. + kProgramCoalesceBufBytes = NVM_PROG_PAGE_SIZE, +}; + +/** + * State for coalescing consecutive, contiguous `PAGE_PROGRAM` payloads into + * fewer, larger NVM write transactions. + */ +typedef struct bootstrap_program_coalesce_ctx { + uint32_t addr; + size_t byte_count; + alignas(uint32_t) uint8_t data[kProgramCoalesceBufBytes]; +} bootstrap_program_coalesce_ctx_t; + +static bootstrap_program_coalesce_ctx_t coalesce_ctx; + +/** + * Writes any bytes currently staged in `coalesce_ctx` to NVM. A no-op if + * nothing is staged. + * + * Must be called before honoring any bootstrap command other than + * `PAGE_PROGRAM` (in particular before `RESET`), so that a staged chunk is + * never silently dropped. + * + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t bootstrap_program_flush(void) { + if (coalesce_ctx.byte_count == 0) { + return kErrorOk; + } + rom_error_t error = bootstrap_page_program( + coalesce_ctx.addr, coalesce_ctx.byte_count, coalesce_ctx.data); + coalesce_ctx.byte_count = 0; + return error; +} + +/** + * Stages a `PAGE_PROGRAM` command's payload for coalescing with the next + * command, flushing to NVM once the staging buffer is full, the next command + * isn't contiguous with what's already staged, or coalescing it in would + * cross an NVM page boundary. + * + * @param addr Address the payload should be written to. + * @param byte_count Number of bytes in `data`. + * @param data Payload data. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t bootstrap_program_coalesce(uint32_t addr, size_t byte_count, + const uint8_t *data) { + bool contiguous = addr == coalesce_ctx.addr + coalesce_ctx.byte_count; + bool fits = coalesce_ctx.byte_count + byte_count <= kProgramCoalesceBufBytes; + bool same_page = coalesce_ctx.addr / NVM_PROG_PAGE_SIZE == + (addr + byte_count - 1) / NVM_PROG_PAGE_SIZE; + if (coalesce_ctx.byte_count > 0 && (!contiguous || !fits || !same_page)) { + HARDENED_RETURN_IF_ERROR(bootstrap_program_flush()); + } + if (coalesce_ctx.byte_count == 0) { + coalesce_ctx.addr = addr; + } + memcpy(coalesce_ctx.data + coalesce_ctx.byte_count, data, byte_count); + coalesce_ctx.byte_count += byte_count; + // Coalescing only pays off when the buffer spans more than one SPI + // payload (RRAM); when it doesn't (flash, where it's exactly one SPI + // payload), every chunk should still flush right away even if it's a + // short final one, matching flash's pre-coalescing behavior. + if ((size_t)kProgramCoalesceBufBytes > kSpiDevicePayloadAreaNumBytes && + coalesce_ctx.byte_count < kProgramCoalesceBufBytes) { + return kErrorOk; + } + return bootstrap_program_flush(); +} + /** * Bootstrap state 1: Wait for an erase command and erase the data * partition. @@ -184,6 +275,13 @@ static rom_error_t bootstrap_handle_program(bootstrap_state_t *state) { return kErrorOk; } + // Every command other than `PAGE_PROGRAM` must flush any coalesced payload + // first, so a staged chunk is never silently dropped (in particular before + // `RESET`, which is how a normal bootstrap session ends). + if (cmd.opcode != kSpiDeviceOpcodePageProgram) { + RETURN_IF_ERROR(bootstrap_program_flush()); + } + rom_error_t error = kErrorUnknown; switch (cmd.opcode) { case kSpiDeviceOpcodeChipErase: @@ -193,8 +291,8 @@ static rom_error_t bootstrap_handle_program(bootstrap_state_t *state) { error = bootstrap_sector_erase(cmd.address); break; case kSpiDeviceOpcodePageProgram: - error = bootstrap_page_program(cmd.address, cmd.payload_byte_count, - cmd.payload); + error = bootstrap_program_coalesce(cmd.address, cmd.payload_byte_count, + cmd.payload); break; case kSpiDeviceOpcodeReset: // In a normal build, this function inlines to nothing. From e9776d00b0699eb5847b75792367b948a71f57e2 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 11:04:27 +0200 Subject: [PATCH 31/41] [nvm_ctrl,sw] use nvm_ctrl in fi test Signed-off-by: Michael Gautschi --- .../tests/penetrationtests/firmware/fi/BUILD | 3 +- .../penetrationtests/firmware/fi/boot_fi.c | 35 ++++++++----------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/sw/device/tests/penetrationtests/firmware/fi/BUILD b/sw/device/tests/penetrationtests/firmware/fi/BUILD index cfaf3cb68cc36..65fd80b3a1f2b 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/BUILD +++ b/sw/device/tests/penetrationtests/firmware/fi/BUILD @@ -303,7 +303,6 @@ cc_library( srcs = ["boot_fi.c"], hdrs = ["boot_fi.h"], deps = [ - "//hw/top:flash_ctrl_c_regs", "//hw/top:rom_ctrl_c_regs", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:csr", @@ -318,8 +317,8 @@ cc_library( "//sw/device/silicon_creator/lib:boot_log", "//sw/device/silicon_creator/lib:epmp_state", "//sw/device/silicon_creator/lib:manifest", + "//sw/device/silicon_creator/lib:nvm_ctrl", "//sw/device/silicon_creator/lib/boot_svc:boot_svc_next_boot_bl0_slot", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:retention_sram", "//sw/device/silicon_creator/lib/drivers:rstmgr", "//sw/device/silicon_creator/rom_ext:rom_ext_manifest", diff --git a/sw/device/tests/penetrationtests/firmware/fi/boot_fi.c b/sw/device/tests/penetrationtests/firmware/fi/boot_fi.c index 15cd688e65a2d..8a7af83656fbc 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/boot_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/boot_fi.c @@ -17,16 +17,15 @@ #include "sw/device/lib/ujson/ujson.h" #include "sw/device/silicon_creator/lib/boot_log.h" #include "sw/device/silicon_creator/lib/boot_svc/boot_svc_next_boot_bl0_slot.h" -#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" #include "sw/device/silicon_creator/lib/drivers/retention_sram.h" #include "sw/device/silicon_creator/lib/drivers/rstmgr.h" #include "sw/device/silicon_creator/lib/epmp_state.h" #include "sw/device/silicon_creator/lib/manifest.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" #include "sw/device/silicon_creator/rom_ext/rom_ext_manifest.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" #include "sw/device/tests/penetrationtests/json/boot_fi_commands.h" -#include "hw/top/flash_ctrl_regs.h" #include "hw/top/rom_ctrl_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" @@ -34,23 +33,20 @@ static dif_rv_core_ibex_t rv_core_ibex; static manifest_t *get_rom_ext_manifest_a(void) { - return (manifest_t *)TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + return (manifest_t *)NVM_DATA_BASE_ADDR; } static manifest_t *get_rom_ext_manifest_b(void) { - return (manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - (TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2)); + return (manifest_t *)(NVM_DATA_BASE_ADDR + NVM_BYTES_PER_SLOT); } static manifest_t *get_firmware_manifest_a(void) { - return (manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - CHIP_ROM_EXT_SIZE_MAX); + return (manifest_t *)(NVM_DATA_BASE_ADDR + CHIP_ROM_EXT_SIZE_MAX); } static manifest_t *get_firmware_manifest_b(void) { - return (manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - CHIP_ROM_EXT_SIZE_MAX + - (TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2)); + return (manifest_t *)(NVM_DATA_BASE_ADDR + NVM_BYTES_PER_SLOT + + CHIP_ROM_EXT_SIZE_MAX); } status_t handle_inactive_firmware_invalidation(ujson_t *uj) { @@ -68,16 +64,16 @@ status_t handle_inactive_firmware_invalidation(ujson_t *uj) { manifest = get_firmware_manifest_a(); } - flash_ctrl_data_default_perms_set( - (flash_ctrl_perms_t){.read = kMultiBitBool4True, - .write = kMultiBitBool4True, - .erase = kMultiBitBool4False}); + nvm_ctrl_data_default_perms_set( + (nvm_page_perms_t){.read = kMultiBitBool4True, + .write = kMultiBitBool4True, + .erase = kMultiBitBool4False}); - uint32_t sig_offset = (uint32_t)&manifest->ecdsa_signature.r[0] - - TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + uint32_t sig_offset = + (uint32_t)&manifest->ecdsa_signature.r[0] - NVM_DATA_BASE_ADDR; uint32_t zero_val = 0; - rom_error_t err = flash_ctrl_data_write(sig_offset, 1, &zero_val); + rom_error_t err = nvm_ctrl_data_write(sig_offset, 1, &zero_val); if (err != kErrorOk) { LOG_ERROR("Failed to corrupt ECDSA signature: 0x%08x", err); @@ -88,10 +84,9 @@ status_t handle_inactive_firmware_invalidation(ujson_t *uj) { err = manifest_ext_get_spx_signature(manifest, &spx_ext); if (err == kErrorOk && spx_ext != NULL) { - uint32_t spx_offset = - (uint32_t)&spx_ext->signature - TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + uint32_t spx_offset = (uint32_t)&spx_ext->signature - NVM_DATA_BASE_ADDR; - err = flash_ctrl_data_write(spx_offset, 1, &zero_val); + err = nvm_ctrl_data_write(spx_offset, 1, &zero_val); if (err != kErrorOk) { LOG_ERROR("Failed to corrupt SPX signature: 0x%08x", err); From 49fac76dfd6840906abb0e333fe660379212e35a Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 11:05:05 +0200 Subject: [PATCH 32/41] [nvm_ctrl,sw] use nvm_ctrl in pmp setup This commit configures the epmp in the imm_section to the NVM region instead of a hardcoded flash region. Signed-off-by: Michael Gautschi --- .../silicon_creator/rom_ext/imm_section/BUILD | 1 + .../rom_ext/imm_section/imm_section_epmp.c | 14 +++++++------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/sw/device/silicon_creator/rom_ext/imm_section/BUILD b/sw/device/silicon_creator/rom_ext/imm_section/BUILD index 3348581f0847e..b5abb5423e46b 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/BUILD +++ b/sw/device/silicon_creator/rom_ext/imm_section/BUILD @@ -100,6 +100,7 @@ cc_library( "//sw/device/silicon_creator/lib:epmp_state", "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib:manifest", + "//sw/device/silicon_creator/lib:nvm_ctrl", "//sw/device/silicon_creator/lib/drivers:epmp", "//sw/device/silicon_creator/lib/drivers:lifecycle", ], diff --git a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_epmp.c b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_epmp.c index 885543d67685a..89cabdd47aad9 100644 --- a/sw/device/silicon_creator/rom_ext/imm_section/imm_section_epmp.c +++ b/sw/device/silicon_creator/rom_ext/imm_section/imm_section_epmp.c @@ -11,6 +11,7 @@ #include "sw/device/silicon_creator/lib/epmp_state.h" #include "sw/device/silicon_creator/lib/error.h" #include "sw/device/silicon_creator/lib/manifest.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. @@ -25,10 +26,9 @@ static const epmp_region_t kMmioRegion = { .end = TOP_EARLGREY_MMIO_BASE_ADDR + TOP_EARLGREY_MMIO_SIZE_BYTES, }; -static const epmp_region_t kFlashRegion = { - .start = TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR, - .end = TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES, +static const epmp_region_t kNvmRegion = { + .start = NVM_DATA_BASE_ADDR, + .end = NVM_DATA_BASE_ADDR + NVM_DATA_SIZE_BYTES, }; static const epmp_region_t kRvDmRegion = { @@ -56,9 +56,9 @@ rom_error_t imm_section_epmp_reconfigure(void) { // This stack guard was in ePMP region 14. epmp_set_napot(11, kStackGuard, kEpmpPermLockedNoAccess); - // ePMP region 12 gives read access to all of flash for both M and U modes. - // This flash region was in ePMP region 5. - epmp_set_napot(12, kFlashRegion, kEpmpPermLockedReadOnly); + // ePMP region 12 gives read access to all of NVM for both M and U modes. + // This region was in ePMP region 5. + epmp_set_napot(12, kNvmRegion, kEpmpPermLockedReadOnly); // ePMP region 13 allows RvDM access. if (lifecycle_is_prod() == kHardenedBoolTrue) { From 3d00a8ccbb3411b6b1a5a5fd218d5a60481a8d67 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 11:06:50 +0200 Subject: [PATCH 33/41] [rom,sw] print mepc in crashdump Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/shutdown.c | 8 ++++++-- sw/device/silicon_creator/lib/shutdown.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/sw/device/silicon_creator/lib/shutdown.c b/sw/device/silicon_creator/lib/shutdown.c index 848de1e9a9255..b5d03d02f14f4 100644 --- a/sw/device/silicon_creator/lib/shutdown.c +++ b/sw/device/silicon_creator/lib/shutdown.c @@ -428,9 +428,13 @@ SHUTDOWN_FUNC(NO_MODIFIERS, shutdown_report_error(rom_error_t reason)) { uart_ctrl_reg = bitfield_bit32_write(uart_ctrl_reg, UART_CTRL_TX_BIT, true); abs_mmio_write32(uart0_base() + UART_CTRL_REG_OFFSET, uart_ctrl_reg); - // Print the error message and the raw life cycle state as reported by the - // hardware. + // Print the error message, the faulting PC (if any; unchanged if `reason` + // didn't originate from a trap), and the raw life cycle state as reported + // by the hardware. + uint32_t mepc; + CSR_READ(CSR_REG_MEPC, &mepc); shutdown_print(kShutdownLogPrefixBootFault, redacted_error); + shutdown_print(kShutdownLogPrefixMepc, mepc); shutdown_print(kShutdownLogPrefixLifecycle, raw_state); shutdown_print(kShutdownLogPrefixVersion, kBuildInfo.scm_revision.scm_revision_high); diff --git a/sw/device/silicon_creator/lib/shutdown.h b/sw/device/silicon_creator/lib/shutdown.h index 6351df8369c00..ebcac6412f87a 100644 --- a/sw/device/silicon_creator/lib/shutdown.h +++ b/sw/device/silicon_creator/lib/shutdown.h @@ -87,6 +87,7 @@ typedef enum shutdown_error_redact { */ typedef enum shutdown_log_prefix { kShutdownLogPrefixBootFault = LOG_PREFIX_('B', 'F', 'V'), + kShutdownLogPrefixMepc = LOG_PREFIX_('E', 'P', 'C'), kShutdownLogPrefixLifecycle = LOG_PREFIX_('L', 'C', 'V'), kShutdownLogPrefixVersion = LOG_PREFIX_('V', 'E', 'R'), } shutdown_log_prefix_t; From 165907dffaa2b2e96d47eaad3f1e40e032ddff57 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 12:08:17 +0200 Subject: [PATCH 34/41] [rom,sw] rename shutdown_flash_kill to shutdown_nvm_kill Disable flash_ctrl or rram_ctrl depending on what is present in the current top. Signed-off-by: Michael Gautschi --- sw/device/silicon_creator/lib/BUILD | 10 ++++++++++ sw/device/silicon_creator/lib/shutdown.c | 13 +++++++++--- .../silicon_creator/lib/shutdown_unittest.cc | 20 ++++++++++++------- 3 files changed, 33 insertions(+), 10 deletions(-) diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index 38be27d6308d0..bac2f8f4a4ea2 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -385,6 +385,10 @@ dual_cc_library( "flash_ctrl", ["HAS_FLASH_CTRL"], [], + ) + opentitan_if_ip( + "rram_ctrl", + ["HAS_RRAM_CTRL"], + [], ) + opentitan_if_ip( "keymgr", ["HAS_KEYMGR"], @@ -427,6 +431,10 @@ dual_cc_library( "flash_ctrl", [dual_cc_device_library_of("//sw/device/silicon_creator/lib/drivers:flash_ctrl")], [], + ) + opentitan_if_ip( + "rram_ctrl", + ["//sw/device/silicon_creator/lib/drivers:rram_ctrl"], + [], ) + opentitan_if_ip( "keymgr", ["//sw/device/silicon_creator/lib/drivers:keymgr"], @@ -441,8 +449,10 @@ cc_test( deps = [ dual_cc_device_library_of(":shutdown"), "//hw/top:flash_ctrl_c_regs", + "//hw/top:rram_ctrl_c_regs", "//hw/top/dt", "//hw/top/dt:flash_ctrl", + "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/silicon_creator/testing:rom_test", "@googletest//:gtest_main", ], diff --git a/sw/device/silicon_creator/lib/shutdown.c b/sw/device/silicon_creator/lib/shutdown.c index b5d03d02f14f4..131c394a1f6fa 100644 --- a/sw/device/silicon_creator/lib/shutdown.c +++ b/sw/device/silicon_creator/lib/shutdown.c @@ -34,6 +34,10 @@ #include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" #endif +#ifdef HAS_RRAM_CTRL +#include "sw/device/silicon_creator/lib/drivers/rram_ctrl.h" +#endif + #ifdef HAS_KEYMGR #include "sw/device/silicon_creator/lib/drivers/keymgr.h" #endif @@ -454,10 +458,13 @@ SHUTDOWN_FUNC(NO_MODIFIERS, shutdown_reset(void)) { kMultiBitBool4True); } -SHUTDOWN_FUNC(NO_MODIFIERS, shutdown_flash_kill(void)) { +SHUTDOWN_FUNC(NO_MODIFIERS, shutdown_nvm_kill(void)) { #ifdef HAS_FLASH_CTRL flash_ctrl_disable(); #endif +#ifdef HAS_RRAM_CTRL + rram_ctrl_disable(); +#endif } SHUTDOWN_FUNC(NO_MODIFIERS, shutdown_keymgr_kill(void)) { @@ -543,9 +550,9 @@ void shutdown_finalize(rom_error_t reason) { shutdown_keymgr_kill(); // Report coverage again to ensure the calls above are reported. coverage_report(); - // Reset before killing the flash to be able to use this also in flash. + // Reset before killing NVM to be able to use this also in NVM. shutdown_reset(); - shutdown_flash_kill(); + shutdown_nvm_kill(); // If we get here, we'll wait for the watchdog to reset the chip. shutdown_hang(); } diff --git a/sw/device/silicon_creator/lib/shutdown_unittest.cc b/sw/device/silicon_creator/lib/shutdown_unittest.cc index 55edbce0924e9..80811bf510740 100644 --- a/sw/device/silicon_creator/lib/shutdown_unittest.cc +++ b/sw/device/silicon_creator/lib/shutdown_unittest.cc @@ -25,7 +25,9 @@ #include "hw/top/flash_ctrl_regs.h" #include "hw/top/lc_ctrl_regs.h" #include "hw/top/otp_ctrl_regs.h" +#include "hw/top/rram_ctrl_regs.h" #include "hw/top/rv_core_ibex_regs.h" +#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" namespace shutdown_unittest { @@ -44,7 +46,7 @@ class MockShutdownImpl : public ::global_mock::GlobalMock { MOCK_METHOD(void, shutdown_software_escalate, ()); MOCK_METHOD(void, shutdown_keymgr_kill, ()); MOCK_METHOD(void, shutdown_reset, ()); - MOCK_METHOD(void, shutdown_flash_kill, ()); + MOCK_METHOD(void, shutdown_nvm_kill, ()); MOCK_METHOD(void, shutdown_hang, ()); }; @@ -63,15 +65,15 @@ void shutdown_keymgr_kill(void) { void shutdown_reset(void) { return MockShutdownImpl::Instance().shutdown_reset(); } -void shutdown_flash_kill(void) { - return MockShutdownImpl::Instance().shutdown_flash_kill(); +void shutdown_nvm_kill(void) { + return MockShutdownImpl::Instance().shutdown_nvm_kill(); } void shutdown_hang(void) { return MockShutdownImpl::Instance().shutdown_hang(); } // Real implementations of the above mocks. -extern void unmocked_shutdown_flash_kill(void); +extern void unmocked_shutdown_nvm_kill(void); extern void unmocked_shutdown_software_escalate(void); } // extern "C" @@ -357,7 +359,7 @@ class ShutdownTest : public rom_test::RomTest { EXPECT_CALL(shutdown_, shutdown_software_escalate()); EXPECT_CALL(shutdown_, shutdown_keymgr_kill()); EXPECT_CALL(shutdown_, shutdown_reset()); - EXPECT_CALL(shutdown_, shutdown_flash_kill()); + EXPECT_CALL(shutdown_, shutdown_nvm_kill()); EXPECT_CALL(shutdown_, shutdown_hang()); } @@ -592,11 +594,15 @@ TEST_F(ShutdownTest, ShutdownFinalize) { shutdown_finalize(kErrorUnknown); } -TEST_F(ShutdownTest, FlashKill) { +TEST_F(ShutdownTest, NvmKill) { const uint32_t flash_ctrl_base = dt_flash_ctrl_reg_block(kDtFlashCtrl, kDtFlashCtrlRegBlockCore); EXPECT_ABS_WRITE32(flash_ctrl_base + FLASH_CTRL_DIS_REG_OFFSET, 0); - unmocked_shutdown_flash_kill(); + // Earlgrey's memory map carries both flash_ctrl and rram_ctrl, so + // shutdown_nvm_kill() disables both NVM controllers. + EXPECT_ABS_WRITE32( + TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + RRAM_CTRL_DIS_REG_OFFSET, 0); + unmocked_shutdown_nvm_kill(); } TEST_F(ShutdownTest, ShutdownIfErrorOk) { SHUTDOWN_IF_ERROR(kErrorOk); } From a50c928db5e7447c637b58c5b279b2e2590453b4 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 17:25:33 +0200 Subject: [PATCH 35/41] [rram_ctrl,hw] grow to 10 memory-protection regions The shared memory-protection region used for emulated info pages needs a dedicated index that doesn't collide with rom_ext/owner_block's use of regions 0-7 (see following sw commit). Bump NumRegions from 8 to 10 and regenerate the reg_pkg/reg_top RTL accordingly. Signed-off-by: Michael Gautschi --- hw/ip/rram_ctrl/data/rram_ctrl.hjson | 4 +- hw/ip/rram_ctrl/rtl/rram_ctrl_core_reg_top.sv | 962 ++++++++++++++---- hw/ip/rram_ctrl/rtl/rram_ctrl_pkg.sv | 2 +- hw/ip/rram_ctrl/rtl/rram_ctrl_reg_pkg.sv | 238 +++-- 4 files changed, 906 insertions(+), 300 deletions(-) diff --git a/hw/ip/rram_ctrl/data/rram_ctrl.hjson b/hw/ip/rram_ctrl/data/rram_ctrl.hjson index 40f3656aa8dd8..ffb046d86bea7 100644 --- a/hw/ip/rram_ctrl/data/rram_ctrl.hjson +++ b/hw/ip/rram_ctrl/data/rram_ctrl.hjson @@ -372,7 +372,7 @@ { name: "NumRegions", desc: "Number of configurable rram regions", type: "int", - default: "8", + default: "10", local: "true" }, { name: "NumInfoPages", @@ -455,7 +455,7 @@ } { name: "RRAM_CTRL.MEM_PROTECTION" - desc: '''For data partitions, SW can designate a memory region of up to 8 regions. + desc: '''For data partitions, SW can designate a memory region of up to 10 regions. Each of these regions can contain more than one page, up to a maximum limit (which is 512 in earlgrey). For each region, SW can establish the access policy by programming RRAM_CTRL.MP_REGION_CFG. In the case of information partitions, the access policy can be configured on a per page basis. diff --git a/hw/ip/rram_ctrl/rtl/rram_ctrl_core_reg_top.sv b/hw/ip/rram_ctrl/rtl/rram_ctrl_core_reg_top.sv index 349a80f97cb02..20a88f868b995 100644 --- a/hw/ip/rram_ctrl/rtl/rram_ctrl_core_reg_top.sv +++ b/hw/ip/rram_ctrl/rtl/rram_ctrl_core_reg_top.sv @@ -57,9 +57,9 @@ module rram_ctrl_core_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [64:0] reg_we_check; + logic [70:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(65) + .OneHotWidth(71) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -130,8 +130,8 @@ module rram_ctrl_core_reg_top ( // Create steering logic always_comb begin reg_steer = - tl_i.a_address[AW-1:0] inside {[260:263]} ? 2'd0 : - tl_i.a_address[AW-1:0] inside {[264:267]} ? 2'd1 : + tl_i.a_address[AW-1:0] inside {[284:287]} ? 2'd0 : + tl_i.a_address[AW-1:0] inside {[288:291]} ? 2'd1 : // Default set to register 2'd2; @@ -257,6 +257,12 @@ module rram_ctrl_core_reg_top ( logic region_cfg_regwen_7_we; logic region_cfg_regwen_7_qs; logic region_cfg_regwen_7_wd; + logic region_cfg_regwen_8_we; + logic region_cfg_regwen_8_qs; + logic region_cfg_regwen_8_wd; + logic region_cfg_regwen_9_we; + logic region_cfg_regwen_9_qs; + logic region_cfg_regwen_9_wd; logic mp_region_cfg_0_we; logic [3:0] mp_region_cfg_0_en_0_qs; logic [3:0] mp_region_cfg_0_en_0_wd; @@ -345,6 +351,28 @@ module rram_ctrl_core_reg_top ( logic [3:0] mp_region_cfg_7_scramble_en_7_wd; logic [3:0] mp_region_cfg_7_ecc_en_7_qs; logic [3:0] mp_region_cfg_7_ecc_en_7_wd; + logic mp_region_cfg_8_we; + logic [3:0] mp_region_cfg_8_en_8_qs; + logic [3:0] mp_region_cfg_8_en_8_wd; + logic [3:0] mp_region_cfg_8_rd_en_8_qs; + logic [3:0] mp_region_cfg_8_rd_en_8_wd; + logic [3:0] mp_region_cfg_8_wr_en_8_qs; + logic [3:0] mp_region_cfg_8_wr_en_8_wd; + logic [3:0] mp_region_cfg_8_scramble_en_8_qs; + logic [3:0] mp_region_cfg_8_scramble_en_8_wd; + logic [3:0] mp_region_cfg_8_ecc_en_8_qs; + logic [3:0] mp_region_cfg_8_ecc_en_8_wd; + logic mp_region_cfg_9_we; + logic [3:0] mp_region_cfg_9_en_9_qs; + logic [3:0] mp_region_cfg_9_en_9_wd; + logic [3:0] mp_region_cfg_9_rd_en_9_qs; + logic [3:0] mp_region_cfg_9_rd_en_9_wd; + logic [3:0] mp_region_cfg_9_wr_en_9_qs; + logic [3:0] mp_region_cfg_9_wr_en_9_wd; + logic [3:0] mp_region_cfg_9_scramble_en_9_qs; + logic [3:0] mp_region_cfg_9_scramble_en_9_wd; + logic [3:0] mp_region_cfg_9_ecc_en_9_qs; + logic [3:0] mp_region_cfg_9_ecc_en_9_wd; logic mp_region_0_we; logic [11:0] mp_region_0_base_0_qs; logic [11:0] mp_region_0_base_0_wd; @@ -385,6 +413,16 @@ module rram_ctrl_core_reg_top ( logic [11:0] mp_region_7_base_7_wd; logic [11:0] mp_region_7_size_7_qs; logic [11:0] mp_region_7_size_7_wd; + logic mp_region_8_we; + logic [11:0] mp_region_8_base_8_qs; + logic [11:0] mp_region_8_base_8_wd; + logic [11:0] mp_region_8_size_8_qs; + logic [11:0] mp_region_8_size_8_wd; + logic mp_region_9_we; + logic [11:0] mp_region_9_base_9_qs; + logic [11:0] mp_region_9_base_9_wd; + logic [11:0] mp_region_9_size_9_qs; + logic [11:0] mp_region_9_size_9_wd; logic default_region_we; logic [3:0] default_region_rd_en_qs; logic [3:0] default_region_rd_en_wd; @@ -1602,6 +1640,64 @@ module rram_ctrl_core_reg_top ( ); + // Subregister 8 of Multireg region_cfg_regwen + // R[region_cfg_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_region_cfg_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (region_cfg_regwen_8_we), + .wd (region_cfg_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (region_cfg_regwen_8_qs) + ); + + + // Subregister 9 of Multireg region_cfg_regwen + // R[region_cfg_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_region_cfg_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (region_cfg_regwen_9_we), + .wd (region_cfg_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (region_cfg_regwen_9_qs) + ); + + // Subregister 0 of Multireg mp_region_cfg // R[mp_region_cfg_0]: V(False) // Create REGWEN-gated WE signal @@ -2730,6 +2826,288 @@ module rram_ctrl_core_reg_top ( ); + // Subregister 8 of Multireg mp_region_cfg + // R[mp_region_cfg_8]: V(False) + // Create REGWEN-gated WE signal + logic mp_region_cfg_8_gated_we; + assign mp_region_cfg_8_gated_we = mp_region_cfg_8_we & region_cfg_regwen_8_qs; + // F[en_8]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_8_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_8_gated_we), + .wd (mp_region_cfg_8_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[8].en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_8_en_8_qs) + ); + + // F[rd_en_8]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_8_rd_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_8_gated_we), + .wd (mp_region_cfg_8_rd_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[8].rd_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_8_rd_en_8_qs) + ); + + // F[wr_en_8]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_8_wr_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_8_gated_we), + .wd (mp_region_cfg_8_wr_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[8].wr_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_8_wr_en_8_qs) + ); + + // F[scramble_en_8]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_8_scramble_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_8_gated_we), + .wd (mp_region_cfg_8_scramble_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[8].scramble_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_8_scramble_en_8_qs) + ); + + // F[ecc_en_8]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_8_ecc_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_8_gated_we), + .wd (mp_region_cfg_8_ecc_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[8].ecc_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_8_ecc_en_8_qs) + ); + + + // Subregister 9 of Multireg mp_region_cfg + // R[mp_region_cfg_9]: V(False) + // Create REGWEN-gated WE signal + logic mp_region_cfg_9_gated_we; + assign mp_region_cfg_9_gated_we = mp_region_cfg_9_we & region_cfg_regwen_9_qs; + // F[en_9]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_9_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_9_gated_we), + .wd (mp_region_cfg_9_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[9].en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_9_en_9_qs) + ); + + // F[rd_en_9]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_9_rd_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_9_gated_we), + .wd (mp_region_cfg_9_rd_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[9].rd_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_9_rd_en_9_qs) + ); + + // F[wr_en_9]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_9_wr_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_9_gated_we), + .wd (mp_region_cfg_9_wr_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[9].wr_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_9_wr_en_9_qs) + ); + + // F[scramble_en_9]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_9_scramble_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_9_gated_we), + .wd (mp_region_cfg_9_scramble_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[9].scramble_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_9_scramble_en_9_qs) + ); + + // F[ecc_en_9]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_mp_region_cfg_9_ecc_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_cfg_9_gated_we), + .wd (mp_region_cfg_9_ecc_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region_cfg[9].ecc_en.q), + .ds (), + + // to register interface (read) + .qs (mp_region_cfg_9_ecc_en_9_qs) + ); + + // Subregister 0 of Multireg mp_region // R[mp_region_0]: V(False) // Create REGWEN-gated WE signal @@ -3210,6 +3588,126 @@ module rram_ctrl_core_reg_top ( ); + // Subregister 8 of Multireg mp_region + // R[mp_region_8]: V(False) + // Create REGWEN-gated WE signal + logic mp_region_8_gated_we; + assign mp_region_8_gated_we = mp_region_8_we & region_cfg_regwen_8_qs; + // F[base_8]: 11:0 + prim_subreg #( + .DW (12), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (12'h0), + .Mubi (1'b0) + ) u_mp_region_8_base_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_8_gated_we), + .wd (mp_region_8_base_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region[8].base.q), + .ds (), + + // to register interface (read) + .qs (mp_region_8_base_8_qs) + ); + + // F[size_8]: 23:12 + prim_subreg #( + .DW (12), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (12'h0), + .Mubi (1'b0) + ) u_mp_region_8_size_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_8_gated_we), + .wd (mp_region_8_size_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region[8].size.q), + .ds (), + + // to register interface (read) + .qs (mp_region_8_size_8_qs) + ); + + + // Subregister 9 of Multireg mp_region + // R[mp_region_9]: V(False) + // Create REGWEN-gated WE signal + logic mp_region_9_gated_we; + assign mp_region_9_gated_we = mp_region_9_we & region_cfg_regwen_9_qs; + // F[base_9]: 11:0 + prim_subreg #( + .DW (12), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (12'h0), + .Mubi (1'b0) + ) u_mp_region_9_base_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_9_gated_we), + .wd (mp_region_9_base_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region[9].base.q), + .ds (), + + // to register interface (read) + .qs (mp_region_9_base_9_qs) + ); + + // F[size_9]: 23:12 + prim_subreg #( + .DW (12), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (12'h0), + .Mubi (1'b0) + ) u_mp_region_9_size_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mp_region_9_gated_we), + .wd (mp_region_9_size_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mp_region[9].size.q), + .ds (), + + // to register interface (read) + .qs (mp_region_9_size_9_qs) + ); + + // R[default_region]: V(False) // F[rd_en]: 3:0 prim_subreg #( @@ -6121,7 +6619,7 @@ module rram_ctrl_core_reg_top ( - logic [64:0] addr_hit; + logic [70:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RRAM_CTRL_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == RRAM_CTRL_INTR_ENABLE_OFFSET); @@ -6141,53 +6639,59 @@ module rram_ctrl_core_reg_top ( addr_hit[15] = (reg_addr == RRAM_CTRL_REGION_CFG_REGWEN_5_OFFSET); addr_hit[16] = (reg_addr == RRAM_CTRL_REGION_CFG_REGWEN_6_OFFSET); addr_hit[17] = (reg_addr == RRAM_CTRL_REGION_CFG_REGWEN_7_OFFSET); - addr_hit[18] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_0_OFFSET); - addr_hit[19] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_1_OFFSET); - addr_hit[20] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_2_OFFSET); - addr_hit[21] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_3_OFFSET); - addr_hit[22] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_4_OFFSET); - addr_hit[23] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_5_OFFSET); - addr_hit[24] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_6_OFFSET); - addr_hit[25] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_7_OFFSET); - addr_hit[26] = (reg_addr == RRAM_CTRL_MP_REGION_0_OFFSET); - addr_hit[27] = (reg_addr == RRAM_CTRL_MP_REGION_1_OFFSET); - addr_hit[28] = (reg_addr == RRAM_CTRL_MP_REGION_2_OFFSET); - addr_hit[29] = (reg_addr == RRAM_CTRL_MP_REGION_3_OFFSET); - addr_hit[30] = (reg_addr == RRAM_CTRL_MP_REGION_4_OFFSET); - addr_hit[31] = (reg_addr == RRAM_CTRL_MP_REGION_5_OFFSET); - addr_hit[32] = (reg_addr == RRAM_CTRL_MP_REGION_6_OFFSET); - addr_hit[33] = (reg_addr == RRAM_CTRL_MP_REGION_7_OFFSET); - addr_hit[34] = (reg_addr == RRAM_CTRL_DEFAULT_REGION_OFFSET); - addr_hit[35] = (reg_addr == RRAM_CTRL_INFO_REGWEN_0_OFFSET); - addr_hit[36] = (reg_addr == RRAM_CTRL_INFO_REGWEN_1_OFFSET); - addr_hit[37] = (reg_addr == RRAM_CTRL_INFO_REGWEN_2_OFFSET); - addr_hit[38] = (reg_addr == RRAM_CTRL_INFO_REGWEN_3_OFFSET); - addr_hit[39] = (reg_addr == RRAM_CTRL_INFO_REGWEN_4_OFFSET); - addr_hit[40] = (reg_addr == RRAM_CTRL_INFO_REGWEN_5_OFFSET); - addr_hit[41] = (reg_addr == RRAM_CTRL_INFO_REGWEN_6_OFFSET); - addr_hit[42] = (reg_addr == RRAM_CTRL_INFO_REGWEN_7_OFFSET); - addr_hit[43] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_0_OFFSET); - addr_hit[44] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_1_OFFSET); - addr_hit[45] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_2_OFFSET); - addr_hit[46] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_3_OFFSET); - addr_hit[47] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_4_OFFSET); - addr_hit[48] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_5_OFFSET); - addr_hit[49] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_6_OFFSET); - addr_hit[50] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_7_OFFSET); - addr_hit[51] = (reg_addr == RRAM_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET); - addr_hit[52] = (reg_addr == RRAM_CTRL_OP_STATUS_OFFSET); - addr_hit[53] = (reg_addr == RRAM_CTRL_STATUS_OFFSET); - addr_hit[54] = (reg_addr == RRAM_CTRL_ERR_CODE_OFFSET); - addr_hit[55] = (reg_addr == RRAM_CTRL_STD_FAULT_STATUS_OFFSET); - addr_hit[56] = (reg_addr == RRAM_CTRL_FAULT_STATUS_OFFSET); - addr_hit[57] = (reg_addr == RRAM_CTRL_ERR_ADDR_OFFSET); - addr_hit[58] = (reg_addr == RRAM_CTRL_CORR_ERR_CNT_OFFSET); - addr_hit[59] = (reg_addr == RRAM_CTRL_CORR_ERR_LOC_OFFSET); - addr_hit[60] = (reg_addr == RRAM_CTRL_PHY_STATUS_OFFSET); - addr_hit[61] = (reg_addr == RRAM_CTRL_SCRATCH_OFFSET); - addr_hit[62] = (reg_addr == RRAM_CTRL_FIFO_LVL_OFFSET); - addr_hit[63] = (reg_addr == RRAM_CTRL_FIFO_CLR_OFFSET); - addr_hit[64] = (reg_addr == RRAM_CTRL_CURR_FIFO_LVL_OFFSET); + addr_hit[18] = (reg_addr == RRAM_CTRL_REGION_CFG_REGWEN_8_OFFSET); + addr_hit[19] = (reg_addr == RRAM_CTRL_REGION_CFG_REGWEN_9_OFFSET); + addr_hit[20] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_0_OFFSET); + addr_hit[21] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_1_OFFSET); + addr_hit[22] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_2_OFFSET); + addr_hit[23] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_3_OFFSET); + addr_hit[24] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_4_OFFSET); + addr_hit[25] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_5_OFFSET); + addr_hit[26] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_6_OFFSET); + addr_hit[27] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_7_OFFSET); + addr_hit[28] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_8_OFFSET); + addr_hit[29] = (reg_addr == RRAM_CTRL_MP_REGION_CFG_9_OFFSET); + addr_hit[30] = (reg_addr == RRAM_CTRL_MP_REGION_0_OFFSET); + addr_hit[31] = (reg_addr == RRAM_CTRL_MP_REGION_1_OFFSET); + addr_hit[32] = (reg_addr == RRAM_CTRL_MP_REGION_2_OFFSET); + addr_hit[33] = (reg_addr == RRAM_CTRL_MP_REGION_3_OFFSET); + addr_hit[34] = (reg_addr == RRAM_CTRL_MP_REGION_4_OFFSET); + addr_hit[35] = (reg_addr == RRAM_CTRL_MP_REGION_5_OFFSET); + addr_hit[36] = (reg_addr == RRAM_CTRL_MP_REGION_6_OFFSET); + addr_hit[37] = (reg_addr == RRAM_CTRL_MP_REGION_7_OFFSET); + addr_hit[38] = (reg_addr == RRAM_CTRL_MP_REGION_8_OFFSET); + addr_hit[39] = (reg_addr == RRAM_CTRL_MP_REGION_9_OFFSET); + addr_hit[40] = (reg_addr == RRAM_CTRL_DEFAULT_REGION_OFFSET); + addr_hit[41] = (reg_addr == RRAM_CTRL_INFO_REGWEN_0_OFFSET); + addr_hit[42] = (reg_addr == RRAM_CTRL_INFO_REGWEN_1_OFFSET); + addr_hit[43] = (reg_addr == RRAM_CTRL_INFO_REGWEN_2_OFFSET); + addr_hit[44] = (reg_addr == RRAM_CTRL_INFO_REGWEN_3_OFFSET); + addr_hit[45] = (reg_addr == RRAM_CTRL_INFO_REGWEN_4_OFFSET); + addr_hit[46] = (reg_addr == RRAM_CTRL_INFO_REGWEN_5_OFFSET); + addr_hit[47] = (reg_addr == RRAM_CTRL_INFO_REGWEN_6_OFFSET); + addr_hit[48] = (reg_addr == RRAM_CTRL_INFO_REGWEN_7_OFFSET); + addr_hit[49] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_0_OFFSET); + addr_hit[50] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_1_OFFSET); + addr_hit[51] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_2_OFFSET); + addr_hit[52] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_3_OFFSET); + addr_hit[53] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_4_OFFSET); + addr_hit[54] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_5_OFFSET); + addr_hit[55] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_6_OFFSET); + addr_hit[56] = (reg_addr == RRAM_CTRL_INFO_PAGE_CFG_7_OFFSET); + addr_hit[57] = (reg_addr == RRAM_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET); + addr_hit[58] = (reg_addr == RRAM_CTRL_OP_STATUS_OFFSET); + addr_hit[59] = (reg_addr == RRAM_CTRL_STATUS_OFFSET); + addr_hit[60] = (reg_addr == RRAM_CTRL_ERR_CODE_OFFSET); + addr_hit[61] = (reg_addr == RRAM_CTRL_STD_FAULT_STATUS_OFFSET); + addr_hit[62] = (reg_addr == RRAM_CTRL_FAULT_STATUS_OFFSET); + addr_hit[63] = (reg_addr == RRAM_CTRL_ERR_ADDR_OFFSET); + addr_hit[64] = (reg_addr == RRAM_CTRL_CORR_ERR_CNT_OFFSET); + addr_hit[65] = (reg_addr == RRAM_CTRL_CORR_ERR_LOC_OFFSET); + addr_hit[66] = (reg_addr == RRAM_CTRL_PHY_STATUS_OFFSET); + addr_hit[67] = (reg_addr == RRAM_CTRL_SCRATCH_OFFSET); + addr_hit[68] = (reg_addr == RRAM_CTRL_FIFO_LVL_OFFSET); + addr_hit[69] = (reg_addr == RRAM_CTRL_FIFO_CLR_OFFSET); + addr_hit[70] = (reg_addr == RRAM_CTRL_CURR_FIFO_LVL_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -6259,7 +6763,13 @@ module rram_ctrl_core_reg_top ( (addr_hit[61] & (|(RRAM_CTRL_CORE_PERMIT[61] & ~reg_be))) | (addr_hit[62] & (|(RRAM_CTRL_CORE_PERMIT[62] & ~reg_be))) | (addr_hit[63] & (|(RRAM_CTRL_CORE_PERMIT[63] & ~reg_be))) | - (addr_hit[64] & (|(RRAM_CTRL_CORE_PERMIT[64] & ~reg_be))))); + (addr_hit[64] & (|(RRAM_CTRL_CORE_PERMIT[64] & ~reg_be))) | + (addr_hit[65] & (|(RRAM_CTRL_CORE_PERMIT[65] & ~reg_be))) | + (addr_hit[66] & (|(RRAM_CTRL_CORE_PERMIT[66] & ~reg_be))) | + (addr_hit[67] & (|(RRAM_CTRL_CORE_PERMIT[67] & ~reg_be))) | + (addr_hit[68] & (|(RRAM_CTRL_CORE_PERMIT[68] & ~reg_be))) | + (addr_hit[69] & (|(RRAM_CTRL_CORE_PERMIT[69] & ~reg_be))) | + (addr_hit[70] & (|(RRAM_CTRL_CORE_PERMIT[70] & ~reg_be))))); end // Generate write-enables @@ -6353,7 +6863,13 @@ module rram_ctrl_core_reg_top ( assign region_cfg_regwen_7_we = addr_hit[17] & reg_we & !reg_error; assign region_cfg_regwen_7_wd = reg_wdata[0]; - assign mp_region_cfg_0_we = addr_hit[18] & reg_we & !reg_error; + assign region_cfg_regwen_8_we = addr_hit[18] & reg_we & !reg_error; + + assign region_cfg_regwen_8_wd = reg_wdata[0]; + assign region_cfg_regwen_9_we = addr_hit[19] & reg_we & !reg_error; + + assign region_cfg_regwen_9_wd = reg_wdata[0]; + assign mp_region_cfg_0_we = addr_hit[20] & reg_we & !reg_error; assign mp_region_cfg_0_en_0_wd = reg_wdata[3:0]; @@ -6364,7 +6880,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[15:12]; assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[19:16]; - assign mp_region_cfg_1_we = addr_hit[19] & reg_we & !reg_error; + assign mp_region_cfg_1_we = addr_hit[21] & reg_we & !reg_error; assign mp_region_cfg_1_en_1_wd = reg_wdata[3:0]; @@ -6375,7 +6891,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[15:12]; assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[19:16]; - assign mp_region_cfg_2_we = addr_hit[20] & reg_we & !reg_error; + assign mp_region_cfg_2_we = addr_hit[22] & reg_we & !reg_error; assign mp_region_cfg_2_en_2_wd = reg_wdata[3:0]; @@ -6386,7 +6902,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[15:12]; assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[19:16]; - assign mp_region_cfg_3_we = addr_hit[21] & reg_we & !reg_error; + assign mp_region_cfg_3_we = addr_hit[23] & reg_we & !reg_error; assign mp_region_cfg_3_en_3_wd = reg_wdata[3:0]; @@ -6397,7 +6913,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[15:12]; assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[19:16]; - assign mp_region_cfg_4_we = addr_hit[22] & reg_we & !reg_error; + assign mp_region_cfg_4_we = addr_hit[24] & reg_we & !reg_error; assign mp_region_cfg_4_en_4_wd = reg_wdata[3:0]; @@ -6408,7 +6924,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[15:12]; assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[19:16]; - assign mp_region_cfg_5_we = addr_hit[23] & reg_we & !reg_error; + assign mp_region_cfg_5_we = addr_hit[25] & reg_we & !reg_error; assign mp_region_cfg_5_en_5_wd = reg_wdata[3:0]; @@ -6419,7 +6935,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[15:12]; assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[19:16]; - assign mp_region_cfg_6_we = addr_hit[24] & reg_we & !reg_error; + assign mp_region_cfg_6_we = addr_hit[26] & reg_we & !reg_error; assign mp_region_cfg_6_en_6_wd = reg_wdata[3:0]; @@ -6430,7 +6946,7 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[15:12]; assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[19:16]; - assign mp_region_cfg_7_we = addr_hit[25] & reg_we & !reg_error; + assign mp_region_cfg_7_we = addr_hit[27] & reg_we & !reg_error; assign mp_region_cfg_7_en_7_wd = reg_wdata[3:0]; @@ -6441,47 +6957,79 @@ module rram_ctrl_core_reg_top ( assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[15:12]; assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[19:16]; - assign mp_region_0_we = addr_hit[26] & reg_we & !reg_error; + assign mp_region_cfg_8_we = addr_hit[28] & reg_we & !reg_error; + + assign mp_region_cfg_8_en_8_wd = reg_wdata[3:0]; + + assign mp_region_cfg_8_rd_en_8_wd = reg_wdata[7:4]; + + assign mp_region_cfg_8_wr_en_8_wd = reg_wdata[11:8]; + + assign mp_region_cfg_8_scramble_en_8_wd = reg_wdata[15:12]; + + assign mp_region_cfg_8_ecc_en_8_wd = reg_wdata[19:16]; + assign mp_region_cfg_9_we = addr_hit[29] & reg_we & !reg_error; + + assign mp_region_cfg_9_en_9_wd = reg_wdata[3:0]; + + assign mp_region_cfg_9_rd_en_9_wd = reg_wdata[7:4]; + + assign mp_region_cfg_9_wr_en_9_wd = reg_wdata[11:8]; + + assign mp_region_cfg_9_scramble_en_9_wd = reg_wdata[15:12]; + + assign mp_region_cfg_9_ecc_en_9_wd = reg_wdata[19:16]; + assign mp_region_0_we = addr_hit[30] & reg_we & !reg_error; assign mp_region_0_base_0_wd = reg_wdata[11:0]; assign mp_region_0_size_0_wd = reg_wdata[23:12]; - assign mp_region_1_we = addr_hit[27] & reg_we & !reg_error; + assign mp_region_1_we = addr_hit[31] & reg_we & !reg_error; assign mp_region_1_base_1_wd = reg_wdata[11:0]; assign mp_region_1_size_1_wd = reg_wdata[23:12]; - assign mp_region_2_we = addr_hit[28] & reg_we & !reg_error; + assign mp_region_2_we = addr_hit[32] & reg_we & !reg_error; assign mp_region_2_base_2_wd = reg_wdata[11:0]; assign mp_region_2_size_2_wd = reg_wdata[23:12]; - assign mp_region_3_we = addr_hit[29] & reg_we & !reg_error; + assign mp_region_3_we = addr_hit[33] & reg_we & !reg_error; assign mp_region_3_base_3_wd = reg_wdata[11:0]; assign mp_region_3_size_3_wd = reg_wdata[23:12]; - assign mp_region_4_we = addr_hit[30] & reg_we & !reg_error; + assign mp_region_4_we = addr_hit[34] & reg_we & !reg_error; assign mp_region_4_base_4_wd = reg_wdata[11:0]; assign mp_region_4_size_4_wd = reg_wdata[23:12]; - assign mp_region_5_we = addr_hit[31] & reg_we & !reg_error; + assign mp_region_5_we = addr_hit[35] & reg_we & !reg_error; assign mp_region_5_base_5_wd = reg_wdata[11:0]; assign mp_region_5_size_5_wd = reg_wdata[23:12]; - assign mp_region_6_we = addr_hit[32] & reg_we & !reg_error; + assign mp_region_6_we = addr_hit[36] & reg_we & !reg_error; assign mp_region_6_base_6_wd = reg_wdata[11:0]; assign mp_region_6_size_6_wd = reg_wdata[23:12]; - assign mp_region_7_we = addr_hit[33] & reg_we & !reg_error; + assign mp_region_7_we = addr_hit[37] & reg_we & !reg_error; assign mp_region_7_base_7_wd = reg_wdata[11:0]; assign mp_region_7_size_7_wd = reg_wdata[23:12]; - assign default_region_we = addr_hit[34] & reg_we & !reg_error; + assign mp_region_8_we = addr_hit[38] & reg_we & !reg_error; + + assign mp_region_8_base_8_wd = reg_wdata[11:0]; + + assign mp_region_8_size_8_wd = reg_wdata[23:12]; + assign mp_region_9_we = addr_hit[39] & reg_we & !reg_error; + + assign mp_region_9_base_9_wd = reg_wdata[11:0]; + + assign mp_region_9_size_9_wd = reg_wdata[23:12]; + assign default_region_we = addr_hit[40] & reg_we & !reg_error; assign default_region_rd_en_wd = reg_wdata[3:0]; @@ -6490,31 +7038,31 @@ module rram_ctrl_core_reg_top ( assign default_region_scramble_en_wd = reg_wdata[11:8]; assign default_region_ecc_en_wd = reg_wdata[15:12]; - assign info_regwen_0_we = addr_hit[35] & reg_we & !reg_error; + assign info_regwen_0_we = addr_hit[41] & reg_we & !reg_error; assign info_regwen_0_wd = reg_wdata[0]; - assign info_regwen_1_we = addr_hit[36] & reg_we & !reg_error; + assign info_regwen_1_we = addr_hit[42] & reg_we & !reg_error; assign info_regwen_1_wd = reg_wdata[0]; - assign info_regwen_2_we = addr_hit[37] & reg_we & !reg_error; + assign info_regwen_2_we = addr_hit[43] & reg_we & !reg_error; assign info_regwen_2_wd = reg_wdata[0]; - assign info_regwen_3_we = addr_hit[38] & reg_we & !reg_error; + assign info_regwen_3_we = addr_hit[44] & reg_we & !reg_error; assign info_regwen_3_wd = reg_wdata[0]; - assign info_regwen_4_we = addr_hit[39] & reg_we & !reg_error; + assign info_regwen_4_we = addr_hit[45] & reg_we & !reg_error; assign info_regwen_4_wd = reg_wdata[0]; - assign info_regwen_5_we = addr_hit[40] & reg_we & !reg_error; + assign info_regwen_5_we = addr_hit[46] & reg_we & !reg_error; assign info_regwen_5_wd = reg_wdata[0]; - assign info_regwen_6_we = addr_hit[41] & reg_we & !reg_error; + assign info_regwen_6_we = addr_hit[47] & reg_we & !reg_error; assign info_regwen_6_wd = reg_wdata[0]; - assign info_regwen_7_we = addr_hit[42] & reg_we & !reg_error; + assign info_regwen_7_we = addr_hit[48] & reg_we & !reg_error; assign info_regwen_7_wd = reg_wdata[0]; - assign info_page_cfg_0_we = addr_hit[43] & reg_we & !reg_error; + assign info_page_cfg_0_we = addr_hit[49] & reg_we & !reg_error; assign info_page_cfg_0_en_0_wd = reg_wdata[3:0]; @@ -6525,7 +7073,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_0_scramble_en_0_wd = reg_wdata[15:12]; assign info_page_cfg_0_ecc_en_0_wd = reg_wdata[19:16]; - assign info_page_cfg_1_we = addr_hit[44] & reg_we & !reg_error; + assign info_page_cfg_1_we = addr_hit[50] & reg_we & !reg_error; assign info_page_cfg_1_en_1_wd = reg_wdata[3:0]; @@ -6536,7 +7084,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_1_scramble_en_1_wd = reg_wdata[15:12]; assign info_page_cfg_1_ecc_en_1_wd = reg_wdata[19:16]; - assign info_page_cfg_2_we = addr_hit[45] & reg_we & !reg_error; + assign info_page_cfg_2_we = addr_hit[51] & reg_we & !reg_error; assign info_page_cfg_2_en_2_wd = reg_wdata[3:0]; @@ -6547,7 +7095,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_2_scramble_en_2_wd = reg_wdata[15:12]; assign info_page_cfg_2_ecc_en_2_wd = reg_wdata[19:16]; - assign info_page_cfg_3_we = addr_hit[46] & reg_we & !reg_error; + assign info_page_cfg_3_we = addr_hit[52] & reg_we & !reg_error; assign info_page_cfg_3_en_3_wd = reg_wdata[3:0]; @@ -6558,7 +7106,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_3_scramble_en_3_wd = reg_wdata[15:12]; assign info_page_cfg_3_ecc_en_3_wd = reg_wdata[19:16]; - assign info_page_cfg_4_we = addr_hit[47] & reg_we & !reg_error; + assign info_page_cfg_4_we = addr_hit[53] & reg_we & !reg_error; assign info_page_cfg_4_en_4_wd = reg_wdata[3:0]; @@ -6569,7 +7117,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_4_scramble_en_4_wd = reg_wdata[15:12]; assign info_page_cfg_4_ecc_en_4_wd = reg_wdata[19:16]; - assign info_page_cfg_5_we = addr_hit[48] & reg_we & !reg_error; + assign info_page_cfg_5_we = addr_hit[54] & reg_we & !reg_error; assign info_page_cfg_5_en_5_wd = reg_wdata[3:0]; @@ -6580,7 +7128,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_5_scramble_en_5_wd = reg_wdata[15:12]; assign info_page_cfg_5_ecc_en_5_wd = reg_wdata[19:16]; - assign info_page_cfg_6_we = addr_hit[49] & reg_we & !reg_error; + assign info_page_cfg_6_we = addr_hit[55] & reg_we & !reg_error; assign info_page_cfg_6_en_6_wd = reg_wdata[3:0]; @@ -6591,7 +7139,7 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_6_scramble_en_6_wd = reg_wdata[15:12]; assign info_page_cfg_6_ecc_en_6_wd = reg_wdata[19:16]; - assign info_page_cfg_7_we = addr_hit[50] & reg_we & !reg_error; + assign info_page_cfg_7_we = addr_hit[56] & reg_we & !reg_error; assign info_page_cfg_7_en_7_wd = reg_wdata[3:0]; @@ -6602,17 +7150,17 @@ module rram_ctrl_core_reg_top ( assign info_page_cfg_7_scramble_en_7_wd = reg_wdata[15:12]; assign info_page_cfg_7_ecc_en_7_wd = reg_wdata[19:16]; - assign hw_info_cfg_override_we = addr_hit[51] & reg_we & !reg_error; + assign hw_info_cfg_override_we = addr_hit[57] & reg_we & !reg_error; assign hw_info_cfg_override_scramble_dis_wd = reg_wdata[3:0]; assign hw_info_cfg_override_ecc_dis_wd = reg_wdata[7:4]; - assign op_status_we = addr_hit[52] & reg_we & !reg_error; + assign op_status_we = addr_hit[58] & reg_we & !reg_error; assign op_status_done_wd = reg_wdata[0]; assign op_status_err_wd = reg_wdata[1]; - assign err_code_we = addr_hit[54] & reg_we & !reg_error; + assign err_code_we = addr_hit[60] & reg_we & !reg_error; assign err_code_op_err_wd = reg_wdata[0]; @@ -6621,26 +7169,26 @@ module rram_ctrl_core_reg_top ( assign err_code_rd_err_wd = reg_wdata[2]; assign err_code_wr_err_wd = reg_wdata[3]; - assign fault_status_we = addr_hit[56] & reg_we & !reg_error; + assign fault_status_we = addr_hit[62] & reg_we & !reg_error; assign fault_status_phy_relbl_err_wd = reg_wdata[9]; - assign corr_err_cnt_we = addr_hit[58] & reg_we & !reg_error; + assign corr_err_cnt_we = addr_hit[64] & reg_we & !reg_error; assign corr_err_cnt_wd = reg_wdata[7:0]; - assign scratch_we = addr_hit[61] & reg_we & !reg_error; + assign scratch_we = addr_hit[67] & reg_we & !reg_error; assign scratch_wd = reg_wdata[31:0]; - assign fifo_lvl_we = addr_hit[62] & reg_we & !reg_error; + assign fifo_lvl_we = addr_hit[68] & reg_we & !reg_error; assign fifo_lvl_wr_wd = reg_wdata[4:0]; assign fifo_lvl_rd_wd = reg_wdata[12:8]; - assign fifo_clr_we = addr_hit[63] & reg_we & !reg_error; + assign fifo_clr_we = addr_hit[69] & reg_we & !reg_error; assign fifo_clr_wr_wd = reg_wdata[0]; assign fifo_clr_rd_wd = reg_wdata[1]; - assign curr_fifo_lvl_re = addr_hit[64] & reg_re & !reg_error; + assign curr_fifo_lvl_re = addr_hit[70] & reg_re & !reg_error; // Assign write-enables to checker logic vector. always_comb begin @@ -6662,53 +7210,59 @@ module rram_ctrl_core_reg_top ( reg_we_check[15] = region_cfg_regwen_5_we; reg_we_check[16] = region_cfg_regwen_6_we; reg_we_check[17] = region_cfg_regwen_7_we; - reg_we_check[18] = mp_region_cfg_0_gated_we; - reg_we_check[19] = mp_region_cfg_1_gated_we; - reg_we_check[20] = mp_region_cfg_2_gated_we; - reg_we_check[21] = mp_region_cfg_3_gated_we; - reg_we_check[22] = mp_region_cfg_4_gated_we; - reg_we_check[23] = mp_region_cfg_5_gated_we; - reg_we_check[24] = mp_region_cfg_6_gated_we; - reg_we_check[25] = mp_region_cfg_7_gated_we; - reg_we_check[26] = mp_region_0_gated_we; - reg_we_check[27] = mp_region_1_gated_we; - reg_we_check[28] = mp_region_2_gated_we; - reg_we_check[29] = mp_region_3_gated_we; - reg_we_check[30] = mp_region_4_gated_we; - reg_we_check[31] = mp_region_5_gated_we; - reg_we_check[32] = mp_region_6_gated_we; - reg_we_check[33] = mp_region_7_gated_we; - reg_we_check[34] = default_region_we; - reg_we_check[35] = info_regwen_0_we; - reg_we_check[36] = info_regwen_1_we; - reg_we_check[37] = info_regwen_2_we; - reg_we_check[38] = info_regwen_3_we; - reg_we_check[39] = info_regwen_4_we; - reg_we_check[40] = info_regwen_5_we; - reg_we_check[41] = info_regwen_6_we; - reg_we_check[42] = info_regwen_7_we; - reg_we_check[43] = info_page_cfg_0_gated_we; - reg_we_check[44] = info_page_cfg_1_gated_we; - reg_we_check[45] = info_page_cfg_2_gated_we; - reg_we_check[46] = info_page_cfg_3_gated_we; - reg_we_check[47] = info_page_cfg_4_gated_we; - reg_we_check[48] = info_page_cfg_5_gated_we; - reg_we_check[49] = info_page_cfg_6_gated_we; - reg_we_check[50] = info_page_cfg_7_gated_we; - reg_we_check[51] = hw_info_cfg_override_we; - reg_we_check[52] = op_status_we; - reg_we_check[53] = 1'b0; - reg_we_check[54] = err_code_we; - reg_we_check[55] = 1'b0; - reg_we_check[56] = fault_status_we; - reg_we_check[57] = 1'b0; - reg_we_check[58] = corr_err_cnt_we; + reg_we_check[18] = region_cfg_regwen_8_we; + reg_we_check[19] = region_cfg_regwen_9_we; + reg_we_check[20] = mp_region_cfg_0_gated_we; + reg_we_check[21] = mp_region_cfg_1_gated_we; + reg_we_check[22] = mp_region_cfg_2_gated_we; + reg_we_check[23] = mp_region_cfg_3_gated_we; + reg_we_check[24] = mp_region_cfg_4_gated_we; + reg_we_check[25] = mp_region_cfg_5_gated_we; + reg_we_check[26] = mp_region_cfg_6_gated_we; + reg_we_check[27] = mp_region_cfg_7_gated_we; + reg_we_check[28] = mp_region_cfg_8_gated_we; + reg_we_check[29] = mp_region_cfg_9_gated_we; + reg_we_check[30] = mp_region_0_gated_we; + reg_we_check[31] = mp_region_1_gated_we; + reg_we_check[32] = mp_region_2_gated_we; + reg_we_check[33] = mp_region_3_gated_we; + reg_we_check[34] = mp_region_4_gated_we; + reg_we_check[35] = mp_region_5_gated_we; + reg_we_check[36] = mp_region_6_gated_we; + reg_we_check[37] = mp_region_7_gated_we; + reg_we_check[38] = mp_region_8_gated_we; + reg_we_check[39] = mp_region_9_gated_we; + reg_we_check[40] = default_region_we; + reg_we_check[41] = info_regwen_0_we; + reg_we_check[42] = info_regwen_1_we; + reg_we_check[43] = info_regwen_2_we; + reg_we_check[44] = info_regwen_3_we; + reg_we_check[45] = info_regwen_4_we; + reg_we_check[46] = info_regwen_5_we; + reg_we_check[47] = info_regwen_6_we; + reg_we_check[48] = info_regwen_7_we; + reg_we_check[49] = info_page_cfg_0_gated_we; + reg_we_check[50] = info_page_cfg_1_gated_we; + reg_we_check[51] = info_page_cfg_2_gated_we; + reg_we_check[52] = info_page_cfg_3_gated_we; + reg_we_check[53] = info_page_cfg_4_gated_we; + reg_we_check[54] = info_page_cfg_5_gated_we; + reg_we_check[55] = info_page_cfg_6_gated_we; + reg_we_check[56] = info_page_cfg_7_gated_we; + reg_we_check[57] = hw_info_cfg_override_we; + reg_we_check[58] = op_status_we; reg_we_check[59] = 1'b0; - reg_we_check[60] = 1'b0; - reg_we_check[61] = scratch_we; - reg_we_check[62] = fifo_lvl_we; - reg_we_check[63] = fifo_clr_we; - reg_we_check[64] = 1'b0; + reg_we_check[60] = err_code_we; + reg_we_check[61] = 1'b0; + reg_we_check[62] = fault_status_we; + reg_we_check[63] = 1'b0; + reg_we_check[64] = corr_err_cnt_we; + reg_we_check[65] = 1'b0; + reg_we_check[66] = 1'b0; + reg_we_check[67] = scratch_we; + reg_we_check[68] = fifo_lvl_we; + reg_we_check[69] = fifo_clr_we; + reg_we_check[70] = 1'b0; end // Read data return @@ -6811,6 +7365,14 @@ module rram_ctrl_core_reg_top ( end addr_hit[18]: begin + reg_rdata_next[0] = region_cfg_regwen_8_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = region_cfg_regwen_9_qs; + end + + addr_hit[20]: begin reg_rdata_next[3:0] = mp_region_cfg_0_en_0_qs; reg_rdata_next[7:4] = mp_region_cfg_0_rd_en_0_qs; reg_rdata_next[11:8] = mp_region_cfg_0_wr_en_0_qs; @@ -6818,7 +7380,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_0_ecc_en_0_qs; end - addr_hit[19]: begin + addr_hit[21]: begin reg_rdata_next[3:0] = mp_region_cfg_1_en_1_qs; reg_rdata_next[7:4] = mp_region_cfg_1_rd_en_1_qs; reg_rdata_next[11:8] = mp_region_cfg_1_wr_en_1_qs; @@ -6826,7 +7388,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_1_ecc_en_1_qs; end - addr_hit[20]: begin + addr_hit[22]: begin reg_rdata_next[3:0] = mp_region_cfg_2_en_2_qs; reg_rdata_next[7:4] = mp_region_cfg_2_rd_en_2_qs; reg_rdata_next[11:8] = mp_region_cfg_2_wr_en_2_qs; @@ -6834,7 +7396,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_2_ecc_en_2_qs; end - addr_hit[21]: begin + addr_hit[23]: begin reg_rdata_next[3:0] = mp_region_cfg_3_en_3_qs; reg_rdata_next[7:4] = mp_region_cfg_3_rd_en_3_qs; reg_rdata_next[11:8] = mp_region_cfg_3_wr_en_3_qs; @@ -6842,7 +7404,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_3_ecc_en_3_qs; end - addr_hit[22]: begin + addr_hit[24]: begin reg_rdata_next[3:0] = mp_region_cfg_4_en_4_qs; reg_rdata_next[7:4] = mp_region_cfg_4_rd_en_4_qs; reg_rdata_next[11:8] = mp_region_cfg_4_wr_en_4_qs; @@ -6850,7 +7412,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_4_ecc_en_4_qs; end - addr_hit[23]: begin + addr_hit[25]: begin reg_rdata_next[3:0] = mp_region_cfg_5_en_5_qs; reg_rdata_next[7:4] = mp_region_cfg_5_rd_en_5_qs; reg_rdata_next[11:8] = mp_region_cfg_5_wr_en_5_qs; @@ -6858,7 +7420,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_5_ecc_en_5_qs; end - addr_hit[24]: begin + addr_hit[26]: begin reg_rdata_next[3:0] = mp_region_cfg_6_en_6_qs; reg_rdata_next[7:4] = mp_region_cfg_6_rd_en_6_qs; reg_rdata_next[11:8] = mp_region_cfg_6_wr_en_6_qs; @@ -6866,7 +7428,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_6_ecc_en_6_qs; end - addr_hit[25]: begin + addr_hit[27]: begin reg_rdata_next[3:0] = mp_region_cfg_7_en_7_qs; reg_rdata_next[7:4] = mp_region_cfg_7_rd_en_7_qs; reg_rdata_next[11:8] = mp_region_cfg_7_wr_en_7_qs; @@ -6874,86 +7436,112 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = mp_region_cfg_7_ecc_en_7_qs; end - addr_hit[26]: begin + addr_hit[28]: begin + reg_rdata_next[3:0] = mp_region_cfg_8_en_8_qs; + reg_rdata_next[7:4] = mp_region_cfg_8_rd_en_8_qs; + reg_rdata_next[11:8] = mp_region_cfg_8_wr_en_8_qs; + reg_rdata_next[15:12] = mp_region_cfg_8_scramble_en_8_qs; + reg_rdata_next[19:16] = mp_region_cfg_8_ecc_en_8_qs; + end + + addr_hit[29]: begin + reg_rdata_next[3:0] = mp_region_cfg_9_en_9_qs; + reg_rdata_next[7:4] = mp_region_cfg_9_rd_en_9_qs; + reg_rdata_next[11:8] = mp_region_cfg_9_wr_en_9_qs; + reg_rdata_next[15:12] = mp_region_cfg_9_scramble_en_9_qs; + reg_rdata_next[19:16] = mp_region_cfg_9_ecc_en_9_qs; + end + + addr_hit[30]: begin reg_rdata_next[11:0] = mp_region_0_base_0_qs; reg_rdata_next[23:12] = mp_region_0_size_0_qs; end - addr_hit[27]: begin + addr_hit[31]: begin reg_rdata_next[11:0] = mp_region_1_base_1_qs; reg_rdata_next[23:12] = mp_region_1_size_1_qs; end - addr_hit[28]: begin + addr_hit[32]: begin reg_rdata_next[11:0] = mp_region_2_base_2_qs; reg_rdata_next[23:12] = mp_region_2_size_2_qs; end - addr_hit[29]: begin + addr_hit[33]: begin reg_rdata_next[11:0] = mp_region_3_base_3_qs; reg_rdata_next[23:12] = mp_region_3_size_3_qs; end - addr_hit[30]: begin + addr_hit[34]: begin reg_rdata_next[11:0] = mp_region_4_base_4_qs; reg_rdata_next[23:12] = mp_region_4_size_4_qs; end - addr_hit[31]: begin + addr_hit[35]: begin reg_rdata_next[11:0] = mp_region_5_base_5_qs; reg_rdata_next[23:12] = mp_region_5_size_5_qs; end - addr_hit[32]: begin + addr_hit[36]: begin reg_rdata_next[11:0] = mp_region_6_base_6_qs; reg_rdata_next[23:12] = mp_region_6_size_6_qs; end - addr_hit[33]: begin + addr_hit[37]: begin reg_rdata_next[11:0] = mp_region_7_base_7_qs; reg_rdata_next[23:12] = mp_region_7_size_7_qs; end - addr_hit[34]: begin + addr_hit[38]: begin + reg_rdata_next[11:0] = mp_region_8_base_8_qs; + reg_rdata_next[23:12] = mp_region_8_size_8_qs; + end + + addr_hit[39]: begin + reg_rdata_next[11:0] = mp_region_9_base_9_qs; + reg_rdata_next[23:12] = mp_region_9_size_9_qs; + end + + addr_hit[40]: begin reg_rdata_next[3:0] = default_region_rd_en_qs; reg_rdata_next[7:4] = default_region_wr_en_qs; reg_rdata_next[11:8] = default_region_scramble_en_qs; reg_rdata_next[15:12] = default_region_ecc_en_qs; end - addr_hit[35]: begin + addr_hit[41]: begin reg_rdata_next[0] = info_regwen_0_qs; end - addr_hit[36]: begin + addr_hit[42]: begin reg_rdata_next[0] = info_regwen_1_qs; end - addr_hit[37]: begin + addr_hit[43]: begin reg_rdata_next[0] = info_regwen_2_qs; end - addr_hit[38]: begin + addr_hit[44]: begin reg_rdata_next[0] = info_regwen_3_qs; end - addr_hit[39]: begin + addr_hit[45]: begin reg_rdata_next[0] = info_regwen_4_qs; end - addr_hit[40]: begin + addr_hit[46]: begin reg_rdata_next[0] = info_regwen_5_qs; end - addr_hit[41]: begin + addr_hit[47]: begin reg_rdata_next[0] = info_regwen_6_qs; end - addr_hit[42]: begin + addr_hit[48]: begin reg_rdata_next[0] = info_regwen_7_qs; end - addr_hit[43]: begin + addr_hit[49]: begin reg_rdata_next[3:0] = info_page_cfg_0_en_0_qs; reg_rdata_next[7:4] = info_page_cfg_0_rd_en_0_qs; reg_rdata_next[11:8] = info_page_cfg_0_wr_en_0_qs; @@ -6961,7 +7549,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_0_ecc_en_0_qs; end - addr_hit[44]: begin + addr_hit[50]: begin reg_rdata_next[3:0] = info_page_cfg_1_en_1_qs; reg_rdata_next[7:4] = info_page_cfg_1_rd_en_1_qs; reg_rdata_next[11:8] = info_page_cfg_1_wr_en_1_qs; @@ -6969,7 +7557,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_1_ecc_en_1_qs; end - addr_hit[45]: begin + addr_hit[51]: begin reg_rdata_next[3:0] = info_page_cfg_2_en_2_qs; reg_rdata_next[7:4] = info_page_cfg_2_rd_en_2_qs; reg_rdata_next[11:8] = info_page_cfg_2_wr_en_2_qs; @@ -6977,7 +7565,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_2_ecc_en_2_qs; end - addr_hit[46]: begin + addr_hit[52]: begin reg_rdata_next[3:0] = info_page_cfg_3_en_3_qs; reg_rdata_next[7:4] = info_page_cfg_3_rd_en_3_qs; reg_rdata_next[11:8] = info_page_cfg_3_wr_en_3_qs; @@ -6985,7 +7573,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_3_ecc_en_3_qs; end - addr_hit[47]: begin + addr_hit[53]: begin reg_rdata_next[3:0] = info_page_cfg_4_en_4_qs; reg_rdata_next[7:4] = info_page_cfg_4_rd_en_4_qs; reg_rdata_next[11:8] = info_page_cfg_4_wr_en_4_qs; @@ -6993,7 +7581,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_4_ecc_en_4_qs; end - addr_hit[48]: begin + addr_hit[54]: begin reg_rdata_next[3:0] = info_page_cfg_5_en_5_qs; reg_rdata_next[7:4] = info_page_cfg_5_rd_en_5_qs; reg_rdata_next[11:8] = info_page_cfg_5_wr_en_5_qs; @@ -7001,7 +7589,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_5_ecc_en_5_qs; end - addr_hit[49]: begin + addr_hit[55]: begin reg_rdata_next[3:0] = info_page_cfg_6_en_6_qs; reg_rdata_next[7:4] = info_page_cfg_6_rd_en_6_qs; reg_rdata_next[11:8] = info_page_cfg_6_wr_en_6_qs; @@ -7009,7 +7597,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_6_ecc_en_6_qs; end - addr_hit[50]: begin + addr_hit[56]: begin reg_rdata_next[3:0] = info_page_cfg_7_en_7_qs; reg_rdata_next[7:4] = info_page_cfg_7_rd_en_7_qs; reg_rdata_next[11:8] = info_page_cfg_7_wr_en_7_qs; @@ -7017,17 +7605,17 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[19:16] = info_page_cfg_7_ecc_en_7_qs; end - addr_hit[51]: begin + addr_hit[57]: begin reg_rdata_next[3:0] = hw_info_cfg_override_scramble_dis_qs; reg_rdata_next[7:4] = hw_info_cfg_override_ecc_dis_qs; end - addr_hit[52]: begin + addr_hit[58]: begin reg_rdata_next[0] = op_status_done_qs; reg_rdata_next[1] = op_status_err_qs; end - addr_hit[53]: begin + addr_hit[59]: begin reg_rdata_next[0] = status_rd_full_qs; reg_rdata_next[1] = status_rd_empty_qs; reg_rdata_next[2] = status_wr_full_qs; @@ -7036,14 +7624,14 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[5] = status_keys_valid_qs; end - addr_hit[54]: begin + addr_hit[60]: begin reg_rdata_next[0] = err_code_op_err_qs; reg_rdata_next[1] = err_code_mp_err_qs; reg_rdata_next[2] = err_code_rd_err_qs; reg_rdata_next[3] = err_code_wr_err_qs; end - addr_hit[55]: begin + addr_hit[61]: begin reg_rdata_next[0] = std_fault_status_reg_intg_err_qs; reg_rdata_next[1] = std_fault_status_lcmgr_err_qs; reg_rdata_next[2] = std_fault_status_lcmgr_intg_err_qs; @@ -7059,7 +7647,7 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[12] = std_fault_status_ctrl_fifo_err_qs; end - addr_hit[56]: begin + addr_hit[62]: begin reg_rdata_next[0] = fault_status_lcmgr_op_err_qs; reg_rdata_next[1] = fault_status_lcmgr_mp_err_qs; reg_rdata_next[2] = fault_status_lcmgr_rd_err_qs; @@ -7076,39 +7664,39 @@ module rram_ctrl_core_reg_top ( reg_rdata_next[13] = fault_status_host_gnt_err_qs; end - addr_hit[57]: begin + addr_hit[63]: begin reg_rdata_next[20:0] = err_addr_qs; end - addr_hit[58]: begin + addr_hit[64]: begin reg_rdata_next[7:0] = corr_err_cnt_qs; end - addr_hit[59]: begin + addr_hit[65]: begin reg_rdata_next[20:0] = corr_err_loc_addr_qs; reg_rdata_next[24] = corr_err_loc_part_qs; end - addr_hit[60]: begin + addr_hit[66]: begin reg_rdata_next[0] = phy_status_wr_busy_qs; reg_rdata_next[1] = phy_status_init_done_qs; end - addr_hit[61]: begin + addr_hit[67]: begin reg_rdata_next[31:0] = scratch_qs; end - addr_hit[62]: begin + addr_hit[68]: begin reg_rdata_next[4:0] = fifo_lvl_wr_qs; reg_rdata_next[12:8] = fifo_lvl_rd_qs; end - addr_hit[63]: begin + addr_hit[69]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; end - addr_hit[64]: begin + addr_hit[70]: begin reg_rdata_next[4:0] = curr_fifo_lvl_wr_qs; reg_rdata_next[12:8] = curr_fifo_lvl_rd_qs; end diff --git a/hw/ip/rram_ctrl/rtl/rram_ctrl_pkg.sv b/hw/ip/rram_ctrl/rtl/rram_ctrl_pkg.sv index fa166e877d53d..3894945813a95 100644 --- a/hw/ip/rram_ctrl/rtl/rram_ctrl_pkg.sv +++ b/hw/ip/rram_ctrl/rtl/rram_ctrl_pkg.sv @@ -27,7 +27,7 @@ package rram_ctrl_pkg; parameter int unsigned BusIntgWidth = tlul_pkg::DataIntgWidth; parameter int unsigned BusFullWidth = BusWidth + BusIntgWidth; - parameter int unsigned MpRegions = 8; // controller protection regions + parameter int unsigned MpRegions = 10; // controller protection regions parameter int unsigned TotalMpRegions = MpRegions + 2; // + default region and init region // RRAM phy parameters diff --git a/hw/ip/rram_ctrl/rtl/rram_ctrl_reg_pkg.sv b/hw/ip/rram_ctrl/rtl/rram_ctrl_reg_pkg.sv index 3e79bf0fbd021..f43299a0e3851 100644 --- a/hw/ip/rram_ctrl/rtl/rram_ctrl_reg_pkg.sv +++ b/hw/ip/rram_ctrl/rtl/rram_ctrl_reg_pkg.sv @@ -8,7 +8,7 @@ package rram_ctrl_reg_pkg; // Param list parameter int unsigned ExecEn = 32'ha26a38f7; - parameter int NumRegions = 8; + parameter int NumRegions = 10; parameter int NumInfoPages = 8; parameter int NumDataPages = 4096; parameter int WordsPerPage = 32; @@ -20,7 +20,7 @@ package rram_ctrl_reg_pkg; parameter int CoreAw = 9; // Number of registers for every interface - parameter int NumRegsCore = 65; + parameter int NumRegsCore = 71; // Alert indices typedef enum int { @@ -599,17 +599,17 @@ package rram_ctrl_reg_pkg; // Register -> HW type for core interface typedef struct packed { - rram_ctrl_reg2hw_intr_state_reg_t intr_state; // [726:721] - rram_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [720:715] - rram_ctrl_reg2hw_intr_test_reg_t intr_test; // [714:703] - rram_ctrl_reg2hw_alert_test_reg_t alert_test; // [702:693] - rram_ctrl_reg2hw_dis_reg_t dis; // [692:685] - rram_ctrl_reg2hw_exec_reg_t exec; // [684:653] - rram_ctrl_reg2hw_init_reg_t init; // [652:652] - rram_ctrl_reg2hw_control_reg_t control; // [651:638] - rram_ctrl_reg2hw_addr_reg_t addr; // [637:617] - rram_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [616:457] - rram_ctrl_reg2hw_mp_region_mreg_t [7:0] mp_region; // [456:265] + rram_ctrl_reg2hw_intr_state_reg_t intr_state; // [814:809] + rram_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [808:803] + rram_ctrl_reg2hw_intr_test_reg_t intr_test; // [802:791] + rram_ctrl_reg2hw_alert_test_reg_t alert_test; // [790:781] + rram_ctrl_reg2hw_dis_reg_t dis; // [780:773] + rram_ctrl_reg2hw_exec_reg_t exec; // [772:741] + rram_ctrl_reg2hw_init_reg_t init; // [740:740] + rram_ctrl_reg2hw_control_reg_t control; // [739:726] + rram_ctrl_reg2hw_addr_reg_t addr; // [725:705] + rram_ctrl_reg2hw_mp_region_cfg_mreg_t [9:0] mp_region_cfg; // [704:505] + rram_ctrl_reg2hw_mp_region_mreg_t [9:0] mp_region; // [504:265] rram_ctrl_reg2hw_default_region_reg_t default_region; // [264:249] rram_ctrl_reg2hw_info_page_cfg_mreg_t [7:0] info_page_cfg; // [248:89] rram_ctrl_reg2hw_hw_info_cfg_override_reg_t hw_info_cfg_override; // [88:81] @@ -657,53 +657,59 @@ package rram_ctrl_reg_pkg; parameter logic [CoreAw-1:0] RRAM_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 3c; parameter logic [CoreAw-1:0] RRAM_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 40; parameter logic [CoreAw-1:0] RRAM_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 44; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 48; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 4c; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 50; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 54; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 58; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 5c; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 60; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 64; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_0_OFFSET = 9'h 68; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_1_OFFSET = 9'h 6c; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_2_OFFSET = 9'h 70; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_3_OFFSET = 9'h 74; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_4_OFFSET = 9'h 78; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_5_OFFSET = 9'h 7c; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_6_OFFSET = 9'h 80; - parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_7_OFFSET = 9'h 84; - parameter logic [CoreAw-1:0] RRAM_CTRL_DEFAULT_REGION_OFFSET = 9'h 88; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_0_OFFSET = 9'h 8c; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_1_OFFSET = 9'h 90; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_2_OFFSET = 9'h 94; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_3_OFFSET = 9'h 98; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_4_OFFSET = 9'h 9c; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_5_OFFSET = 9'h a0; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_6_OFFSET = 9'h a4; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_7_OFFSET = 9'h a8; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_0_OFFSET = 9'h ac; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_1_OFFSET = 9'h b0; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_2_OFFSET = 9'h b4; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_3_OFFSET = 9'h b8; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_4_OFFSET = 9'h bc; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_5_OFFSET = 9'h c0; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_6_OFFSET = 9'h c4; - parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_7_OFFSET = 9'h c8; - parameter logic [CoreAw-1:0] RRAM_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET = 9'h cc; - parameter logic [CoreAw-1:0] RRAM_CTRL_OP_STATUS_OFFSET = 9'h d0; - parameter logic [CoreAw-1:0] RRAM_CTRL_STATUS_OFFSET = 9'h d4; - parameter logic [CoreAw-1:0] RRAM_CTRL_ERR_CODE_OFFSET = 9'h d8; - parameter logic [CoreAw-1:0] RRAM_CTRL_STD_FAULT_STATUS_OFFSET = 9'h dc; - parameter logic [CoreAw-1:0] RRAM_CTRL_FAULT_STATUS_OFFSET = 9'h e0; - parameter logic [CoreAw-1:0] RRAM_CTRL_ERR_ADDR_OFFSET = 9'h e4; - parameter logic [CoreAw-1:0] RRAM_CTRL_CORR_ERR_CNT_OFFSET = 9'h e8; - parameter logic [CoreAw-1:0] RRAM_CTRL_CORR_ERR_LOC_OFFSET = 9'h ec; - parameter logic [CoreAw-1:0] RRAM_CTRL_PHY_STATUS_OFFSET = 9'h f0; - parameter logic [CoreAw-1:0] RRAM_CTRL_SCRATCH_OFFSET = 9'h f4; - parameter logic [CoreAw-1:0] RRAM_CTRL_FIFO_LVL_OFFSET = 9'h f8; - parameter logic [CoreAw-1:0] RRAM_CTRL_FIFO_CLR_OFFSET = 9'h fc; - parameter logic [CoreAw-1:0] RRAM_CTRL_CURR_FIFO_LVL_OFFSET = 9'h 100; + parameter logic [CoreAw-1:0] RRAM_CTRL_REGION_CFG_REGWEN_8_OFFSET = 9'h 48; + parameter logic [CoreAw-1:0] RRAM_CTRL_REGION_CFG_REGWEN_9_OFFSET = 9'h 4c; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 50; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 54; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 58; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 5c; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 60; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 64; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 68; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 6c; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_8_OFFSET = 9'h 70; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_CFG_9_OFFSET = 9'h 74; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_0_OFFSET = 9'h 78; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_1_OFFSET = 9'h 7c; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_2_OFFSET = 9'h 80; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_3_OFFSET = 9'h 84; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_4_OFFSET = 9'h 88; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_5_OFFSET = 9'h 8c; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_6_OFFSET = 9'h 90; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_7_OFFSET = 9'h 94; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_8_OFFSET = 9'h 98; + parameter logic [CoreAw-1:0] RRAM_CTRL_MP_REGION_9_OFFSET = 9'h 9c; + parameter logic [CoreAw-1:0] RRAM_CTRL_DEFAULT_REGION_OFFSET = 9'h a0; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_0_OFFSET = 9'h a4; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_1_OFFSET = 9'h a8; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_2_OFFSET = 9'h ac; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_3_OFFSET = 9'h b0; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_4_OFFSET = 9'h b4; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_5_OFFSET = 9'h b8; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_6_OFFSET = 9'h bc; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_REGWEN_7_OFFSET = 9'h c0; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_0_OFFSET = 9'h c4; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_1_OFFSET = 9'h c8; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_2_OFFSET = 9'h cc; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_3_OFFSET = 9'h d0; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_4_OFFSET = 9'h d4; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_5_OFFSET = 9'h d8; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_6_OFFSET = 9'h dc; + parameter logic [CoreAw-1:0] RRAM_CTRL_INFO_PAGE_CFG_7_OFFSET = 9'h e0; + parameter logic [CoreAw-1:0] RRAM_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET = 9'h e4; + parameter logic [CoreAw-1:0] RRAM_CTRL_OP_STATUS_OFFSET = 9'h e8; + parameter logic [CoreAw-1:0] RRAM_CTRL_STATUS_OFFSET = 9'h ec; + parameter logic [CoreAw-1:0] RRAM_CTRL_ERR_CODE_OFFSET = 9'h f0; + parameter logic [CoreAw-1:0] RRAM_CTRL_STD_FAULT_STATUS_OFFSET = 9'h f4; + parameter logic [CoreAw-1:0] RRAM_CTRL_FAULT_STATUS_OFFSET = 9'h f8; + parameter logic [CoreAw-1:0] RRAM_CTRL_ERR_ADDR_OFFSET = 9'h fc; + parameter logic [CoreAw-1:0] RRAM_CTRL_CORR_ERR_CNT_OFFSET = 9'h 100; + parameter logic [CoreAw-1:0] RRAM_CTRL_CORR_ERR_LOC_OFFSET = 9'h 104; + parameter logic [CoreAw-1:0] RRAM_CTRL_PHY_STATUS_OFFSET = 9'h 108; + parameter logic [CoreAw-1:0] RRAM_CTRL_SCRATCH_OFFSET = 9'h 10c; + parameter logic [CoreAw-1:0] RRAM_CTRL_FIFO_LVL_OFFSET = 9'h 110; + parameter logic [CoreAw-1:0] RRAM_CTRL_FIFO_CLR_OFFSET = 9'h 114; + parameter logic [CoreAw-1:0] RRAM_CTRL_CURR_FIFO_LVL_OFFSET = 9'h 118; // Reset values for hwext registers and their fields for core interface parameter logic [5:0] RRAM_CTRL_INTR_TEST_RESVAL = 6'h 0; @@ -729,10 +735,10 @@ package rram_ctrl_reg_pkg; parameter logic [4:0] RRAM_CTRL_CURR_FIFO_LVL_RD_RESVAL = 5'h 0; // Window parameters for core interface - parameter logic [CoreAw-1:0] RRAM_CTRL_WR_FIFO_OFFSET = 9'h 104; + parameter logic [CoreAw-1:0] RRAM_CTRL_WR_FIFO_OFFSET = 9'h 11c; parameter int unsigned RRAM_CTRL_WR_FIFO_SIZE = 'h 4; parameter int unsigned RRAM_CTRL_WR_FIFO_IDX = 0; - parameter logic [CoreAw-1:0] RRAM_CTRL_RD_FIFO_OFFSET = 9'h 108; + parameter logic [CoreAw-1:0] RRAM_CTRL_RD_FIFO_OFFSET = 9'h 120; parameter int unsigned RRAM_CTRL_RD_FIFO_SIZE = 'h 4; parameter int unsigned RRAM_CTRL_RD_FIFO_IDX = 1; @@ -756,6 +762,8 @@ package rram_ctrl_reg_pkg; RRAM_CTRL_REGION_CFG_REGWEN_5, RRAM_CTRL_REGION_CFG_REGWEN_6, RRAM_CTRL_REGION_CFG_REGWEN_7, + RRAM_CTRL_REGION_CFG_REGWEN_8, + RRAM_CTRL_REGION_CFG_REGWEN_9, RRAM_CTRL_MP_REGION_CFG_0, RRAM_CTRL_MP_REGION_CFG_1, RRAM_CTRL_MP_REGION_CFG_2, @@ -764,6 +772,8 @@ package rram_ctrl_reg_pkg; RRAM_CTRL_MP_REGION_CFG_5, RRAM_CTRL_MP_REGION_CFG_6, RRAM_CTRL_MP_REGION_CFG_7, + RRAM_CTRL_MP_REGION_CFG_8, + RRAM_CTRL_MP_REGION_CFG_9, RRAM_CTRL_MP_REGION_0, RRAM_CTRL_MP_REGION_1, RRAM_CTRL_MP_REGION_2, @@ -772,6 +782,8 @@ package rram_ctrl_reg_pkg; RRAM_CTRL_MP_REGION_5, RRAM_CTRL_MP_REGION_6, RRAM_CTRL_MP_REGION_7, + RRAM_CTRL_MP_REGION_8, + RRAM_CTRL_MP_REGION_9, RRAM_CTRL_DEFAULT_REGION, RRAM_CTRL_INFO_REGWEN_0, RRAM_CTRL_INFO_REGWEN_1, @@ -806,7 +818,7 @@ package rram_ctrl_reg_pkg; } rram_ctrl_core_id_e; // Register width information to check illegal writes for core interface - parameter logic [3:0] RRAM_CTRL_CORE_PERMIT [65] = '{ + parameter logic [3:0] RRAM_CTRL_CORE_PERMIT [71] = '{ 4'b 0001, // index[ 0] RRAM_CTRL_INTR_STATE 4'b 0001, // index[ 1] RRAM_CTRL_INTR_ENABLE 4'b 0001, // index[ 2] RRAM_CTRL_INTR_TEST @@ -825,53 +837,59 @@ package rram_ctrl_reg_pkg; 4'b 0001, // index[15] RRAM_CTRL_REGION_CFG_REGWEN_5 4'b 0001, // index[16] RRAM_CTRL_REGION_CFG_REGWEN_6 4'b 0001, // index[17] RRAM_CTRL_REGION_CFG_REGWEN_7 - 4'b 0111, // index[18] RRAM_CTRL_MP_REGION_CFG_0 - 4'b 0111, // index[19] RRAM_CTRL_MP_REGION_CFG_1 - 4'b 0111, // index[20] RRAM_CTRL_MP_REGION_CFG_2 - 4'b 0111, // index[21] RRAM_CTRL_MP_REGION_CFG_3 - 4'b 0111, // index[22] RRAM_CTRL_MP_REGION_CFG_4 - 4'b 0111, // index[23] RRAM_CTRL_MP_REGION_CFG_5 - 4'b 0111, // index[24] RRAM_CTRL_MP_REGION_CFG_6 - 4'b 0111, // index[25] RRAM_CTRL_MP_REGION_CFG_7 - 4'b 0111, // index[26] RRAM_CTRL_MP_REGION_0 - 4'b 0111, // index[27] RRAM_CTRL_MP_REGION_1 - 4'b 0111, // index[28] RRAM_CTRL_MP_REGION_2 - 4'b 0111, // index[29] RRAM_CTRL_MP_REGION_3 - 4'b 0111, // index[30] RRAM_CTRL_MP_REGION_4 - 4'b 0111, // index[31] RRAM_CTRL_MP_REGION_5 - 4'b 0111, // index[32] RRAM_CTRL_MP_REGION_6 - 4'b 0111, // index[33] RRAM_CTRL_MP_REGION_7 - 4'b 0011, // index[34] RRAM_CTRL_DEFAULT_REGION - 4'b 0001, // index[35] RRAM_CTRL_INFO_REGWEN_0 - 4'b 0001, // index[36] RRAM_CTRL_INFO_REGWEN_1 - 4'b 0001, // index[37] RRAM_CTRL_INFO_REGWEN_2 - 4'b 0001, // index[38] RRAM_CTRL_INFO_REGWEN_3 - 4'b 0001, // index[39] RRAM_CTRL_INFO_REGWEN_4 - 4'b 0001, // index[40] RRAM_CTRL_INFO_REGWEN_5 - 4'b 0001, // index[41] RRAM_CTRL_INFO_REGWEN_6 - 4'b 0001, // index[42] RRAM_CTRL_INFO_REGWEN_7 - 4'b 0111, // index[43] RRAM_CTRL_INFO_PAGE_CFG_0 - 4'b 0111, // index[44] RRAM_CTRL_INFO_PAGE_CFG_1 - 4'b 0111, // index[45] RRAM_CTRL_INFO_PAGE_CFG_2 - 4'b 0111, // index[46] RRAM_CTRL_INFO_PAGE_CFG_3 - 4'b 0111, // index[47] RRAM_CTRL_INFO_PAGE_CFG_4 - 4'b 0111, // index[48] RRAM_CTRL_INFO_PAGE_CFG_5 - 4'b 0111, // index[49] RRAM_CTRL_INFO_PAGE_CFG_6 - 4'b 0111, // index[50] RRAM_CTRL_INFO_PAGE_CFG_7 - 4'b 0001, // index[51] RRAM_CTRL_HW_INFO_CFG_OVERRIDE - 4'b 0001, // index[52] RRAM_CTRL_OP_STATUS - 4'b 0001, // index[53] RRAM_CTRL_STATUS - 4'b 0001, // index[54] RRAM_CTRL_ERR_CODE - 4'b 0011, // index[55] RRAM_CTRL_STD_FAULT_STATUS - 4'b 0011, // index[56] RRAM_CTRL_FAULT_STATUS - 4'b 0111, // index[57] RRAM_CTRL_ERR_ADDR - 4'b 0001, // index[58] RRAM_CTRL_CORR_ERR_CNT - 4'b 1111, // index[59] RRAM_CTRL_CORR_ERR_LOC - 4'b 0001, // index[60] RRAM_CTRL_PHY_STATUS - 4'b 1111, // index[61] RRAM_CTRL_SCRATCH - 4'b 0011, // index[62] RRAM_CTRL_FIFO_LVL - 4'b 0001, // index[63] RRAM_CTRL_FIFO_CLR - 4'b 0011 // index[64] RRAM_CTRL_CURR_FIFO_LVL + 4'b 0001, // index[18] RRAM_CTRL_REGION_CFG_REGWEN_8 + 4'b 0001, // index[19] RRAM_CTRL_REGION_CFG_REGWEN_9 + 4'b 0111, // index[20] RRAM_CTRL_MP_REGION_CFG_0 + 4'b 0111, // index[21] RRAM_CTRL_MP_REGION_CFG_1 + 4'b 0111, // index[22] RRAM_CTRL_MP_REGION_CFG_2 + 4'b 0111, // index[23] RRAM_CTRL_MP_REGION_CFG_3 + 4'b 0111, // index[24] RRAM_CTRL_MP_REGION_CFG_4 + 4'b 0111, // index[25] RRAM_CTRL_MP_REGION_CFG_5 + 4'b 0111, // index[26] RRAM_CTRL_MP_REGION_CFG_6 + 4'b 0111, // index[27] RRAM_CTRL_MP_REGION_CFG_7 + 4'b 0111, // index[28] RRAM_CTRL_MP_REGION_CFG_8 + 4'b 0111, // index[29] RRAM_CTRL_MP_REGION_CFG_9 + 4'b 0111, // index[30] RRAM_CTRL_MP_REGION_0 + 4'b 0111, // index[31] RRAM_CTRL_MP_REGION_1 + 4'b 0111, // index[32] RRAM_CTRL_MP_REGION_2 + 4'b 0111, // index[33] RRAM_CTRL_MP_REGION_3 + 4'b 0111, // index[34] RRAM_CTRL_MP_REGION_4 + 4'b 0111, // index[35] RRAM_CTRL_MP_REGION_5 + 4'b 0111, // index[36] RRAM_CTRL_MP_REGION_6 + 4'b 0111, // index[37] RRAM_CTRL_MP_REGION_7 + 4'b 0111, // index[38] RRAM_CTRL_MP_REGION_8 + 4'b 0111, // index[39] RRAM_CTRL_MP_REGION_9 + 4'b 0011, // index[40] RRAM_CTRL_DEFAULT_REGION + 4'b 0001, // index[41] RRAM_CTRL_INFO_REGWEN_0 + 4'b 0001, // index[42] RRAM_CTRL_INFO_REGWEN_1 + 4'b 0001, // index[43] RRAM_CTRL_INFO_REGWEN_2 + 4'b 0001, // index[44] RRAM_CTRL_INFO_REGWEN_3 + 4'b 0001, // index[45] RRAM_CTRL_INFO_REGWEN_4 + 4'b 0001, // index[46] RRAM_CTRL_INFO_REGWEN_5 + 4'b 0001, // index[47] RRAM_CTRL_INFO_REGWEN_6 + 4'b 0001, // index[48] RRAM_CTRL_INFO_REGWEN_7 + 4'b 0111, // index[49] RRAM_CTRL_INFO_PAGE_CFG_0 + 4'b 0111, // index[50] RRAM_CTRL_INFO_PAGE_CFG_1 + 4'b 0111, // index[51] RRAM_CTRL_INFO_PAGE_CFG_2 + 4'b 0111, // index[52] RRAM_CTRL_INFO_PAGE_CFG_3 + 4'b 0111, // index[53] RRAM_CTRL_INFO_PAGE_CFG_4 + 4'b 0111, // index[54] RRAM_CTRL_INFO_PAGE_CFG_5 + 4'b 0111, // index[55] RRAM_CTRL_INFO_PAGE_CFG_6 + 4'b 0111, // index[56] RRAM_CTRL_INFO_PAGE_CFG_7 + 4'b 0001, // index[57] RRAM_CTRL_HW_INFO_CFG_OVERRIDE + 4'b 0001, // index[58] RRAM_CTRL_OP_STATUS + 4'b 0001, // index[59] RRAM_CTRL_STATUS + 4'b 0001, // index[60] RRAM_CTRL_ERR_CODE + 4'b 0011, // index[61] RRAM_CTRL_STD_FAULT_STATUS + 4'b 0011, // index[62] RRAM_CTRL_FAULT_STATUS + 4'b 0111, // index[63] RRAM_CTRL_ERR_ADDR + 4'b 0001, // index[64] RRAM_CTRL_CORR_ERR_CNT + 4'b 1111, // index[65] RRAM_CTRL_CORR_ERR_LOC + 4'b 0001, // index[66] RRAM_CTRL_PHY_STATUS + 4'b 1111, // index[67] RRAM_CTRL_SCRATCH + 4'b 0011, // index[68] RRAM_CTRL_FIFO_LVL + 4'b 0001, // index[69] RRAM_CTRL_FIFO_CLR + 4'b 0011 // index[70] RRAM_CTRL_CURR_FIFO_LVL }; endpackage From 2f34516cc9fd39ece28a6f04f5ec376d695ad48a Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 17:25:33 +0200 Subject: [PATCH 36/41] [rram_ctrl,nvm_ctrl,sw] dedicate MP region 8 to emulated info pages kRramCtrlEmulRegion (the shared region backing the 14 emulated info pages: OwnerSlot0/1, DiceCerts, BootData0/1, ...) previously reused region 7, one of owner_block's configurable slots, as a stopgap. Now that rram_ctrl has 10 regions, give it a real, non-conflicting index (8) instead. nvm_ctrl_init() now actually configures this region, which it previously left unconfigured. nvm_testutils.c has its own parallel implementation of the same emulated-page mechanism (kRramRelocatedRegion, same page range) with the identical latent collision at region 0; fixed the same way for consistency, even though no current caller exercises that path. Signed-off-by: Michael Gautschi --- sw/device/lib/testing/nvm_testutils.c | 15 +++++++++++---- .../silicon_creator/lib/drivers/rram_ctrl.h | 13 ++++++++++++- sw/device/silicon_creator/lib/nvm_ctrl.c | 16 ++++++++++++++++ 3 files changed, 39 insertions(+), 5 deletions(-) diff --git a/sw/device/lib/testing/nvm_testutils.c b/sw/device/lib/testing/nvm_testutils.c index a71798cf5f462..b4e92ecc1b7e8 100644 --- a/sw/device/lib/testing/nvm_testutils.c +++ b/sw/device/lib/testing/nvm_testutils.c @@ -62,12 +62,19 @@ typedef struct { // a single memory-protection region (`kRramRelocatedRegion`), covering // `kRramRelocatedPageCount` reserved data pages starting at // `kRramEmulPageBase`, with read and write always enabled and never -// locked — RRAM only has 8 configurable data regions, fewer than the 14 -// relocated pages, so there is no room for per-page permissions yet. Giving -// relocated pages (or groups of them) their own protection will require +// locked — there is no room for per-page permissions yet. Giving relocated +// pages (or groups of them) their own protection will require further // hardware changes to add more data regions. enum { - kRramRelocatedRegion = 0, + // Must match `kRramCtrlEmulRegion` (rram_ctrl.h): this is the same + // shared emulated-page region (same `kRramEmulPageBase`/count), just + // reached through this separate testutils driver path instead of + // `nvm_ctrl`/`rram_ctrl`. Cannot be 0 or 1 for the same reason given + // there: `rom_ext_nvm_protect_self()` (rom_ext.c) unconditionally + // reconfigures those two regions for ROM_EXT's own code range before any + // owner code (including FT personalize, which runs as an owner-slot + // image after a real ROM_EXT boot) gets to run. + kRramRelocatedRegion = 8, // First data-partition page reserved for relocated pages. kPageMap's // `page_id` values for `emul` = 1 entries are absolute data-partition page // indices already offset by this base. diff --git a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h index 95f05c536b787..a498bb0c7bbeb 100644 --- a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h +++ b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h @@ -63,8 +63,19 @@ enum { /** * Memory-protection region index (of `RRAM_CTRL_PARAM_NUM_REGIONS`) used * for the shared emulated-page region. + * + * Cannot be 0 or 1: `rom_ext_nvm_protect_self()` (rom_ext.c) unconditionally + * reconfigures those two regions for ROM_EXT's own code range, before + * `ownership_init()` ever runs -- confirmed by observing `OwnerSlot0`/ + * `OwnerSlot1` writes still fail with `kErrorRramCtrlDataWrite` even after + * this region is granted read/write access at region 0 during + * `nvm_ctrl_init()`. Regions 2-7 are claimed on demand by owner-configurable + * BL0 slot regions (`owner_block.c`'s `kRomExtRegions + mp_index`, up to 6 + * of them). `RRAM_CTRL_PARAM_NUM_REGIONS` was grown from 8 to 10 to give + * the emulated-page region its own dedicated index (8) without stealing + * from that owner-configurable range; region 9 remains spare. */ - kRramCtrlEmulRegion = 0, + kRramCtrlEmulRegion = 8, }; /** diff --git a/sw/device/silicon_creator/lib/nvm_ctrl.c b/sw/device/silicon_creator/lib/nvm_ctrl.c index aa08b22ea2553..785d661aecd24 100644 --- a/sw/device/silicon_creator/lib/nvm_ctrl.c +++ b/sw/device/silicon_creator/lib/nvm_ctrl.c @@ -270,6 +270,22 @@ void nvm_ctrl_init(void) { .read = kMultiBitBool4True, .write = kMultiBitBool4False, }); + // Emulated info pages (e.g. OwnerSlot0/1, DiceCerts, BootData0/1) don't + // get individual permissions like real info pages; they all share this one + // memory-protection region instead. Grant it read/write access so they can + // be written during boot. + rram_ctrl_data_region_protect( + kRramCtrlEmulRegion, kRramCtrlEmulPageBase, kRramCtrlEmulPageCount, + (rram_ctrl_perms_t){ + .read = kMultiBitBool4True, + .write = kMultiBitBool4True, + }, + rram_ctrl_data_default_cfg_get(), kHardenedBoolFalse); + // Unlocked, `rram_ctrl_data_region_protect()` performs 2 sec_mmio-tracked + // writes (MP_REGION_${region} and MP_REGION_CFG_${region}), not the 1 + // implied by `kRramCtrlSecMmioDataRegionProtect` -- that constant appears + // to under-count by one; using the literal here instead of relying on it. + SEC_MMIO_WRITE_INCREMENT(2); } void nvm_ctrl_disable(void) { rram_ctrl_disable(); } From 0e446f446049d8cd770b6e791d3326b11261f2bf Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Tue, 28 Jul 2026 17:25:33 +0200 Subject: [PATCH 37/41] [nvm_ctrl,sw] use nvm_ctrl for ROM_EXT manifest addressing and attestation seed reads Replace remaining direct TOP_EARLGREY_FLASH_CTRL_* address/size references with the tech-agnostic nvm_ctrl.h equivalents (NVM_DATA_BASE_ADDR, NVM_DATA_SIZE_BYTES) in ROM_EXT manifest lookup and boot policy pointer code, and switch otbn_boot_attestation_keygen_seed() to nvm_ctrl_info_read_zeros_on_read_error(). Signed-off-by: Michael Gautschi --- .../sw/device/silicon_creator/BUILD | 3 +- .../silicon_creator/lib/otbn_boot_services.c | 30 +++++-------------- sw/device/silicon_creator/lib/BUILD | 5 +++- sw/device/silicon_creator/lib/manifest.c | 4 +-- .../manuf/base/ft_personalize.c | 5 ++-- sw/device/silicon_creator/rom_ext/BUILD | 8 +++-- .../rom_ext/e2e/ownership/flash_contents.c | 8 ++--- .../silicon_creator/rom_ext/e2e/rescue/BUILD | 1 + .../rom_ext/e2e/verified_boot/boot_test.c | 9 ++---- .../rom_ext/rom_ext_boot_policy_ptrs.h | 23 +++++++------- .../rom_ext/rom_ext_manifest.c | 11 ++++--- 11 files changed, 46 insertions(+), 61 deletions(-) diff --git a/hw/top_earlgrey/sw/device/silicon_creator/BUILD b/hw/top_earlgrey/sw/device/silicon_creator/BUILD index c3242567e33e4..61c7904a1d9fb 100644 --- a/hw/top_earlgrey/sw/device/silicon_creator/BUILD +++ b/hw/top_earlgrey/sw/device/silicon_creator/BUILD @@ -14,10 +14,9 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ "//sw/device/lib/base:macros", - "//sw/device/lib/base:memory", "//sw/device/silicon_creator/lib:attestation", "//sw/device/silicon_creator/lib:dbg_print", "//sw/device/silicon_creator/lib:error", - "//sw/device/silicon_creator/lib/drivers:flash_ctrl", + "//sw/device/silicon_creator/lib:nvm_ctrl", ], ) diff --git a/hw/top_earlgrey/sw/device/silicon_creator/lib/otbn_boot_services.c b/hw/top_earlgrey/sw/device/silicon_creator/lib/otbn_boot_services.c index cea972a8a9acc..646cf2d214ccd 100644 --- a/hw/top_earlgrey/sw/device/silicon_creator/lib/otbn_boot_services.c +++ b/hw/top_earlgrey/sw/device/silicon_creator/lib/otbn_boot_services.c @@ -3,31 +3,17 @@ // SPDX-License-Identifier: Apache-2.0 #include "sw/device/lib/base/macros.h" -#include "sw/device/lib/base/memory.h" #include "sw/device/silicon_creator/lib/attestation.h" -#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" OT_WARN_UNUSED_RESULT rom_error_t otbn_boot_attestation_keygen_seed(uint32_t seed_idx, uint32_t *seed) { - // Read seed from flash info page. - uint32_t seed_flash_offset = 0 + (seed_idx * kAttestationSeedBytes); - rom_error_t err = - flash_ctrl_info_read(&kFlashCtrlInfoPageAttestationKeySeeds, - seed_flash_offset, kAttestationSeedWords, seed); - - if (err != kErrorOk) { - flash_ctrl_error_code_t flash_ctrl_err_code; - flash_ctrl_error_code_get(&flash_ctrl_err_code); - if (flash_ctrl_err_code.rd_err) { - // If we encountered a read error, this means the attestation seed page - // has not been provisioned yet. In this case, we clear the seed and - // continue, which will simply result in generating an invalid identity. - memset(seed, 0, kAttestationSeedBytes); - return kErrorOk; - } - return err; - } - - return kErrorOk; + // Read seed from the attestation key seeds info page. If the page has not + // been provisioned yet, this returns all-zero words, which will simply + // result in generating an invalid identity. + uint32_t seed_offset = 0 + (seed_idx * kAttestationSeedBytes); + return nvm_ctrl_info_read_zeros_on_read_error(kNvmInfoPageAttestationKeySeeds, + seed_offset, + kAttestationSeedWords, seed); } diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index bac2f8f4a4ea2..4dd52d7c1d018 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -307,7 +307,10 @@ dual_cc_library( deps = dual_inputs( device = [ "//hw/top:top_lib", - ], + ] + opentitan_select_top( + {"earlgrey": [":nvm_ctrl"]}, + [], + ), host = [ "//sw/device/lib/base:global_mock", "//sw/device/silicon_creator/testing:rom_test", diff --git a/sw/device/silicon_creator/lib/manifest.c b/sw/device/silicon_creator/lib/manifest.c index b451e29a712af..e78c178c79a3e 100644 --- a/sw/device/silicon_creator/lib/manifest.c +++ b/sw/device/silicon_creator/lib/manifest.c @@ -10,8 +10,8 @@ #include "hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h" #define EFLASH_SIZE_BYES TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES #elif defined(OPENTITAN_IS_EARLGREY) -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" -#define EFLASH_SIZE_BYES TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" +#define EFLASH_SIZE_BYES NVM_DATA_SIZE_BYTES #elif defined(OPENTITAN_IS_DARJEELING) #include "hw/top_darjeeling/sw/autogen/top_darjeeling.h" #define EFLASH_SIZE_BYES TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES diff --git a/sw/device/silicon_creator/manuf/base/ft_personalize.c b/sw/device/silicon_creator/manuf/base/ft_personalize.c index 317168e8ec307..7d35adae048ea 100644 --- a/sw/device/silicon_creator/manuf/base/ft_personalize.c +++ b/sw/device/silicon_creator/manuf/base/ft_personalize.c @@ -219,15 +219,14 @@ static status_t log_self_hash(perso_blob_t *perso_blob_to_host) { * Return a pointer to the ROM_EXT manifest located in the slot a. */ static const manifest_t *rom_ext_manifest_a_get(void) { - return (const manifest_t *)TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + return (const manifest_t *)NVM_DATA_BASE_ADDR; } /* * Return a pointer to the ROM_EXT manifest located in the slot b. */ static const manifest_t *rom_ext_manifest_b_get(void) { - return (const manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - (TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2)); + return (const manifest_t *)(NVM_DATA_BASE_ADDR + (NVM_DATA_SIZE_BYTES / 2)); } extern const uint32_t kCreatorSwCfgManufStateValue; diff --git a/sw/device/silicon_creator/rom_ext/BUILD b/sw/device/silicon_creator/rom_ext/BUILD index d82b635b33ae7..ad64bb94e1b8d 100644 --- a/sw/device/silicon_creator/rom_ext/BUILD +++ b/sw/device/silicon_creator/rom_ext/BUILD @@ -5,6 +5,7 @@ load("@rules_pkg//pkg:mappings.bzl", "pkg_filegroup", "pkg_files") load("//rules:files.bzl", "output_groups") load("//rules:const.bzl", "CONST", "hex") +load("//hw/top:defs.bzl", "opentitan_select_top") load("//rules:cross_platform.bzl", "dual_cc_device_library_of", "dual_cc_library", "dual_inputs") load("//rules:linker.bzl", "ld_library") load("//rules:manifest.bzl", "manifest") @@ -64,9 +65,9 @@ cc_library( hdrs = ["rom_ext_manifest.h"], target_compatible_with = [OPENTITAN_CPU], deps = [ - "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:macros", "//sw/device/silicon_creator/lib:manifest", + "//sw/device/silicon_creator/lib:nvm_ctrl", ], ) @@ -80,6 +81,10 @@ dual_cc_library( shared = ["rom_ext_boot_policy_ptrs.h"], ), deps = dual_inputs( + device = opentitan_select_top( + {"earlgrey": ["//sw/device/silicon_creator/lib:nvm_ctrl"]}, + [], + ), host = [ "//sw/device/lib/base:global_mock", "//sw/device/silicon_creator/testing:rom_test", @@ -89,7 +94,6 @@ dual_cc_library( "//sw/device/silicon_creator/lib/base:chip", "//sw/device/lib/base:macros", "//sw/device/silicon_creator/lib:manifest", - "//hw/top_earlgrey/sw/autogen:top_earlgrey", ], ), ) diff --git a/sw/device/silicon_creator/rom_ext/e2e/ownership/flash_contents.c b/sw/device/silicon_creator/rom_ext/e2e/ownership/flash_contents.c index 1d97b13056db1..538322784c1fc 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/ownership/flash_contents.c +++ b/sw/device/silicon_creator/rom_ext/e2e/ownership/flash_contents.c @@ -9,16 +9,12 @@ #include "sw/device/silicon_creator/lib/drivers/retention_sram.h" #include "sw/device/silicon_creator/lib/nvm_ctrl.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" - OTTF_DEFINE_TEST_CONFIG(); status_t flash_contents_print(boot_log_t *boot_log) { TRY(boot_log_check(boot_log)); - uint32_t *data = (uint32_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - boot_log->rom_ext_size); - uint32_t *end = - (uint32_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + NVM_BYTES_PER_BANK); + uint32_t *data = (uint32_t *)(NVM_DATA_BASE_ADDR + boot_log->rom_ext_size); + uint32_t *end = (uint32_t *)(NVM_DATA_BASE_ADDR + NVM_BYTES_PER_BANK); uint32_t incr = NVM_BYTES_PER_PAGE / sizeof(uint32_t); for (; data < end; data += incr) { diff --git a/sw/device/silicon_creator/rom_ext/e2e/rescue/BUILD b/sw/device/silicon_creator/rom_ext/e2e/rescue/BUILD index 7d59d76414ef4..f7e242216b380 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/rescue/BUILD +++ b/sw/device/silicon_creator/rom_ext/e2e/rescue/BUILD @@ -95,6 +95,7 @@ _CONFIGS = { "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/silicon_creator/lib:boot_log", "//sw/device/silicon_creator/lib:manifest", + "//sw/device/silicon_creator/lib:nvm_ctrl", "//sw/device/silicon_creator/lib/drivers:retention_sram", ], ) diff --git a/sw/device/silicon_creator/rom_ext/e2e/verified_boot/boot_test.c b/sw/device/silicon_creator/rom_ext/e2e/verified_boot/boot_test.c index 3dbc2694d199e..7aabc550e9ad9 100644 --- a/sw/device/silicon_creator/rom_ext/e2e/verified_boot/boot_test.c +++ b/sw/device/silicon_creator/rom_ext/e2e/verified_boot/boot_test.c @@ -95,15 +95,12 @@ status_t keymgr_print(void) { return OK_STATUS(); } #ifdef WITH_MANIFEST #include "sw/device/silicon_creator/lib/manifest.h" - -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" status_t manifest_print(void) { - const manifest_t *a = - (const manifest_t *)TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR; + const manifest_t *a = (const manifest_t *)NVM_DATA_BASE_ADDR; const manifest_t *b = - (const manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - (TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2)); + (const manifest_t *)(NVM_DATA_BASE_ADDR + (NVM_DATA_SIZE_BYTES / 2)); LOG_INFO("slot_a rom_ext_id = %C", a->identifier); LOG_INFO("slot_a rom_ext_version = %u.%u", a->version_major, a->version_minor); diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_boot_policy_ptrs.h b/sw/device/silicon_creator/rom_ext/rom_ext_boot_policy_ptrs.h index 279c815428ea9..6cbe48b1f84e5 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_boot_policy_ptrs.h +++ b/sw/device/silicon_creator/rom_ext/rom_ext_boot_policy_ptrs.h @@ -9,40 +9,41 @@ #include "sw/device/silicon_creator/lib/base/chip.h" #include "sw/device/silicon_creator/lib/manifest.h" -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" - #ifdef __cplusplus extern "C" { #endif // __cplusplus -static_assert((TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES % 2) == 0, - "Flash size is not divisible by 2"); - #ifdef OT_PLATFORM_RV32 +// Only needed by the inline definitions below: the host/mock build compiles +// this header too (via mock_rom_ext_boot_policy_ptrs.cc), but only declares +// the plain function prototypes in the #else branch, so it must not require +// nvm_ctrl.h (which isn't a host dependency, and isn't buildable for every +// top -- see nvm_ctrl.h/rram_ctrl.h). +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" + +static_assert((NVM_DATA_SIZE_BYTES % 2) == 0, "NVM size is not divisible by 2"); /** * Returns a pointer to the manifest of the first owner boot stage image stored - * in flash slot A. + * in NVM slot A. * * @return Pointer to the manifest of the first owner boot stage image in slot * A. */ OT_WARN_UNUSED_RESULT inline const manifest_t *rom_ext_boot_policy_manifest_a_get(void) { - return (const manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - CHIP_ROM_EXT_SIZE_MAX); + return (const manifest_t *)(NVM_DATA_BASE_ADDR + CHIP_ROM_EXT_SIZE_MAX); } /** * Returns a pointer to the manifest of the first owner boot stage image stored - * in flash slot B. + * in NVM slot B. * * @return Pointer to the manifest of the first owner boot stage image in slot * B. */ OT_WARN_UNUSED_RESULT inline const manifest_t *rom_ext_boot_policy_manifest_b_get(void) { - return (const manifest_t *)(TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + - (TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2) + + return (const manifest_t *)(NVM_DATA_BASE_ADDR + (NVM_DATA_SIZE_BYTES / 2) + CHIP_ROM_EXT_SIZE_MAX); } #else diff --git a/sw/device/silicon_creator/rom_ext/rom_ext_manifest.c b/sw/device/silicon_creator/rom_ext/rom_ext_manifest.c index 7210301235926..31d56efbae0f5 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext_manifest.c +++ b/sw/device/silicon_creator/rom_ext/rom_ext_manifest.c @@ -5,19 +5,18 @@ #include "sw/device/silicon_creator/rom_ext/rom_ext_manifest.h" #include "sw/device/silicon_creator/lib/manifest.h" - -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. +#include "sw/device/silicon_creator/lib/nvm_ctrl.h" enum { - kFlashHalf = TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES / 2, + kNvmHalf = NVM_DATA_SIZE_BYTES / 2, }; const manifest_t *rom_ext_manifest(void) { uintptr_t pc = 0; asm("auipc %[pc], 0;" : [pc] "=r"(pc)); - // Align the PC to the current flash side. The ROM_EXT must be the first - // entity in each flash side, so this alignment is the manifest address. - pc &= ~((uintptr_t)kFlashHalf - 1); + // Align the PC to the current NVM side. The ROM_EXT must be the first + // entity in each NVM side, so this alignment is the manifest address. + pc &= ~((uintptr_t)kNvmHalf - 1); return (const manifest_t *)pc; } From 09bd0f36c32f3f7d206f268011af3420ef60cc1b Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 29 Jul 2026 10:06:43 +0200 Subject: [PATCH 38/41] [rram_ctrl,sw] Allocate 4 pages for OwnerSlot0/1 owner_block_t is 2048 bytes (OT_ASSERT_SIZE(owner_block_t, 2048)), but OwnerSlot0/OwnerSlot1 were each only allocated 1 emulated RRAM page (512 bytes), and nvm_ctrl_info_read/write compute emulated-page addresses as page_id*512+offset with no bounds clamp to a single page. Every write to OwnerSlot0 was silently spilling its extra 1536 bytes into OwnerSlot1/CreatorReserved0/OwnerReserved4, and OwnerSlot1's own write further corrupted OwnerReserved5. Add a num_pages field to rram_ctrl_info_page_t and extend RRAM_CTRL_INFO_PAGES_DEFINE with a 4th column so a logical page can reserve more than one contiguous physical page. OwnerSlot0/OwnerSlot1 now each get their real 4-page allocation. Signed-off-by: Michael Gautschi --- .../silicon_creator/lib/drivers/rram_ctrl.c | 9 +-- .../silicon_creator/lib/drivers/rram_ctrl.h | 70 +++++++++++++------ 2 files changed, 52 insertions(+), 27 deletions(-) diff --git a/sw/device/silicon_creator/lib/drivers/rram_ctrl.c b/sw/device/silicon_creator/lib/drivers/rram_ctrl.c index c35729fe1d86e..0ee92440cb312 100644 --- a/sw/device/silicon_creator/lib/drivers/rram_ctrl.c +++ b/sw/device/silicon_creator/lib/drivers/rram_ctrl.c @@ -22,10 +22,11 @@ #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Info pages. -#define INFO_PAGE_STRUCT_DEF_(name_, page_id_, emulated_) \ - const rram_ctrl_info_page_t name_ = { \ - .page_id = (page_id_), \ - .emulated = (emulated_), \ +#define INFO_PAGE_STRUCT_DEF_(name_, page_id_, emulated_, num_pages_) \ + const rram_ctrl_info_page_t name_ = { \ + .page_id = (page_id_), \ + .emulated = (emulated_), \ + .num_pages = (num_pages_), \ }; RRAM_CTRL_INFO_PAGES_DEFINE(INFO_PAGE_STRUCT_DEF_); #undef INFO_PAGE_STRUCT_DEF_ diff --git a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h index a498bb0c7bbeb..32deeff29d1ff 100644 --- a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h +++ b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h @@ -50,6 +50,16 @@ typedef struct rram_ctrl_info_page { * a real RRAM info page. */ bool emulated; + /** + * Number of contiguous physical pages backing this logical page. + * + * Real info pages are always 1 (there's no way to combine physical info + * pages). Emulated pages can span multiple contiguous data-partition pages + * to fit content larger than 512 bytes; callers reading/writing more than + * `num_pages * 512` bytes will silently spill into the next logical page's + * storage, since nothing enforces this bound at the read/write call site. + */ + uint32_t num_pages; } rram_ctrl_info_page_t; /** @@ -59,7 +69,7 @@ typedef struct rram_ctrl_info_page { */ enum { kRramCtrlEmulPageBase = 4064, - kRramCtrlEmulPageCount = 14, + kRramCtrlEmulPageCount = 20, /** * Memory-protection region index (of `RRAM_CTRL_PARAM_NUM_REGIONS`) used * for the shared emulated-page region. @@ -81,40 +91,53 @@ enum { /** * Table of RRAM information pages. * - * Columns: Name, physical page index, whether emulated. + * Columns: Name, physical page index, whether emulated, number of contiguous + * physical pages backing it (see `rram_ctrl_info_page_t.num_pages`). * We use an X macro to facilitate writing enums, switch statements, and unit * tests using the constants here, mirroring `FLASH_CTRL_INFO_PAGES_DEFINE`. + * + * Emulated-page offsets below are manually cumulative (each is the previous + * entry's offset + its `num_pages`) since a page occupying more than one + * slot has no entries of its own for its 2nd-Nth pages. */ // clang-format off #define RRAM_CTRL_INFO_PAGES_DEFINE(X) \ /** * Real, individually-protected info pages. */ \ - X(kRramCtrlInfoPageFactoryId, 0, false) \ - X(kRramCtrlInfoPageAttestationKeySeeds, 1, false) \ - X(kRramCtrlInfoPageFactoryCerts, 2, false) \ - X(kRramCtrlInfoPageCreatorSecret, 5, false) \ - X(kRramCtrlInfoPageOwnerSecret, 6, false) \ - X(kRramCtrlInfoPageWaferAuthSecret, 7, false) \ + X(kRramCtrlInfoPageFactoryId, 0, false, 1) \ + X(kRramCtrlInfoPageAttestationKeySeeds, 1, false, 1) \ + X(kRramCtrlInfoPageFactoryCerts, 2, false, 1) \ + X(kRramCtrlInfoPageCreatorSecret, 5, false, 1) \ + X(kRramCtrlInfoPageOwnerSecret, 6, false, 1) \ + X(kRramCtrlInfoPageWaferAuthSecret, 7, false, 1) \ /** * Emulated info pages, relocated onto the data partition. All share * `kRramCtrlEmulRegion`'s memory protection; see the TODO on * `rram_ctrl_info_page_t`. + * + * `owner_block_t` (backing OwnerSlot0/1) is 2048 bytes + * (`OT_ASSERT_SIZE(owner_block_t, 2048)`) -- 4 pages, not 1. Previously + * each only got 1 page, so every write silently overflowed into the next + * 3 logical pages' storage. OwnerSlot0/1 below now each reserve 4 pages + * (their 2nd-4th pages have no named entry of their own, matching how a + * single-page entry's extent is implied by its consumer's read/write size + * rather than a field in this table). */ \ - X(kRramCtrlInfoPageOwnerReserved0, kRramCtrlEmulPageBase + 0, true) \ - X(kRramCtrlInfoPageOwnerReserved1, kRramCtrlEmulPageBase + 1, true) \ - X(kRramCtrlInfoPageOwnerReserved2, kRramCtrlEmulPageBase + 2, true) \ - X(kRramCtrlInfoPageOwnerReserved3, kRramCtrlEmulPageBase + 3, true) \ - X(kRramCtrlInfoPageBootData0, kRramCtrlEmulPageBase + 4, true) \ - X(kRramCtrlInfoPageBootData1, kRramCtrlEmulPageBase + 5, true) \ - X(kRramCtrlInfoPageOwnerSlot0, kRramCtrlEmulPageBase + 6, true) \ - X(kRramCtrlInfoPageOwnerSlot1, kRramCtrlEmulPageBase + 7, true) \ - X(kRramCtrlInfoPageCreatorReserved0, kRramCtrlEmulPageBase + 8, true) \ - X(kRramCtrlInfoPageOwnerReserved4, kRramCtrlEmulPageBase + 9, true) \ - X(kRramCtrlInfoPageOwnerReserved5, kRramCtrlEmulPageBase + 10, true) \ - X(kRramCtrlInfoPageOwnerReserved6, kRramCtrlEmulPageBase + 11, true) \ - X(kRramCtrlInfoPageOwnerReserved7, kRramCtrlEmulPageBase + 12, true) \ - X(kRramCtrlInfoPageDiceCerts, kRramCtrlEmulPageBase + 13, true) \ + X(kRramCtrlInfoPageOwnerReserved0, kRramCtrlEmulPageBase + 0, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved1, kRramCtrlEmulPageBase + 1, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved2, kRramCtrlEmulPageBase + 2, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved3, kRramCtrlEmulPageBase + 3, true, 1) \ + X(kRramCtrlInfoPageBootData0, kRramCtrlEmulPageBase + 4, true, 1) \ + X(kRramCtrlInfoPageBootData1, kRramCtrlEmulPageBase + 5, true, 1) \ + X(kRramCtrlInfoPageOwnerSlot0, kRramCtrlEmulPageBase + 6, true, 4) \ + X(kRramCtrlInfoPageOwnerSlot1, kRramCtrlEmulPageBase + 10, true, 4) \ + X(kRramCtrlInfoPageCreatorReserved0, kRramCtrlEmulPageBase + 14, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved4, kRramCtrlEmulPageBase + 15, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved5, kRramCtrlEmulPageBase + 16, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved6, kRramCtrlEmulPageBase + 17, true, 1) \ + X(kRramCtrlInfoPageOwnerReserved7, kRramCtrlEmulPageBase + 18, true, 1) \ + X(kRramCtrlInfoPageDiceCerts, kRramCtrlEmulPageBase + 19, true, 1) \ // clang-format on /** @@ -122,8 +145,9 @@ enum { * @param name_ Name of the enumeration constant. * @param page_id_ Physical page index of the info page. * @param emulated_ Whether the page is emulated on the data partition. + * @param num_pages_ Number of contiguous physical pages backing this page. */ -#define INFO_PAGE_STRUCT_DECL_(name_, page_id_, emulated_) \ +#define INFO_PAGE_STRUCT_DECL_(name_, page_id_, emulated_, num_pages_) \ extern const rram_ctrl_info_page_t name_; /** From 0aee831a72a4fdcac3ec077ced9750b205d5f449 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 29 Jul 2026 10:07:42 +0200 Subject: [PATCH 39/41] [nvm_ctrl,rram_ctrl,sw] size DiceCerts/FactoryCerts correctly, move FactoryCerts to emulated DiceCerts (holding CDI_0 + CDI_1, ~1.3KB) and FactoryCerts (holding a UDS cert, ~800 bytes) both need more than one 512-byte RRAM page, but dice_page_t was sized for exactly one, so building/checking either cert overflowed the buffer (kErrorPersoTlvOutputBufTooSmall) or read past the page into stale/unrelated memory. Both DiceCerts and FactoryCerts are now 4 pages (2048 Bytes which is equal to the flash). The sizes of the two pages are deliberately equal, since they share one dice_page_t buffer type/format that only works correctly if both are the same size. A static_assert in dice_chain.h enforces that equality at compile time, so a future change to one without the other fails the build instead of silently reintroducing an overflow. Add compile-time kSize constants generated from the same RRAM_CTRL_INFO_PAGES_DEFINE table. These constants can be used to size read/write transactions and to allocate the right buffers to hold a page. Signed-off-by: Michael Gautschi --- .../silicon_creator/lib/cert/dice_chain.c | 17 +++--- .../silicon_creator/lib/cert/dice_chain.h | 13 +++- .../silicon_creator/lib/drivers/rram_ctrl.h | 59 +++++++++++++++---- sw/device/silicon_creator/lib/nvm_ctrl.h | 21 +++++++ 4 files changed, 86 insertions(+), 24 deletions(-) diff --git a/sw/device/silicon_creator/lib/cert/dice_chain.c b/sw/device/silicon_creator/lib/cert/dice_chain.c index 5f14a230a060e..cf2e0d2590800 100644 --- a/sw/device/silicon_creator/lib/cert/dice_chain.c +++ b/sw/device/silicon_creator/lib/cert/dice_chain.c @@ -22,10 +22,6 @@ #include "sw/device/silicon_creator/lib/ownership/datatypes.h" #include "sw/device/silicon_creator/manuf/base/perso_tlv_data.h" -enum { - kNvmPageSize = NVM_BYTES_PER_PAGE, -}; - /** * Defines a class for parsing and building the DICE cert chain. * @@ -217,11 +213,10 @@ static rom_error_t dice_chain_load_nvm(nvm_info_page_t info_page) { RETURN_IF_ERROR(dice_chain_flush_nvm()); // Read in a DICE certificate(s) page. - static_assert(sizeof(dice_chain.page) == kNvmPageSize, - "Invalid dice_chain buffer size"); RETURN_IF_ERROR(nvm_ctrl_info_read_zeros_on_read_error( info_page, /*offset=*/0, - /*word_count=*/kNvmPageSize / sizeof(uint32_t), &dice_chain.page)); + /*word_count=*/sizeof(dice_chain.page) / sizeof(uint32_t), + &dice_chain.page)); // Resets the flash page status. dice_chain.data_dirty = kHardenedBoolFalse; @@ -512,12 +507,14 @@ rom_error_t dice_chain_flush_nvm(void) { RETURN_IF_ERROR(dice_chain_seal_page()); RETURN_IF_ERROR(nvm_ctrl_info_erase(dice_chain.info_page)); - static_assert(sizeof(dice_chain.page) == kNvmPageSize, - "Invalid dice_chain buffer size"); + // Only `DiceCerts` is ever flushed (it's the only page `dice_chain_*` + // ever builds/pushes certs to); `FactoryCerts` is read-only, provisioned + // once during manufacturing (see `ft_personalize.c`). + HARDENED_CHECK_EQ(dice_chain.info_page, kNvmInfoPageDiceCerts); RETURN_IF_ERROR(nvm_ctrl_info_write( dice_chain.info_page, /*offset=*/0, - /*word_count=*/NVM_BYTES_PER_PAGE / sizeof(uint32_t), + /*word_count=*/sizeof(dice_chain.page) / sizeof(uint32_t), &dice_chain.page)); dice_chain.data_dirty = kHardenedBoolFalse; } diff --git a/sw/device/silicon_creator/lib/cert/dice_chain.h b/sw/device/silicon_creator/lib/cert/dice_chain.h index 0aac2a02ef7dc..b33f2f96f0b42 100644 --- a/sw/device/silicon_creator/lib/cert/dice_chain.h +++ b/sw/device/silicon_creator/lib/cert/dice_chain.h @@ -17,8 +17,17 @@ extern "C" { #endif +// `DiceCerts` and `FactoryCerts` share one `dice_page_t` buffer type/format, +// which only works correctly if they're actually the same size -- see the +// comment on their table entries in rram_ctrl.h's +// `RRAM_CTRL_INFO_PAGES_DEFINE`. If a future change gives them different page +// counts again, this catches it at compile time instead of silently +// reintroducing an over-read/overflow. +static_assert(kNvmInfoPageDiceCertsSize == kNvmInfoPageFactoryCertsSize, + "DiceCerts and FactoryCerts must be the same size"); + enum { - kDicePageDataSize = NVM_BYTES_PER_PAGE - sizeof(hmac_digest_t), + kDicePageDataSize = kNvmInfoPageDiceCertsSize - sizeof(hmac_digest_t), }; /** @@ -29,7 +38,7 @@ typedef struct dice_page { hmac_digest_t digest; } dice_page_t; -static_assert(sizeof(dice_page_t) == NVM_BYTES_PER_PAGE, +static_assert(sizeof(dice_page_t) == kNvmInfoPageDiceCertsSize, "Invalid dice page size"); /** diff --git a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h index 32deeff29d1ff..4bf1c893feecd 100644 --- a/sw/device/silicon_creator/lib/drivers/rram_ctrl.h +++ b/sw/device/silicon_creator/lib/drivers/rram_ctrl.h @@ -11,6 +11,8 @@ #include "sw/device/lib/base/multibits.h" #include "sw/device/silicon_creator/lib/error.h" +#include "hw/top/rram_ctrl_regs.h" // Generated. + #ifdef __cplusplus extern "C" { #endif @@ -20,13 +22,21 @@ extern "C" { * * Unlike flash, RRAM has only `RRAM_CTRL_PARAM_NUM_INFO_PAGES` (8) physical * info pages, too few for the 20 logical pages named in `nvm_info_page_t`. - * The 6 most security-sensitive pages (including the ones + * 5 security-sensitive pages (including the ones * `nvm_ctrl_creator_info_pages_lockdown()` must revoke creator access to) get * a real, individually-protected info page (`emulated` = false). The - * remaining 14 are "emulated": relocated onto reserved pages of the (much + * remaining 15 are "emulated": relocated onto reserved pages of the (much * larger) RRAM data partition, all sharing a single memory-protection region * with permissions that can't be restricted per-page. * + * `FactoryCerts` used to be real, but its content (a UDS cert, ~800 bytes) + * doesn't fit in one 512-byte info page, and info pages can't be combined + * like data pages can -- so it moved to emulated, spanning 4 pages (matching + * `DiceCerts`; see the table below). This means it lost its individual + * read-only lockdown; it's now only as protected as the shared emulated-page + * region, i.e. as writable as `OwnerSlot0`/`OwnerSlot1`/etc. A known, + * accepted tradeoff for now. + * * TODO(#XXXX): because 3 of the 7 pages `nvm_ctrl_creator_info_pages_lockdown` * must revoke (`BootData0`, `BootData1`, `CreatorReserved0`) are emulated and * share a region with owner-needed pages (`OwnerSlot0`, `OwnerSlot1`, @@ -69,7 +79,7 @@ typedef struct rram_ctrl_info_page { */ enum { kRramCtrlEmulPageBase = 4064, - kRramCtrlEmulPageCount = 20, + kRramCtrlEmulPageCount = 27, /** * Memory-protection region index (of `RRAM_CTRL_PARAM_NUM_REGIONS`) used * for the shared emulated-page region. @@ -103,11 +113,12 @@ enum { // clang-format off #define RRAM_CTRL_INFO_PAGES_DEFINE(X) \ /** - * Real, individually-protected info pages. + * Real, individually-protected info pages. Always 1 page each -- there's + * no way to combine physical info pages, so anything needing more than + * 512 bytes must be an emulated page instead (see below). */ \ X(kRramCtrlInfoPageFactoryId, 0, false, 1) \ X(kRramCtrlInfoPageAttestationKeySeeds, 1, false, 1) \ - X(kRramCtrlInfoPageFactoryCerts, 2, false, 1) \ X(kRramCtrlInfoPageCreatorSecret, 5, false, 1) \ X(kRramCtrlInfoPageOwnerSecret, 6, false, 1) \ X(kRramCtrlInfoPageWaferAuthSecret, 7, false, 1) \ @@ -117,12 +128,16 @@ enum { * `rram_ctrl_info_page_t`. * * `owner_block_t` (backing OwnerSlot0/1) is 2048 bytes - * (`OT_ASSERT_SIZE(owner_block_t, 2048)`) -- 4 pages, not 1. Previously - * each only got 1 page, so every write silently overflowed into the next - * 3 logical pages' storage. OwnerSlot0/1 below now each reserve 4 pages - * (their 2nd-4th pages have no named entry of their own, matching how a - * single-page entry's extent is implied by its consumer's read/write size - * rather than a field in this table). + * (`OT_ASSERT_SIZE(owner_block_t, 2048)`) -- 4 pages, not 1. `DiceCerts` + * and `FactoryCerts` are both sized to 4 pages too, deliberately equal + * (see the `static_assert` in dice_chain.h) even though their actual + * content (~1.3KB and ~800 bytes respectively) would technically fit in + * fewer: both share one `dice_page_t` buffer type, which only works + * correctly if they're the same size. `FactoryCerts` (moved here from the + * real pages above; see the TODO on `rram_ctrl_info_page_t`) previously + * didn't need to span pages at all as a real page; all three previously + * got only 1 page, so writes silently overflowed into the next logical + * page(s)' storage. */ \ X(kRramCtrlInfoPageOwnerReserved0, kRramCtrlEmulPageBase + 0, true, 1) \ X(kRramCtrlInfoPageOwnerReserved1, kRramCtrlEmulPageBase + 1, true, 1) \ @@ -137,7 +152,8 @@ enum { X(kRramCtrlInfoPageOwnerReserved5, kRramCtrlEmulPageBase + 16, true, 1) \ X(kRramCtrlInfoPageOwnerReserved6, kRramCtrlEmulPageBase + 17, true, 1) \ X(kRramCtrlInfoPageOwnerReserved7, kRramCtrlEmulPageBase + 18, true, 1) \ - X(kRramCtrlInfoPageDiceCerts, kRramCtrlEmulPageBase + 19, true, 1) \ + X(kRramCtrlInfoPageDiceCerts, kRramCtrlEmulPageBase + 19, true, 4) \ + X(kRramCtrlInfoPageFactoryCerts, kRramCtrlEmulPageBase + 23, true, 4) \ // clang-format on /** @@ -157,6 +173,25 @@ RRAM_CTRL_INFO_PAGES_DEFINE(INFO_PAGE_STRUCT_DECL_); #undef INFO_PAGE_STRUCT_DECL_ +/** + * Helper macro for declaring a `Size` compile-time constant: the + * total on-NVM byte size backing a logical page, i.e. + * `num_pages_ * RRAM_CTRL_PARAM_BYTES_PER_PAGE`. Callers should use these + * instead of re-deriving a page's size from `num_pages` themselves, so the + * page table in `RRAM_CTRL_INFO_PAGES_DEFINE` stays the only place page + * counts are written down. + * @param name_ Name of the enumeration constant. + * @param page_id_ Physical page index of the info page. + * @param emulated_ Whether the page is emulated on the data partition. + * @param num_pages_ Number of contiguous physical pages backing this page. + */ +#define INFO_PAGE_SIZE_ENUM_(name_, page_id_, emulated_, num_pages_) \ + name_##Size = (num_pages_) * RRAM_CTRL_PARAM_BYTES_PER_PAGE, + +enum { RRAM_CTRL_INFO_PAGES_DEFINE(INFO_PAGE_SIZE_ENUM_) }; + +#undef INFO_PAGE_SIZE_ENUM_ + /** * The following constants represent the expected number of sec_mmio * register writes performed by functions provided in this module. See diff --git a/sw/device/silicon_creator/lib/nvm_ctrl.h b/sw/device/silicon_creator/lib/nvm_ctrl.h index 0ac0cfbdf6bf7..453727b67fd59 100644 --- a/sw/device/silicon_creator/lib/nvm_ctrl.h +++ b/sw/device/silicon_creator/lib/nvm_ctrl.h @@ -18,6 +18,8 @@ #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #ifdef HAS_RRAM_CTRL +#include "sw/device/silicon_creator/lib/drivers/rram_ctrl.h" + #include "hw/top/rram_ctrl_regs.h" #endif // HAS_RRAM_CTRL @@ -203,6 +205,25 @@ typedef enum nvm_info_page { kNvmInfoPageDiceCerts = 19, } nvm_info_page_t; +/** + * Byte size of `DiceCerts`/`FactoryCerts`, the two logical pages whose + * on-NVM capacity varies with NVM technology (see `rram_ctrl.h`'s + * `RRAM_CTRL_INFO_PAGES_DEFINE`, which is the source of truth these mirror + * for RRAM). Every other logical page is exactly one `NVM_BYTES_PER_PAGE`, + * on both technologies. + */ +#ifdef HAS_RRAM_CTRL +enum { + kNvmInfoPageDiceCertsSize = kRramCtrlInfoPageDiceCertsSize, + kNvmInfoPageFactoryCertsSize = kRramCtrlInfoPageFactoryCertsSize, +}; +#else +enum { + kNvmInfoPageDiceCertsSize = NVM_BYTES_PER_PAGE, + kNvmInfoPageFactoryCertsSize = NVM_BYTES_PER_PAGE, +}; +#endif // HAS_RRAM_CTRL + // --------------------------------------------------------------------------- // SEC_MMIO write-increment constants // --------------------------------------------------------------------------- From 68f0c804141d330fd2f73e447e22898e022a2183 Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 29 Jul 2026 13:49:47 +0200 Subject: [PATCH 40/41] [ci,fpga] skip flash specific tests on CI These tests cannot pass anymore with RRAM. Signed-off-by: Michael Gautschi --- sw/device/tests/BUILD | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 98a7afd4721fc..75381a39c043b 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -1842,11 +1842,8 @@ opentitan_test( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, ), - # Run also as ROM_EXT stage as test coverage is reduced in silicon owner stage. - run_in_ci = [ - "//hw/top_earlgrey:fpga_cw340_sival_rom_ext", - "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys", - ], + # No longer relevant on RRAM; exclude all FPGA variants from CI entirely. + fpga = fpga_params(tags = ["skip_in_ci"]), deps = [ "//hw/top:otp_ctrl_c_regs", "//hw/top_earlgrey/sw/autogen:top_earlgrey", @@ -1990,11 +1987,9 @@ opentitan_test( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, ), - # Run also as ROM_EXT stage as test coverage is reduced in silicon owner stage. - run_in_ci = [ - "//hw/top_earlgrey:fpga_cw340_sival_rom_ext", - "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys", - ], + # No longer relevant on RRAM (no flash clock domain to test); exclude all + # FPGA variants from CI entirely. + fpga = fpga_params(tags = ["skip_in_ci"]), verilator = verilator_params(timeout = "long"), deps = [ "//hw/top:otp_ctrl_c_regs", @@ -2020,11 +2015,8 @@ opentitan_test( "//hw/top_earlgrey:silicon_creator": None, }, ), - # Run also as ROM_EXT stage as test coverage is reduced in silicon owner stage. - run_in_ci = [ - "//hw/top_earlgrey:fpga_cw340_sival_rom_ext", - "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys", - ], + # No longer relevant on RRAM; exclude all FPGA variants from CI entirely. + fpga = fpga_params(tags = ["skip_in_ci"]), verilator = verilator_params(timeout = "long"), deps = [ "//hw/top/dt", From 8cb1fac224dc6147ce19cdf5e16f3c404da389be Mon Sep 17 00:00:00 2001 From: Michael Gautschi Date: Wed, 29 Jul 2026 19:17:28 +0200 Subject: [PATCH 41/41] [nvm_testutils,sw] Initialize rram_ctrl during boot for sram execution. Unlike flash, the RRAM controller does not allow software read/write operations to the RRAM without initializing the controller. (which reads the scrambling keys) Signed-off-by: Michael Gautschi --- sw/device/lib/testing/nvm_testutils.h | 4 ++++ sw/device/silicon_creator/manuf/lib/sram_start.S | 8 ++++++++ .../silicon_creator/manuf/lib/sram_start_no_ast_init.S | 7 +++++++ 3 files changed, 19 insertions(+) diff --git a/sw/device/lib/testing/nvm_testutils.h b/sw/device/lib/testing/nvm_testutils.h index 7064199d11f6a..100e90c00edf2 100644 --- a/sw/device/lib/testing/nvm_testutils.h +++ b/sw/device/lib/testing/nvm_testutils.h @@ -143,6 +143,10 @@ status_t nvm_testutils_read_info_page(nvm_info_page_t page, * from OTP, and enables NVM access and instruction fetch. Call this once * from test ROM before any other NVM operation. * + * Unlike flash, RRAM cannot simply be read once its PHY is ready. The + * controller must be initialized before the RRAM can be read/written via + * software. + * * @param otp_nvm_default_cfg CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG OTP word; * pass 0 when HAS_OTP_CTRL is not available or the field reads as zero. * Applied to both flash and RRAM default region scrambling/ECC config; the diff --git a/sw/device/silicon_creator/manuf/lib/sram_start.S b/sw/device/silicon_creator/manuf/lib/sram_start.S index e9eb079163d9e..aa5c35a547594 100644 --- a/sw/device/silicon_creator/manuf/lib/sram_start.S +++ b/sw/device/silicon_creator/manuf/lib/sram_start.S @@ -189,6 +189,14 @@ sram_start: (MULTIBIT_ASM_BOOL4_FALSE << EDN_CTRL_CMD_FIFO_RST_OFFSET) sw t0, EDN_CTRL_REG_OFFSET(a0) + // This SRAM program runs with ROM execution disabled (JTAG-injected + // directly), so nothing else has brought up the NVM controller yet. + // Without this, any NVM access below (including ast_program_config's own + // read of AST calibration data) hangs forever waiting on a transaction + // that a not-yet-initialized controller never completes. + li a0, 0 // No OTP-derived default region config available yet. + call nvm_testutils_rom_init + // Configure the AST li a0, 0 // Do not run in verbose mode. call ast_program_config diff --git a/sw/device/silicon_creator/manuf/lib/sram_start_no_ast_init.S b/sw/device/silicon_creator/manuf/lib/sram_start_no_ast_init.S index 03440df3032e8..cc8233fb01a18 100644 --- a/sw/device/silicon_creator/manuf/lib/sram_start_no_ast_init.S +++ b/sw/device/silicon_creator/manuf/lib/sram_start_no_ast_init.S @@ -176,6 +176,13 @@ sram_start: (MULTIBIT_ASM_BOOL4_FALSE << EDN_CTRL_CMD_FIFO_RST_OFFSET) sw t0, EDN_CTRL_REG_OFFSET(a0) + // This SRAM program runs with ROM execution disabled (JTAG-injected + // directly), so nothing else has brought up the NVM controller yet. + // Without this, any NVM access in test_main hangs forever waiting on a + // transaction that a not-yet-initialized controller never completes. + li a0, 0 // No OTP-derived default region config available yet. + call nvm_testutils_rom_init + // Jump into the C program entry point. call test_main