diff --git a/cspdk/ge_on_si/tech.py b/cspdk/ge_on_si/tech.py index cfa7d82..876bd54 100644 --- a/cspdk/ge_on_si/tech.py +++ b/cspdk/ge_on_si/tech.py @@ -60,7 +60,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG), thickness=thickness_slab, zmin=0.0, - material="ge", + material="Ge", info={"mesh_order": 2}, sidewall_angle=10, width_to_z=0.5, @@ -69,7 +69,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG), thickness=thickness_wg, zmin=0.0, - material="ge", + material="Ge", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, diff --git a/cspdk/si220/cband/samples/mode_solver_r.py b/cspdk/si220/cband/samples/mode_solver_r.py index ff024a0..43f587b 100644 --- a/cspdk/si220/cband/samples/mode_solver_r.py +++ b/cspdk/si220/cband/samples/mode_solver_r.py @@ -10,8 +10,8 @@ core_width=0.45, core_thickness=0.22, slab_thickness=0.0, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) @@ -23,8 +23,8 @@ core_width=0.4, core_thickness=0.22, slab_thickness=0.1, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) diff --git a/cspdk/si220/cband/samples/mode_solver_s.py b/cspdk/si220/cband/samples/mode_solver_s.py index 7c16a74..76aa412 100644 --- a/cspdk/si220/cband/samples/mode_solver_s.py +++ b/cspdk/si220/cband/samples/mode_solver_s.py @@ -10,8 +10,8 @@ core_width=0.45, core_thickness=0.22, slab_thickness=0.0, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) @@ -23,8 +23,8 @@ core_width=0.40, core_thickness=0.22, slab_thickness=0.0, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) diff --git a/cspdk/si220/cband/tech.py b/cspdk/si220/cband/tech.py index bf0be0d..cf74954 100644 --- a/cspdk/si220/cband/tech.py +++ b/cspdk/si220/cband/tech.py @@ -81,7 +81,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG) - LogicalLayer(layer=LAYER.GRA), thickness=thickness_wg, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -91,7 +91,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG) & LogicalLayer(layer=LAYER.GRA), thickness=thickness_grating, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -101,7 +101,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.SLAB), thickness=thickness_slab, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -117,7 +117,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.PAD), thickness=thickness_metal, zmin=zmin_metal + thickness_metal, - material="Aluminum", + material="Al", info={"mesh_order": 2}, ), ) diff --git a/cspdk/si220/oband/samples/mode_solver_r.py b/cspdk/si220/oband/samples/mode_solver_r.py index ff024a0..43f587b 100644 --- a/cspdk/si220/oband/samples/mode_solver_r.py +++ b/cspdk/si220/oband/samples/mode_solver_r.py @@ -10,8 +10,8 @@ core_width=0.45, core_thickness=0.22, slab_thickness=0.0, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) @@ -23,8 +23,8 @@ core_width=0.4, core_thickness=0.22, slab_thickness=0.1, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) diff --git a/cspdk/si220/oband/samples/mode_solver_s.py b/cspdk/si220/oband/samples/mode_solver_s.py index 7c16a74..76aa412 100644 --- a/cspdk/si220/oband/samples/mode_solver_s.py +++ b/cspdk/si220/oband/samples/mode_solver_s.py @@ -10,8 +10,8 @@ core_width=0.45, core_thickness=0.22, slab_thickness=0.0, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) @@ -23,8 +23,8 @@ core_width=0.40, core_thickness=0.22, slab_thickness=0.0, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) diff --git a/cspdk/si220/oband/tech.py b/cspdk/si220/oband/tech.py index 982a4f5..10de9d2 100644 --- a/cspdk/si220/oband/tech.py +++ b/cspdk/si220/oband/tech.py @@ -81,7 +81,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG) - LogicalLayer(layer=LAYER.GRA), thickness=thickness_wg, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -91,7 +91,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG) & LogicalLayer(layer=LAYER.GRA), thickness=thickness_grating, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -101,7 +101,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.SLAB), thickness=thickness_slab, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -117,7 +117,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.PAD), thickness=thickness_metal, zmin=zmin_metal + thickness_metal, - material="Aluminum", + material="Al", info={"mesh_order": 2}, ), ) diff --git a/cspdk/si340/tech.py b/cspdk/si340/tech.py index 89d58b8..112f19f 100644 --- a/cspdk/si340/tech.py +++ b/cspdk/si340/tech.py @@ -84,7 +84,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG) - LogicalLayer(layer=LAYER.GRA), thickness=thickness_wg, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -94,7 +94,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG) & LogicalLayer(layer=LAYER.GRA), thickness=thickness_grating, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -104,7 +104,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.SLAB), thickness=thickness_slab, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -120,7 +120,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.PAD), thickness=thickness_metal, zmin=zmin_metal + thickness_metal, - material="Aluminum", + material="Al", info={"mesh_order": 2}, ), ) diff --git a/cspdk/si500/samples/mode_solver_r500.py b/cspdk/si500/samples/mode_solver_r500.py index 15b6b4f..8d1e9d2 100644 --- a/cspdk/si500/samples/mode_solver_r500.py +++ b/cspdk/si500/samples/mode_solver_r500.py @@ -10,8 +10,8 @@ core_width=0.45, core_thickness=0.5, slab_thickness=0.2, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) @@ -23,8 +23,8 @@ core_width=0.4, core_thickness=0.5, slab_thickness=0.2, - core_material="si", - clad_material="sio2", + core_material="Si", + clad_material="SiO2", group_index_step=10 * nm, ) diff --git a/cspdk/si500/tech.py b/cspdk/si500/tech.py index f25c992..5b265fb 100644 --- a/cspdk/si500/tech.py +++ b/cspdk/si500/tech.py @@ -82,7 +82,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG), thickness=thickness_wg, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -91,7 +91,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.SLAB), thickness=thickness_slab, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -107,7 +107,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.PAD), thickness=thickness_metal, zmin=zmin_metal + thickness_metal, - material="Aluminum", + material="Al", info={"mesh_order": 2}, ), ) diff --git a/cspdk/si_sus/tech.py b/cspdk/si_sus/tech.py index e649d25..81c656b 100644 --- a/cspdk/si_sus/tech.py +++ b/cspdk/si_sus/tech.py @@ -69,7 +69,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.WG_MARK), thickness=thickness_wg, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -78,7 +78,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.SLAB), thickness=thickness_slab, zmin=0.0, - material="si", + material="Si", info={"mesh_order": 2}, sidewall_angle=10, width_to_z=0.5, diff --git a/cspdk/sin200/tech.py b/cspdk/sin200/tech.py index bd6cf11..ad7e108 100644 --- a/cspdk/sin200/tech.py +++ b/cspdk/sin200/tech.py @@ -64,7 +64,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.NITRIDE), thickness=thickness_nitride, zmin=0.0, - material="sin", + material="SiN", info={"mesh_order": 2}, sidewall_angle=10, width_to_z=0.5, @@ -73,7 +73,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.NITRIDE_ETCH), thickness=thickness_nitride, zmin=0.0, - material="sin", + material="SiN", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -89,7 +89,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.PAD), thickness=thickness_metal, zmin=zmin_metal + thickness_metal, - material="Aluminum", + material="Al", info={"mesh_order": 2}, ), ) diff --git a/cspdk/sin300/samples/mode_solver_n.py b/cspdk/sin300/samples/mode_solver_n.py index 0cd6af0..59f6ba6 100644 --- a/cspdk/sin300/samples/mode_solver_n.py +++ b/cspdk/sin300/samples/mode_solver_n.py @@ -10,8 +10,8 @@ core_width=1.20, core_thickness=0.3, slab_thickness=0.0, - core_material="sin", - clad_material="sio2", + core_material="SiN", + clad_material="SiO2", group_index_step=10 * nm, ) @@ -23,8 +23,8 @@ core_width=0.95, core_thickness=0.3, slab_thickness=0.0, - core_material="sin", - clad_material="sio2", + core_material="SiN", + clad_material="SiO2", group_index_step=10 * nm, ) diff --git a/cspdk/sin300/tech.py b/cspdk/sin300/tech.py index b84a91b..dbf0834 100644 --- a/cspdk/sin300/tech.py +++ b/cspdk/sin300/tech.py @@ -66,7 +66,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.NITRIDE), thickness=thickness_nitride, zmin=0.0, - material="sin", + material="SiN", info={"mesh_order": 2}, sidewall_angle=10, width_to_z=0.5, @@ -75,7 +75,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.NITRIDE_ETCH), thickness=thickness_nitride, zmin=0.0, - material="sin", + material="SiN", info={"mesh_order": 1}, sidewall_angle=10, width_to_z=0.5, @@ -91,7 +91,7 @@ def get_layer_stack( layer=LogicalLayer(layer=LAYER.PAD), thickness=thickness_metal, zmin=zmin_metal + thickness_metal, - material="Aluminum", + material="Al", info={"mesh_order": 2}, ), ) diff --git a/docs/notebooks/meep_dc.ipynb b/docs/notebooks/meep_dc.ipynb index d00b8ef..b262772 100644 --- a/docs/notebooks/meep_dc.ipynb +++ b/docs/notebooks/meep_dc.ipynb @@ -72,7 +72,7 @@ "sim = meep.Simulation()\n", "\n", "sim.geometry(component=c, z_crop=\"auto\")\n", - "sim.materials = {\"si\": 3.47, \"SiO2\": 1.44}\n", + "sim.materials = {\"Si\": 3.47, \"SiO2\": 1.44}\n", "sim.source(port=\"o1\", wavelength=1.55, wavelength_span=0.04)\n", "sim.monitors = [\"o1\", \"o2\", \"o3\", \"o4\"]\n", "sim.domain(pml=1.0, margin=0.5)\n", diff --git a/docs/notebooks/meep_mmi.ipynb b/docs/notebooks/meep_mmi.ipynb index fdf5eda..2f8219a 100644 --- a/docs/notebooks/meep_mmi.ipynb +++ b/docs/notebooks/meep_mmi.ipynb @@ -92,7 +92,7 @@ "sim = meep.Simulation()\n", "\n", "sim.geometry(component=c, z_crop=\"auto\")\n", - "sim.materials = {\"si\": 3.47, \"SiO2\": 1.44}\n", + "sim.materials = {\"Si\": 3.47, \"SiO2\": 1.44}\n", "sim.source(port=\"o1\", wavelength=1.55, wavelength_span=0.04)\n", "sim.monitors = [\"o1\", \"o2\", \"o3\", \"o4\"]\n", "sim.domain(pml=1.0, margin=0.5)\n", diff --git a/tests/test_material_coverage.py b/tests/test_material_coverage.py new file mode 100644 index 0000000..0a4321e --- /dev/null +++ b/tests/test_material_coverage.py @@ -0,0 +1,45 @@ +"""Pilot coverage test: cspdk material names resolve against pdk-spec. + +pdk-spec is a local/unpublished package, so this test is guarded by +``pytest.importorskip`` and skips cleanly wherever it is not installed +(e.g. in CI). It runs once someone installs pdk-spec editable into the +cspdk venv. +""" + +import pytest + +from cspdk.ge_on_si.tech import LAYER_STACK as LAYER_STACK_GE_ON_SI +from cspdk.si220.cband.tech import LAYER_STACK as LAYER_STACK_SI220_CBAND +from cspdk.si220.oband.tech import LAYER_STACK as LAYER_STACK_SI220_OBAND +from cspdk.si340.tech import LAYER_STACK as LAYER_STACK_SI340 +from cspdk.si500.tech import LAYER_STACK as LAYER_STACK_SI500 +from cspdk.si_sus.tech import LAYER_STACK as LAYER_STACK_SI_SUS +from cspdk.sin200.tech import LAYER_STACK as LAYER_STACK_SIN200 +from cspdk.sin300.tech import LAYER_STACK as LAYER_STACK_SIN300 + +# local-only for now; skips in CI (and anywhere pdk-spec is not installed) +pdk_spec = pytest.importorskip("pdk_spec") + +LAYER_STACKS = { + "si220.cband": LAYER_STACK_SI220_CBAND, + "si220.oband": LAYER_STACK_SI220_OBAND, + "si340": LAYER_STACK_SI340, + "si500": LAYER_STACK_SI500, + "si_sus": LAYER_STACK_SI_SUS, + "sin200": LAYER_STACK_SIN200, + "sin300": LAYER_STACK_SIN300, + "ge_on_si": LAYER_STACK_GE_ON_SI, +} + + +def test_all_materials_resolve(): + """Assert every sub-PDK's LAYER_STACK has no dangling material names.""" + from pdk_spec import check_material_coverage + + material_cards = {**pdk_spec.material_cards} + dangling = {} + for name, stack in LAYER_STACKS.items(): + missing = check_material_coverage(stack, material_cards) + if missing: + dangling[name] = missing + assert dangling == {}, f"unresolved material names: {dangling}"