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18 lines (18 loc) · 733 Bytes
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[submodule "hw/chisel/src/main/resources/verilog-axi"]
path = hw/chisel/src/main/resources/verilog-axi
url = https://github.com/alexforencich/verilog-axi.git
[submodule "syn/bdf"]
path = syn/bdf
url = https://github.com/Avnet/bdf.git
[submodule "hw/chisel/deps/diplomacy"]
path = hw/chisel/deps/diplomacy
url = git@github.com:chipsalliance/diplomacy.git
[submodule "hw/chisel/deps/cde"]
path = hw/chisel/deps/cde
url = git@github.com:chipsalliance/cde.git
[submodule "hw/chisel/deps/berkeley-hardfloat"]
path = hw/chisel/deps/berkeley-hardfloat
url = git@github.com:ucb-bar/berkeley-hardfloat.git
[submodule "hw/chisel/deps/rocketchip"]
path = hw/chisel/deps/rocketchip
url = git@github.com:chipsalliance/rocket-chip.git